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14<h1 align="left">MI_DumpWramList* <IMG src="../../image/TWL.gif" align="middle"></h1>
15<h2>Syntax</h2>
16
17<dl>
18  <dd><CODE>#include &lt;twl/mi.h&gt;</CODE></dd>
19  <dd> </dd>
20  <dd><CODE>void MI_DumpWramList( <A href="../mi_constant.html">MIWramPos</A> wram );</CODE></dd>
21</dl>
22<dl>
23  <dd><CODE>void MI_DumpWramListAll( void );</CODE></dd>
24</dl>
25<dl>
26  <dd>(#define)</dd>
27  <dd><CODE>void MI_DumpWramList_A();</CODE></dd>
28  <dd><CODE>void MI_DumpWramList_B();</CODE></dd>
29  <dd><CODE>void MI_DumpWramList_C();</CODE></dd>
30</dl>
31<h2>Arguments</h2>
32<TABLE border="1" width="100%">
33  <TBODY>
34    <TR>
35      <TD width="13%"><EM><STRONG>wram</STRONG></EM></TD>
36      <TD width="87%">WRAM to display.</TD>
37    </TR>
38  </TBODY>
39</TABLE>
40
41<h2>Return Values</h2>
42<p>None.</p>
43
44<H2>Description</H2>
45<P>Displays the status of the WRAM.<BR>This function is used for debugging. It won't do anything in FINALROM builds.</P>
46<P>The <SPAN class="argument">wram</SPAN> for <CODE>MI_DumpWramList</CODE> is of type <CODE><A href="../mi_constant.html">MIWramPos</A></CODE> and specifies the target WRAM. It should be <CODE>MI_WRAM_A</CODE>, <CODE>MI_WRAM_B</CODE>, or <CODE>MI_WRAM_C</CODE>. The <CODE>MI_DumpWramListAll</CODE> function specifies all WRAMs.</P>
47<P>It will be displayed as follows:<BR>
48</P>
49<BLOCKQUOTE>
50<P><PRE>----WRAM-A (3000000-2ffffff)
51	ALLOC RESERVE
52slot0  ARM9  ARM9
53slot1  ARM7  ARM7
54slot2  ARM7  ----
55slot3  ----  ----</PRE></P>
56</BLOCKQUOTE>
57<P>ALLOC indicates the processor that has been assigned. In the example above, slot 0 is assigned to the ARM9, and slots 1 and 2 are assigned to the ARM7. Slot 3 has not yet been assigned.<BR><BR>
58RESERVE indicates the processors that have reservations. In the example above, slot 0 has been reserved for the ARM9, and slot 1 has been reserved for the ARM7. Slots 2 and 3 are not reserved.<BR><BR>
59In the example above, the WRAM-A region is shown as 0x3000000-0x2ffffff, but if WRAM-A has been configured so that it cannot be read from the ARM9, the end of this range may be a lower-order address than the start of this range.</P>
60<P><CODE>MI_DumpWramList_A</CODE> is the #define directive of <CODE>MI_DumpWramList( MI_WRAM_A )</CODE>. <BR><CODE>MI_DumpWramList_B</CODE> is the #define directive of <CODE>MI_DumpWramList( MI_WRAM_B )</CODE>. <BR><CODE>MI_DumpWramList_C</CODE> is the #define directive of <CODE>MI_DumpWramList( MI_WRAM_C )</CODE>. <BR>
61</P>
62<h2>See Also</h2>
63<P><A href="about_Wram.html">Overview (Work RAM)</A>, <A href="../mi_constant.html">MI-Related Constants</A></P>
64
65<H2>Revision History</H2>
66<P>2007/10/24 Initial version.</P>
67<hr><p>CONFIDENTIAL</p></body>
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