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7<TITLE>MI_GetNDmaArbitramentRoundRobinCycle</TITLE>
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11<H1 align="left">MI_GetNDmaArbitramentRoundRobinCycle <IMG src="../../image/TWL.gif" width="24" height="12" border="0" align=middle></H1>
12<H2>Syntax</H2>
13<DL>
14  <DD><CODE>#include &lt;twl/mi.h&gt;</CODE><BR>
15  <BR>
16  <CODE>u32 MI_GetNDmaArbitramentRoundRobinCycle( void );</CODE>
17  </DL>
18<H2>Arguments</H2>
19<P>None.</P>
20<H2>Return Values</H2>
21<P>Returns the &quot;number of cycles&quot; parameter when the DMA arbitration method is set to round-robin.</P>
22<H2>Description</H2>
23<P>Gets the &quot;number of cycles&quot; parameter that is currently set when the DMA arbitration method for the TWL's new DMA is set to round-robin.</P>
24<P>This is the number of cycles that can be run when there is a request from the DSP or ARM9 for the AHB bus. It will be ignored when there are no requests from the DSP or ARM9 for the AHB bus.</P>
25<P>This configuration value has no particular meaning when the DMA arbitration method is set to fixed.</P>
26<P>The table below shows the values that can be obtained.</P>
27<TABLE border="1">
28  <TBODY>
29    <TR>
30      <TH>Value</TH>
31      <TH>Description</TH>
32    </TR>
33    <TR>
34      <TD><CODE>MI_NDMA_RCYCLE_0</CODE></TD>
35      <TD>0 cycles             </TD>
36    </TR>
37    <TR>
38      <TD><CODE>MI_NDMA_RCYCLE_1</CODE></TD>
39      <TD>1 cycle</TD>
40    </TR>
41    <TR>
42      <TD><CODE>MI_NDMA_RCYCLE_2</CODE></TD>
43      <TD>2 cycles</TD>
44    </TR>
45    <TR>
46      <TD><CODE>MI_NDMA_RCYCLE_4</CODE></TD>
47      <TD>4 cycles</TD>
48    </TR>
49    <TR>
50      <TD><CODE>MI_NDMA_RCYCLE_8</CODE></TD>
51      <TD>8 cycles</TD>
52    </TR>
53    <TR>
54      <TD><CODE>MI_NDMA_RCYCLE_16</CODE></TD>
55      <TD>16 cycles</TD>
56    </TR>
57    <TR>
58      <TD><CODE>MI_NDMA_RCYCLE_32</CODE></TD>
59      <TD>32 cycles</TD>
60    </TR>
61    <TR>
62      <TD><CODE>MI_NDMA_RCYCLE_64</CODE></TD>
63      <TD>64 cycles</TD>
64    </TR>
65    <TR>
66      <TD><CODE>MI_NDMA_RCYCLE_128</CODE></TD>
67      <TD>128 cycles</TD>
68    </TR>
69    <TR>
70      <TD><CODE>MI_NDMA_RCYCLE_256</CODE></TD>
71      <TD>256 cycles</TD>
72    </TR>
73    <TR>
74      <TD><CODE>MI_NDMA_RCYCLE_512</CODE></TD>
75      <TD>512 cycles</TD>
76    </TR>
77    <TR>
78      <TD><CODE>MI_NDMA_RCYCLE_1024</CODE></TD>
79      <TD>1024 cycles</TD>
80    </TR>
81    <TR>
82      <TD><CODE>MI_NDMA_RCYCLE_2048</CODE></TD>
83      <TD>2048 cycles</TD>
84    </TR>
85    <TR>
86      <TD><CODE>MI_NDMA_RCYCLE_4096</CODE></TD>
87      <TD>4096 cycles</TD>
88    </TR>
89    <TR>
90      <TD><CODE>MI_NDMA_RCYCLE_8192</CODE></TD>
91      <TD>8192 cycles</TD>
92    </TR>
93    <TR>
94      <TD><CODE>MI_NDMA_RCYCLE_16384</CODE></TD>
95      <TD>16384 cycles</TD>
96    </TR>
97  </TBODY>
98</TABLE>
99<H2>Internal Operation</H2>
100<P>Accesses the DMA_GCNT register.</P>
101<H2>See Also</H2>
102<P><CODE><A href="MI_SetNDmaArbitrament.html">MI_SetNDmaArbitrament</A>, <A href="MI_GetNDmaArbitrament.html">MI_GetNDmaArbitrament</A><BR></CODE></P>
103<H2>Revision History</H2>
104<P>2007/09/07 Initial version.</P>
105<hr><p>CONFIDENTIAL</p></body>
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