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11<H1 align="left">MI_DmaRecv* <IMG src="../../image/NTR.gif" align="middle"><IMG src="../../image/TWL.gif" align="middle"></H1>
12<H2>Syntax</H2>
13<DL>
14<DD><CODE>#include &lt;nitro/mi.h&gt;</CODE><BR> <BR> <CODE>void MI_DmaRecv32( u32 dmaNo,<BR> volatile const void* src,<BR> void* dest,</CODE><BR> <CODE> u32 size );</CODE><BR> <BR> <CODE>void MI_DmaRecv32_SetUp( u32 dmaNo,<BR> volatile const void* src,<BR> void* dest,</CODE><BR> <CODE> u32 size );</CODE><BR> <BR> <CODE>void MI_DmaRecv16( u32 dmaNo,<BR> volatile const void* src,<BR> void* dest,<BR> u32 size );</CODE><BR> <BR> <CODE>void MI_DmaRecv16_SetUp( u32 dmaNo,<BR> volatile const void* src,<BR> void* dest,<BR> u32 size );</CODE><BR> <BR> <CODE>void MI_DmaRecv32Async( u32 dmaNo,<BR> volatile const void* src,<BR> void* dest,<BR> u32 size,</CODE><BR> <CODE>MIDmaCallback callback,<BR> void* arg );<BR></CODE><BR> <CODE>void MI_DmaRecv32Async_SetUp( u32 dmaNo,<BR> volatile const void* src,<BR> void* dest,<BR> u32 size,</CODE><BR> <CODE>MIDmaCallback callback,<BR> void* arg );<BR></CODE><BR> <CODE>void MI_DmaRecv16Async( u32 dmaNo,<BR> volatile const void* src,<BR> void* dest,<BR> u32 size,</CODE><BR> <CODE>MIDmaCallback callback,<BR> void* arg );</CODE><BR> <BR> <CODE>void MI_DmaRecv16Async_SetUp( u32 dmaNo,<BR> volatile const void* src,<BR> void* dest,<BR> u32 size,</CODE><BR> <CODE>MIDmaCallback callback,<BR> void* arg );</CODE><BR>
15</DL>
16<H2>Arguments</H2>
17<TABLE border="1" width="100%">
18  <TBODY>
19    <TR>
20<TD width="13%"><EM><STRONG>dmaNo</STRONG></EM></TD>
21<TD width="87%">DMA channel used.</TD>
22    </TR>
23    <TR>
24<TD width="13%"><EM><STRONG>src</STRONG></EM></TD>
25<TD width="87%">The transfer source address.</TD>
26    </TR>
27    <TR>
28<TD width="13%"><EM><STRONG>dest</STRONG></EM></TD>
29<TD width="87%">The transfer destination address.</TD>
30    </TR>
31    <TR>
32<TD><EM><STRONG>size</STRONG></EM></TD>
33<TD>Transfer size.</TD>
34    </TR>
35    <TR>
36<TD><EM><STRONG>callback</STRONG></EM></TD>
37<TD>Callback when DMA ends.</TD>
38    </TR>
39    <TR>
40<TD><EM><STRONG>arg</STRONG></EM></TD>
41<TD>Callback argument when DMA ends.</TD>
42    </TR>
43  </TBODY>
44</TABLE>
45<H2>Return Values</H2>
46<P>None.</P>
47<H2>Description</H2>
48<P>Uses DMA to receive data from the same address.<BR>The function does not change the address of the transfer source. It increments only the transfer destination address and repeatedly receives data from a contiguous region.</P>
49<P>The <CODE>*_SetUp</CODE> functions only configure the given settings without actually performing DMA. To actually start DMA, call the <CODE><A href="MI_DmaRestart.html">MI_DmaRestart</A></CODE> function.</P>
50<P><CODE>MI_DmaRecv16()</CODE> and <CODE>MI_DmaRecv16Async()</CODE> transfer in 16-bit units. Both the transfer source address and the transfer destination address must be 2-byte aligned. <CODE>MI_DmaRecv32()</CODE> and <CODE>MI_DmaRecv32Async()</CODE> transfer in 32-bit units. Both the transfer source address and the transfer destination address must be 4-byte aligned.</P>
51<P><CODE>MI_DmaRecv16()</CODE> and <CODE>MI_DmaRecv32()</CODE> wait within the function until DMA completes. <CODE>MI_DmaRecv16Async()</CODE> and <CODE>MI_DmaRecv32Async()</CODE> call the <B><I>callback</I></B> function when DMA ends. The callback, <code>callback</code>, is a <code>MIDmaCallback</code> type (a <code>void</code> type function that takes one <code>void*</code> argument). <code>callback</code> is called from the system DMA interrupt handler and therefore is called even if interrupts are prohibited.</P>
52<P>It is necessary to understand how to use Async-type APIs in order to obtain maximum functionality. Refer to the <CODE><A href="MI_DmaCopy.html">MI_DmaCopy</A></CODE> function for more information about this.</P>
53<H3><br> DMA Controller Bugs</H3>
54<P>See the section titled &quot;DMA Controller Bugs&quot; in the reference for the <CODE><A href="MI_DmaCopy.html">MI_DmaCopy</A></CODE> function.</P>
55<H2>Internal Operation</H2>
56<P>Uses the following IO registers: DMA<i>n</i> source register (0x40000B0 + 12<i>n</i>), DMA<i>n</i> destination register (0x40000B4 + 12<i>n</i>), and DMA<i>n</i> control register (0x40000B8 + 12<i>n</i>). (<i>n</i> specifies the DMA channel.))</P>
57<H2>See Also</H2>
58<P><CODE><A href="MI_DmaCopy.html">MI_DmaCopy*</A><BR><A href="MI_DmaFill.html">MI_DmaFill*</A><BR><A href="MI_DmaClear.html">MI_DmaClear*</A><BR><A href="MI_DmaSend.html">MI_DmaSend*</A><BR><A href="../memory/MI_CpuRecv.html">MI_CpuRecv*</A><BR><A href="MI_DmaRestart.html">MI_DmaRestart</A><BR></CODE></P>
59<H2>Revision History</H2>
60<P>2009/11/20 Added a description of a problem with the DMA controller.<BR>2007/10/31 Added <CODE>_SetUp()</CODE>. <BR>2007/10/23 Initial version.</P>
61<hr><p>CONFIDENTIAL</p></body>
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