1 /*---------------------------------------------------------------------------* 2 Project: PICA register macro header 3 File: gx_MacroShader.h 4 5 Copyright (C)2010 Nintendo Co., Ltd. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 $Revision: 25382 $ 14 *---------------------------------------------------------------------------*/ 15 16 #ifndef NN_GX_CTR_PICA_MACRO_SHADER_H_ 17 #define NN_GX_CTR_PICA_MACRO_SHADER_H_ 18 19 #include <nn/gx/CTR/gx_MacroCommon.h> 20 21 /////////////////////////////////// 22 // Draw API 23 // Geometry Misc Registers 24 /* 25 struct CommandDrawAPIMode0 26 { 27 u32 geometryUse : 2; 28 CMD_PADDING(6); 29 u32 mode : 1; 30 CMD_PADDING(1); // set to 0 [9:9] 31 CMD_PADDING(21); 32 u32 geometryUseMode : 1; 33 }; 34 */ 35 36 // PICA_REG_DRAW_MODE0 0x229 37 #define PICA_CMD_DATA_DRAW_MODE0(useGeometryShader, drawMode, useGeometryShaderSubdivision) \ 38 ( (useGeometryShader ? 2 : 0) | \ 39 (drawMode) << 8 | \ 40 0 << 9 | \ 41 ( (useGeometryShaderSubdivision) ? 1 : 0) << 31) 42 43 #define PICA_CMD_SET_DRAW_MODE0(drawMode) \ 44 PICA_CMD_DATA_DRAW_MODE0(0x0, drawMode, 0x0), \ 45 PICA_CMD_HEADER_SINGLE_BE(PICA_REG_DRAW_MODE0, 0x2) 46 47 #define PICA_CMD_SET_VERTEX_ATTR_ARRAYS_BASE_ADDR_DUMMY() \ 48 0x0, PICA_CMD_HEADER_BURST_BE(PICA_REG_VERTEX_ATTR_ARRAYS_BASE_ADDR, 30, 0x0), \ 49 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, \ 50 0x0, 0x0, \ 51 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, \ 52 0x0, 0x0, \ 53 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, \ 54 0x0, 0x0 55 56 #define PICA_CMD_SET_DRAW_MODE0_DUMMY_BEGIN() \ 57 0x0, PICA_CMD_HEADER_BURST_BE(PICA_REG_VS_OUT_REG_NUM2, 10, 0x0), \ 58 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, \ 59 0x0, 0x0, \ 60 PICA_CMD_SET_VERTEX_ATTR_ARRAYS_BASE_ADDR_DUMMY() 61 62 #define PICA_CMD_SET_DRAW_MODE0_DUMMY_END() \ 63 PICA_CMD_SET_VERTEX_ATTR_ARRAYS_BASE_ADDR_DUMMY() 64 65 #define PICA_CMD_SET_VS_GS_MODE(useGeometryShader, useGeometryShaderSubdivision) \ 66 PICA_CMD_SET_DRAW_MODE0_DUMMY_BEGIN(), \ 67 PICA_CMD_DATA_DRAW_MODE0(useGeometryShader, 0x0, useGeometryShaderSubdivision), \ 68 PICA_CMD_HEADER_SINGLE_BE(PICA_REG_DRAW_MODE0, 0x9), \ 69 PICA_CMD_SET_DRAW_MODE0_DUMMY_END() 70 71 /* 72 struct CommandDrawAPIMode0 73 { 74 u32 func : 1; 75 CMD_PADDING(7); 76 u32 mode : 1; 77 CMD_PADDING(23); 78 }; 79 */ 80 81 // PICA_REG_START_DRAW_FUNC 0x245 82 #define PICA_CMD_DATA_START_DRAW_FUNC(data) \ 83 ( (data) ? 1 : 0 ) 84 85 // PICA_REG_DRAW_MODE1 0x253 86 #define PICA_CMD_DATA_DRAW_MODE1(func, mode) \ 87 ( (func) | (mode) << 8 ) 88 89 #define PICA_CMD_SET_DRAW_MODE1(func, mode) \ 90 PICA_CMD_DATA_DRAW_MODE1(func, mode), PICA_CMD_HEADER_SINGLE_BE(PICA_REG_DRAW_MODE1, 0x3) 91 92 // PICA_REG_DRAW_VERTEX_NUM 0x228 93 #define PICA_CMD_DATA_DRAW_VERTEX_NUM(num) (num) 94 95 // PICA_REG_DRAW_VERTEX_OFFSET 0x22a 96 #define PICA_CMD_DATA_DRAW_VERTEX_OFFSET(offset) (offset) 97 98 // PICA_REG_START_DRAW_ARRAY 0x22e 99 #define PICA_CMD_DATA_START_DRAW_ARRAY(start) (start) 100 101 #define PICA_CMD_SET_START_DRAW_ARRAY(start) \ 102 PICA_CMD_DATA_START_DRAW_FUNC(0x0), PICA_CMD_HEADER_SINGLE_BE(PICA_REG_START_DRAW_FUNC0, 0x1), \ 103 PICA_CMD_DATA_START_DRAW_ARRAY(start), PICA_CMD_HEADER_SINGLE(PICA_REG_START_DRAW_ARRAY), \ 104 PICA_CMD_DATA_START_DRAW_FUNC(0x1), PICA_CMD_HEADER_SINGLE_BE(PICA_REG_START_DRAW_FUNC0, 0x1), \ 105 0x1, PICA_CMD_HEADER_SINGLE(PICA_REG_VERTEX_FUNC), \ 106 0, PICA_CMD_HEADER_SINGLE_BE(PICA_REG_DRAW_MODE2, 0x8), \ 107 0, PICA_CMD_HEADER_SINGLE_BE(PICA_REG_DRAW_MODE2, 0x8) 108 109 // PICA_REG_START_DRAW_ELEMENT 0x22f 110 #define PICA_CMD_DATA_START_DRAW_ELEMENT(start) (start) 111 112 #define PICA_CMD_SET_START_DRAW_ELEMENT(start) \ 113 PICA_CMD_DATA_START_DRAW_FUNC(0x0), PICA_CMD_HEADER_SINGLE_BE(PICA_REG_START_DRAW_FUNC0, 0x1), \ 114 PICA_CMD_DATA_START_DRAW_ELEMENT(start), PICA_CMD_HEADER_SINGLE(PICA_REG_START_DRAW_ELEMENT), \ 115 PICA_CMD_DATA_START_DRAW_FUNC(0x1), PICA_CMD_HEADER_SINGLE_BE(PICA_REG_START_DRAW_FUNC0, 0x1), \ 116 0x1, PICA_CMD_HEADER_SINGLE(PICA_REG_VERTEX_FUNC), \ 117 0, PICA_CMD_HEADER_SINGLE_BE(PICA_REG_DRAW_MODE2, 0x8), \ 118 0, PICA_CMD_HEADER_SINGLE_BE(PICA_REG_DRAW_MODE2, 0x8) 119 120 /////////////////////////////////// 121 // Vertex Shader float value 122 /* 123 struct CommandVSFloatAddr 124 { 125 u32 index : 8; 126 CMD_PADDING(23); 127 u32 mode : 1; 128 129 }; 130 */ 131 // PICA_REG_VS_FLOAT_ADDR 0x2c0 132 133 enum PicaDataVSFloat 134 { 135 PICA_DATA_VS_F24 = 0x0, 136 PICA_DATA_VS_F32 = 0x1 137 }; 138 139 #define PICA_CMD_DATA_VS_FLOAT_ADDR(mode, index) \ 140 ( (index) & 0xff | ( (mode) ? 0x80000000 : 0) ) 141 142 #define PICA_CMD_SET_VS_FLOAT_ADDR(mode, index) \ 143 PICA_CMD_DATA_VS_FLOAT_ADDR(mode, index), PICA_CMD_HEADER_SINGLE(PICA_REG_VS_FLOAT_ADDR) 144 145 // PICA_REG_VS_FLOAT 0x2c1 to 0x2c8 146 #define PICA_CMD_DATA_VS_FLOAT(data) (data) 147 148 /////////////////////////////////// 149 // Vertex Shader Bool 150 151 // PICA_REG_VS_BOOL 0x2b0 152 153 #define PICA_CMD_DATA_VS_BOOL(b) \ 154 ( (b) | 0x7fff0000 ) 155 156 /////////////////////////////////// 157 // Vertex Shader Integer 158 /* 159 struct CommandVSInt 160 { 161 u32 x : 8; 162 u32 y : 8; 163 u32 z : 8; 164 CMD_PADDING(8); 165 }; 166 */ 167 // PICA_REG_VS_INT0 0x2b1 to 0x2b4 168 #define PICA_CMD_DATA_VS_INT(x, y, z) ( (x) | (y) << 8 | (z) << 16 ) 169 170 /////////////////////////////////// 171 // Vertex Shader Start Address 172 173 // PICA_REG_VS_START_ADDR 0x2ba 174 #define PICA_CMD_DATA_VS_START_ADDR(data) \ 175 ( (data) | 0x7fff0000 ) 176 177 /////////////////////////////////// 178 // Vertex Shader Attribute Number 179 180 // PICA_REG_VS_ATTR_NUM0 0x2b9 181 #define PICA_CMD_DATA_VS_ATTR_NUM0(num) \ 182 ( ((num - 1) & 0xf) | ( 0xa0000000 ) ) 183 184 // PICA_REG_VS_ATTR_NUM1 0x242 185 #define PICA_CMD_DATA_VS_ATTR_NUM1(num) \ 186 ( (num - 1) & 0xf ) 187 188 #define PICA_CMD_SET_VS_ATTR_NUM(num) \ 189 PICA_CMD_DATA_VS_ATTR_NUM0(num), PICA_CMD_HEADER_SINGLE_BE(PICA_REG_VS_ATTR_NUM0, 0xB), \ 190 PICA_CMD_DATA_VS_ATTR_NUM1(num), PICA_CMD_HEADER_SINGLE(PICA_REG_VS_ATTR_NUM1) \ 191 192 /////////////////////////////////// 193 // Draw API 194 // Vertex Shader Output Register Number 195 // Geometry Shader Output Register Number 196 197 #define PICA_CMD_DATA_VS_GS_OUT_REG_NUM(num) (num) 198 199 // PICA_REG_VS_OUT_REG_NUM0 0x04f 200 // PICA_REG_GS_OUT_REG_NUM0 0x04f 201 #define PICA_CMD_DATA_VS_GS_OUT_REG_NUM0(num) (num) 202 203 // PICA_REG_VS_OUT_REG_NUM1 0x24a 204 #define PICA_CMD_DATA_VS_GS_OUT_REG_NUM1(num) ( (num) - 1 ) 205 206 // PICA_REG_VS_OUT_REG_NUM2 0x251 207 #define PICA_CMD_DATA_VS_GS_OUT_REG_NUM2(num) ( (num) - 1 ) 208 209 210 /* 211 struct CommandVSOutRegNum 212 { 213 u32 num : 4; 214 CMD_PADDING(4); 215 u32 mode : 1; 216 CMD_PADDING(23); 217 }; 218 */ 219 220 enum PicaDataDrawMode 221 { 222 PICA_DATA_DRAW_TRIANGLE_STRIP = 0x1, 223 PICA_DATA_DRAW_TRIANGLE_FAN = 0x2, 224 PICA_DATA_DRAW_TRIANGLES = 0x3, 225 PICA_DATA_DRAW_GEOMETRY_PRIMITIVE = 0x3 226 }; 227 228 // PICA_REG_VS_OUT_REG_NUM3 0x25e 229 // PICA_REG_GS_OUT_REG_NUM3 0x25e 230 #define PICA_CMD_DATA_VS_GS_OUT_REG_NUM3(num, mode) \ 231 ( (num - 1) | (mode) << 8 ) 232 233 #define PICA_CMD_SET_DRAW_MODE2(mode) \ 234 ((mode) << 8), \ 235 PICA_CMD_HEADER_SINGLE_BE(PICA_REG_VS_OUT_REG_NUM3, 0x2) 236 237 #define PICA_CMD_SET_VS_GS_OUT_REG_NUM(num) \ 238 num, PICA_CMD_HEADER_SINGLE(PICA_REG_VS_OUT_REG_NUM0), \ 239 (num - 1), PICA_CMD_HEADER_SINGLE(PICA_REG_VS_OUT_REG_NUM1), \ 240 (num - 1), PICA_CMD_HEADER_SINGLE(PICA_REG_VS_OUT_REG_NUM2), \ 241 (num - 1), PICA_CMD_HEADER_SINGLE_BE(PICA_REG_VS_OUT_REG_NUM3, 0x1) 242 243 /////////////////////////////////// 244 // Vertex Shader Output Register Mask 245 246 // PICA_REG_VS_OUT_REG_MASK 0x2bd 247 #define PICA_CMD_DATA_VS_OUT_MASK(mask) \ 248 ( (mask) & 0xffff ) 249 250 /////////////////////////////////// 251 // Vertex Shader Output Attribute 252 // Geometry Shader Output Attribute 253 enum PicaDataVSOutAttr 254 { 255 PICA_DATA_VS_OUT_ATTR_X = 0x00, 256 PICA_DATA_VS_OUT_ATTR_Y = 0x01, 257 PICA_DATA_VS_OUT_ATTR_Z = 0x02, 258 PICA_DATA_VS_OUT_ATTR_W = 0x03, 259 PICA_DATA_VS_OUT_ATTR_QUART_X = 0x04, 260 PICA_DATA_VS_OUT_ATTR_QUART_Y = 0x05, 261 PICA_DATA_VS_OUT_ATTR_QUART_Z = 0x06, 262 PICA_DATA_VS_OUT_ATTR_QUART_W = 0x07, 263 PICA_DATA_VS_OUT_ATTR_R = 0x08, 264 PICA_DATA_VS_OUT_ATTR_G = 0x09, 265 PICA_DATA_VS_OUT_ATTR_B = 0x0a, 266 PICA_DATA_VS_OUT_ATTR_A = 0x0b, 267 PICA_DATA_VS_OUT_ATTR_TEX0_U = 0x0c, 268 PICA_DATA_VS_OUT_ATTR_TEX0_V = 0x0d, 269 PICA_DATA_VS_OUT_ATTR_TEX1_U = 0x0e, 270 PICA_DATA_VS_OUT_ATTR_TEX1_V = 0x0f, 271 PICA_DATA_VS_OUT_ATTR_TEX0_W = 0x10, 272 PICA_DATA_VS_OUT_ATTR_VIEW_X = 0x12, 273 PICA_DATA_VS_OUT_ATTR_VIEW_Y = 0x13, 274 PICA_DATA_VS_OUT_ATTR_VIEW_Z = 0x14, 275 PICA_DATA_VS_OUT_ATTR_TEX2_U = 0x16, 276 PICA_DATA_VS_OUT_ATTR_TEX2_V = 0x17, 277 PICA_DATA_VS_OUT_ATTR_INVALID = 0x1f 278 }; 279 280 /* 281 struct CommandVSOutAttr 282 { 283 u32 attr_x : 5; 284 CMD_PADDING(3); 285 u32 attr_y : 5; 286 CMD_PADDING(3); 287 u32 attr_z : 5; 288 CMD_PADDING(3); 289 u32 attr_w : 5; 290 CMD_PADDING(3); 291 }; 292 */ 293 294 // PICA_REG_VS_OUT_ATTR0 0x050 to 0x056 295 // PICA_REG_GS_OUT_ATTR0 0x050 to 0x056 296 #define PICA_CMD_DATA_VS_GS_OUT_ATTR(attr_x, attr_y, attr_z, attr_w) \ 297 ( (attr_x) | (attr_y) << 8 | (attr_z) << 16 | (attr_w) << 24 ) 298 299 // PICA_REG_VS_OUT_ATTR_MODE 0x064 300 // PICA_REG_GS_OUT_ATTR_MODE 0x064 301 #define PICA_CMD_DATA_VS_GS_OUT_ATTR_MODE( mode ) (mode) 302 303 /////////////////////////////////// 304 // Vertex Shader Output Attribute clock 305 // Geometry Shader Output Attribute clock 306 /* 307 struct CommandVSOutAttrClk 308 { 309 u32 verZ : 1; 310 u32 col : 1; 311 CMD_PADDING(6); 312 u32 tex0 : 1; 313 u32 tex1 : 1; 314 u32 tex2 : 1; 315 CMD_PADDING(5); 316 u32 tex0_w : 1; 317 CMD_PADDING(7); 318 u32 view_quart : 1; 319 CMD_PADDING(7); 320 }; 321 */ 322 323 // PICA_REG_VS_OUT_ATTR_CLK 0x06f 324 // PICA_REG_GS_OUT_ATTR_CLK 0x06f 325 #define PICA_CMD_DATA_VS_GS_OUT_ATTR_CLK(posZ, col, tex0, tex1, tex2, tex0_w, view_quart) \ 326 ( ((posZ) ? 1 : 0) | \ 327 ((col) ? 1 : 0) << 1 | \ 328 ((tex0) ? 1 : 0) << 8 | \ 329 ((tex1) ? 1 : 0) << 9 | \ 330 ((tex2) ? 1 : 0) << 10 | \ 331 ((tex0_w) ? 1 : 0) << 16 | \ 332 ((view_quart) ? 1 : 0) << 24 ) 333 334 /////////////////////////////////// 335 // Vertex Shader Program Code 336 337 // PICA_REG_VS_PROG_ADDR 0x2cb 338 #define PICA_CMD_DATA_VS_PROG_ADDR(addr) (addr) 339 340 // PICA_REG_VS_PROG_SWIZZLE_ADDR 0x2d5 341 #define PICA_CMD_DATA_VS_PROG_SWIZZLE_ADDR(addr) (addr) 342 343 // PICA_REG_VS_PROG_DATA0 0x2cc to 0x2d3 344 #define PICA_CMD_DATA_VS_PROG_DATA(data) (data) 345 346 // PICA_REG_VS_PROG_SWIZZLE_DATA0 0x2d6 to 0x2dd 347 #define PICA_CMD_DATA_VS_PROG_SWIZZLE_DATA(data) (data) 348 349 // PICA_REG_VS_PROG_END 0x2bf 350 #define PICA_CMD_DATA_VS_PROG_END(data) (data) 351 352 /////////////////////////////////// 353 // Vertex Shader Attribute Input Register Map 354 /* 355 struct CommandVSAttrInputRegMap0 356 u32 index1 : 4; 357 u32 index2 : 4; 358 u32 index3 : 4; 359 u32 index4 : 4; 360 u32 index5 : 4; 361 u32 index6 : 4; 362 u32 index7 : 4; 363 u32 index8 : 4; 364 }; 365 */ 366 367 // PICA_REG_VS_ATTR_IN_REG_MAP0 0x2bb 368 #define PICA_CMD_DATA_VS_ATTR_IN_REG_MAP0(index1, index2, index3, index4, index5, index6, index7, index8) \ 369 ((index1) | (index2) << 4 | (index3) << 8 | (index4) << 12 | \ 370 (index5) << 16 | (index6) << 20 | (index7) << 24 | (index8) << 28 ) 371 372 /* 373 struct CommandVSAttrInputRegMap1 374 { 375 u32 index9 : 4; 376 u32 index10 : 4; 377 u32 index11 : 4; 378 u32 index12 : 4; 379 CMD_PADDING(16); 380 381 }; 382 */ 383 384 // PICA_REG_VS_ATTR_IN_REG_MAP1 0x2bc 385 #define PICA_CMD_DATA_VS_ATTR_IN_REG_MAP1(index9, index10, index11, index12) \ 386 ((index9) | (index10) << 4 | (index11) << 8 | (index12) << 12) 387 388 /////////////////////////////////// 389 // Vertex Shader Fixed Attribute 390 391 // PICA_REG_VS_FIXED_ATTR 0x232 392 #define PICA_CMD_DATA_VS_FIXED_ATTR(order) ( (order) & 0xf ) 393 394 // PICA_REG_VS_FIXED_ATTR_DATA0 0x233 to 0x235 395 #define PICA_CMD_DATA_VS_FIXED_ATTR_DATA(data) (data) 396 397 #define PICA_CMD_SET_VS_FIXED_ATTR(order, c0, c1, c2) \ 398 PICA_CMD_DATA_VS_FIXED_ATTR(order), PICA_CMD_HEADER_BURSTSEQ( PICA_REG_VS_FIXED_ATTR, 4), \ 399 (u32)(c0), (u32)(c1), \ 400 (u32)(c2), PICA_CMD_DATA_ZERO() 401 402 /////////////////////////////////// 403 // Vertex Attribute Arrays 404 /* 405 struct CommandVtxAttrArraysBaseAddr 406 { 407 CMD_PADDING(1); 408 u32 addr : 28; 409 CMD_PADDING(3); 410 }; 411 */ 412 // PICA_REG_VERTEX_ATTR_ARRAYS_BASE_ADDR 0x200 413 #define PICA_CMD_DATA_VERTEX_ATTR_ARRAYS_BASE_ADDR(addr) ( ((u32)(addr) >> 4) << 1 ) 414 415 /* 416 struct CommandVAttrArrays 417 { 418 u32 attr0 : 4; 419 u32 attr1 : 4; 420 u32 attr2 : 4; 421 u32 attr3 : 4; 422 u32 attr4 : 4; 423 u32 attr5 : 4; 424 u32 attr6 : 4; 425 u32 attr7 : 4; 426 }; 427 */ 428 enum PicaDataVertexAttrType 429 { 430 PICA_DATA_SIZE_1_BYTE = 0x0, 431 PICA_DATA_SIZE_1_UNSIGNED_BYTE = 0x1, 432 PICA_DATA_SIZE_1_SHORT = 0x2, 433 PICA_DATA_SIZE_1_FLOAT = 0x3, 434 PICA_DATA_SIZE_2_BYTE = 0x4, 435 PICA_DATA_SIZE_2_UNSIGNED_BYTE = 0x5, 436 PICA_DATA_SIZE_2_SHORT = 0x6, 437 PICA_DATA_SIZE_2_FLOAT = 0x7, 438 PICA_DATA_SIZE_3_BYTE = 0x8, 439 PICA_DATA_SIZE_3_UNSIGNED_BYTE = 0x9, 440 PICA_DATA_SIZE_3_SHORT = 0xa, 441 PICA_DATA_SIZE_3_FLOAT = 0xb, 442 PICA_DATA_SIZE_4_BYTE = 0xc, 443 PICA_DATA_SIZE_4_UNSIGNED_BYTE = 0xd, 444 PICA_DATA_SIZE_4_SHORT = 0xe, 445 PICA_DATA_SIZE_4_FLOAT = 0xf 446 }; 447 448 // PICA_REG_VERTEX_ATTR_ARRAYS0 0x201 449 #define PICA_CMD_DATA_VERTEX_ATTR_ARRAYS0(attr0, attr1, attr2, attr3, attr4, attr5, attr6, attr7) \ 450 ((attr0) | (attr1) << 4 | (attr2) << 8 | (attr3) << 12 | \ 451 (attr4) << 16 | (attr5) << 20 | (attr6) << 24 | (attr7) << 28) 452 453 // PICA_REG_VERTEX_ATTR_ARRAYS1 0x202 454 #define PICA_CMD_DATA_VERTEX_ATTR_ARRAYS1(attr8, attr9, attr10, attr11, mask, attrNum) \ 455 ( (attr8) | \ 456 (attr9) << 4 | \ 457 (attr10) << 8 | \ 458 (attr11) << 12 | \ 459 (mask) << 16 | \ 460 ((attrNum) - 1) << 28 ) 461 462 // PICA_REG_LOAD_ARRAY0_ATTR_OFFSET 0x203 463 #define PICA_CMD_DATA_LOAD_ARRAY0_ATTR_OFFSET(offset) (offset) 464 465 /* 466 struct CommandLodArray0Element 467 { 468 u32 attr0 : 4; 469 u32 attr1 : 4; 470 u32 attr2 : 4; 471 u32 attr3 : 4; 472 u32 attr4 : 4; 473 u32 attr5 : 4; 474 u32 attr6 : 4; 475 u32 attr7 : 4; 476 }; 477 */ 478 enum PicaDataVertexAttr 479 { 480 PICA_DATA_VERTEX_0_ATTR = 0x0, 481 PICA_DATA_VERTEX_1_ATTR = 0x1, 482 PICA_DATA_VERTEX_2_ATTR = 0x2, 483 PICA_DATA_VERTEX_3_ATTR = 0x3, 484 PICA_DATA_VERTEX_4_ATTR = 0x4, 485 PICA_DATA_VERTEX_5_ATTR = 0x5, 486 PICA_DATA_VERTEX_6_ATTR = 0x6, 487 PICA_DATA_VERTEX_7_ATTR = 0x7, 488 PICA_DATA_VERTEX_8_ATTR = 0x8, 489 PICA_DATA_VERTEX_9_ATTR = 0x9, 490 PICA_DATA_VERTEX_a_ATTR = 0xa, 491 PICA_DATA_VERTEX_b_ATTR = 0xb, 492 PICA_DATA_PADDING_4_BYTE = 0xc, 493 PICA_DATA_PADDING_8_BYTE = 0xd, 494 PICA_DATA_PADDING_12_BYTE = 0xe, 495 PICA_DATA_PADDING_16_BYTE = 0xf 496 }; 497 498 // PICA_REG_LOAD_ARRAY0_ELEMENT0 0x204 499 #define PICA_CMD_DATA_LOAD_ARRAY_ELEMENT0(attr0, attr1, attr2, attr3, attr4, attr5, attr6, attr7) \ 500 ( (attr0) | (attr1) << 4 | (attr2) << 8 | (attr3) << 12 | \ 501 (attr4) << 16 | (attr5) << 20 | (attr6) << 24 | (attr7) << 28) 502 503 // PICA_REG_LOAD_ARRAY0_ELEMENT1 0x205 504 #define PICA_CMD_DATA_LOAD_ARRAY_ELEMENT1(attr8, attr9, attr10, attr11, byteNum, elementNum) \ 505 ( (attr8) | \ 506 (attr9) << 4 | \ 507 (attr10) << 8 | \ 508 (attr11) << 12 | \ 509 (byteNum) << 16 | \ 510 (elementNum) << 28 ) 511 512 513 /* 514 struct CommandIndexArrayAddrOffset 515 { 516 u32 offset : 28; 517 CMD_PADDING(3); 518 u32 type : 1; 519 }; 520 */ 521 522 enum PicaDataIndexArray 523 { 524 PICA_DATA_INDEX_ARRAY_UNSIGNED_BYTE = 0x0, 525 PICA_DATA_INDEX_ARRAY_UNSIGNED_SHORT = 0x1 526 }; 527 528 // PICA_REG_INDEX_ARRAY_ADDR_OFFSET 0x227 529 #define PICA_CMD_DATA_INDEX_ARRAY_ADDR_OFFSET(offset, type) \ 530 ( (offset) | ((type) ? 0x80000000 : 0 ) ) 531 532 /////////////////////////////////// 533 // Geometry Shader Over View 534 535 // PICA_REG_VS_COM_MODE 0x244 536 #define PICA_CMD_DATA_VS_COM_MODE(mode) ((mode) ? 1 : 0) 537 538 #define PICA_CMD_SET_VS_COM_MODE(mode) \ 539 PICA_CMD_DATA_VS_COM_MODE(mode), PICA_CMD_HEADER_SINGLE_BE(PICA_REG_VS_COM_MODE, 0x1) 540 541 /////////////////////////////////// 542 // Geometry Shader float value 543 /* 544 struct CommandGSFloatAddr 545 { 546 u32 index : 8; 547 CMD_PADDING(23); 548 u32 mode : 1; 549 550 }; 551 */ 552 553 enum PicaDataGSFloat 554 { 555 PICA_DATA_GS_F24 = 0x0, 556 PICA_DATA_GS_F32 = 0x1 557 }; 558 559 // PICA_REG_GS_FLOAT_ADDR 0x290 560 561 #define PICA_CMD_DATA_GS_FLOAT_ADDR(mode, index) \ 562 ( ((index) & 0xff) | (mode) << 31 ) 563 564 #define PICA_CMD_SET_GS_FLOAT_ADDR(mode, index) \ 565 PICA_CMD_DATA_GS_FLOAT_ADDR(mode, index), PICA_CMD_HEADER_SINGLE(PICA_REG_GS_FLOAT_ADDR) 566 567 // PICA_REG_GS_FLOAT_DATA 0x291 to 0x298 568 #define PICA_CMD_DATA_GS_FLOAT_DATA(data) (data) 569 570 /////////////////////////////////// 571 // Geometry Shader Bool 572 573 // PICA_REG_GS_BOOL 0x280 574 #define PICA_CMD_DATA_GS_BOOL(b) \ 575 ( (b) | 0x7fff0000 ) 576 577 /////////////////////////////////// 578 // Geometry Shader Integer 579 /* 580 struct CommandGSInt 581 { 582 u32 x : 8; 583 u32 y : 8; 584 u32 z : 8; 585 CMD_PADDING(8); 586 }; 587 */ 588 // PICA_REG_GS_INT0 0x281 to 0x284 589 #define PICA_CMD_DATA_GS_INT(x, y, z) ( (x) | (y) << 8 | (z) << 16 ) 590 591 /////////////////////////////////// 592 // Geometry Shader Start Address 593 594 // PICA_REG_GS_START_ADDR 0x28a 595 #define PICA_CMD_DATA_GS_START_ADDR(data) \ 596 ( (data) | 0x7fff0000 ) 597 598 /////////////////////////////////// 599 // Geometry Shader Attribute Number 600 // Geometry Misc Registers 601 /* 602 struct CommandGSAttrNum 603 { 604 u32 num : 4; 605 CMD_PADDING(4); 606 u32 mode0 : 8; 607 CMD_PADDING(8); 608 u32 mode1 : 8; 609 }; 610 */ 611 612 // 0x289[15:8] : 0x1/0x0, 613 // 0x289[31:24] : 0x08/0xa0, 614 615 616 // PICA_REG_GS_ATTR_NUM 0x289 617 #define PICA_CMD_DATA_GS_ATTR_NUM(geometryShaderVertexAttrInputNum, useGeometrySubdivision, useGeometryShader) \ 618 ( ( (geometryShaderVertexAttrInputNum) - 1) | \ 619 ( (useGeometrySubdivision) ? 1 : 0) << 8 | \ 620 ( ((useGeometryShader) ? 0x08 : 0xa0) << 24 ) ) 621 622 #define PICA_CMD_SET_GS_ATTR_NUM(geometryShaderVertexAttrInputNum, useGeometrySubdivision, useGeometryShader) \ 623 PICA_CMD_DATA_GS_ATTR_NUM(geometryShaderVertexAttrInputNum, useGeometrySubdivision, useGeometryShader), \ 624 PICA_CMD_HEADER_SINGLE_BE(PICA_REG_GS_ATTR_NUM, 0xB) 625 626 /////////////////////////////////// 627 // Geometry Shader Output Register Mask 628 629 // PICA_REG_GS_OUT_REG_MASK 0x28d 630 #define PICA_CMD_DATA_GS_OUT_MASK(mask) \ 631 ( (mask) & 0xffff ) 632 633 /////////////////////////////////// 634 // Geometry Shader Program Code 635 636 637 // PICA_REG_GS_PROG_ADDR 0x29b 638 #define PICA_CMD_DATA_GS_PROG_ADDR(addr) (addr) 639 640 // PICA_REG_GS_PROG_SWIZZLE_ADDR 0x2a5 641 #define PICA_CMD_DATA_GS_PROG_SWIZZLE_ADDR(addr) (addr) 642 643 // PICA_REG_GS_PROG_DATA0 0x29c to 0x2a3 644 #define PICA_CMD_DATA_GS_PROG_DATA(data) (data) 645 646 // PICA_REG_GS_PROG_SWIZZLE_DATA0 0x2a6 to 0x2ad 647 #define PICA_CMD_DATA_GS_PROG_SWIZZLE_DATA(data) (data) 648 649 /////////////////////////////////// 650 // Geometry Shader Attribute Input Register Map 651 /* 652 struct CommandGSAttrInputRegMap0 653 u32 index1 : 4; 654 u32 index2 : 4; 655 u32 index3 : 4; 656 u32 index4 : 4; 657 u32 index5 : 4; 658 u32 index6 : 4; 659 u32 index7 : 4; 660 u32 index8 : 4; 661 }; 662 */ 663 664 // PICA_REG_GS_ATTR_IN_REG_MAP0 0x28b 665 #define PICA_CMD_DATA_GS_ATTR_IN_REG_MAP0(index1, index2, index3, index4, index5, index6, index7, index8) \ 666 ( (index1) | (index2) << 4 | (index3) << 8 | (index4) << 12 | \ 667 (index5) << 16 | (index6) << 20 | (index7) << 24 | (index8) << 28 ) 668 669 /* 670 struct CommandGSAttrInputRegMap1 671 { 672 u32 index9 : 4; 673 u32 index10 : 4; 674 u32 index11 : 4; 675 u32 index12 : 4; 676 CMD_PADDING(16); 677 678 }; 679 */ 680 681 // PICA_REG_GS_ATTR_IN_REG_MAP1 0x28c 682 #define PICA_CMD_DATA_GS_ATTR_IN_MAP1(index9, index10, index11, index12) \ 683 ((index9) | (index10) << 4 | (index11) << 8 | (index12) << 12) 684 685 #define PICA_CMD_SET_GS_ATTR_IN_MAP_RESERVED() \ 686 0x76543210, PICA_CMD_HEADER_SINGLE(PICA_REG_GS_ATTR_IN_REG_MAP0), \ 687 0xfedcba98, PICA_CMD_HEADER_SINGLE(PICA_REG_GS_ATTR_IN_REG_MAP1) 688 689 /////////////////////////////////// 690 // Geometry Misc Registers 691 692 enum PicaDataGSMode 693 { 694 PICA_DATA_GS_OTHER_MODE = 0x0, 695 PICA_DATA_GS_SUBDIVISION_MODE = 0x1, 696 PICA_DATA_GS_SUBDIVISION_CATMULL_MODE = 0x3, 697 PICA_DATA_GS_SUBDIVISION_LOOP_MODE = 0x5, 698 PICA_DATA_GS_PARTICLE_MODE = 0x2 699 }; 700 701 // PICA_REG_GS_MISC_REG0 0x252 702 #define PICA_CMD_DATA_GS_MISC_REG0(mode) \ 703 ( (mode & PICA_DATA_GS_SUBDIVISION_MODE) ? 0x1 : ( (mode == PICA_DATA_GS_PARTICLE_MODE) ? 0x01004302 : 0) ) 704 705 #define PICA_CMD_SET_GS_MISC_REG0_SUBDIVISION() \ 706 PICA_CMD_DATA_GS_MISC_REG0(PICA_DATA_GS_SUBDIVISION_MODE), \ 707 PICA_CMD_HEADER_SINGLE(PICA_REG_GS_MISC_REG0) 708 709 #define PICA_CMD_SET_GS_MISC_REG0_SUBDIVISION_CATMULL() \ 710 PICA_CMD_DATA_GS_MISC_REG0(PICA_DATA_GS_SUBDIVISION_CATMULL_MODE), \ 711 PICA_CMD_HEADER_SINGLE(PICA_REG_GS_MISC_REG0) 712 713 #define PICA_CMD_SET_GS_MISC_REG0_SUBDIVISION_LOOP() \ 714 PICA_CMD_DATA_GS_MISC_REG0(PICA_DATA_GS_SUBDIVISION_LOOP_MODE), \ 715 PICA_CMD_HEADER_SINGLE(PICA_REG_GS_MISC_REG0) 716 717 #define PICA_CMD_SET_GS_MISC_REG0_PARTICLE() \ 718 PICA_CMD_DATA_GS_MISC_REG0(PICA_DATA_GS_PARTICLE_MODE), \ 719 PICA_CMD_HEADER_SINGLE(PICA_REG_GS_MISC_REG0) 720 721 #define PICA_CMD_SET_GS_MISC_REG0_OTHER() \ 722 PICA_CMD_DATA_GS_MISC_REG0(PICA_DATA_GS_OTHER_MODE), \ 723 PICA_CMD_HEADER_SINGLE(PICA_REG_GS_MISC_REG0) 724 725 // PICA_REG_GS_MISC_REG1 0x254 726 #define PICA_CMD_DATA_GS_MISC_REG1(mode) \ 727 ( (mode == PICA_DATA_GS_SUBDIVISION_CATMULL_MODE) ? 3 : ( (mode == PICA_DATA_GS_SUBDIVISION_LOOP_MODE) ? 2 : 0) ) 728 729 /////////////////////////////////// 730 // Appendex Registers 731 732 // PICA_REG_START_DRAW_FUNC1 0x25f 733 #define PICA_CMD_DATA_START_DRAW_FUNC1(resetVertexTriangleIndex) \ 734 ( (resetVertexTriangleIndex) ? 1 : 0 ) 735 736 #endif // NN_GX_CTR_PICA_MACRO_SHADER_H_ 737