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9<title>DCFreeze</title>
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14<h1>DCFreeze</h1>
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17<h2>C Specification</h2>
18<BLOCKQUOTE>
19<pre><CODE>#include &lt;revolution/os.h&gt;
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21void DCFreeze ( void );</CODE></pre>
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23<h2>Arguments</h2>
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25<p>None.</p>
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27<h2>Return Values</h2>
28
29<p>None.</p>
30
31<h2>Description</h2>
32
33<p>The current contents of the L1 data cache are locked and will not be invalidated. Hits are still serviced, but misses go straight to L2 cache or 60x bus.&nbsp;Even if the cache is frozen, most cache operations (for example, <code><a href="DCFlushRange.html">DCFlushRange</a></code>) will still execute.</p>
34
35<p>In PowerPC architecture jargon, this feature is referred to as locking the data cache.&nbsp;In Revolution, freeze is used to distinguish between the locked cache and DMA features.</p>
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38
39<h2>See Also</h2>
40
41<p><a href="../list.html#Cache" target="contents">Cache Functions</a>, <br> <code><a href="DCUnfreeze.html">DCUnfreeze</a>, <a href="ICFreeze.html">ICFreeze</a>, <a href="ICUnfreeze.html">ICUnfreeze</a></code></p>
42
43<h2>Revision History</h2><p></p>
44
45<P>03/01/2006 Initial version.</p>
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