1 /*---------------------------------------------------------------------------* 2 Project: TwlSDK - IO Register List - 3 File: twl/hw/ARM9/ioreg_DSP.h 4 5 Copyright 2007-2008 Nintendo. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 *---------------------------------------------------------------------------*/ 14 // 15 // I was generated automatically, don't edit me directly!!! 16 // 17 #ifndef TWL_HW_ARM9_IOREG_DSP_H_ 18 #define TWL_HW_ARM9_IOREG_DSP_H_ 19 20 #ifndef SDK_ASM 21 #include <nitro/types.h> 22 #include <twl/hw/ARM9/mmap_global.h> 23 #endif 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* 30 * Definition of Register offsets, addresses and variables. 31 */ 32 33 34 /* PDATA */ 35 36 #define REG_PDATA_OFFSET 0x4300 37 #define REG_PDATA_ADDR (HW_REG_BASE + REG_PDATA_OFFSET) 38 #define reg_DSP_PDATA (*( REGType16v *) REG_PDATA_ADDR) 39 40 /* PADR */ 41 42 #define REG_PADR_OFFSET 0x4304 43 #define REG_PADR_ADDR (HW_REG_BASE + REG_PADR_OFFSET) 44 #define reg_DSP_PADR (*( REGType16v *) REG_PADR_ADDR) 45 46 /* PCFG */ 47 48 #define REG_PCFG_OFFSET 0x4308 49 #define REG_PCFG_ADDR (HW_REG_BASE + REG_PCFG_OFFSET) 50 #define reg_DSP_PCFG (*( REGType16v *) REG_PCFG_ADDR) 51 52 /* PSTS */ 53 54 #define REG_PSTS_OFFSET 0x430c 55 #define REG_PSTS_ADDR (HW_REG_BASE + REG_PSTS_OFFSET) 56 #define reg_DSP_PSTS (*(const REGType16v *) REG_PSTS_ADDR) 57 58 /* PSEM */ 59 60 #define REG_PSEM_OFFSET 0x4310 61 #define REG_PSEM_ADDR (HW_REG_BASE + REG_PSEM_OFFSET) 62 #define reg_DSP_PSEM (*( REGType16v *) REG_PSEM_ADDR) 63 64 /* PMASK */ 65 66 #define REG_PMASK_OFFSET 0x4314 67 #define REG_PMASK_ADDR (HW_REG_BASE + REG_PMASK_OFFSET) 68 #define reg_DSP_PMASK (*( REGType16v *) REG_PMASK_ADDR) 69 70 /* PCLEAR */ 71 72 #define REG_PCLEAR_OFFSET 0x4318 73 #define REG_PCLEAR_ADDR (HW_REG_BASE + REG_PCLEAR_OFFSET) 74 #define reg_DSP_PCLEAR (*( REGType16v *) REG_PCLEAR_ADDR) 75 76 /* SEM */ 77 78 #define REG_SEM_OFFSET 0x431c 79 #define REG_SEM_ADDR (HW_REG_BASE + REG_SEM_OFFSET) 80 #define reg_DSP_SEM (*(const REGType16v *) REG_SEM_ADDR) 81 82 /* COM0 */ 83 84 #define REG_COM0_OFFSET 0x4320 85 #define REG_COM0_ADDR (HW_REG_BASE + REG_COM0_OFFSET) 86 #define reg_DSP_COM0 (*( REGType16v *) REG_COM0_ADDR) 87 88 /* REP0 */ 89 90 #define REG_REP0_OFFSET 0x4324 91 #define REG_REP0_ADDR (HW_REG_BASE + REG_REP0_OFFSET) 92 #define reg_DSP_REP0 (*(const REGType16v *) REG_REP0_ADDR) 93 94 /* COM1 */ 95 96 #define REG_COM1_OFFSET 0x4328 97 #define REG_COM1_ADDR (HW_REG_BASE + REG_COM1_OFFSET) 98 #define reg_DSP_COM1 (*( REGType16v *) REG_COM1_ADDR) 99 100 /* REP1 */ 101 102 #define REG_REP1_OFFSET 0x432c 103 #define REG_REP1_ADDR (HW_REG_BASE + REG_REP1_OFFSET) 104 #define reg_DSP_REP1 (*(const REGType16v *) REG_REP1_ADDR) 105 106 /* COM2 */ 107 108 #define REG_COM2_OFFSET 0x4330 109 #define REG_COM2_ADDR (HW_REG_BASE + REG_COM2_OFFSET) 110 #define reg_DSP_COM2 (*( REGType16v *) REG_COM2_ADDR) 111 112 /* REP2 */ 113 114 #define REG_REP2_OFFSET 0x4334 115 #define REG_REP2_ADDR (HW_REG_BASE + REG_REP2_OFFSET) 116 #define reg_DSP_REP2 (*(const REGType16v *) REG_REP2_ADDR) 117 118 119 /* 120 * Definitions of Register fields 121 */ 122 123 124 /* PDATA */ 125 126 /* PADR */ 127 128 /* PCFG */ 129 130 #define REG_DSP_PCFG_MEMSEL_SHIFT 12 131 #define REG_DSP_PCFG_MEMSEL_SIZE 4 132 #define REG_DSP_PCFG_MEMSEL_MASK 0xf000 133 134 #define REG_DSP_PCFG_PRIE2_SHIFT 11 135 #define REG_DSP_PCFG_PRIE2_SIZE 1 136 #define REG_DSP_PCFG_PRIE2_MASK 0x0800 137 138 #define REG_DSP_PCFG_PRIE1_SHIFT 10 139 #define REG_DSP_PCFG_PRIE1_SIZE 1 140 #define REG_DSP_PCFG_PRIE1_MASK 0x0400 141 142 #define REG_DSP_PCFG_PRIE0_SHIFT 9 143 #define REG_DSP_PCFG_PRIE0_SIZE 1 144 #define REG_DSP_PCFG_PRIE0_MASK 0x0200 145 146 #define REG_DSP_PCFG_WFEIE_SHIFT 8 147 #define REG_DSP_PCFG_WFEIE_SIZE 1 148 #define REG_DSP_PCFG_WFEIE_MASK 0x0100 149 150 #define REG_DSP_PCFG_WFFIE_SHIFT 7 151 #define REG_DSP_PCFG_WFFIE_SIZE 1 152 #define REG_DSP_PCFG_WFFIE_MASK 0x0080 153 154 #define REG_DSP_PCFG_RFNEIE_SHIFT 6 155 #define REG_DSP_PCFG_RFNEIE_SIZE 1 156 #define REG_DSP_PCFG_RFNEIE_MASK 0x0040 157 158 #define REG_DSP_PCFG_RFFIE_SHIFT 5 159 #define REG_DSP_PCFG_RFFIE_SIZE 1 160 #define REG_DSP_PCFG_RFFIE_MASK 0x0020 161 162 #define REG_DSP_PCFG_RS_SHIFT 4 163 #define REG_DSP_PCFG_RS_SIZE 1 164 #define REG_DSP_PCFG_RS_MASK 0x0010 165 166 #define REG_DSP_PCFG_DRS_SHIFT 2 167 #define REG_DSP_PCFG_DRS_SIZE 2 168 #define REG_DSP_PCFG_DRS_MASK 0x000c 169 170 #define REG_DSP_PCFG_AIM_SHIFT 1 171 #define REG_DSP_PCFG_AIM_SIZE 1 172 #define REG_DSP_PCFG_AIM_MASK 0x0002 173 174 #define REG_DSP_PCFG_DSPR_SHIFT 0 175 #define REG_DSP_PCFG_DSPR_SIZE 1 176 #define REG_DSP_PCFG_DSPR_MASK 0x0001 177 178 #ifndef SDK_ASM 179 #define REG_DSP_PCFG_FIELD( memsel, prie2, prie1, prie0, wfeie, wffie, rfneie, rffie, rs, drs, aim, dspr ) \ 180 (u16)( \ 181 ((u32)(memsel) << REG_DSP_PCFG_MEMSEL_SHIFT) | \ 182 ((u32)(prie2) << REG_DSP_PCFG_PRIE2_SHIFT) | \ 183 ((u32)(prie1) << REG_DSP_PCFG_PRIE1_SHIFT) | \ 184 ((u32)(prie0) << REG_DSP_PCFG_PRIE0_SHIFT) | \ 185 ((u32)(wfeie) << REG_DSP_PCFG_WFEIE_SHIFT) | \ 186 ((u32)(wffie) << REG_DSP_PCFG_WFFIE_SHIFT) | \ 187 ((u32)(rfneie) << REG_DSP_PCFG_RFNEIE_SHIFT) | \ 188 ((u32)(rffie) << REG_DSP_PCFG_RFFIE_SHIFT) | \ 189 ((u32)(rs) << REG_DSP_PCFG_RS_SHIFT) | \ 190 ((u32)(drs) << REG_DSP_PCFG_DRS_SHIFT) | \ 191 ((u32)(aim) << REG_DSP_PCFG_AIM_SHIFT) | \ 192 ((u32)(dspr) << REG_DSP_PCFG_DSPR_SHIFT)) 193 #endif 194 195 196 /* PSTS */ 197 198 #define REG_DSP_PSTS_RCOMIM2_SHIFT 15 199 #define REG_DSP_PSTS_RCOMIM2_SIZE 1 200 #define REG_DSP_PSTS_RCOMIM2_MASK 0x8000 201 202 #define REG_DSP_PSTS_RCOMIM1_SHIFT 14 203 #define REG_DSP_PSTS_RCOMIM1_SIZE 1 204 #define REG_DSP_PSTS_RCOMIM1_MASK 0x4000 205 206 #define REG_DSP_PSTS_RCOMIM0_SHIFT 13 207 #define REG_DSP_PSTS_RCOMIM0_SIZE 1 208 #define REG_DSP_PSTS_RCOMIM0_MASK 0x2000 209 210 #define REG_DSP_PSTS_RRI2_SHIFT 12 211 #define REG_DSP_PSTS_RRI2_SIZE 1 212 #define REG_DSP_PSTS_RRI2_MASK 0x1000 213 214 #define REG_DSP_PSTS_RRI1_SHIFT 11 215 #define REG_DSP_PSTS_RRI1_SIZE 1 216 #define REG_DSP_PSTS_RRI1_MASK 0x0800 217 218 #define REG_DSP_PSTS_RRI0_SHIFT 10 219 #define REG_DSP_PSTS_RRI0_SIZE 1 220 #define REG_DSP_PSTS_RRI0_MASK 0x0400 221 222 #define REG_DSP_PSTS_PSEMI_SHIFT 9 223 #define REG_DSP_PSTS_PSEMI_SIZE 1 224 #define REG_DSP_PSTS_PSEMI_MASK 0x0200 225 226 #define REG_DSP_PSTS_WFEI_SHIFT 8 227 #define REG_DSP_PSTS_WFEI_SIZE 1 228 #define REG_DSP_PSTS_WFEI_MASK 0x0100 229 230 #define REG_DSP_PSTS_WFFI_SHIFT 7 231 #define REG_DSP_PSTS_WFFI_SIZE 1 232 #define REG_DSP_PSTS_WFFI_MASK 0x0080 233 234 #define REG_DSP_PSTS_RFNEI_SHIFT 6 235 #define REG_DSP_PSTS_RFNEI_SIZE 1 236 #define REG_DSP_PSTS_RFNEI_MASK 0x0040 237 238 #define REG_DSP_PSTS_RFFI_SHIFT 5 239 #define REG_DSP_PSTS_RFFI_SIZE 1 240 #define REG_DSP_PSTS_RFFI_MASK 0x0020 241 242 #define REG_DSP_PSTS_PRST_SHIFT 2 243 #define REG_DSP_PSTS_PRST_SIZE 1 244 #define REG_DSP_PSTS_PRST_MASK 0x0004 245 246 #define REG_DSP_PSTS_WTIP_SHIFT 1 247 #define REG_DSP_PSTS_WTIP_SIZE 1 248 #define REG_DSP_PSTS_WTIP_MASK 0x0002 249 250 #define REG_DSP_PSTS_RTIP_SHIFT 0 251 #define REG_DSP_PSTS_RTIP_SIZE 1 252 #define REG_DSP_PSTS_RTIP_MASK 0x0001 253 254 #ifndef SDK_ASM 255 #define REG_DSP_PSTS_FIELD( rcomim2, rcomim1, rcomim0, rri2, rri1, rri0, psemi, wfei, wffi, rfnei, rffi, prst, wtip, rtip ) \ 256 (u16)( \ 257 ((u32)(rcomim2) << REG_DSP_PSTS_RCOMIM2_SHIFT) | \ 258 ((u32)(rcomim1) << REG_DSP_PSTS_RCOMIM1_SHIFT) | \ 259 ((u32)(rcomim0) << REG_DSP_PSTS_RCOMIM0_SHIFT) | \ 260 ((u32)(rri2) << REG_DSP_PSTS_RRI2_SHIFT) | \ 261 ((u32)(rri1) << REG_DSP_PSTS_RRI1_SHIFT) | \ 262 ((u32)(rri0) << REG_DSP_PSTS_RRI0_SHIFT) | \ 263 ((u32)(psemi) << REG_DSP_PSTS_PSEMI_SHIFT) | \ 264 ((u32)(wfei) << REG_DSP_PSTS_WFEI_SHIFT) | \ 265 ((u32)(wffi) << REG_DSP_PSTS_WFFI_SHIFT) | \ 266 ((u32)(rfnei) << REG_DSP_PSTS_RFNEI_SHIFT) | \ 267 ((u32)(rffi) << REG_DSP_PSTS_RFFI_SHIFT) | \ 268 ((u32)(prst) << REG_DSP_PSTS_PRST_SHIFT) | \ 269 ((u32)(wtip) << REG_DSP_PSTS_WTIP_SHIFT) | \ 270 ((u32)(rtip) << REG_DSP_PSTS_RTIP_SHIFT)) 271 #endif 272 273 274 /* PSEM */ 275 276 /* PMASK */ 277 278 /* PCLEAR */ 279 280 /* SEM */ 281 282 /* COM0 */ 283 284 /* REP0 */ 285 286 /* COM1 */ 287 288 /* REP1 */ 289 290 /* COM2 */ 291 292 /* REP2 */ 293 294 #ifdef __cplusplus 295 } /* extern "C" */ 296 #endif 297 298 /* TWL_HW_ARM9_IOREG_DSP_H_ */ 299 #endif 300