1 /*---------------------------------------------------------------------------* 2 Project: PPC user-level register definitions. 3 File: ppc_asm_user.h 4 5 Copyright (C) 2010-2011 Nintendo. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 *---------------------------------------------------------------------------*/ 14 15 #ifndef _PPC_ASM_USER_H_INCLUDED_ 16 #define _PPC_ASM_USER_H_INCLUDED_ 17 18 #if defined(__GNUC__) && !defined(__ghs__) 19 #ifndef __ASSEMBLER__ 20 __asm__ 21 ( 22 ".equ fp0, 0\n\t" 23 ".equ fp1, 1\n\t" 24 ".equ fp2, 2\n\t" 25 ".equ fp3, 3\n\t" 26 ".equ fp4, 4\n\t" 27 ".equ fp5, 5\n\t" 28 ".equ fp6, 6\n\t" 29 ".equ fp7, 7\n\t" 30 ".equ fp8, 8\n\t" 31 ".equ fp9, 9\n\t" 32 ".equ fp10, 10\n\t" 33 ".equ fp11, 11\n\t" 34 ".equ fp12, 12\n\t" 35 ".equ fp13, 13\n\t" 36 ".equ fp14, 14\n\t" 37 ".equ fp15, 15\n\t" 38 ".equ fp16, 16\n\t" 39 ".equ fp17, 17\n\t" 40 ".equ fp18, 18\n\t" 41 ".equ fp19, 19\n\t" 42 ".equ fp20, 20\n\t" 43 ".equ fp21, 21\n\t" 44 ".equ fp22, 22\n\t" 45 ".equ fp23, 23\n\t" 46 ".equ fp24, 24\n\t" 47 ".equ fp25, 25\n\t" 48 ".equ fp26, 26\n\t" 49 ".equ fp27, 27\n\t" 50 ".equ fp28, 28\n\t" 51 ".equ fp29, 29\n\t" 52 ".equ fp30, 30\n\t" 53 ".equ fp31, 31\n\t" 54 55 ".equ psr0, 0\n\t" 56 ".equ psr1, 1\n\t" 57 ".equ psr2, 2\n\t" 58 ".equ psr3, 3\n\t" 59 ".equ psr4, 4\n\t" 60 ".equ psr5, 5\n\t" 61 ".equ psr6, 6\n\t" 62 ".equ psr7, 7\n\t" 63 ".equ psr8, 8\n\t" 64 ".equ psr9, 9\n\t" 65 ".equ psr10, 10\n\t" 66 ".equ psr11, 11\n\t" 67 ".equ psr12, 12\n\t" 68 ".equ psr13, 13\n\t" 69 ".equ psr14, 14\n\t" 70 ".equ psr15, 15\n\t" 71 ".equ psr16, 16\n\t" 72 ".equ psr17, 17\n\t" 73 ".equ psr18, 18\n\t" 74 ".equ psr19, 19\n\t" 75 ".equ psr20, 20\n\t" 76 ".equ psr21, 21\n\t" 77 ".equ psr22, 22\n\t" 78 ".equ psr23, 23\n\t" 79 ".equ psr24, 24\n\t" 80 ".equ psr25, 25\n\t" 81 ".equ psr26, 26\n\t" 82 ".equ psr27, 27\n\t" 83 ".equ psr28, 28\n\t" 84 ".equ psr29, 29\n\t" 85 ".equ psr30, 30\n\t" 86 ".equ psr31, 31\n\t" 87 88 ".equ gqr0, 0\n\t" 89 ".equ gqr1, 1\n\t" 90 ".equ gqr2, 2\n\t" 91 ".equ gqr3, 3\n\t" 92 ".equ gqr4, 4\n\t" 93 ".equ gqr5, 5\n\t" 94 ".equ gqr6, 6\n\t" 95 ".equ gqr7, 7\n\t" 96 ); 97 #endif // __GNUC__ 98 #endif // __ASSEMBLER__ 99 100 /*---------------------------------------------------------------------------* 101 PIR - Processor Per-Core ID Register (Espresso Only) 102 *---------------------------------------------------------------------------*/ 103 #define PIR 1007 104 #define PIR_MASK 0x03 105 #define PIR_MASK_START 30 106 #define PIR_MASK_END 31 107 #define PIR_CORE0 0 108 #define PIR_CORE1 1 109 #define PIR_CORE2 2 110 111 #define CTR 9 // count register 112 #define XER 1 113 #define LR 8 114 115 #define USIA 939 // sampled instruction addr 116 117 #define UPMC1 937 // performance counters 118 #define UPMC2 938 119 #define UPMC3 941 120 #define UPMC4 942 121 #define PMC1_OV 0x80000000 // Overflow 122 #define PMC1_COUNTER 0x7FFFFFFF // Counter value 123 #define PMC2_OV 0x80000000 // Overflow 124 #define PMC2_COUNTER 0x7FFFFFFF // Counter value 125 #define PMC3_OV 0x80000000 // Overflow 126 #define PMC3_COUNTER 0x7FFFFFFF // Counter value 127 #define PMC4_OV 0x80000000 // Overflow 128 #define PMC4_COUNTER 0x7FFFFFFF // Counter value 129 130 /*---------------------------------------------------------------------------* 131 PMC1 Events 132 *---------------------------------------------------------------------------*/ 133 #define MMCR0_PMC1_HOLD 0x00000000 // Register holds current value 134 #define MMCR0_PMC1_CYCLE 0x00000040 // Processor cycles 135 #define MMCR0_PMC1_INSTRUCTION 0x00000080 // # of instructions completed. 136 #define MMCR0_PMC1_TRANSITION 0x000000C0 // # of transitions for 0 to 1 137 #define MMCR0_PMC1_DISPATCHED 0x00000100 // # of instructions dispatched 138 #define MMCR0_PMC1_EIEIO 0x00000140 // # of eieio instructions completed 139 #define MMCR0_PMC1_ITLB_CYCLE 0x00000180 // # of cycles spent performing table search op. for the ITLB 140 #define MMCR0_PMC1_L2_HIT 0x000001C0 // # of access that hit the L2. 141 #define MMCR0_PMC1_EA 0x00000200 // # of valid instruction EAs delivered to the memory subsystem 142 #define MMCR0_PMC1_IABR 0x00000240 // # of time the address of an instruction matches the IABR 143 #define MMCR0_PMC1_L1_MISS 0x00000280 // # of loads that miss the L1 144 #define MMCR0_PMC1_Bx_UNRESOLVED 0x000002C0 // # of branches that are unresolved when processed 145 #define MMCR0_PMC1_Bx_STALL_CYCLE 0x00000300 // # of cycles that dispatcher stalls due to a second 146 #define MMCR0_PMC1_CIU_LOAD 0x00000500 // # load requests to CIU 147 #define MMCR0_PMC1_BIU_ADDR_ONLY 0x00000540 // # address only requests it BIU 148 #define MMCR0_PMC1_60X_DBEAT 0x000005C0 // # of data beats on bus 149 150 /*---------------------------------------------------------------------------* 151 PMC2 Events 152 *---------------------------------------------------------------------------*/ 153 #define MMCR0_PMC2_HOLD 0x00000000 // Register holds current value 154 #define MMCR0_PMC2_CYCLE 0x00000001 // Processor cycles 155 #define MMCR0_PMC2_INSTRUCTION 0x00000002 // # of instructions completed 156 #define MMCR0_PMC2_TRANSITION 0x00000003 // # of time-base (lower) bit transitions 157 #define MMCR0_PMC2_DISPATCHED 0x00000004 // # of instructions dispatched 158 #define MMCR0_PMC2_IC_MISS 0x00000005 // # of L1 instruction cache misses 159 #define MMCR0_PMC2_ITLB_MISS 0x00000006 // # of ITLB misses 160 #define MMCR0_PMC2_L2_I_MISS 0x00000007 // # of L2 instruction misses 161 #define MMCR0_PMC2_Bx_FALL_TROUGH 0x00000008 // # of fall-through branches 162 #define MMCR0_PMC2_RESERVED_LOAD 0x0000000A // # of reserved loads completed 163 #define MMCR0_PMC2_LOAD_STORE 0x0000000B // # of completed loads and stores 164 #define MMCR0_PMC2_SNOOP 0x0000000C // # of snoops 165 #define MMCR0_PMC2_L1_CASTOUT 0x0000000D // # of L1 castouts to L2 166 #define MMCR0_PMC2_SYSTEM 0x0000000E // # of completed system unit instructions 167 #define MMCR0_PMC2_IC_FETCH_MISS 0x0000000F // # of instruction fetch misses in the L1 168 #define MMCR0_PMC2_Bx_OUT_OF_ORDER 0x00000010 // # of branches allowing out-of-order execution 169 #define MMCR0_PMC2_CIU_STORE 0x00000014 // # store requests to CIU 170 171 /*---------------------------------------------------------------------------* 172 PMC3 Events 173 *---------------------------------------------------------------------------*/ 174 #define MMCR1_PMC3_HOLD 0x00000000 // Register holds current value 175 #define MMCR1_PMC3_CYCLE 0x08000000 // Processor cycles 176 #define MMCR1_PMC3_INSTRUCTION 0x10000000 // # of instructions completed 177 #define MMCR1_PMC3_TRANSITION 0x18000000 // # of time-base (lower) bit transitions 178 #define MMCR1_PMC3_DISPATCHED 0x20000000 // # of instructions dispatched 179 #define MMCR1_PMC3_DC_MISS 0x28000000 // # of L1 data cache misses 180 #define MMCR1_PMC3_DTLB_MISS 0x30000000 // # of DTLB misses 181 #define MMCR1_PMC3_L2_D_MISS 0x38000000 // # of L2 data misses 182 #define MMCR1_PMC3_Bx_TAKEN 0x40000000 // # predicted branches that were taken 183 #define MMCR1_PMC3_COND_STORE 0x50000000 // # of store conditional instructions completed 184 #define MMCR1_PMC3_FPU 0x58000000 // # of instructions completed from the FPU 185 #define MMCR1_PMC3_L2_SNOOP_CASTOUT 0x60000000 // # of L2 castout caused by snoops to modified lines 186 #define MMCR1_PMC3_L2_HIT 0x68000000 // # of cache operations that hit in the L2 cache 187 #define MMCR1_PMC3_L1_MISS_CYCLE 0x78000000 // # of cycles generated by L1 load misses 188 #define MMCR1_PMC3_Bx_SECOND 0x80000000 // # of branches in the second speculative branch resolved correctly 189 #define MMCR1_PMC3_BPU_LR_CR 0x88000000 // # of cycles the BPU stalls due to LR or CR unresolved dependencies 190 #define MMCR1_PMC3_CIU_ADDR_ONLY 0xa0000000 // # address-only requests to CIU 191 #define MMCR1_PMC3_BIU_LOAD 0xa8000000 // # loads requests to BIU 192 193 /*---------------------------------------------------------------------------* 194 PMC4 Events 195 *---------------------------------------------------------------------------*/ 196 #define MMCR1_PMC4_HOLD 0x00000000 // Register holds current value 197 #define MMCR1_PMC4_CYCLE 0x00400000 // Processor cycles 198 #define MMCR1_PMC4_INSTRUCTION 0x00800000 // # of instructions completed 199 #define MMCR1_PMC4_TRANSITION 0x00C00000 // # of time-base (lower) bit transitions 200 #define MMCR1_PMC4_DISPATCHED 0x01000000 // # of instructions dispatched 201 #define MMCR1_PMC4_L2_CASTOUT 0x01400000 // # of L2 castouts 202 #define MMCR1_PMC4_DTLB_CYCLE 0x01800000 // # of cycles spent performing table searches for DTLB accesses 203 #define MMCR1_PMC4_Bx_MISSED 0x02000000 // # of mispredicted branches 204 #define MMCR1_PMC4_COND_STORE_INT 0x02800000 // # of store conditional instructions completed 205 // with reservation intact 206 #define MMCR1_PMC4_SYNC 0x02C00000 // # of completed sync instructions 207 #define MMCR1_PMC4_SNOOP_RETRY 0x03000000 // # of snoop request retries 208 #define MMCR1_PMC4_INTEGER 0x03400000 // # of completed integer operations 209 #define MMCR1_PMC4_BPU_THIRD 0x03800000 // # of cycles the BPU cannot process new branches 210 #define MMCR1_PMC4_L2_INTERV 0x04000000 // L2 interventions 211 #define MMCR1_PMC4_TLB_SNOOP 0x04400000 // tlbie snoops 212 #define MMCR1_PMC4_BIU_STORE 0x05400000 // BIU stores 213 // due to having two unresolved branches 214 215 #define UMMCR0 936 // monitor control 216 #define UMMCR1 940 217 218 #define UTBU 269 // time base upper 219 #define UTBL 268 // lower 220 221 #define UGQR0 896 // quantization registers 222 #define UGQR1 897 223 #define UGQR2 898 224 #define UGQR3 899 225 #define UGQR4 900 226 #define UGQR5 901 227 #define UGQR6 902 228 #define UGQR7 903 229 #define GQR_LOAD_SCALE_MASK 0x3F000000 // load scale field 230 #define GQR_LOAD_TYPE_MASK 0x00070000 // load type field 231 #define GQR_STORE_SCALE_MASK 0x00003F00 // store scale field 232 #define GQR_STORE_TYPE_MASK 0x00000007 // store type field 233 234 #define UHID2 904 // user HID2 235 236 #define UWPAR 905 // write gather pipe 237 238 #define UDMAU 906 // user mode DMA registers 239 #define UDMAL 907 240 241 #endif // _PPC_ASM_USER_H_INCLUDED_ 242