1 /*---------------------------------------------------------------------------* 2 Project: TwlSDK - IO Register List - 3 File: twl/hw/ARM9/ioreg_OS.h 4 5 Copyright 2007-2008 Nintendo. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 *---------------------------------------------------------------------------*/ 14 // 15 // I was generated automatically, don't edit me directly!!! 16 // 17 #ifndef TWL_HW_ARM9_IOREG_OS_H_ 18 #define TWL_HW_ARM9_IOREG_OS_H_ 19 20 #ifndef SDK_ASM 21 #include <nitro/types.h> 22 #include <twl/hw/ARM9/mmap_global.h> 23 #endif 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* 30 * Definition of Register offsets, addresses and variables. 31 */ 32 33 34 /* TM0CNT_L */ 35 36 #define REG_TM0CNT_L_OFFSET 0x100 37 #define REG_TM0CNT_L_ADDR (HW_REG_BASE + REG_TM0CNT_L_OFFSET) 38 #define reg_OS_TM0CNT_L (*( REGType16v *) REG_TM0CNT_L_ADDR) 39 40 /* TM0CNT_H */ 41 42 #define REG_TM0CNT_H_OFFSET 0x102 43 #define REG_TM0CNT_H_ADDR (HW_REG_BASE + REG_TM0CNT_H_OFFSET) 44 #define reg_OS_TM0CNT_H (*( REGType16v *) REG_TM0CNT_H_ADDR) 45 46 /* TM1CNT_L */ 47 48 #define REG_TM1CNT_L_OFFSET 0x104 49 #define REG_TM1CNT_L_ADDR (HW_REG_BASE + REG_TM1CNT_L_OFFSET) 50 #define reg_OS_TM1CNT_L (*( REGType16v *) REG_TM1CNT_L_ADDR) 51 52 /* TM1CNT_H */ 53 54 #define REG_TM1CNT_H_OFFSET 0x106 55 #define REG_TM1CNT_H_ADDR (HW_REG_BASE + REG_TM1CNT_H_OFFSET) 56 #define reg_OS_TM1CNT_H (*( REGType16v *) REG_TM1CNT_H_ADDR) 57 58 /* TM2CNT_L */ 59 60 #define REG_TM2CNT_L_OFFSET 0x108 61 #define REG_TM2CNT_L_ADDR (HW_REG_BASE + REG_TM2CNT_L_OFFSET) 62 #define reg_OS_TM2CNT_L (*( REGType16v *) REG_TM2CNT_L_ADDR) 63 64 /* TM2CNT_H */ 65 66 #define REG_TM2CNT_H_OFFSET 0x10a 67 #define REG_TM2CNT_H_ADDR (HW_REG_BASE + REG_TM2CNT_H_OFFSET) 68 #define reg_OS_TM2CNT_H (*( REGType16v *) REG_TM2CNT_H_ADDR) 69 70 /* TM3CNT_L */ 71 72 #define REG_TM3CNT_L_OFFSET 0x10c 73 #define REG_TM3CNT_L_ADDR (HW_REG_BASE + REG_TM3CNT_L_OFFSET) 74 #define reg_OS_TM3CNT_L (*( REGType16v *) REG_TM3CNT_L_ADDR) 75 76 /* TM3CNT_H */ 77 78 #define REG_TM3CNT_H_OFFSET 0x10e 79 #define REG_TM3CNT_H_ADDR (HW_REG_BASE + REG_TM3CNT_H_OFFSET) 80 #define reg_OS_TM3CNT_H (*( REGType16v *) REG_TM3CNT_H_ADDR) 81 82 /* IME */ 83 84 #define REG_IME_OFFSET 0x208 85 #define REG_IME_ADDR (HW_REG_BASE + REG_IME_OFFSET) 86 #define reg_OS_IME (*( REGType16v *) REG_IME_ADDR) 87 88 /* IE */ 89 90 #define REG_IE_OFFSET 0x210 91 #define REG_IE_ADDR (HW_REG_BASE + REG_IE_OFFSET) 92 #define reg_OS_IE (*( REGType32v *) REG_IE_ADDR) 93 94 /* IF */ 95 96 #define REG_IF_OFFSET 0x214 97 #define REG_IF_ADDR (HW_REG_BASE + REG_IF_OFFSET) 98 #define reg_OS_IF (*( REGType32v *) REG_IF_ADDR) 99 100 /* PAUSE */ 101 102 #define REG_PAUSE_OFFSET 0x300 103 #define REG_PAUSE_ADDR (HW_REG_BASE + REG_PAUSE_OFFSET) 104 #define reg_OS_PAUSE (*( REGType16v *) REG_PAUSE_ADDR) 105 106 107 /* 108 * Definitions of Register fields 109 */ 110 111 112 /* TM0CNT_L */ 113 114 #define REG_OS_TM0CNT_L_TIMER0CNT_SHIFT 0 115 #define REG_OS_TM0CNT_L_TIMER0CNT_SIZE 16 116 #define REG_OS_TM0CNT_L_TIMER0CNT_MASK 0xffff 117 118 #ifndef SDK_ASM 119 #define REG_OS_TM0CNT_L_FIELD( timer0cnt ) \ 120 (u16)( \ 121 ((u32)(timer0cnt) << REG_OS_TM0CNT_L_TIMER0CNT_SHIFT)) 122 #endif 123 124 125 /* TM0CNT_H */ 126 127 #define REG_OS_TM0CNT_H_E_SHIFT 7 128 #define REG_OS_TM0CNT_H_E_SIZE 1 129 #define REG_OS_TM0CNT_H_E_MASK 0x0080 130 131 #define REG_OS_TM0CNT_H_I_SHIFT 6 132 #define REG_OS_TM0CNT_H_I_SIZE 1 133 #define REG_OS_TM0CNT_H_I_MASK 0x0040 134 135 #define REG_OS_TM0CNT_H_PS_SHIFT 0 136 #define REG_OS_TM0CNT_H_PS_SIZE 2 137 #define REG_OS_TM0CNT_H_PS_MASK 0x0003 138 139 #ifndef SDK_ASM 140 #define REG_OS_TM0CNT_H_FIELD( e, i, ps ) \ 141 (u16)( \ 142 ((u32)(e) << REG_OS_TM0CNT_H_E_SHIFT) | \ 143 ((u32)(i) << REG_OS_TM0CNT_H_I_SHIFT) | \ 144 ((u32)(ps) << REG_OS_TM0CNT_H_PS_SHIFT)) 145 #endif 146 147 148 /* TM1CNT_L */ 149 150 #define REG_OS_TM1CNT_L_TIMER1CNT_SHIFT 0 151 #define REG_OS_TM1CNT_L_TIMER1CNT_SIZE 16 152 #define REG_OS_TM1CNT_L_TIMER1CNT_MASK 0xffff 153 154 #ifndef SDK_ASM 155 #define REG_OS_TM1CNT_L_FIELD( timer1cnt ) \ 156 (u16)( \ 157 ((u32)(timer1cnt) << REG_OS_TM1CNT_L_TIMER1CNT_SHIFT)) 158 #endif 159 160 161 /* TM1CNT_H */ 162 163 #define REG_OS_TM1CNT_H_E_SHIFT 7 164 #define REG_OS_TM1CNT_H_E_SIZE 1 165 #define REG_OS_TM1CNT_H_E_MASK 0x0080 166 167 #define REG_OS_TM1CNT_H_I_SHIFT 6 168 #define REG_OS_TM1CNT_H_I_SIZE 1 169 #define REG_OS_TM1CNT_H_I_MASK 0x0040 170 171 #define REG_OS_TM1CNT_H_CH_SHIFT 2 172 #define REG_OS_TM1CNT_H_CH_SIZE 1 173 #define REG_OS_TM1CNT_H_CH_MASK 0x0004 174 175 #define REG_OS_TM1CNT_H_PS_SHIFT 0 176 #define REG_OS_TM1CNT_H_PS_SIZE 2 177 #define REG_OS_TM1CNT_H_PS_MASK 0x0003 178 179 #ifndef SDK_ASM 180 #define REG_OS_TM1CNT_H_FIELD( e, i, ch, ps ) \ 181 (u16)( \ 182 ((u32)(e) << REG_OS_TM1CNT_H_E_SHIFT) | \ 183 ((u32)(i) << REG_OS_TM1CNT_H_I_SHIFT) | \ 184 ((u32)(ch) << REG_OS_TM1CNT_H_CH_SHIFT) | \ 185 ((u32)(ps) << REG_OS_TM1CNT_H_PS_SHIFT)) 186 #endif 187 188 189 /* TM2CNT_L */ 190 191 #define REG_OS_TM2CNT_L_TIMER2CNT_SHIFT 0 192 #define REG_OS_TM2CNT_L_TIMER2CNT_SIZE 16 193 #define REG_OS_TM2CNT_L_TIMER2CNT_MASK 0xffff 194 195 #ifndef SDK_ASM 196 #define REG_OS_TM2CNT_L_FIELD( timer2cnt ) \ 197 (u16)( \ 198 ((u32)(timer2cnt) << REG_OS_TM2CNT_L_TIMER2CNT_SHIFT)) 199 #endif 200 201 202 /* TM2CNT_H */ 203 204 #define REG_OS_TM2CNT_H_E_SHIFT 7 205 #define REG_OS_TM2CNT_H_E_SIZE 1 206 #define REG_OS_TM2CNT_H_E_MASK 0x0080 207 208 #define REG_OS_TM2CNT_H_I_SHIFT 6 209 #define REG_OS_TM2CNT_H_I_SIZE 1 210 #define REG_OS_TM2CNT_H_I_MASK 0x0040 211 212 #define REG_OS_TM2CNT_H_CH_SHIFT 2 213 #define REG_OS_TM2CNT_H_CH_SIZE 1 214 #define REG_OS_TM2CNT_H_CH_MASK 0x0004 215 216 #define REG_OS_TM2CNT_H_PS_SHIFT 0 217 #define REG_OS_TM2CNT_H_PS_SIZE 2 218 #define REG_OS_TM2CNT_H_PS_MASK 0x0003 219 220 #ifndef SDK_ASM 221 #define REG_OS_TM2CNT_H_FIELD( e, i, ch, ps ) \ 222 (u16)( \ 223 ((u32)(e) << REG_OS_TM2CNT_H_E_SHIFT) | \ 224 ((u32)(i) << REG_OS_TM2CNT_H_I_SHIFT) | \ 225 ((u32)(ch) << REG_OS_TM2CNT_H_CH_SHIFT) | \ 226 ((u32)(ps) << REG_OS_TM2CNT_H_PS_SHIFT)) 227 #endif 228 229 230 /* TM3CNT_L */ 231 232 #define REG_OS_TM3CNT_L_TIMER2CNT_SHIFT 0 233 #define REG_OS_TM3CNT_L_TIMER2CNT_SIZE 16 234 #define REG_OS_TM3CNT_L_TIMER2CNT_MASK 0xffff 235 236 #ifndef SDK_ASM 237 #define REG_OS_TM3CNT_L_FIELD( timer2cnt ) \ 238 (u16)( \ 239 ((u32)(timer2cnt) << REG_OS_TM3CNT_L_TIMER2CNT_SHIFT)) 240 #endif 241 242 243 /* TM3CNT_H */ 244 245 #define REG_OS_TM3CNT_H_E_SHIFT 7 246 #define REG_OS_TM3CNT_H_E_SIZE 1 247 #define REG_OS_TM3CNT_H_E_MASK 0x0080 248 249 #define REG_OS_TM3CNT_H_I_SHIFT 6 250 #define REG_OS_TM3CNT_H_I_SIZE 1 251 #define REG_OS_TM3CNT_H_I_MASK 0x0040 252 253 #define REG_OS_TM3CNT_H_CH_SHIFT 2 254 #define REG_OS_TM3CNT_H_CH_SIZE 1 255 #define REG_OS_TM3CNT_H_CH_MASK 0x0004 256 257 #define REG_OS_TM3CNT_H_PS_SHIFT 0 258 #define REG_OS_TM3CNT_H_PS_SIZE 2 259 #define REG_OS_TM3CNT_H_PS_MASK 0x0003 260 261 #ifndef SDK_ASM 262 #define REG_OS_TM3CNT_H_FIELD( e, i, ch, ps ) \ 263 (u16)( \ 264 ((u32)(e) << REG_OS_TM3CNT_H_E_SHIFT) | \ 265 ((u32)(i) << REG_OS_TM3CNT_H_I_SHIFT) | \ 266 ((u32)(ch) << REG_OS_TM3CNT_H_CH_SHIFT) | \ 267 ((u32)(ps) << REG_OS_TM3CNT_H_PS_SHIFT)) 268 #endif 269 270 271 /* IME */ 272 273 #define REG_OS_IME_IME_SHIFT 0 274 #define REG_OS_IME_IME_SIZE 1 275 #define REG_OS_IME_IME_MASK 0x0001 276 277 #ifndef SDK_ASM 278 #define REG_OS_IME_FIELD( ime ) \ 279 (u16)( \ 280 ((u32)(ime) << REG_OS_IME_IME_SHIFT)) 281 #endif 282 283 284 /* IE */ 285 286 #define REG_OS_IE_ND3_SHIFT 31 287 #define REG_OS_IE_ND3_SIZE 1 288 #define REG_OS_IE_ND3_MASK 0x80000000 289 290 #define REG_OS_IE_ND2_SHIFT 30 291 #define REG_OS_IE_ND2_SIZE 1 292 #define REG_OS_IE_ND2_MASK 0x40000000 293 294 #define REG_OS_IE_ND1_SHIFT 29 295 #define REG_OS_IE_ND1_SIZE 1 296 #define REG_OS_IE_ND1_MASK 0x20000000 297 298 #define REG_OS_IE_ND0_SHIFT 28 299 #define REG_OS_IE_ND0_SIZE 1 300 #define REG_OS_IE_ND0_MASK 0x10000000 301 302 #define REG_OS_IE_MIB_SHIFT 27 303 #define REG_OS_IE_MIB_SIZE 1 304 #define REG_OS_IE_MIB_MASK 0x08000000 305 306 #define REG_OS_IE_MCB_SHIFT 26 307 #define REG_OS_IE_MCB_SIZE 1 308 #define REG_OS_IE_MCB_MASK 0x04000000 309 310 #define REG_OS_IE_CAM_SHIFT 25 311 #define REG_OS_IE_CAM_SIZE 1 312 #define REG_OS_IE_CAM_MASK 0x02000000 313 314 #define REG_OS_IE_DSP_SHIFT 24 315 #define REG_OS_IE_DSP_SIZE 1 316 #define REG_OS_IE_DSP_MASK 0x01000000 317 318 #define REG_OS_IE_DWE_SHIFT 23 319 #define REG_OS_IE_DWE_SIZE 1 320 #define REG_OS_IE_DWE_MASK 0x00800000 321 322 #define REG_OS_IE_DRE_SHIFT 22 323 #define REG_OS_IE_DRE_SIZE 1 324 #define REG_OS_IE_DRE_MASK 0x00400000 325 326 #define REG_OS_IE_GF_SHIFT 21 327 #define REG_OS_IE_GF_SIZE 1 328 #define REG_OS_IE_GF_MASK 0x00200000 329 330 #define REG_OS_IE_MIA_SHIFT 20 331 #define REG_OS_IE_MIA_SIZE 1 332 #define REG_OS_IE_MIA_MASK 0x00100000 333 334 #define REG_OS_IE_MI_SHIFT 20 335 #define REG_OS_IE_MI_SIZE 1 336 #define REG_OS_IE_MI_MASK 0x00100000 337 338 #define REG_OS_IE_MCA_SHIFT 19 339 #define REG_OS_IE_MCA_SIZE 1 340 #define REG_OS_IE_MCA_MASK 0x00080000 341 342 #define REG_OS_IE_MC_SHIFT 19 343 #define REG_OS_IE_MC_SIZE 1 344 #define REG_OS_IE_MC_MASK 0x00080000 345 346 #define REG_OS_IE_IFN_SHIFT 18 347 #define REG_OS_IE_IFN_SIZE 1 348 #define REG_OS_IE_IFN_MASK 0x00040000 349 350 #define REG_OS_IE_IFE_SHIFT 17 351 #define REG_OS_IE_IFE_SIZE 1 352 #define REG_OS_IE_IFE_MASK 0x00020000 353 354 #define REG_OS_IE_A7_SHIFT 16 355 #define REG_OS_IE_A7_SIZE 1 356 #define REG_OS_IE_A7_MASK 0x00010000 357 358 #define REG_OS_IE_MCBDET_SHIFT 15 359 #define REG_OS_IE_MCBDET_SIZE 1 360 #define REG_OS_IE_MCBDET_MASK 0x00008000 361 362 #define REG_OS_IE_MCADET_SHIFT 14 363 #define REG_OS_IE_MCADET_SIZE 1 364 #define REG_OS_IE_MCADET_MASK 0x00004000 365 366 #define REG_OS_IE_I_D_SHIFT 13 367 #define REG_OS_IE_I_D_SIZE 1 368 #define REG_OS_IE_I_D_MASK 0x00002000 369 370 #define REG_OS_IE_K_SHIFT 12 371 #define REG_OS_IE_K_SIZE 1 372 #define REG_OS_IE_K_MASK 0x00001000 373 374 #define REG_OS_IE_D3_SHIFT 11 375 #define REG_OS_IE_D3_SIZE 1 376 #define REG_OS_IE_D3_MASK 0x00000800 377 378 #define REG_OS_IE_D2_SHIFT 10 379 #define REG_OS_IE_D2_SIZE 1 380 #define REG_OS_IE_D2_MASK 0x00000400 381 382 #define REG_OS_IE_D1_SHIFT 9 383 #define REG_OS_IE_D1_SIZE 1 384 #define REG_OS_IE_D1_MASK 0x00000200 385 386 #define REG_OS_IE_D0_SHIFT 8 387 #define REG_OS_IE_D0_SIZE 1 388 #define REG_OS_IE_D0_MASK 0x00000100 389 390 #define REG_OS_IE_T3_SHIFT 6 391 #define REG_OS_IE_T3_SIZE 1 392 #define REG_OS_IE_T3_MASK 0x00000040 393 394 #define REG_OS_IE_T2_SHIFT 5 395 #define REG_OS_IE_T2_SIZE 1 396 #define REG_OS_IE_T2_MASK 0x00000020 397 398 #define REG_OS_IE_T1_SHIFT 4 399 #define REG_OS_IE_T1_SIZE 1 400 #define REG_OS_IE_T1_MASK 0x00000010 401 402 #define REG_OS_IE_T0_SHIFT 3 403 #define REG_OS_IE_T0_SIZE 1 404 #define REG_OS_IE_T0_MASK 0x00000008 405 406 #define REG_OS_IE_VE_SHIFT 2 407 #define REG_OS_IE_VE_SIZE 1 408 #define REG_OS_IE_VE_MASK 0x00000004 409 410 #define REG_OS_IE_HB_SHIFT 1 411 #define REG_OS_IE_HB_SIZE 1 412 #define REG_OS_IE_HB_MASK 0x00000002 413 414 #define REG_OS_IE_VB_SHIFT 0 415 #define REG_OS_IE_VB_SIZE 1 416 #define REG_OS_IE_VB_MASK 0x00000001 417 418 #ifndef SDK_ASM 419 #define REG_OS_IE_FIELD( nd3, nd2, nd1, nd0, mib, mcb, cam, dsp, dwe, dre, gf, mia, mi, mca, mc, ifn, ife, a7, mcbdet, mcadet, i_d, k, d3, d2, d1, d0, t3, t2, t1, t0, ve, hb, vb ) \ 420 (u32)( \ 421 ((u32)(nd3) << REG_OS_IE_ND3_SHIFT) | \ 422 ((u32)(nd2) << REG_OS_IE_ND2_SHIFT) | \ 423 ((u32)(nd1) << REG_OS_IE_ND1_SHIFT) | \ 424 ((u32)(nd0) << REG_OS_IE_ND0_SHIFT) | \ 425 ((u32)(mib) << REG_OS_IE_MIB_SHIFT) | \ 426 ((u32)(mcb) << REG_OS_IE_MCB_SHIFT) | \ 427 ((u32)(cam) << REG_OS_IE_CAM_SHIFT) | \ 428 ((u32)(dsp) << REG_OS_IE_DSP_SHIFT) | \ 429 ((u32)(dwe) << REG_OS_IE_DWE_SHIFT) | \ 430 ((u32)(dre) << REG_OS_IE_DRE_SHIFT) | \ 431 ((u32)(gf) << REG_OS_IE_GF_SHIFT) | \ 432 ((u32)(mia) << REG_OS_IE_MIA_SHIFT) | \ 433 ((u32)(mi) << REG_OS_IE_MI_SHIFT) | \ 434 ((u32)(mca) << REG_OS_IE_MCA_SHIFT) | \ 435 ((u32)(mc) << REG_OS_IE_MC_SHIFT) | \ 436 ((u32)(ifn) << REG_OS_IE_IFN_SHIFT) | \ 437 ((u32)(ife) << REG_OS_IE_IFE_SHIFT) | \ 438 ((u32)(a7) << REG_OS_IE_A7_SHIFT) | \ 439 ((u32)(mcbdet) << REG_OS_IE_MCBDET_SHIFT) | \ 440 ((u32)(mcadet) << REG_OS_IE_MCADET_SHIFT) | \ 441 ((u32)(i_d) << REG_OS_IE_I_D_SHIFT) | \ 442 ((u32)(k) << REG_OS_IE_K_SHIFT) | \ 443 ((u32)(d3) << REG_OS_IE_D3_SHIFT) | \ 444 ((u32)(d2) << REG_OS_IE_D2_SHIFT) | \ 445 ((u32)(d1) << REG_OS_IE_D1_SHIFT) | \ 446 ((u32)(d0) << REG_OS_IE_D0_SHIFT) | \ 447 ((u32)(t3) << REG_OS_IE_T3_SHIFT) | \ 448 ((u32)(t2) << REG_OS_IE_T2_SHIFT) | \ 449 ((u32)(t1) << REG_OS_IE_T1_SHIFT) | \ 450 ((u32)(t0) << REG_OS_IE_T0_SHIFT) | \ 451 ((u32)(ve) << REG_OS_IE_VE_SHIFT) | \ 452 ((u32)(hb) << REG_OS_IE_HB_SHIFT) | \ 453 ((u32)(vb) << REG_OS_IE_VB_SHIFT)) 454 #endif 455 456 457 /* IF */ 458 459 #define REG_OS_IF_ND3_SHIFT 31 460 #define REG_OS_IF_ND3_SIZE 1 461 #define REG_OS_IF_ND3_MASK 0x80000000 462 463 #define REG_OS_IF_ND2_SHIFT 30 464 #define REG_OS_IF_ND2_SIZE 1 465 #define REG_OS_IF_ND2_MASK 0x40000000 466 467 #define REG_OS_IF_ND1_SHIFT 29 468 #define REG_OS_IF_ND1_SIZE 1 469 #define REG_OS_IF_ND1_MASK 0x20000000 470 471 #define REG_OS_IF_ND0_SHIFT 28 472 #define REG_OS_IF_ND0_SIZE 1 473 #define REG_OS_IF_ND0_MASK 0x10000000 474 475 #define REG_OS_IF_MIB_SHIFT 27 476 #define REG_OS_IF_MIB_SIZE 1 477 #define REG_OS_IF_MIB_MASK 0x08000000 478 479 #define REG_OS_IF_MCB_SHIFT 26 480 #define REG_OS_IF_MCB_SIZE 1 481 #define REG_OS_IF_MCB_MASK 0x04000000 482 483 #define REG_OS_IF_CAM_SHIFT 25 484 #define REG_OS_IF_CAM_SIZE 1 485 #define REG_OS_IF_CAM_MASK 0x02000000 486 487 #define REG_OS_IF_DSP_SHIFT 24 488 #define REG_OS_IF_DSP_SIZE 1 489 #define REG_OS_IF_DSP_MASK 0x01000000 490 491 #define REG_OS_IF_DWE_SHIFT 23 492 #define REG_OS_IF_DWE_SIZE 1 493 #define REG_OS_IF_DWE_MASK 0x00800000 494 495 #define REG_OS_IF_DRE_SHIFT 22 496 #define REG_OS_IF_DRE_SIZE 1 497 #define REG_OS_IF_DRE_MASK 0x00400000 498 499 #define REG_OS_IF_GF_SHIFT 21 500 #define REG_OS_IF_GF_SIZE 1 501 #define REG_OS_IF_GF_MASK 0x00200000 502 503 #define REG_OS_IF_MIA_SHIFT 20 504 #define REG_OS_IF_MIA_SIZE 1 505 #define REG_OS_IF_MIA_MASK 0x00100000 506 507 #define REG_OS_IF_MI_SHIFT 20 508 #define REG_OS_IF_MI_SIZE 1 509 #define REG_OS_IF_MI_MASK 0x00100000 510 511 #define REG_OS_IF_MCA_SHIFT 19 512 #define REG_OS_IF_MCA_SIZE 1 513 #define REG_OS_IF_MCA_MASK 0x00080000 514 515 #define REG_OS_IF_MC_SHIFT 19 516 #define REG_OS_IF_MC_SIZE 1 517 #define REG_OS_IF_MC_MASK 0x00080000 518 519 #define REG_OS_IF_IFN_SHIFT 18 520 #define REG_OS_IF_IFN_SIZE 1 521 #define REG_OS_IF_IFN_MASK 0x00040000 522 523 #define REG_OS_IF_IFE_SHIFT 17 524 #define REG_OS_IF_IFE_SIZE 1 525 #define REG_OS_IF_IFE_MASK 0x00020000 526 527 #define REG_OS_IF_A7_SHIFT 16 528 #define REG_OS_IF_A7_SIZE 1 529 #define REG_OS_IF_A7_MASK 0x00010000 530 531 #define REG_OS_IF_MCBDET_SHIFT 15 532 #define REG_OS_IF_MCBDET_SIZE 1 533 #define REG_OS_IF_MCBDET_MASK 0x00008000 534 535 #define REG_OS_IF_MCADET_SHIFT 14 536 #define REG_OS_IF_MCADET_SIZE 1 537 #define REG_OS_IF_MCADET_MASK 0x00004000 538 539 #define REG_OS_IF_I_D_SHIFT 13 540 #define REG_OS_IF_I_D_SIZE 1 541 #define REG_OS_IF_I_D_MASK 0x00002000 542 543 #define REG_OS_IF_K_SHIFT 12 544 #define REG_OS_IF_K_SIZE 1 545 #define REG_OS_IF_K_MASK 0x00001000 546 547 #define REG_OS_IF_D3_SHIFT 11 548 #define REG_OS_IF_D3_SIZE 1 549 #define REG_OS_IF_D3_MASK 0x00000800 550 551 #define REG_OS_IF_D2_SHIFT 10 552 #define REG_OS_IF_D2_SIZE 1 553 #define REG_OS_IF_D2_MASK 0x00000400 554 555 #define REG_OS_IF_D1_SHIFT 9 556 #define REG_OS_IF_D1_SIZE 1 557 #define REG_OS_IF_D1_MASK 0x00000200 558 559 #define REG_OS_IF_D0_SHIFT 8 560 #define REG_OS_IF_D0_SIZE 1 561 #define REG_OS_IF_D0_MASK 0x00000100 562 563 #define REG_OS_IF_T3_SHIFT 6 564 #define REG_OS_IF_T3_SIZE 1 565 #define REG_OS_IF_T3_MASK 0x00000040 566 567 #define REG_OS_IF_T2_SHIFT 5 568 #define REG_OS_IF_T2_SIZE 1 569 #define REG_OS_IF_T2_MASK 0x00000020 570 571 #define REG_OS_IF_T1_SHIFT 4 572 #define REG_OS_IF_T1_SIZE 1 573 #define REG_OS_IF_T1_MASK 0x00000010 574 575 #define REG_OS_IF_T0_SHIFT 3 576 #define REG_OS_IF_T0_SIZE 1 577 #define REG_OS_IF_T0_MASK 0x00000008 578 579 #define REG_OS_IF_VE_SHIFT 2 580 #define REG_OS_IF_VE_SIZE 1 581 #define REG_OS_IF_VE_MASK 0x00000004 582 583 #define REG_OS_IF_HB_SHIFT 1 584 #define REG_OS_IF_HB_SIZE 1 585 #define REG_OS_IF_HB_MASK 0x00000002 586 587 #define REG_OS_IF_VB_SHIFT 0 588 #define REG_OS_IF_VB_SIZE 1 589 #define REG_OS_IF_VB_MASK 0x00000001 590 591 #ifndef SDK_ASM 592 #define REG_OS_IF_FIELD( nd3, nd2, nd1, nd0, mib, mcb, cam, dsp, dwe, dre, gf, mia, mi, mca, mc, ifn, ife, a7, mcbdet, mcadet, i_d, k, d3, d2, d1, d0, t3, t2, t1, t0, ve, hb, vb ) \ 593 (u32)( \ 594 ((u32)(nd3) << REG_OS_IF_ND3_SHIFT) | \ 595 ((u32)(nd2) << REG_OS_IF_ND2_SHIFT) | \ 596 ((u32)(nd1) << REG_OS_IF_ND1_SHIFT) | \ 597 ((u32)(nd0) << REG_OS_IF_ND0_SHIFT) | \ 598 ((u32)(mib) << REG_OS_IF_MIB_SHIFT) | \ 599 ((u32)(mcb) << REG_OS_IF_MCB_SHIFT) | \ 600 ((u32)(cam) << REG_OS_IF_CAM_SHIFT) | \ 601 ((u32)(dsp) << REG_OS_IF_DSP_SHIFT) | \ 602 ((u32)(dwe) << REG_OS_IF_DWE_SHIFT) | \ 603 ((u32)(dre) << REG_OS_IF_DRE_SHIFT) | \ 604 ((u32)(gf) << REG_OS_IF_GF_SHIFT) | \ 605 ((u32)(mia) << REG_OS_IF_MIA_SHIFT) | \ 606 ((u32)(mi) << REG_OS_IF_MI_SHIFT) | \ 607 ((u32)(mca) << REG_OS_IF_MCA_SHIFT) | \ 608 ((u32)(mc) << REG_OS_IF_MC_SHIFT) | \ 609 ((u32)(ifn) << REG_OS_IF_IFN_SHIFT) | \ 610 ((u32)(ife) << REG_OS_IF_IFE_SHIFT) | \ 611 ((u32)(a7) << REG_OS_IF_A7_SHIFT) | \ 612 ((u32)(mcbdet) << REG_OS_IF_MCBDET_SHIFT) | \ 613 ((u32)(mcadet) << REG_OS_IF_MCADET_SHIFT) | \ 614 ((u32)(i_d) << REG_OS_IF_I_D_SHIFT) | \ 615 ((u32)(k) << REG_OS_IF_K_SHIFT) | \ 616 ((u32)(d3) << REG_OS_IF_D3_SHIFT) | \ 617 ((u32)(d2) << REG_OS_IF_D2_SHIFT) | \ 618 ((u32)(d1) << REG_OS_IF_D1_SHIFT) | \ 619 ((u32)(d0) << REG_OS_IF_D0_SHIFT) | \ 620 ((u32)(t3) << REG_OS_IF_T3_SHIFT) | \ 621 ((u32)(t2) << REG_OS_IF_T2_SHIFT) | \ 622 ((u32)(t1) << REG_OS_IF_T1_SHIFT) | \ 623 ((u32)(t0) << REG_OS_IF_T0_SHIFT) | \ 624 ((u32)(ve) << REG_OS_IF_VE_SHIFT) | \ 625 ((u32)(hb) << REG_OS_IF_HB_SHIFT) | \ 626 ((u32)(vb) << REG_OS_IF_VB_SHIFT)) 627 #endif 628 629 630 /* PAUSE */ 631 632 #define REG_OS_PAUSE_MOD_SHIFT 14 633 #define REG_OS_PAUSE_MOD_SIZE 2 634 #define REG_OS_PAUSE_MOD_MASK 0xc000 635 636 #define REG_OS_PAUSE_JTAG_E_SHIFT 1 637 #define REG_OS_PAUSE_JTAG_E_SIZE 1 638 #define REG_OS_PAUSE_JTAG_E_MASK 0x0002 639 640 #define REG_OS_PAUSE_CHK_SHIFT 0 641 #define REG_OS_PAUSE_CHK_SIZE 1 642 #define REG_OS_PAUSE_CHK_MASK 0x0001 643 644 #ifndef SDK_ASM 645 #define REG_OS_PAUSE_FIELD( mod, jtag_e, chk ) \ 646 (u16)( \ 647 ((u32)(mod) << REG_OS_PAUSE_MOD_SHIFT) | \ 648 ((u32)(jtag_e) << REG_OS_PAUSE_JTAG_E_SHIFT) | \ 649 ((u32)(chk) << REG_OS_PAUSE_CHK_SHIFT)) 650 #endif 651 652 653 #ifdef __cplusplus 654 } /* extern "C" */ 655 #endif 656 657 /* TWL_HW_ARM9_IOREG_OS_H_ */ 658 #endif 659