1 /*---------------------------------------------------------------------------* 2 Project: TwlSDK - IO Register List - 3 File: twl/hw/ARM9/ioreg_CAM.h 4 5 Copyright 2007-2008 Nintendo. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 *---------------------------------------------------------------------------*/ 14 // 15 // I was generated automatically, don't edit me directly!!! 16 // 17 #ifndef TWL_HW_ARM9_IOREG_CAM_H_ 18 #define TWL_HW_ARM9_IOREG_CAM_H_ 19 20 #ifndef SDK_ASM 21 #include <nitro/types.h> 22 #include <twl/hw/ARM9/mmap_global.h> 23 #endif 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* 30 * Definition of Register offsets, addresses and variables. 31 */ 32 33 34 /* MCNT */ 35 36 #define REG_MCNT_OFFSET 0x4200 37 #define REG_MCNT_ADDR (HW_REG_BASE + REG_MCNT_OFFSET) 38 #define reg_CAM_MCNT (*( REGType16v *) REG_MCNT_ADDR) 39 40 /* CNT */ 41 42 #define REG_CNT_OFFSET 0x4202 43 #define REG_CNT_ADDR (HW_REG_BASE + REG_CNT_OFFSET) 44 #define reg_CAM_CNT (*( REGType16v *) REG_CNT_ADDR) 45 46 /* DAT */ 47 48 #define REG_DAT_OFFSET 0x4204 49 #define REG_DAT_ADDR (HW_REG_BASE + REG_DAT_OFFSET) 50 #define reg_CAM_DAT (*(const REGType32v *) REG_DAT_ADDR) 51 52 /* SOFS */ 53 54 #define REG_SOFS_OFFSET 0x4210 55 #define REG_SOFS_ADDR (HW_REG_BASE + REG_SOFS_OFFSET) 56 #define reg_CAM_SOFS (*( REGType32v *) REG_SOFS_ADDR) 57 58 /* EOFS */ 59 60 #define REG_EOFS_OFFSET 0x4214 61 #define REG_EOFS_ADDR (HW_REG_BASE + REG_EOFS_OFFSET) 62 #define reg_CAM_EOFS (*( REGType32v *) REG_EOFS_ADDR) 63 64 65 /* 66 * Definitions of Register fields 67 */ 68 69 70 /* MCNT */ 71 72 #define REG_CAM_MCNT_INI_SHIFT 7 73 #define REG_CAM_MCNT_INI_SIZE 1 74 #define REG_CAM_MCNT_INI_MASK 0x0080 75 76 #define REG_CAM_MCNT_V28_SHIFT 6 77 #define REG_CAM_MCNT_V28_SIZE 1 78 #define REG_CAM_MCNT_V28_MASK 0x0040 79 80 #define REG_CAM_MCNT_VIO_SHIFT 5 81 #define REG_CAM_MCNT_VIO_SIZE 1 82 #define REG_CAM_MCNT_VIO_MASK 0x0020 83 84 #define REG_CAM_MCNT_V18_SHIFT 4 85 #define REG_CAM_MCNT_V18_SIZE 1 86 #define REG_CAM_MCNT_V18_MASK 0x0010 87 88 #define REG_CAM_MCNT_IRCLK_SHIFT 3 89 #define REG_CAM_MCNT_IRCLK_SIZE 1 90 #define REG_CAM_MCNT_IRCLK_MASK 0x0008 91 92 #define REG_CAM_MCNT_SYNC_SHIFT 2 93 #define REG_CAM_MCNT_SYNC_SIZE 1 94 #define REG_CAM_MCNT_SYNC_MASK 0x0004 95 96 #define REG_CAM_MCNT_RST_SHIFT 1 97 #define REG_CAM_MCNT_RST_SIZE 1 98 #define REG_CAM_MCNT_RST_MASK 0x0002 99 100 #define REG_CAM_MCNT_STBY_SHIFT 0 101 #define REG_CAM_MCNT_STBY_SIZE 1 102 #define REG_CAM_MCNT_STBY_MASK 0x0001 103 104 #ifndef SDK_ASM 105 #define REG_CAM_MCNT_FIELD( ini, v28, vio, v18, irclk, sync, rst, stby ) \ 106 (u16)( \ 107 ((u32)(ini) << REG_CAM_MCNT_INI_SHIFT) | \ 108 ((u32)(v28) << REG_CAM_MCNT_V28_SHIFT) | \ 109 ((u32)(vio) << REG_CAM_MCNT_VIO_SHIFT) | \ 110 ((u32)(v18) << REG_CAM_MCNT_V18_SHIFT) | \ 111 ((u32)(irclk) << REG_CAM_MCNT_IRCLK_SHIFT) | \ 112 ((u32)(sync) << REG_CAM_MCNT_SYNC_SHIFT) | \ 113 ((u32)(rst) << REG_CAM_MCNT_RST_SHIFT) | \ 114 ((u32)(stby) << REG_CAM_MCNT_STBY_SHIFT)) 115 #endif 116 117 118 /* CNT */ 119 120 #define REG_CAM_CNT_E_SHIFT 15 121 #define REG_CAM_CNT_E_SIZE 1 122 #define REG_CAM_CNT_E_MASK 0x8000 123 124 #define REG_CAM_CNT_T_SHIFT 14 125 #define REG_CAM_CNT_T_SIZE 1 126 #define REG_CAM_CNT_T_MASK 0x4000 127 128 #define REG_CAM_CNT_F_SHIFT 13 129 #define REG_CAM_CNT_F_SIZE 1 130 #define REG_CAM_CNT_F_MASK 0x2000 131 132 #define REG_CAM_CNT_IREQI_SHIFT 11 133 #define REG_CAM_CNT_IREQI_SIZE 1 134 #define REG_CAM_CNT_IREQI_MASK 0x0800 135 136 #define REG_CAM_CNT_IREQBE_SHIFT 10 137 #define REG_CAM_CNT_IREQBE_SIZE 1 138 #define REG_CAM_CNT_IREQBE_MASK 0x0400 139 140 #define REG_CAM_CNT_IREQVS_SHIFT 8 141 #define REG_CAM_CNT_IREQVS_SIZE 2 142 #define REG_CAM_CNT_IREQVS_MASK 0x0300 143 144 #define REG_CAM_CNT_CL_SHIFT 5 145 #define REG_CAM_CNT_CL_SIZE 1 146 #define REG_CAM_CNT_CL_MASK 0x0020 147 148 #define REG_CAM_CNT_ERR_SHIFT 4 149 #define REG_CAM_CNT_ERR_SIZE 1 150 #define REG_CAM_CNT_ERR_MASK 0x0010 151 152 #define REG_CAM_CNT_TL_SHIFT 0 153 #define REG_CAM_CNT_TL_SIZE 4 154 #define REG_CAM_CNT_TL_MASK 0x000f 155 156 #ifndef SDK_ASM 157 #define REG_CAM_CNT_FIELD( e, t, f, ireqi, ireqbe, ireqvs, cl, err, tl ) \ 158 (u16)( \ 159 ((u32)(e) << REG_CAM_CNT_E_SHIFT) | \ 160 ((u32)(t) << REG_CAM_CNT_T_SHIFT) | \ 161 ((u32)(f) << REG_CAM_CNT_F_SHIFT) | \ 162 ((u32)(ireqi) << REG_CAM_CNT_IREQI_SHIFT) | \ 163 ((u32)(ireqbe) << REG_CAM_CNT_IREQBE_SHIFT) | \ 164 ((u32)(ireqvs) << REG_CAM_CNT_IREQVS_SHIFT) | \ 165 ((u32)(cl) << REG_CAM_CNT_CL_SHIFT) | \ 166 ((u32)(err) << REG_CAM_CNT_ERR_SHIFT) | \ 167 ((u32)(tl) << REG_CAM_CNT_TL_SHIFT)) 168 #endif 169 170 171 /* DAT */ 172 173 #define REG_CAM_DAT_DATA_SHIFT 0 174 #define REG_CAM_DAT_DATA_SIZE 32 175 #define REG_CAM_DAT_DATA_MASK 0xffffffff 176 177 #ifndef SDK_ASM 178 #define REG_CAM_DAT_FIELD( data ) \ 179 (u32)( \ 180 ((u32)(data) << REG_CAM_DAT_DATA_SHIFT)) 181 #endif 182 183 184 /* SOFS */ 185 186 #define REG_CAM_SOFS_VOFS_SHIFT 16 187 #define REG_CAM_SOFS_VOFS_SIZE 9 188 #define REG_CAM_SOFS_VOFS_MASK 0x01ff0000 189 190 #define REG_CAM_SOFS_HOFS_SHIFT 0 191 #define REG_CAM_SOFS_HOFS_SIZE 10 192 #define REG_CAM_SOFS_HOFS_MASK 0x000003ff 193 194 #ifndef SDK_ASM 195 #define REG_CAM_SOFS_FIELD( vofs, hofs ) \ 196 (u32)( \ 197 ((u32)(vofs) << REG_CAM_SOFS_VOFS_SHIFT) | \ 198 ((u32)(hofs) << REG_CAM_SOFS_HOFS_SHIFT)) 199 #endif 200 201 202 /* EOFS */ 203 204 #define REG_CAM_EOFS_VOFS_SHIFT 16 205 #define REG_CAM_EOFS_VOFS_SIZE 9 206 #define REG_CAM_EOFS_VOFS_MASK 0x01ff0000 207 208 #define REG_CAM_EOFS_HOFS_SHIFT 0 209 #define REG_CAM_EOFS_HOFS_SIZE 10 210 #define REG_CAM_EOFS_HOFS_MASK 0x000003ff 211 212 #ifndef SDK_ASM 213 #define REG_CAM_EOFS_FIELD( vofs, hofs ) \ 214 (u32)( \ 215 ((u32)(vofs) << REG_CAM_EOFS_VOFS_SHIFT) | \ 216 ((u32)(hofs) << REG_CAM_EOFS_HOFS_SHIFT)) 217 #endif 218 219 220 #ifdef __cplusplus 221 } /* extern "C" */ 222 #endif 223 224 /* TWL_HW_ARM9_IOREG_CAM_H_ */ 225 #endif 226