1 /*---------------------------------------------------------------------------* 2 Project: TwlSDK - include - PXI 3 File: regname.h 4 5 Copyright 2003-2008 Nintendo. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 $Date:: 2008-09-18#$ 14 $Rev: 8573 $ 15 $Author: okubata_ryoma $ 16 *---------------------------------------------------------------------------*/ 17 18 #ifndef NITRO_PXI_COMMON_REGNAME_H_ 19 #define NITRO_PXI_COMMON_REGNAME_H_ 20 21 #include <nitro/types.h> 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 // Register rename 28 typedef enum 29 { 30 PXI_PROC_ARM9 = 0, 31 PXI_PROC_ARM7 = 1 32 } 33 PXIProc; 34 35 #ifdef SDK_ARM9 36 37 #define PXI_PROC_ARM PXI_PROC_ARM9 38 39 #define reg_PXI_FIFO_CNT reg_PXI_SUBP_FIFO_CNT 40 #define REG_PXI_FIFO_CNT_ERR_MASK REG_PXI_SUBP_FIFO_CNT_ERR_MASK 41 #define REG_PXI_FIFO_CNT_SEND_CL_MASK REG_PXI_SUBP_FIFO_CNT_SEND_CL_MASK 42 #define REG_PXI_FIFO_CNT_SEND_FULL_MASK REG_PXI_SUBP_FIFO_CNT_SEND_FULL_MASK 43 #define REG_PXI_FIFO_CNT_SEND_TI_MASK REG_PXI_SUBP_FIFO_CNT_SEND_TI_MASK 44 #define REG_PXI_FIFO_CNT_RECV_RI_MASK REG_PXI_SUBP_FIFO_CNT_RECV_RI_MASK 45 #define REG_PXI_FIFO_CNT_RECV_EMP_MASK REG_PXI_SUBP_FIFO_CNT_RECV_EMP_MASK 46 #define REG_PXI_FIFO_CNT_E_MASK REG_PXI_SUBP_FIFO_CNT_E_MASK 47 48 #define REG_PXI_INTF_ADDR REG_SUBPINTF_ADDR 49 #define reg_PXI_INTF reg_PXI_SUBPINTF 50 #define REG_PXI_INTF_I_MASK REG_PXI_SUBPINTF_I_MASK 51 #define REG_PXI_INTF_IREQ_MASK REG_PXI_SUBPINTF_IREQ_MASK 52 #define REG_PXI_INTF_SEND_MASK REG_PXI_SUBPINTF_A9STATUS_MASK 53 #define REG_PXI_INTF_SEND_SHIFT REG_PXI_SUBPINTF_A9STATUS_SHIFT 54 #define REG_PXI_INTF_RECV_MASK REG_PXI_SUBPINTF_A7STATUS_MASK 55 #define REG_PXI_INTF_RECV_SHIFT REG_PXI_SUBPINTF_A7STATUS_SHIFT 56 57 #else // SDK_ARM7 58 59 #define PXI_PROC_ARM PXI_PROC_ARM7 60 61 #define reg_PXI_FIFO_CNT reg_PXI_MAINP_FIFO_CNT 62 #define REG_PXI_FIFO_CNT_ERR_MASK REG_PXI_MAINP_FIFO_CNT_ERR_MASK 63 #define REG_PXI_FIFO_CNT_SEND_CL_MASK REG_PXI_MAINP_FIFO_CNT_SEND_CL_MASK 64 #define REG_PXI_FIFO_CNT_SEND_FULL_MASK REG_PXI_MAINP_FIFO_CNT_SEND_FULL_MASK 65 #define REG_PXI_FIFO_CNT_SEND_TI_MASK REG_PXI_MAINP_FIFO_CNT_SEND_TI_MASK 66 #define REG_PXI_FIFO_CNT_RECV_RI_MASK REG_PXI_MAINP_FIFO_CNT_RECV_RI_MASK 67 #define REG_PXI_FIFO_CNT_RECV_EMP_MASK REG_PXI_MAINP_FIFO_CNT_RECV_EMP_MASK 68 #define REG_PXI_FIFO_CNT_E_MASK REG_PXI_MAINP_FIFO_CNT_E_MASK 69 70 #define REG_PXI_INTF_ADDR REG_MAINPINTF_ADDR 71 #define reg_PXI_INTF reg_PXI_MAINPINTF 72 #define REG_PXI_INTF_I_MASK REG_PXI_MAINPINTF_I_MASK 73 #define REG_PXI_INTF_IREQ_MASK REG_PXI_MAINPINTF_IREQ_MASK 74 #define REG_PXI_INTF_SEND_MASK REG_PXI_MAINPINTF_A7STATUS_MASK 75 #define REG_PXI_INTF_SEND_SHIFT REG_PXI_MAINPINTF_A7STATUS_SHIFT 76 #define REG_PXI_INTF_RECV_MASK REG_PXI_MAINPINTF_A9STATUS_MASK 77 #define REG_PXI_INTF_RECV_SHIFT REG_PXI_MAINPINTF_A9STATUS_SHIFT 78 79 #endif 80 81 #ifdef __cplusplus 82 } /* extern "C" */ 83 #endif 84 /* NITRO_PXI_COMMON_REGNAME_H_ */ 85 #endif 86