1 /*---------------------------------------------------------------------------*
2 Project: TwlSDK - MI
3 File: mi_sharedWram.c
4
5 Copyright 2007-2008 Nintendo. All rights reserved.
6
7 These coded instructions, statements, and computer programs contain
8 proprietary information of Nintendo of America Inc. and/or Nintendo
9 Company Ltd., and are protected by Federal copyright law. They may
10 not be disclosed to third parties or copied or duplicated in any form,
11 in whole or in part, without the prior written consent of Nintendo.
12
13 $Date:: 2008-12-03#$
14 $Rev: 9490 $
15 $Author: yada $
16 *---------------------------------------------------------------------------*/
17 #ifdef SDK_ARM9
18 #include <twl.h>
19 #else
20 #include <twl_sp.h>
21 #endif
22
23 #include <nitro/os/common/system.h>
24
25 // Remove only branch when operating TWL from MI_InitWramManager
26 static void MIi_InitWramManager(void);
MI_InitWramManager(void)27 void MI_InitWramManager(void)
28 {
29 if (OS_IsRunOnTwl() == FALSE)
30 {
31 return;
32 }
33 MIi_InitWramManager();
34 }
35
36 #ifdef SDK_ARM9
37 #include <twl/ltdmain_begin.h>
38 #endif
39
40
41 #ifdef SDK_ARM9
42 //================================================================================
43 // low level functions of wram banks
44 //================================================================================
45 /*---------------------------------------------------------------------------*
46 Name: MIi_SetWramBank_A / MIi_SetWramBank_B / MIi_SetWramBank_C
47
48 Description: Configures shared WRAM bank
49
50 Arguments: num ; slot num
51 WRAM_A:0-3 WRAM_B:0-7 WRAM_C:0-7
52 proc : master select
53 MI_WRAM_ARM9 : ARM9
54 MI_WRAM_ARM7 : ARM7
55 MI_WRAM_DSP : DSP (only for WRAM_B and WRAM_C)
56 offset: offset of WRAM allocation
57 (for WRAM_A)
58 MI_WRAM_OFFSET_0KB : 0KB from top
59 MI_WRAM_OFFSET_64KB : 64KB from top
60 MI_WRAM_OFFSET_128KB : 128KB from top
61 MI_WRAM_OFFSET_192KB : 192KB from top
62
63 (for WRAM_B and WRAM_C)
64 MI_WRAM_OFFSET_0KB : 0KB from top
65 MI_WRAM_OFFSET_32KB : 32KB from top
66 MI_WRAM_OFFSET_64KB : 64KB from top
67 MI_WRAM_OFFSET_96KB : 96KB from top
68 MI_WRAM_OFFSET_128KB : 128KB from top
69 MI_WRAM_OFFSET_160KB : 160KB from top
70 MI_WRAM_OFFSET_192KB : 192KB from top
71 MI_WRAM_OFFSET_224KB : 224KB from top
72
73 enable: enable flag
74 MI_WRAM_ENABLE : enable
75 MI_WRAM_DISABLE : disable
76
77 Returns: None.
78 *---------------------------------------------------------------------------*/
MIi_SetWramBank_A(int num,MIWramProc proc,MIWramOffset offset,MIWramEnable enable)79 void MIi_SetWramBank_A( int num, MIWramProc proc, MIWramOffset offset, MIWramEnable enable )
80 {
81 SDK_ASSERT( 0<=num && num<MI_WRAM_A_MAX_NUM );
82 SDK_ASSERT( (offset & 1) == 0 );
83 SDK_ASSERT( proc == MI_WRAM_ARM9 || proc == MI_WRAM_ARM7 );
84
85 *(vu8*)(REG_MBK_A0_ADDR + num)
86 = (vu8)((enable? REG_MI_MBK_A0_E_MASK: 0) | proc | ((offset>>1)<<REG_MI_MBK_A0_OF_SHIFT));
87 }
88
89 //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MIi_SetWramBank_B(int num,MIWramProc proc,MIWramOffset offset,MIWramEnable enable)90 void MIi_SetWramBank_B( int num, MIWramProc proc, MIWramOffset offset, MIWramEnable enable )
91 {
92 SDK_ASSERT( 0<=num && num<MI_WRAM_B_MAX_NUM );
93
94 *(vu8*)(REG_MBK_B0_ADDR + num)
95 = (vu8)((enable? REG_MI_MBK_B0_E_MASK: 0) | proc | (offset<<REG_MI_MBK_B0_OF_SHIFT));
96 }
97
98 //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MIi_SetWramBank_C(int num,MIWramProc proc,MIWramOffset offset,MIWramEnable enable)99 void MIi_SetWramBank_C( int num, MIWramProc proc, MIWramOffset offset, MIWramEnable enable )
100 {
101 SDK_ASSERT( 0<=num && num<MI_WRAM_C_MAX_NUM );
102
103 *(vu8*)(REG_MBK_C0_ADDR + num)
104 = (vu8)((enable? REG_MI_MBK_C0_E_MASK: 0) | proc | (offset<<REG_MI_MBK_C0_OF_SHIFT));
105 }
106
107 //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MIi_SetWramBank(MIWramPos wram,int num,MIWramProc proc,MIWramOffset offset,MIWramEnable enable)108 void MIi_SetWramBank( MIWramPos wram, int num, MIWramProc proc, MIWramOffset offset, MIWramEnable enable )
109 {
110 static void (*f[3])( int, MIWramProc, MIWramOffset, MIWramEnable ) =
111 {
112 MIi_SetWramBank_A, MIi_SetWramBank_B, MIi_SetWramBank_C
113 };
114
115 SDK_ASSERT( 0<=wram && wram<3 );
116 (f[wram])( num, proc, offset, enable );
117 }
118
119 /*---------------------------------------------------------------------------*
120 Name: MIi_GetWramBank_A / MIi_SetWramBank_B / MIi_SetWramBank_C
121
122 Description: Gets WRAM bank setting
123
124 Arguments: num ; slot num
125
126 Returns: value of setting
127 *---------------------------------------------------------------------------*/
MIi_GetWramBank_A(int num)128 vu8 MIi_GetWramBank_A( int num )
129 {
130 SDK_ASSERT( 0<=num && num<MI_WRAM_A_MAX_NUM );
131 return *(vu8*)(REG_MBK_A0_ADDR + num);
132 }
133 //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MIi_GetWramBank_B(int num)134 vu8 MIi_GetWramBank_B( int num )
135 {
136 SDK_ASSERT( 0<=num && num<MI_WRAM_B_MAX_NUM );
137 return *(vu8*)(REG_MBK_B0_ADDR + num);
138 }
139 //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MIi_GetWramBank_C(int num)140 vu8 MIi_GetWramBank_C( int num )
141 {
142 SDK_ASSERT( 0<=num && num<MI_WRAM_C_MAX_NUM );
143 return *(vu8*)(REG_MBK_C0_ADDR + num);
144 }
145 //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MIi_GetWramBank(MIWramPos wram,int num)146 static vu8 MIi_GetWramBank( MIWramPos wram, int num )
147 {
148 static vu8 (*f[3])( int ) =
149 {
150 MIi_GetWramBank_A, MIi_GetWramBank_B, MIi_GetWramBank_C
151 };
152
153 SDK_ASSERT( 0<=wram && wram<3 );
154 return (f[wram])( num );
155 }
156
157 /*---------------------------------------------------------------------------*
158 Name: MIi_SetWramBankMaster_A / MIi_SetWramBankMaster_B / MIi_SetWramBankMaster_C
159
160 Description: Sets master of shared WRAM bank
161
162 Arguments: num ; slot num
163 WRAM_A:0-3 WRAM_B:0-7 WRAM_C:0-7
164
165 proc : master select
166 MI_WRAM_ARM9 : ARM9
167 MI_WRAM_ARM7 : ARM7
168 MI_WRAM_DSP : DSP (only for WRAM_B and WRAM_C)
169
170 Returns: None.
171 *---------------------------------------------------------------------------*/
MIi_SetWramBankMaster_A(int num,MIWramProc proc)172 void MIi_SetWramBankMaster_A( int num, MIWramProc proc )
173 {
174 vu8* p = (vu8*)(REG_MBK_A0_ADDR + num);
175
176 SDK_ASSERT( 0<=num && num<MI_WRAM_A_MAX_NUM );
177 *p = (u8)(*p & ~MI_WRAM_MASTER_MASK_A | proc);
178 }
179 //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MIi_SetWramBankMaster_B(int num,MIWramProc proc)180 void MIi_SetWramBankMaster_B( int num, MIWramProc proc )
181 {
182 vu8* p = (vu8*)(REG_MBK_B0_ADDR + num);
183
184 SDK_ASSERT( 0<=num && num<MI_WRAM_B_MAX_NUM );
185 *p = (u8)(*p & ~MI_WRAM_MASTER_MASK_B | proc);
186 }
187 //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MIi_SetWramBankMaster_C(int num,MIWramProc proc)188 void MIi_SetWramBankMaster_C( int num, MIWramProc proc )
189 {
190 vu8* p = (vu8*)(REG_MBK_C0_ADDR + num);
191
192 SDK_ASSERT( 0<=num && num<MI_WRAM_C_MAX_NUM );
193 *p = (u8)(*p & ~MI_WRAM_MASTER_MASK_C | proc);
194 }
195 //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MIi_SetWramBankMaster(MIWramPos wram,int num,MIWramProc proc)196 void MIi_SetWramBankMaster( MIWramPos wram, int num, MIWramProc proc )
197 {
198 static void (*f[3])( int, MIWramProc ) =
199 {
200 MIi_SetWramBankMaster_A, MIi_SetWramBankMaster_B, MIi_SetWramBankMaster_C
201 };
202 SDK_ASSERT( 0<=wram && wram<3 );
203 (f[wram])( num, proc );
204 }
205
206 /*---------------------------------------------------------------------------*
207 Name: MIi_SetWramBankEnable_A / MIi_SetWramBankEnable_B / MIi_SetWramBankEnable_C
208
209 Description: Sets enable bit of shared WRAM bank
210
211 Arguments: num ; slot num
212 WRAM_A:0-3 WRAM_B:0-7 WRAM_C:0-7
213
214 enable: enable bit
215 MI_WRAM_ENABLE : enable
216 MI_WRAM_DISABLE : disable
217
218 Returns: None.
219 *---------------------------------------------------------------------------*/
MIi_SetWramBankEnable_A(int num,MIWramEnable enable)220 void MIi_SetWramBankEnable_A( int num, MIWramEnable enable )
221 {
222 vu8* p = (vu8*)(REG_MBK_A0_ADDR + num);
223
224 SDK_ASSERT( 0<=num && num<MI_WRAM_A_MAX_NUM );
225 *p = (u8)(*p & ~MI_WRAM_ENABLE_MASK_A | (enable? MI_WRAM_ENABLE_MASK_A: 0));
226 }
227 //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MIi_SetWramBankEnable_B(int num,MIWramEnable enable)228 void MIi_SetWramBankEnable_B( int num, MIWramEnable enable )
229 {
230 vu8* p = (vu8*)(REG_MBK_B0_ADDR + num);
231
232 SDK_ASSERT( 0<=num && num<MI_WRAM_B_MAX_NUM );
233 *p = (u8)(*p & ~MI_WRAM_ENABLE_MASK_B | (enable? MI_WRAM_ENABLE_MASK_B: 0));
234 }
235 //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MIi_SetWramBankEnable_C(int num,MIWramEnable enable)236 void MIi_SetWramBankEnable_C( int num, MIWramEnable enable )
237 {
238 vu8* p = (vu8*)(REG_MBK_C0_ADDR + num);
239
240 SDK_ASSERT( 0<=num && num<MI_WRAM_C_MAX_NUM );
241 *p = (u8)(*p & ~MI_WRAM_ENABLE_MASK_C | (enable? MI_WRAM_ENABLE_MASK_C: 0));
242 }
243 //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MIi_SetWramBankEnable(MIWramPos wram,int num,MIWramEnable enable)244 void MIi_SetWramBankEnable( MIWramPos wram, int num, MIWramEnable enable )
245 {
246 static void (*f[3])( int, MIWramEnable ) =
247 {
248 MIi_SetWramBankEnable_A, MIi_SetWramBankEnable_B, MIi_SetWramBankEnable_C
249 };
250
251 SDK_ASSERT( 0<=wram && wram<3 );
252 (f[wram])( num, enable );
253 }
254 #endif
255
256 /*---------------------------------------------------------------------------*
257 Name: MI_GetWramBankMaster_A / MI_GetWramBankMaster_B / MI_GetWramBankMaster_C
258
259 Description: Gets master which is set to shared WRAM bank
260
261 Arguments: num ; slot num
262 WRAM_A:0-3 WRAM_B:0-7 WRAM_C:0-7
263
264 Returns: master select
265 MI_WRAM_ARM9 : ARM9
266 MI_WRAM_ARM7 : ARM7
267 MI_WRAM_DSP : DSP (only for WRAM_B and WRAM_C)
268 *---------------------------------------------------------------------------*/
MI_GetWramBankMaster_A(int num)269 MIWramProc MI_GetWramBankMaster_A( int num )
270 {
271 SDK_ASSERT( 0<=num && num<MI_WRAM_A_MAX_NUM );
272 return (MIWramProc)( *(REGType8v*)(REG_MBK_A0_ADDR + num) & MI_WRAM_MASTER_MASK_A );
273 }
MI_GetWramBankMaster_B(int num)274 MIWramProc MI_GetWramBankMaster_B( int num )
275 {
276 SDK_ASSERT( 0<=num && num<MI_WRAM_B_MAX_NUM );
277 return (MIWramProc)( *(REGType8v*)(REG_MBK_B0_ADDR + num) & MI_WRAM_MASTER_MASK_B );
278 }
MI_GetWramBankMaster_C(int num)279 MIWramProc MI_GetWramBankMaster_C( int num )
280 {
281 SDK_ASSERT( 0<=num && num<MI_WRAM_C_MAX_NUM );
282 return (MIWramProc)( *(REGType8v*)(REG_MBK_C0_ADDR + num) & MI_WRAM_MASTER_MASK_C );
283 }
MI_GetWramBankMaster(MIWramPos wram,int num)284 MIWramProc MI_GetWramBankMaster( MIWramPos wram, int num )
285 {
286 static MIWramProc (*f[3])( int ) =
287 {
288 MI_GetWramBankMaster_A, MI_GetWramBankMaster_B, MI_GetWramBankMaster_C
289 };
290
291 SDK_ASSERT( 0<=wram && wram<3 );
292 return (f[wram])( num );
293 }
294
295 /*---------------------------------------------------------------------------*
296 Name: MI_GetWramBankOffset_A / MI_GetWramBankOffset_B / MI_GetWramBankOffset_C
297
298 Description: Gets offset which is set to shared WRAM bank
299
300 Arguments: num ; slot num
301 WRAM_A:0-3 WRAM_B:0-7 WRAM_C:0-7
302
303 Returns: offset: offset of WRAM allocation
304 (for WRAM_A)
305 MI_WRAM_OFFSET_0KB : 0KB from top
306 MI_WRAM_OFFSET_64KB : 64KB from top
307 MI_WRAM_OFFSET_128KB : 128KB from top
308 MI_WRAM_OFFSET_192KB : 192KB from top
309
310 (for WRAM_B and WRAM_C)
311 MI_WRAM_OFFSET_0KB : 0KB from top
312 MI_WRAM_OFFSET_32KB : 32KB from top
313 MI_WRAM_OFFSET_64KB : 64KB from top
314 MI_WRAM_OFFSET_96KB : 96KB from top
315 MI_WRAM_OFFSET_128KB : 128KB from top
316 MI_WRAM_OFFSET_160KB : 160KB from top
317 MI_WRAM_OFFSET_192KB : 192KB from top
318 MI_WRAM_OFFSET_224KB : 224KB from top
319
320 *---------------------------------------------------------------------------*/
MI_GetWramBankOffset_A(int num)321 MIWramOffset MI_GetWramBankOffset_A( int num )
322 {
323 SDK_ASSERT( 0<=num && num<MI_WRAM_A_MAX_NUM );
324 return (MIWramOffset)( (*(REGType8v*)(REG_MBK_A0_ADDR + num) & MI_WRAM_OFFSET_MASK_A) >> MI_WRAM_OFFSET_SHIFT_A << 1 );
325 }
MI_GetWramBankOffset_B(int num)326 MIWramOffset MI_GetWramBankOffset_B( int num )
327 {
328 SDK_ASSERT( 0<=num && num<MI_WRAM_B_MAX_NUM );
329 return (MIWramOffset)( (*(REGType8v*)(REG_MBK_B0_ADDR + num) & MI_WRAM_OFFSET_MASK_B) >> MI_WRAM_OFFSET_SHIFT_B );
330 }
MI_GetWramBankOffset_C(int num)331 MIWramOffset MI_GetWramBankOffset_C( int num )
332 {
333 SDK_ASSERT( 0<=num && num<MI_WRAM_C_MAX_NUM );
334 return (MIWramOffset)( (*(REGType8v*)(REG_MBK_C0_ADDR + num) & MI_WRAM_OFFSET_MASK_C) >> MI_WRAM_OFFSET_SHIFT_C );
335 }
MI_GetWramBankOffset(MIWramPos wram,int num)336 MIWramOffset MI_GetWramBankOffset( MIWramPos wram, int num )
337 {
338 static MIWramOffset (*f[3])( int ) =
339 {
340 MI_GetWramBankOffset_A, MI_GetWramBankOffset_B, MI_GetWramBankOffset_C
341 };
342
343 SDK_ASSERT( 0<=wram && wram<3 );
344 return (f[wram])( num );
345 }
346
347 /*---------------------------------------------------------------------------*
348 Name: MI_GetWramBankEnable_A / MI_GetWramBankEnable_B /MI_GetWramBankEnable_C
349
350 Description: Gets enable/disable which is set to shared WRAM bank
351
352 Arguments: num ; slot num
353 WRAM_A:0-3 WRAM_B:0-7 WRAM_C:0-7
354
355 Returns: enable flag
356 MI_WRAM_ENABLE : enable
357 MI_WRAM_DISABLE : disable
358
359 *---------------------------------------------------------------------------*/
MI_GetWramBankEnable_A(int num)360 MIWramEnable MI_GetWramBankEnable_A( int num )
361 {
362 SDK_ASSERT( 0<=num && num<MI_WRAM_A_MAX_NUM );
363 return (*(REGType8v*)(REG_MBK_A0_ADDR + num) & MI_WRAM_ENABLE_MASK_A)? MI_WRAM_ENABLE: MI_WRAM_DISABLE;
364 }
MI_GetWramBankEnable_B(int num)365 MIWramEnable MI_GetWramBankEnable_B( int num )
366 {
367 SDK_ASSERT( 0<=num && num<MI_WRAM_B_MAX_NUM );
368 return (*(REGType8v*)(REG_MBK_B0_ADDR + num) & MI_WRAM_ENABLE_MASK_B)? MI_WRAM_ENABLE: MI_WRAM_DISABLE;
369 }
MI_GetWramBankEnable_C(int num)370 MIWramEnable MI_GetWramBankEnable_C( int num )
371 {
372 SDK_ASSERT( 0<=num && num<MI_WRAM_C_MAX_NUM );
373 return (*(REGType8v*)(REG_MBK_C0_ADDR + num) & MI_WRAM_ENABLE_MASK_C)? MI_WRAM_ENABLE: MI_WRAM_DISABLE;
374 }
MI_GetWramBankEnable(MIWramPos wram,int num)375 MIWramEnable MI_GetWramBankEnable( MIWramPos wram, int num )
376 {
377 static MIWramEnable (*f[3])( int ) =
378 {
379 MI_GetWramBankEnable_A, MI_GetWramBankEnable_B, MI_GetWramBankEnable_C
380 };
381
382 SDK_ASSERT( 0<=wram && wram<3 );
383 return (f[wram])( num );
384 }
385
386 //================================================================================
387 // low level functions of wram maps
388 //================================================================================
389 /*---------------------------------------------------------------------------*
390 Name: MIi_SetWramMap_A
391
392 Description: Sets WRAM_A map
393
394 Arguments: start: start address
395 0x03000000 - 0x03FF0000 (64KB step)
396
397 end: end address
398 0x02FFFFFF - 0x03FFFFFF (64KB step)
399
400 image: MI_WRAM_IMAGE_64KB
401 MI_WRAM_IMAGE_128KB
402 MI_WRAM_IMAGE_256KB
403
404 Returns: None.
405 *---------------------------------------------------------------------------*/
MIi_SetWramMap_A(u32 start,u32 end,MIWramImage image)406 void MIi_SetWramMap_A( u32 start, u32 end, MIWramImage image )
407 {
408 SDK_ASSERT( image == MI_WRAM_IMAGE_64KB ||
409 image == MI_WRAM_IMAGE_128KB ||
410 image == MI_WRAM_IMAGE_256KB );
411 SDK_ASSERT( (start & 0xffff) == 0 && 0x03000000 <= start && start <= 0x03ff0000);
412 SDK_ASSERT( (end & 0xffff) == 0xffff && 0x02ffffff <= end && end <= 0x03ffffff);
413
414 reg_MI_MBK6 = (image << REG_MI_MBK6_WA_ISIZE_SHIFT)
415 | ((start-0x03000000) >> (16 - REG_MI_MBK6_WA_SADDR_SHIFT))
416 | ((end -0x02ffffff) << (REG_MI_MBK6_WA_EADDR_SHIFT - 16));
417 }
418
419 /*---------------------------------------------------------------------------*
420 Name: MIi_SetWramMap_B
421
422 Description: Sets WRAM_B map
423
424 Arguments: start: start address
425 0x03000000 - 0x03FF0000 (32KB step)
426
427 end: end address
428 0x02FFFFFF - 0x03FFFFFF (32KB step)
429
430 image: MI_WRAM_IMAGE_32KB
431 MI_WRAM_IMAGE_64KB
432 MI_WRAM_IMAGE_128KB
433 MI_WRAM_IMAGE_256KB
434
435 Returns: None.
436 *---------------------------------------------------------------------------*/
MIi_SetWramMap_B(u32 start,u32 end,MIWramImage image)437 void MIi_SetWramMap_B( u32 start, u32 end, MIWramImage image )
438 {
439 SDK_ASSERT( (start & 0x7fff) == 0 && 0x03000000 <= start && start <= 0x03ff8000);
440 SDK_ASSERT( (end & 0x7fff) == 0x7fff && 0x02ffffff <= end && end <= 0x03ffffff);
441
442 reg_MI_MBK7 = (image << REG_MI_MBK7_WB_ISIZE_SHIFT)
443 | ((start-0x03000000) >> (16 - REG_MI_MBK7_WB_SADDR_SHIFT))
444 | ((end -0x02ffffff) << (REG_MI_MBK7_WB_EADDR_SHIFT - 16));
445 }
446
447 /*---------------------------------------------------------------------------*
448 Name: MIi_SetWramMap_C
449
450 Description: Sets WRAM_C map
451
452 Arguments: start: start address
453 0x03000000 - 0x03FF0000 (32KB step)
454
455 end: end address
456 0x02FFFFFF - 0x03FFFFFF (32KB step)
457
458 image: MI_WRAM_IMAGE_32KB
459 MI_WRAM_IMAGE_64KB
460 MI_WRAM_IMAGE_128KB
461 MI_WRAM_IMAGE_256KB
462
463 Returns: None.
464 *---------------------------------------------------------------------------*/
MIi_SetWramMap_C(u32 start,u32 end,MIWramImage image)465 void MIi_SetWramMap_C( u32 start, u32 end, MIWramImage image )
466 {
467 SDK_ASSERT( (start & 0x7fff) == 0 && 0x03000000 <= start && start <= 0x03ff8000);
468 SDK_ASSERT( (end & 0x7fff) == 0x7fff && 0x02ffffff <= end && end <= 0x03ffffff);
469
470 reg_MI_MBK8 = (image << REG_MI_MBK8_WC_ISIZE_SHIFT)
471 | ((start-0x03000000) >> (16 - REG_MI_MBK8_WC_SADDR_SHIFT))
472 | ((end -0x02ffffff) << (REG_MI_MBK8_WC_EADDR_SHIFT - 16));
473 }
474
475 /*---------------------------------------------------------------------------*
476 Name: MI_GetWramMapStart_A / MI_GetWramMapStart_B / MI_GetWramMapStart_C
477
478 Description: Gets start address of shared WRAM
479
480 Arguments: None.
481
482 Return: start: start address
483 (for WRAM_A)
484 0x03000000 - 0x03FF0000 (64KB step)
485 (for WRAM_B and WRAM_C)
486 0x03000000 - 0x03FF0000 (32KB step)
487 *---------------------------------------------------------------------------*/
MI_GetWramMapStart_A(void)488 u32 MI_GetWramMapStart_A(void)
489 {
490 #ifdef SDK_ARM9
491 u32 wramReg = reg_MI_MBK6;
492 #else
493 u32 wramReg = *(u32*)(HW_TWL_ROM_HEADER_BUF + 0x0194);
494 #endif
495 return HW_WRAM_BASE + (((wramReg & REG_MI_MBK6_WA_SADDR_MASK) >> REG_MI_MBK6_WA_SADDR_SHIFT) << 16);
496 }
MI_GetWramMapStart_B(void)497 u32 MI_GetWramMapStart_B(void)
498 {
499 #ifdef SDK_ARM9
500 u32 wramReg = reg_MI_MBK7;
501 #else
502 u32 wramReg = *(u32*)(HW_TWL_ROM_HEADER_BUF + 0x0198);
503 #endif
504 return HW_WRAM_BASE + (((wramReg & REG_MI_MBK7_WB_SADDR_MASK) >> REG_MI_MBK7_WB_SADDR_SHIFT) << 15);
505 }
MI_GetWramMapStart_C(void)506 u32 MI_GetWramMapStart_C(void)
507 {
508 #ifdef SDK_ARM9
509 u32 wramReg = reg_MI_MBK8;
510 #else
511 u32 wramReg = *(u32*)(HW_TWL_ROM_HEADER_BUF + 0x019C);
512 #endif
513 return HW_WRAM_BASE + (((wramReg & REG_MI_MBK8_WC_SADDR_MASK) >> REG_MI_MBK8_WC_SADDR_SHIFT) << 15);
514 }
MI_GetWramMapStart(MIWramPos wram)515 u32 MI_GetWramMapStart( MIWramPos wram )
516 {
517 static u32 (*f[3])( void ) =
518 {
519 MI_GetWramMapStart_A, MI_GetWramMapStart_B, MI_GetWramMapStart_C
520 };
521 SDK_ASSERT( 0<=wram && wram<3 );
522 return (f[wram])();
523 }
524
525 /*---------------------------------------------------------------------------*
526 Name: MI_GetWramMapEnd_A / MI_GetWramMapEnd_B / MI_GetWramMapEnd_C
527
528 Description: Gets end address of shared WRAM
529
530 Arguments: None.
531
532 Returns: end: end address
533 (for WRAM_A)
534 0x02FFFFFF - 0x03FFFFFF (64KB step)
535 (for WRAM_B and WRAM_C)
536 0x02FFFFFF - 0x03FF0000 (32KB step)
537 *---------------------------------------------------------------------------*/
MI_GetWramMapEnd_A(void)538 u32 MI_GetWramMapEnd_A(void)
539 {
540 #ifdef SDK_ARM9
541 u32 wramReg = reg_MI_MBK6;
542 #else
543 u32 wramReg = *(u32*)(HW_TWL_ROM_HEADER_BUF + 0x0194);
544 #endif
545 return (HW_WRAM_BASE-1) + (((wramReg & REG_MI_MBK6_WA_EADDR_MASK) >> REG_MI_MBK6_WA_EADDR_SHIFT) << 16);
546 }
MI_GetWramMapEnd_B(void)547 u32 MI_GetWramMapEnd_B(void)
548 {
549 #ifdef SDK_ARM9
550 u32 wramReg = reg_MI_MBK7;
551 #else
552 u32 wramReg = *(u32*)(HW_TWL_ROM_HEADER_BUF + 0x0198);
553 #endif
554 return (HW_WRAM_BASE-1) + (((wramReg & REG_MI_MBK7_WB_EADDR_MASK) >> REG_MI_MBK7_WB_EADDR_SHIFT) << 15);
555 }
MI_GetWramMapEnd_C(void)556 u32 MI_GetWramMapEnd_C(void)
557 {
558 #ifdef SDK_ARM9
559 u32 wramReg = reg_MI_MBK8;
560 #else
561 u32 wramReg = *(u32*)(HW_TWL_ROM_HEADER_BUF + 0x019C);
562 #endif
563 return (HW_WRAM_BASE-1) + (((wramReg & REG_MI_MBK8_WC_EADDR_MASK) >> REG_MI_MBK8_WC_EADDR_SHIFT) << 15);
564 }
MI_GetWramMapEnd(MIWramPos wram)565 u32 MI_GetWramMapEnd( MIWramPos wram )
566 {
567 static u32 (*f[3])( void ) =
568 {
569 MI_GetWramMapEnd_A, MI_GetWramMapEnd_B, MI_GetWramMapEnd_C
570 };
571 SDK_ASSERT( 0<=wram && wram<3 );
572 return (f[wram])();
573 }
574
575 /*---------------------------------------------------------------------------*
576 Name: MI_GetWramMapImage_A / MI_GetWramMapImage_B / MI_GetWramMapImage_C
577
578 Description: Gets image setting of shared WRAM
579
580 Arguments: None.
581
582 Returns: image: MI_WRAM_IMAGE_32KB (only for WRAM_B and WRAM_C)
583 MI_WRAM_IMAGE_64KB
584 MI_WRAM_IMAGE_128KB
585 MI_WRAM_IMAGE_256KB
586 *---------------------------------------------------------------------------*/
MI_GetWramMapImage_A(void)587 MIWramImage MI_GetWramMapImage_A(void)
588 {
589 #ifdef SDK_ARM9
590 u32 wramReg = reg_MI_MBK6;
591 #else
592 u32 wramReg = *(u32*)(HW_TWL_ROM_HEADER_BUF + 0x0194);
593 #endif
594 MIWramImage image = (MIWramImage)((wramReg & REG_MI_MBK6_WA_ISIZE_MASK) >> REG_MI_MBK6_WA_ISIZE_SHIFT);
595 if ( image == MI_WRAM_IMAGE_32KB )
596 {
597 image = MI_WRAM_IMAGE_64KB;
598 }
599 return image;
600 }
MI_GetWramMapImage_B(void)601 MIWramImage MI_GetWramMapImage_B(void)
602 {
603 #ifdef SDK_ARM9
604 u32 wramReg = reg_MI_MBK7;
605 #else
606 u32 wramReg = *(u32*)(HW_TWL_ROM_HEADER_BUF + 0x0198);
607 #endif
608 return (MIWramImage)((wramReg & REG_MI_MBK7_WB_ISIZE_MASK) >> REG_MI_MBK7_WB_ISIZE_SHIFT);
609 }
MI_GetWramMapImage_C(void)610 MIWramImage MI_GetWramMapImage_C(void)
611 {
612 #ifdef SDK_ARM9
613 u32 wramReg = reg_MI_MBK8;
614 #else
615 u32 wramReg = *(u32*)(HW_TWL_ROM_HEADER_BUF + 0x019C);
616 #endif
617 return (MIWramImage)((wramReg & REG_MI_MBK8_WC_ISIZE_MASK) >> REG_MI_MBK8_WC_ISIZE_SHIFT);
618 }
MI_GetWramMapImage(MIWramPos wram)619 MIWramImage MI_GetWramMapImage( MIWramPos wram )
620 {
621 static MIWramImage (*f[3])( void ) =
622 {
623 MI_GetWramMapImage_A, MI_GetWramMapImage_B, MI_GetWramMapImage_C
624 };
625 SDK_ASSERT( 0<=wram && wram<3 );
626 return (f[wram])();
627 }
628
629 /*---------------------------------------------------------------------------*
630 Name: MI_IsWramSlotLocked_A / MI_IsWramSlotLocked_B / MI_IsWramSlotLocked_C
631
632 Description: Checks if WRAM slot locked
633
634 Arguments: num: slot num
635 WRAM_A:0-3 WRAM_B:0-7 WRAM_C:0-7
636
637 Returns: TRUE: locked
638 FALSE: not locked
639 *---------------------------------------------------------------------------*/
MI_IsWramSlotLocked_A(int num)640 BOOL MI_IsWramSlotLocked_A( int num )
641 {
642 SDK_ASSERT( 0<=num && num<MI_WRAM_A_MAX_NUM );
643
644 return ( reg_MI_MBK_A_LOCK & (1 << (num+REG_MI_MBK_A_LOCK_A0_SHIFT)) )? TRUE: FALSE;
645 }
MI_IsWramSlotLocked_B(int num)646 BOOL MI_IsWramSlotLocked_B( int num )
647 {
648 SDK_ASSERT( 0<=num && num<MI_WRAM_B_MAX_NUM );
649
650 return ( reg_MI_MBK_B_LOCK & (1 << (num+REG_MI_MBK_B_LOCK_B0_SHIFT)) )? TRUE: FALSE;
651 }
MI_IsWramSlotLocked_C(int num)652 BOOL MI_IsWramSlotLocked_C( int num )
653 {
654 SDK_ASSERT( 0<=num && num<MI_WRAM_C_MAX_NUM );
655
656 return ( reg_MI_MBK_C_LOCK & (1 << (num+REG_MI_MBK_C_LOCK_C0_SHIFT)) )? TRUE: FALSE;
657 }
MI_IsWramSlotLocked(MIWramPos wram,int num)658 BOOL MI_IsWramSlotLocked( MIWramPos wram, int num )
659 {
660 static BOOL (*f[3])( int ) =
661 {
662 MI_IsWramSlotLocked_A, MI_IsWramSlotLocked_B, MI_IsWramSlotLocked_C
663 };
664 SDK_ASSERT( 0<=wram && wram<3 );
665 return (f[wram])( num );
666 }
667
668
669 //================================================================================
670 // WRAM manager
671 //================================================================================
672 #define MIi_PXI_COMMAND_ALLOC 1
673 #define MIi_PXI_COMMAND_ALLOC_SLOT 2
674
675 #define MIi_PXI_COMMAND_FREE 3
676 #define MIi_PXI_COMMAND_FREE_SLOT 4
677
678 #define MIi_PXI_COMMAND_SWITCH 5
679 #define MIi_PXI_COMMAND_SWITCH_SLOT 6
680
681 #define MIi_PXI_COMMAND_RESERVE 7
682 #define MIi_PXI_COMMAND_RESERVE_SLOT 8
683
684 #define MIi_PXI_COMMAND_CANCEL 9
685 #define MIi_PXI_COMMAND_CANCEL_SLOT 10
686
687 #define MIi_PXI_COMMAND_GET_RESERVE 11
688
689 #define MIi_PXI_COMMAND_LOCKWRAM 12 // arm9->arm7
690 #define MIi_PXI_COMMAND_UNLOCKWRAM 13 // arm9->arm7
691
692 #define MIi_PXI_COMMAND_GET_ALLOCATABLE 14
693
694 #define MIi_SENDTYPE_COMMAND (FALSE)
695 #define MIi_SENDTYPE_RESULT (TRUE)
696
697 static void MIi_CallbackForPxi( PXIFifoTag tag, u32 data, BOOL sendType );
698
699 static int MIi_LockForPxi( volatile BOOL* finishFlag, u32* ptr );
700 static void MIi_WaitWhileBusy( volatile BOOL* finished );
701 static void MIi_SendToPxi( BOOL sendType, u32 data );
702
703 static u32 MIi_MakeData( u32 command, MIWramPos wram, MIWramProc proc, u32 data );
704 static void MIi_TakeApartData( u32 pxiData, u32* command, MIWramPos* wram, MIWramProc* proc, u32* data );
705
706 static BOOL lock = FALSE;
707 static volatile BOOL* finishPtr = FALSE;
708 static u32* resultPtr = NULL;
709
710 static u32 MIi_DoAllocWram( MIWramPos wram, MIWramSize size, MIWramProc proc );
711 static u32 MIi_DoAllocWramSlot( MIWramPos wram, int slot, MIWramSize size, MIWramProc proc );
712 static int MIi_DoFreeWram( MIWramPos wram, MIWramProc proc );
713 static int MIi_DoFreeWramSlot( MIWramPos wram, int slot, MIWramSize size, MIWramProc proc );
714 static int MIi_DoSwitchWram( MIWramPos wram, MIWramProc proc, MIWramProc newProc );
715 static int MIi_DoSwitchWramSlot( MIWramPos wram, int slot, MIWramSize size, MIWramProc proc, MIWramProc newProc );
716 static u32 MIi_DoReserveWram( MIWramPos wram, MIWramSize size, MIWramProc proc );
717 static u32 MIi_DoReserveWramSlot( MIWramPos wram, int slot, MIWramSize size, MIWramProc proc );
718 static int MIi_DoCancelWram( MIWramPos wram, MIWramProc proc );
719 static int MIi_DoCancelWramSlot( MIWramPos wram, int slot, MIWramSize size, MIWramProc proc );
720 static int MIi_DoLockWramSlots( MIWramPos wram, u32 slots );
721 static int MIi_DoUnlockWramSlots( MIWramPos wram, u32 slots );
722 static int MIi_DoGetAllocatableWramSlot( MIWramPos wram, MIWramProc proc );
723
724 static OSIntrMode MIi_LockWramManagerDI( u16* lockid );
725 static void MIi_UnlockWramManagerRI( u16 lockid, OSIntrMode e );
726
727 //----------------------------------------------------------------
728 // manager info
729 //----------------------------------------------------------------
730 #ifdef SDK_ARM9
731 //---- wram status
732 static struct
733 {
734 u16 wram[3][MI_WRAM_B_MAX_NUM];
735 } MIi_Info;
736
737 #define MI_MAN_WRAM_RESERVE_SHIFT 8
738 #define MI_MAN_WRAM_MASTER_SHIFT 0
739
740 #define MI_MAN_WRAM_RESERVE_MASK (3<<MI_MAN_WRAM_RESERVE_SHIFT)
741 #define MI_MAN_WRAM_MASTER_MASK (3<<MI_MAN_WRAM_MASTER_SHIFT)
742
743 //---- reservation
MIi_GetReservation(MIWramPos wram,int num)744 static inline int MIi_GetReservation( MIWramPos wram, int num )
745 {
746 return (MIi_Info.wram[wram][num] & MI_MAN_WRAM_RESERVE_MASK)>>MI_MAN_WRAM_RESERVE_SHIFT;
747 }
748 #define MIi_GetReservation_A(num) (MIi_GetReservation( MI_WRAM_A, (num) ))
749 #define MIi_GetReservation_B(num) (MIi_GetReservation( MI_WRAM_B, (num) ))
750 #define MIi_GetReservation_C(num) (MIi_GetReservation( MI_WRAM_C, (num) ))
751
MIi_SetReservation(MIWramPos wram,int num,int val)752 static inline void MIi_SetReservation( MIWramPos wram, int num, int val)
753 {
754 MIi_Info.wram[wram][num] = (u16)(MIi_Info.wram[wram][num]
755 & ~MI_MAN_WRAM_RESERVE_MASK
756 | (val<<MI_MAN_WRAM_RESERVE_SHIFT));
757 }
758 #define MIi_SetReservation_A(num,val) do{ MIi_SetReservation( MI_WRAM_A, (num), (val) ); } while(0)
759 #define MIi_SetReservation_B(num,val) do{ MIi_SetReservation( MI_WRAM_B, (num), (val) ); } while(0)
760 #define MIi_SetReservation_C(num,val) do{ MIi_SetReservation( MI_WRAM_C, (num), (val) ); } while(0)
761 //---- master
MIi_GetMaster(MIWramPos wram,int num)762 static inline int MIi_GetMaster( MIWramPos wram, int num )
763 {
764 return (MIi_Info.wram[wram][num] & MI_MAN_WRAM_MASTER_MASK)>>MI_MAN_WRAM_MASTER_SHIFT;
765 }
766 #define MIi_GetMaster_A(num) (MIi_GetMaster( MI_WRAM_A, (num) ))
767 #define MIi_GetMaster_B(num) (MIi_GetMaster( MI_WRAM_B, (num) ))
768 #define MIi_GetMaster_C(num) (MIi_GetMaster( MI_WRAM_C, (num) ))
769
MIi_SetMaster(MIWramPos wram,int num,int val)770 static inline void MIi_SetMaster( MIWramPos wram, int num, int val)
771 {
772 MIi_Info.wram[wram][num] = (u16)(MIi_Info.wram[wram][num]
773 & ~MI_MAN_WRAM_MASTER_MASK
774 | (val<<MI_MAN_WRAM_MASTER_SHIFT));
775 }
776 #define MIi_SetMaster_A(num,val) do{ MIi_SetMaster( MI_WRAM_A, (num), (val) ); } while(0)
777 #define MIi_SetMaster_B(num,val) do{ MIi_SetMaster( MI_WRAM_B, (num), (val) ); } while(0)
778 #define MIi_SetMaster_C(num,val) do{ MIi_SetMaster( MI_WRAM_C, (num), (val) ); } while(0)
779 #endif
780
781 //---- address
MIi_GetAddress_A(int num)782 static u32 MIi_GetAddress_A( int num )
783 {
784 return (u32)(MI_GetWramMapStart_A() + MI_WRAM_A_SLOT_SIZE * num );
785 }
MIi_GetAddress_B(int num)786 static u32 MIi_GetAddress_B( int num )
787 {
788 return (u32)(MI_GetWramMapStart_B() + MI_WRAM_B_SLOT_SIZE * num );
789 }
MIi_GetAddress_C(int num)790 static u32 MIi_GetAddress_C( int num )
791 {
792 return (u32)(MI_GetWramMapStart_C() + MI_WRAM_C_SLOT_SIZE * num );
793 }
MIi_GetAddress(MIWramPos wram,int num)794 static inline u32 MIi_GetAddress( MIWramPos wram, int num )
795 {
796 if (wram == MI_WRAM_A)
797 {
798 return MIi_GetAddress_A( num );
799 }
800 if (wram == MI_WRAM_B)
801 {
802 return MIi_GetAddress_B( num );
803 }
804 if (wram == MI_WRAM_C)
805 {
806 return MIi_GetAddress_C( num );
807
808 }
809 return 0;
810 }
811
812 /*---------------------------------------------------------------------------*
813 Name: MI_InitWramManager
814
815 Description: Initializes the WRAM manager on ARM7
816
817 Arguments: None.
818
819 Returns: None.
820 *---------------------------------------------------------------------------*/
MIi_InitWramManager(void)821 static void MIi_InitWramManager(void)
822 {
823 static BOOL sInitialized = FALSE;
824
825 #ifdef SDK_ARM9
826 int n;
827 #endif
828
829 if ( sInitialized )
830 {
831 return;
832 }
833 sInitialized = TRUE;
834
835 #ifdef SDK_ARM9
836 //---- wramA setting
837 for( n=0; n<MI_WRAM_A_MAX_NUM; n++ )
838 {
839 u8 val = MIi_GetWramBank_A(n);
840 switch( val & 1 )
841 {
842 case 0:
843 MIi_SetReservation_A( n, MI_WRAM_ARM9 );
844 MIi_SetMaster_A( n, MI_WRAM_ARM9 );
845 break;
846 case 1:
847 MIi_SetReservation_A( n, MI_WRAM_ARM7 );
848 MIi_SetMaster_A( n, MI_WRAM_ARM7 );
849 break;
850 }
851 }
852
853 //---- wramB setting
854 for( n=0; n<MI_WRAM_B_MAX_NUM; n++ )
855 {
856 u8 val = MIi_GetWramBank_B(n);
857 switch( val & 3 )
858 {
859 case 0:
860 MIi_SetReservation_B( n, MI_WRAM_ARM9 );
861 MIi_SetMaster_B( n, MI_WRAM_ARM9 );
862 break;
863 case 1:
864 MIi_SetReservation_B( n, MI_WRAM_ARM7 );
865 MIi_SetMaster_B( n, MI_WRAM_ARM7 );
866 break;
867 default:
868 MIi_SetReservation_B( n, MI_WRAM_DSP );
869 MIi_SetMaster_B( n, MI_WRAM_DSP );
870 break;
871 }
872 }
873
874
875
876 //---- wramC setting
877 for( n=0; n<MI_WRAM_C_MAX_NUM; n++ )
878 {
879 u8 val = MIi_GetWramBank_C(n);
880 switch( val & 3 )
881 {
882 case 0:
883 MIi_SetReservation_C( n, MI_WRAM_ARM9 );
884 MIi_SetMaster_C( n, MI_WRAM_ARM9 );
885 break;
886 case 1:
887 MIi_SetReservation_C( n, MI_WRAM_ARM7 );
888 MIi_SetMaster_C( n, MI_WRAM_ARM7 );
889 break;
890 default:
891 MIi_SetReservation_C( n, MI_WRAM_DSP );
892 MIi_SetMaster_C( n, MI_WRAM_DSP );
893 break;
894 }
895 }
896
897 //---- pxi callback setting
898 PXI_SetFifoRecvCallback( PXI_FIFO_TAG_MI, MIi_CallbackForPxi );
899
900 #else
901 //---- wait for ARM9's preparation
902 while (! PXI_IsCallbackReady(PXI_FIFO_TAG_MI, PXI_PROC_ARM9 ))
903 {
904 SVC_WaitByLoop(1);
905 }
906
907 //---- pxi callback setting
908 PXI_SetFifoRecvCallback( PXI_FIFO_TAG_MI, MIi_CallbackForPxi );
909 #endif
910 }
911
912 /*---------------------------------------------------------------------------*
913 Name: (MIi_CallbackForPxi)
914
915 Description: MI callback for pxi
916
917 Arguments: tag :
918 data:
919 sendType :
920
921 Returns: None.
922 *---------------------------------------------------------------------------*/
MIi_CallbackForPxi(PXIFifoTag tag,u32 data,BOOL sendType)923 static void MIi_CallbackForPxi( PXIFifoTag tag, u32 data, BOOL sendType )
924 {
925 #pragma unused( tag )
926
927 if (sendType == MIi_SENDTYPE_COMMAND)
928 {
929 u32 command, param;
930 MIWramPos wram;
931 MIWramProc proc;
932 u32 retval = 0;
933
934 MIi_TakeApartData( data, &command, &wram, &proc, ¶m );
935 //OS_Printf(" com=%d wram=%d proc=%d param=0x%x\n", command, wram, proc, param );
936
937 #ifdef SDK_ARM9
938 switch( command )
939 {
940 case MIi_PXI_COMMAND_ALLOC:
941 {
942 u32 size = (param>>8) & 0xff;
943 retval = MIi_DoAllocWram( wram, (MIWramSize)size, proc );
944 }
945 break;
946 case MIi_PXI_COMMAND_ALLOC_SLOT:
947 {
948 int slot = (int)(param>>8) & 0xff;
949 MIWramSize size = (MIWramSize)(param & 0xff);
950 retval = MIi_DoAllocWramSlot( wram, slot, size, proc );
951 }
952 break;
953 case MIi_PXI_COMMAND_FREE:
954 {
955 retval = (u32)MIi_DoFreeWram( wram, proc );
956 }
957 break;
958 case MIi_PXI_COMMAND_FREE_SLOT:
959 {
960 int slot = (int)((param>>8) & 0xff);
961 MIWramSize size = (MIWramSize)(param & 0xff);
962 retval = (u32)MIi_DoFreeWramSlot( wram, slot, size, proc );
963 }
964 break;
965 case MIi_PXI_COMMAND_SWITCH:
966 {
967 MIWramProc newProc = (MIWramProc)((param>>12) & 3);
968 retval = (u32)MIi_DoSwitchWram( wram, proc, newProc );
969 }
970 break;
971 case MIi_PXI_COMMAND_SWITCH_SLOT:
972 {
973 int slot = (int)((param>>8) & 0xf);
974 MIWramSize size = (MIWramSize)(param & 0xff);
975 MIWramProc newProc = (MIWramProc)((param>>12) & 3);
976 retval = (u32)MIi_DoSwitchWramSlot( wram, slot, size, proc, newProc );
977 }
978 break;
979 case MIi_PXI_COMMAND_RESERVE:
980 {
981 u32 size = (param & 0xff);
982 retval = MIi_DoReserveWram( wram, (MIWramSize)size, proc );
983 }
984 break;
985 case MIi_PXI_COMMAND_RESERVE_SLOT:
986 {
987 int slot = (int)((param>>8) & 0xff);
988 MIWramSize size = (MIWramSize)(param & 0xff);
989 retval = MIi_DoReserveWramSlot( wram, slot, size, proc );
990 }
991 break;
992 case MIi_PXI_COMMAND_CANCEL:
993 {
994 retval = (u32)MIi_DoCancelWram( wram, proc );
995 }
996 break;
997 case MIi_PXI_COMMAND_CANCEL_SLOT:
998 {
999 int slot = (int)((param>>8) & 0xff);
1000 MIWramSize size = (MIWramSize)(param & 0xff);
1001 retval = (u32)MIi_DoCancelWramSlot( wram, slot, size, proc );
1002 }
1003 break;
1004 case MIi_PXI_COMMAND_GET_RESERVE:
1005 {
1006 retval = (u32)MIi_GetReservation( wram, (int)param );
1007 }
1008 break;
1009 case MIi_PXI_COMMAND_GET_ALLOCATABLE:
1010 {
1011 retval = (u8)MIi_DoGetAllocatableWramSlot( wram, proc );
1012 }
1013 break;
1014 }
1015 #else
1016 switch( command )
1017 {
1018 case MIi_PXI_COMMAND_LOCKWRAM:
1019 {
1020 retval = (u32)MIi_DoLockWramSlots( wram, param );
1021 }
1022 break;
1023 case MIi_PXI_COMMAND_UNLOCKWRAM:
1024 {
1025 retval = (u32)MIi_DoUnlockWramSlots( wram, param );
1026 }
1027 break;
1028 }
1029 #endif
1030 MIi_SendToPxi( MIi_SENDTYPE_RESULT, retval );
1031 }
1032 else
1033 {
1034 if ( resultPtr )
1035 {
1036 *resultPtr = data;
1037 }
1038 if ( finishPtr )
1039 {
1040 *finishPtr = TRUE;
1041 }
1042
1043 //---- unlock
1044 lock = FALSE;
1045 }
1046 }
1047
1048 /*---------------------------------------------------------------------------*
1049 Name: MI_AllocWram
1050
1051 Description: allocate WRAM slot
1052
1053 Arguments: wram wram position
1054 MI_WRAM_A : WRAM A
1055 MI_WRAM_B : WRAM B
1056 MI_WRAM_C : WRAM C
1057 size: size to allocate
1058 (for WRAM_A)
1059 MI_WRAM_SIZE_0KB : 0KB
1060 MI_WRAM_SIZE_64KB : 64KB
1061 MI_WRAM_SIZE_128KB : 128KB
1062 MI_WRAM_SIZE_192KB : 192KB
1063 MI_WRAM_SIZE_256KB : 256KB
1064
1065 (for WRAM_B and WRAM_C)
1066 MI_WRAM_SIZE_0KB : 0KB
1067 MI_WRAM_SIZE_32KB : 16KB
1068 MI_WRAM_SIZE_64KB : 32KB
1069 MI_WRAM_SIZE_96KB : 64KB
1070 MI_WRAM_SIZE_128KB : 128KB
1071 MI_WRAM_SIZE_160KB : 160KB
1072 MI_WRAM_SIZE_192KB : 192KB
1073 MI_WRAM_SIZE_224KB : 224KB
1074 MI_WRAM_SIZE_256KB : 256KB
1075 proc : processor
1076 MI_WRAM_ARM9 : ARM9
1077 MI_WRAM_ARM7 : ARM7
1078 MI_WRAM_DSP : DSP
1079
1080 Returns: top address of allocated WRAM
1081 0 : failure
1082 *---------------------------------------------------------------------------*/
MI_AllocWram(MIWramPos wram,MIWramSize size,MIWramProc proc)1083 u32 MI_AllocWram( MIWramPos wram, MIWramSize size, MIWramProc proc )
1084 {
1085 u32 result;
1086 u16 lockid;
1087
1088 OSIntrMode e = MIi_LockWramManagerDI( &lockid );
1089 result = MIi_DoAllocWram( wram, size, proc );
1090 MIi_UnlockWramManagerRI( lockid, e );
1091
1092 return result;
1093 }
1094
1095 //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MIi_DoAllocWram(MIWramPos wram,MIWramSize size,MIWramProc proc)1096 static u32 MIi_DoAllocWram( MIWramPos wram, MIWramSize size, MIWramProc proc )
1097 {
1098 #ifdef SDK_ARM9
1099 int blocks = (int)( (wram == MI_WRAM_A)? (size/2): size );
1100 int allocated = 0;
1101 int firstBlock;
1102 int n;
1103 int maxNum = (wram == MI_WRAM_A)? MI_WRAM_A_MAX_NUM: MI_WRAM_B_MAX_NUM;
1104
1105 for( n=0; n<maxNum; n++ )
1106 {
1107 int master = MIi_GetMaster( wram, n );
1108 int reserve = MIi_GetReservation( wram, n );
1109
1110 if ( master == MI_WRAM_FREE && (reserve == proc || reserve == MI_WRAM_FREE) )
1111 {
1112 if ( allocated == 0 )
1113 {
1114 firstBlock = n;
1115 }
1116
1117 if ( ++ allocated >= blocks )
1118 {
1119 break;
1120 }
1121 }
1122 else
1123 {
1124 allocated = 0;
1125 }
1126 }
1127
1128 //---- no space not enough to alloc
1129 if ( allocated < blocks )
1130 {
1131 return 0;
1132 }
1133
1134 for( n=0; n<blocks; n++ )
1135 {
1136 MIi_SetMaster(wram, firstBlock+n, proc);
1137 MIi_SetWramBankMaster( wram, firstBlock+n, proc);
1138 MIi_SetWramBankEnable( wram, firstBlock+n, MI_WRAM_ENABLE );
1139 }
1140
1141 return MIi_GetAddress(wram, firstBlock);
1142
1143 #else
1144 volatile BOOL finished = FALSE;
1145 u32 result;
1146
1147 if ( ! MIi_LockForPxi( &finished, &result ) )
1148 {
1149 result = 0;
1150 }
1151 else
1152 {
1153 u32 data = MIi_MakeData( MIi_PXI_COMMAND_ALLOC, wram, proc, (u32)(size<<8) );
1154 MIi_SendToPxi( MIi_SENDTYPE_COMMAND, data );
1155 MIi_WaitWhileBusy( &finished );
1156 }
1157 return result;
1158 #endif
1159 }
1160
1161 /*---------------------------------------------------------------------------*
1162 Name: MI_AllocWramSlot
1163
1164 Description: Allocates specified WRAM slot
1165
1166 Arguments: wram wram position
1167 MI_WRAM_A : WRAM A
1168 MI_WRAM_B : WRAM B
1169 MI_WRAM_C : WRAM C
1170 slot: wram slot
1171 (A)0-3, (B,C)0-7
1172 size: size to allocate
1173 MI_WRAM_SIZE_xxKB
1174
1175 proc : processor
1176 MI_WRAM_ARM9 : ARM9
1177 MI_WRAM_ARM7 : ARM7
1178 MI_WRAM_DSP : DSP
1179
1180 Returns: top address of allocated WRAM
1181 0 : failure
1182 *---------------------------------------------------------------------------*/
MI_AllocWramSlot(MIWramPos wram,int slot,MIWramSize size,MIWramProc proc)1183 u32 MI_AllocWramSlot( MIWramPos wram, int slot, MIWramSize size, MIWramProc proc )
1184 {
1185 u32 result;
1186 u16 lockid;
1187
1188 OSIntrMode e = MIi_LockWramManagerDI( &lockid );
1189 result = MIi_DoAllocWramSlot( wram, slot, size, proc );
1190 MIi_UnlockWramManagerRI( lockid, e );
1191
1192 return result;
1193 }
1194
1195 //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MIi_DoAllocWramSlot(MIWramPos wram,int slot,MIWramSize size,MIWramProc proc)1196 static u32 MIi_DoAllocWramSlot( MIWramPos wram, int slot, MIWramSize size, MIWramProc proc )
1197 {
1198 #ifdef SDK_ARM9
1199 int blocks = (int)( (wram == MI_WRAM_A)? (size/2): size );
1200 int n;
1201 int maxNum = (wram == MI_WRAM_A)? MI_WRAM_A_MAX_NUM: MI_WRAM_B_MAX_NUM;
1202
1203 SDK_ASSERT( 0 <= slot && slot < maxNum );
1204
1205 for( n=slot; n<slot+blocks; n++ )
1206 {
1207 int reserve = MIi_GetReservation( wram, n );
1208 int master = MIi_GetMaster( wram, n );
1209
1210 if ( master == MI_WRAM_FREE && (reserve == proc || reserve == MI_WRAM_FREE) )
1211 {
1212 // do nothing
1213 }
1214 else
1215 {
1216 return 0;
1217 }
1218 }
1219
1220 for( n=slot; n<slot+blocks; n++ )
1221 {
1222 MIi_SetMaster(wram, n, proc);
1223 MIi_SetWramBankMaster( wram, n, proc);
1224 MIi_SetWramBankEnable( wram, n, MI_WRAM_ENABLE );
1225 }
1226
1227 return MIi_GetAddress(wram, slot);
1228
1229 #else
1230 volatile BOOL finished = FALSE;
1231 u32 result;
1232
1233 if ( ! MIi_LockForPxi( &finished, &result ) )
1234 {
1235 result = 0;
1236 }
1237 else
1238 {
1239 u32 data = MIi_MakeData( MIi_PXI_COMMAND_ALLOC_SLOT, wram, proc, (u32)(slot<<8)|size );
1240 MIi_SendToPxi( MIi_SENDTYPE_COMMAND, data );
1241 MIi_WaitWhileBusy( &finished );
1242 }
1243 return result;
1244 #endif
1245 }
1246
1247 /*---------------------------------------------------------------------------*
1248 Name: MI_FreeWram
1249
1250 Description: Deallocates WRAM
1251
1252 Arguments: wram wram position
1253 MI_WRAM_A : WRAM A
1254 MI_WRAM_B : WRAM B
1255 MI_WRAM_C : WRAM C
1256
1257 proc : processor
1258 MI_WRAM_ARM9 : ARM9
1259 MI_WRAM_ARM7 : ARM7
1260 MI_WRAM_DSP : DSP
1261
1262 Returns: number of blocks set to be allocated.
1263 -1 means failure
1264 *---------------------------------------------------------------------------*/
MI_FreeWram(MIWramPos wram,MIWramProc proc)1265 int MI_FreeWram( MIWramPos wram, MIWramProc proc )
1266 {
1267 int result;
1268 u16 lockid;
1269
1270 OSIntrMode e = MIi_LockWramManagerDI( &lockid );
1271 result = MIi_DoFreeWram( wram, proc );
1272 MIi_UnlockWramManagerRI( lockid, e );
1273
1274 return result;
1275 }
1276
1277 //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MIi_DoFreeWram(MIWramPos wram,MIWramProc proc)1278 static int MIi_DoFreeWram( MIWramPos wram, MIWramProc proc )
1279 {
1280 #ifdef SDK_ARM9
1281 int n;
1282 int freeCount = 0;
1283 int maxNum = (wram == MI_WRAM_A)? MI_WRAM_A_MAX_NUM: MI_WRAM_B_MAX_NUM;
1284
1285 for( n=0; n<maxNum; n++ )
1286 {
1287 int master = MIi_GetMaster( wram, n );
1288 if ( master == proc )
1289 {
1290 MIi_SetMaster(wram, n, MI_WRAM_FREE);
1291 MIi_SetWramBankMaster(wram, n, MI_WRAM_ARM7/*dummy*/ );
1292 MIi_SetWramBankEnable(wram, n, MI_WRAM_DISABLE );
1293 freeCount ++;
1294 }
1295 }
1296
1297 return freeCount;
1298
1299 #else
1300 volatile BOOL finished = FALSE;
1301 u32 result;
1302
1303 if ( ! MIi_LockForPxi( &finished, &result ) )
1304 {
1305 return -1;
1306 }
1307 else
1308 {
1309 u32 data = MIi_MakeData( MIi_PXI_COMMAND_FREE, wram, proc, 0 );
1310 MIi_SendToPxi( MIi_SENDTYPE_COMMAND, data );
1311 MIi_WaitWhileBusy( &finished );
1312 }
1313 return (int)result;
1314 #endif
1315 }
1316
1317 /*---------------------------------------------------------------------------*
1318 Name: MI_FreeWramSlot
1319
1320 Description: Deallocates WRAM
1321
1322 Arguments: wram wram position
1323 MI_WRAM_A : WRAM A
1324 MI_WRAM_B : WRAM B
1325 MI_WRAM_C : WRAM C
1326 slot: slot number
1327 (for WRAM_A)
1328 0-3
1329 (for WRAM_B and WRAM_C)
1330 0-7
1331 size:
1332 (for WRAM_A)
1333 MI_WRAM_SIZE_0KB : 0KB
1334 MI_WRAM_SIZE_64KB : 64KB
1335 MI_WRAM_SIZE_128KB : 128KB
1336 MI_WRAM_SIZE_192KB : 192KB
1337 MI_WRAM_SIZE_256KB : 256KB
1338
1339 (for WRAM_B and WRAM_C)
1340 MI_WRAM_SIZE_0KB : 0KB
1341 MI_WRAM_SIZE_32KB : 16KB
1342 MI_WRAM_SIZE_64KB : 32KB
1343 MI_WRAM_SIZE_96KB : 64KB
1344 MI_WRAM_SIZE_128KB : 128KB
1345 MI_WRAM_SIZE_160KB : 160KB
1346 MI_WRAM_SIZE_192KB : 192KB
1347 MI_WRAM_SIZE_224KB : 224KB
1348 MI_WRAM_SIZE_256KB : 256KB
1349
1350 proc : processor
1351 MI_WRAM_ARM9 : ARM9
1352 MI_WRAM_ARM7 : ARM7
1353 MI_WRAM_DSP : DSP
1354
1355 Returns: number of blocks set to be allocated.
1356 -1 means failure
1357 *---------------------------------------------------------------------------*/
MI_FreeWramSlot(MIWramPos wram,int slot,MIWramSize size,MIWramProc proc)1358 int MI_FreeWramSlot( MIWramPos wram, int slot, MIWramSize size, MIWramProc proc )
1359 {
1360 int result;
1361 u16 lockid;
1362
1363 OSIntrMode e = MIi_LockWramManagerDI( &lockid );
1364 result = MIi_DoFreeWramSlot( wram, slot, size, proc );
1365 MIi_UnlockWramManagerRI( lockid, e );
1366
1367 return result;
1368 }
1369
1370 //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MIi_DoFreeWramSlot(MIWramPos wram,int slot,MIWramSize size,MIWramProc proc)1371 static int MIi_DoFreeWramSlot( MIWramPos wram, int slot, MIWramSize size, MIWramProc proc )
1372 {
1373 #ifdef SDK_ARM9
1374 int blocks = (int)( (wram == MI_WRAM_A)? (size/2): size );
1375 int n;
1376 int freeCount = 0;
1377
1378 for( n=slot; n<slot+blocks; n++ )
1379 {
1380 int master = MIi_GetMaster( wram, n );
1381 if ( master == proc )
1382 {
1383 MIi_SetMaster(wram, n, MI_WRAM_FREE);
1384 MIi_SetWramBankMaster(wram, n, MI_WRAM_ARM7/*dummy*/ );
1385 MIi_SetWramBankEnable(wram, n, MI_WRAM_DISABLE );
1386 freeCount ++;
1387 }
1388 }
1389
1390 return freeCount;
1391
1392 #else
1393 volatile BOOL finished = FALSE;
1394 u32 result;
1395
1396 if ( ! MIi_LockForPxi( &finished, &result ) )
1397 {
1398 return -1;
1399 }
1400 else
1401 {
1402 u32 data = MIi_MakeData( MIi_PXI_COMMAND_FREE_SLOT, wram, proc, (u32)(slot<<8)|size );
1403 MIi_SendToPxi( MIi_SENDTYPE_COMMAND, data );
1404 MIi_WaitWhileBusy( &finished );
1405 }
1406 return (int)result;
1407 #endif
1408 }
1409
1410 /*---------------------------------------------------------------------------*
1411 Name: MI_SwitchWram
1412
1413 Description: Switches WRAM master
1414
1415 Arguments: wram wram position
1416 MI_WRAM_A : WRAM A
1417 MI_WRAM_B : WRAM B
1418 MI_WRAM_C : WRAM C
1419
1420 proc : processor
1421 MI_WRAM_ARM9 : ARM9
1422 MI_WRAM_ARM7 : ARM7
1423 MI_WRAM_DSP : DSP
1424
1425 newProc : processor
1426 MI_WRAM_ARM9 : ARM9
1427 MI_WRAM_ARM7 : ARM7
1428 MI_WRAM_DSP : DSP
1429
1430 Returns: number of changed slot
1431 -1 means failure
1432 *---------------------------------------------------------------------------*/
MI_SwitchWram(MIWramPos wram,MIWramProc proc,MIWramProc newProc)1433 int MI_SwitchWram( MIWramPos wram, MIWramProc proc, MIWramProc newProc )
1434 {
1435 int result;
1436 u16 lockid;
1437
1438 OSIntrMode e = MIi_LockWramManagerDI( &lockid );
1439 result = MIi_DoSwitchWram( wram, proc, newProc );
1440 MIi_UnlockWramManagerRI( lockid, e );
1441
1442 return result;
1443 }
1444
1445 //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MIi_DoSwitchWram(MIWramPos wram,MIWramProc proc,MIWramProc newProc)1446 static int MIi_DoSwitchWram( MIWramPos wram, MIWramProc proc, MIWramProc newProc )
1447 {
1448 #ifdef SDK_ARM9
1449 int n;
1450 int retval = 0;
1451 int maxNum = (wram == MI_WRAM_A)? MI_WRAM_A_MAX_NUM: MI_WRAM_B_MAX_NUM;
1452
1453 for( n=0; n<maxNum; n++ )
1454 {
1455 int master = MIi_GetMaster( wram, n );
1456 if ( master == proc )
1457 {
1458 MIi_SetMaster(wram, n, newProc);
1459 MIi_SetWramBankMaster(wram, n, newProc );
1460 MIi_SetWramBankEnable(wram, n, MI_WRAM_ENABLE );
1461 retval ++;
1462 }
1463 }
1464 return retval;
1465
1466 #else
1467 volatile BOOL finished = FALSE;
1468 u32 result;
1469
1470 if ( ! MIi_LockForPxi( &finished, &result ) )
1471 {
1472 return -1;
1473 }
1474 else
1475 {
1476 u32 data = MIi_MakeData( MIi_PXI_COMMAND_SWITCH, wram, proc, (u32)(newProc<<12) );
1477 MIi_SendToPxi( MIi_SENDTYPE_COMMAND, data );
1478 MIi_WaitWhileBusy( &finished );
1479 }
1480 return (int)result;
1481 #endif
1482 }
1483
1484 /*---------------------------------------------------------------------------*
1485 Name: MI_SwitchWramSlot
1486
1487 Description: Switches WRAM master
1488
1489 Arguments: wram wram position
1490 MI_WRAM_A : WRAM A
1491 MI_WRAM_B : WRAM B
1492 MI_WRAM_C : WRAM C
1493
1494 slot: slot number
1495 (for WRAM_A)
1496 0-3
1497 (for WRAM_B and WRAM_C)
1498 0-7
1499 size:
1500 (for WRAM_A)
1501 MI_WRAM_SIZE_0KB : 0KB
1502 MI_WRAM_SIZE_64KB : 64KB
1503 MI_WRAM_SIZE_128KB : 128KB
1504 MI_WRAM_SIZE_192KB : 192KB
1505 MI_WRAM_SIZE_256KB : 256KB
1506
1507 (for WRAM_B and WRAM_C)
1508 MI_WRAM_SIZE_0KB : 0KB
1509 MI_WRAM_SIZE_32KB : 16KB
1510 MI_WRAM_SIZE_64KB : 32KB
1511 MI_WRAM_SIZE_96KB : 64KB
1512 MI_WRAM_SIZE_128KB : 128KB
1513 MI_WRAM_SIZE_160KB : 160KB
1514 MI_WRAM_SIZE_192KB : 192KB
1515 MI_WRAM_SIZE_224KB : 224KB
1516 MI_WRAM_SIZE_256KB : 256KB
1517
1518 proc : processor
1519 MI_WRAM_ARM9 : ARM9
1520 MI_WRAM_ARM7 : ARM7
1521 MI_WRAM_DSP : DSP
1522
1523 newProc : processor
1524 MI_WRAM_ARM9 : ARM9
1525 MI_WRAM_ARM7 : ARM7
1526 MI_WRAM_DSP : DSP
1527
1528 Returns: number of changed slot
1529 -1 means failure
1530 *---------------------------------------------------------------------------*/
MI_SwitchWramSlot(MIWramPos wram,int slot,MIWramSize size,MIWramProc proc,MIWramProc newProc)1531 int MI_SwitchWramSlot( MIWramPos wram, int slot, MIWramSize size, MIWramProc proc, MIWramProc newProc )
1532 {
1533 int result;
1534 u16 lockid;
1535
1536 OSIntrMode e = MIi_LockWramManagerDI( &lockid );
1537 result = MIi_DoSwitchWramSlot( wram, slot, size, proc, newProc );
1538 MIi_UnlockWramManagerRI( lockid, e );
1539
1540 return result;
1541 }
1542
1543 //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MIi_DoSwitchWramSlot(MIWramPos wram,int slot,MIWramSize size,MIWramProc proc,MIWramProc newProc)1544 static int MIi_DoSwitchWramSlot( MIWramPos wram, int slot, MIWramSize size, MIWramProc proc, MIWramProc newProc )
1545 {
1546 #ifdef SDK_ARM9
1547 int blocks = (int)( (wram == MI_WRAM_A)? (size/2): size );
1548 int retval = 0;
1549 int n;
1550
1551 for( n=slot; n<slot+blocks; n++ )
1552 {
1553 int master = MIi_GetMaster( wram, n );
1554 if ( master == proc )
1555 {
1556 MIi_SetMaster(wram, n, newProc);
1557 MIi_SetWramBankMaster(wram, n, newProc );
1558 MIi_SetWramBankEnable(wram, n, MI_WRAM_ENABLE );
1559 retval ++;
1560 }
1561 }
1562 return retval;
1563
1564 #else
1565 volatile BOOL finished = FALSE;
1566 u32 result;
1567
1568 if ( ! MIi_LockForPxi( &finished, &result ) )
1569 {
1570 return -1;
1571 }
1572 else
1573 {
1574 u32 data = MIi_MakeData( MIi_PXI_COMMAND_SWITCH_SLOT, wram, proc, (u32)((newProc<<12)|(slot<<8)|(size)) );
1575 MIi_SendToPxi( MIi_SENDTYPE_COMMAND, data );
1576 MIi_WaitWhileBusy( &finished );
1577 }
1578 return (int)result;
1579 #endif
1580 }
1581
1582 /*---------------------------------------------------------------------------*
1583 Name: MI_ReserveWram
1584
1585 Description: Reserves WRAM
1586
1587 Arguments: wram wram position
1588 MI_WRAM_A : WRAM A
1589 MI_WRAM_B : WRAM B
1590 MI_WRAM_C : WRAM C
1591 size: size to reserve
1592 MI_WRAM_SIZE_0KB : 0KB
1593 MI_WRAM_SIZE_32KB : 16KB
1594 MI_WRAM_SIZE_64KB : 32KB
1595 MI_WRAM_SIZE_96KB : 64KB
1596 MI_WRAM_SIZE_128KB : 128KB
1597 MI_WRAM_SIZE_160KB : 160KB
1598 MI_WRAM_SIZE_192KB : 192KB
1599 MI_WRAM_SIZE_224KB : 224KB
1600 MI_WRAM_SIZE_256KB : 256KB
1601 proc : processor
1602 MI_WRAM_ARM9 : ARM9
1603 MI_WRAM_ARM7 : ARM7
1604 MI_WRAM_DSP : DSP
1605
1606 Returns: top address of reserved WRAM
1607 0 means failure
1608 *---------------------------------------------------------------------------*/
MI_ReserveWram(MIWramPos wram,MIWramSize size,MIWramProc proc)1609 u32 MI_ReserveWram( MIWramPos wram, MIWramSize size, MIWramProc proc )
1610 {
1611 u32 result;
1612 u16 lockid;
1613
1614 OSIntrMode e = MIi_LockWramManagerDI( &lockid );
1615 result = MIi_DoReserveWram( wram, size, proc );
1616 MIi_UnlockWramManagerRI( lockid, e );
1617
1618 return result;
1619 }
1620
1621 //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MIi_DoReserveWram(MIWramPos wram,MIWramSize size,MIWramProc proc)1622 static u32 MIi_DoReserveWram( MIWramPos wram, MIWramSize size, MIWramProc proc )
1623 {
1624 #ifdef SDK_ARM9
1625 int blocks = (int)( (wram == MI_WRAM_A)? (size/2): size );
1626 int allocated = 0;
1627 int firstBlock;
1628 int n;
1629 int maxNum = (wram == MI_WRAM_A)? MI_WRAM_A_MAX_NUM: MI_WRAM_B_MAX_NUM;
1630
1631 for( n=0; n<maxNum; n++ )
1632 {
1633 int master = MIi_GetMaster( wram, n );
1634 int reserve = MIi_GetReservation( wram, n );
1635
1636 if ( master == MI_WRAM_FREE && reserve == MI_WRAM_FREE )
1637 {
1638 if ( allocated == 0 )
1639 {
1640 firstBlock = n;
1641 }
1642
1643 if ( ++ allocated >= blocks )
1644 {
1645 break;
1646 }
1647 }
1648 else
1649 {
1650 allocated = 0;
1651 }
1652 }
1653
1654 if ( allocated < blocks )
1655 {
1656 return 0;
1657 }
1658
1659 for( n=0; n<blocks; n++ )
1660 {
1661 MIi_SetReservation(wram, firstBlock+n, proc);
1662 }
1663
1664 return MIi_GetAddress(wram, firstBlock);
1665
1666 #else
1667 u32 result;
1668 volatile BOOL finished = FALSE;
1669
1670 if ( ! MIi_LockForPxi( &finished, &result ) )
1671 {
1672 result = 0;
1673 }
1674 else
1675 {
1676 u32 data = MIi_MakeData( MIi_PXI_COMMAND_RESERVE, wram, proc, size );
1677 MIi_SendToPxi( MIi_SENDTYPE_COMMAND, data );
1678 MIi_WaitWhileBusy( &finished );
1679 }
1680 return result;
1681 #endif
1682 }
1683
1684
1685 /*---------------------------------------------------------------------------*
1686 Name: MI_ReserveWramSlot
1687
1688 Description: Reserves specified WRAM slot
1689
1690 Arguments: wram wram position
1691 MI_WRAM_A : WRAM A
1692 MI_WRAM_B : WRAM B
1693 MI_WRAM_C : WRAM C
1694 slot: wram slot
1695 size: size to reserve
1696 MI_WRAM_SIZE_0KB : 0KB
1697 MI_WRAM_SIZE_32KB : 16KB
1698 MI_WRAM_SIZE_64KB : 32KB
1699 MI_WRAM_SIZE_96KB : 64KB
1700 MI_WRAM_SIZE_128KB : 128KB
1701 MI_WRAM_SIZE_160KB : 160KB
1702 MI_WRAM_SIZE_192KB : 192KB
1703 MI_WRAM_SIZE_224KB : 224KB
1704 MI_WRAM_SIZE_256KB : 256KB
1705 proc : processor
1706 MI_WRAM_ARM9 : ARM9
1707 MI_WRAM_ARM7 : ARM7
1708 MI_WRAM_DSP : DSP
1709
1710 Returns: top address of reserved WRAM
1711 0 means failure
1712 *---------------------------------------------------------------------------*/
MI_ReserveWramSlot(MIWramPos wram,int slot,MIWramSize size,MIWramProc proc)1713 u32 MI_ReserveWramSlot( MIWramPos wram, int slot, MIWramSize size, MIWramProc proc )
1714 {
1715 u32 result;
1716 u16 lockid;
1717
1718 OSIntrMode e = MIi_LockWramManagerDI( &lockid );
1719 result = MIi_DoReserveWramSlot( wram, slot, size, proc );
1720 MIi_UnlockWramManagerRI( lockid, e );
1721
1722 return result;
1723 }
1724
1725 //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MIi_DoReserveWramSlot(MIWramPos wram,int slot,MIWramSize size,MIWramProc proc)1726 static u32 MIi_DoReserveWramSlot( MIWramPos wram, int slot, MIWramSize size, MIWramProc proc )
1727 {
1728 #ifdef SDK_ARM9
1729 int blocks = (int)( (wram == MI_WRAM_A)? (size/2): size );
1730 int n;
1731 int maxNum = (wram == MI_WRAM_A)? MI_WRAM_A_MAX_NUM: MI_WRAM_B_MAX_NUM;
1732
1733 SDK_ASSERT( 0 <= slot && slot < maxNum );
1734
1735 for( n=slot; n<slot+blocks; n++ )
1736 {
1737 int master = MIi_GetMaster( wram, slot );
1738 int reserve = MIi_GetReservation( wram, slot );
1739
1740 if ( master == MI_WRAM_FREE && reserve == MI_WRAM_FREE )
1741 {
1742 // do nothing
1743 }
1744 else
1745 {
1746 return 0;
1747 }
1748 }
1749
1750 for( n=slot; n<slot+blocks; n++ )
1751 {
1752 MIi_SetReservation(wram, n, proc);
1753 }
1754
1755 return MIi_GetAddress(wram, slot);
1756
1757 #else
1758 u32 result;
1759 volatile BOOL finished = FALSE;
1760
1761 if ( ! MIi_LockForPxi( &finished, &result ) )
1762 {
1763 result = 0;
1764 }
1765 else
1766 {
1767 u32 data = MIi_MakeData( MIi_PXI_COMMAND_RESERVE_SLOT, wram, proc, (u32)(slot<<8)|size );
1768 MIi_SendToPxi( MIi_SENDTYPE_COMMAND, data );
1769 MIi_WaitWhileBusy( &finished );
1770 }
1771 return result;
1772 #endif
1773 }
1774
1775 /*---------------------------------------------------------------------------*
1776 Name: MI_CancelWram
1777
1778 Description: Cancels reserved WRAM
1779
1780 Arguments: wram wram position
1781 MI_WRAM_A : WRAM A
1782 MI_WRAM_B : WRAM B
1783 MI_WRAM_C : WRAM C
1784 proc : processor
1785 MI_WRAM_ARM9 : ARM9
1786 MI_WRAM_ARM7 : ARM7
1787 MI_WRAM_DSP : DSP
1788
1789 Returns: number of canceled blocks
1790 -1 means failure
1791 *---------------------------------------------------------------------------*/
MI_CancelWram(MIWramPos wram,MIWramProc proc)1792 int MI_CancelWram( MIWramPos wram, MIWramProc proc )
1793 {
1794 int result;
1795 u16 lockid;
1796
1797 OSIntrMode e = MIi_LockWramManagerDI( &lockid );
1798 result = MIi_DoCancelWram( wram, proc );
1799 MIi_UnlockWramManagerRI( lockid, e );
1800
1801 return result;
1802 }
1803
1804 //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MIi_DoCancelWram(MIWramPos wram,MIWramProc proc)1805 static int MIi_DoCancelWram( MIWramPos wram, MIWramProc proc )
1806 {
1807 #ifdef SDK_ARM9
1808 int retval = 0;
1809 int maxNum = (wram == MI_WRAM_A)? MI_WRAM_A_MAX_NUM: MI_WRAM_B_MAX_NUM;
1810 int n;
1811
1812 for( n=0; n<maxNum; n++ )
1813 {
1814 if (MIi_GetReservation(wram,n) == proc)
1815 {
1816 MIi_SetReservation(wram, n, MI_WRAM_FREE);
1817 retval ++;
1818 }
1819 }
1820 return retval;
1821
1822 #else
1823 volatile BOOL finished = FALSE;
1824 u32 result;
1825
1826 if ( ! MIi_LockForPxi( &finished, &result ) )
1827 {
1828 return -1;
1829 }
1830 else
1831 {
1832 u32 data = MIi_MakeData( MIi_PXI_COMMAND_CANCEL, wram, proc, 0 );
1833 MIi_SendToPxi( MIi_SENDTYPE_COMMAND, data );
1834 MIi_WaitWhileBusy( &finished );
1835 }
1836 return (int)result;
1837 #endif
1838 }
1839
1840 /*---------------------------------------------------------------------------*
1841 Name: MI_CancelWramSlot
1842
1843 Description: Cancels reserved WRAM
1844
1845 Arguments: wram wram position
1846 MI_WRAM_A : WRAM A
1847 MI_WRAM_B : WRAM B
1848 MI_WRAM_C : WRAM C
1849
1850 slot: slot number
1851 (for WRAM_A)
1852 0-3
1853 (for WRAM_B and WRAM_C)
1854 0-7
1855 size:
1856 (for WRAM_A)
1857 MI_WRAM_SIZE_0KB : 0KB
1858 MI_WRAM_SIZE_64KB : 64KB
1859 MI_WRAM_SIZE_128KB : 128KB
1860 MI_WRAM_SIZE_192KB : 192KB
1861 MI_WRAM_SIZE_256KB : 256KB
1862
1863 (for WRAM_B and WRAM_C)
1864 MI_WRAM_SIZE_0KB : 0KB
1865 MI_WRAM_SIZE_32KB : 16KB
1866 MI_WRAM_SIZE_64KB : 32KB
1867 MI_WRAM_SIZE_96KB : 64KB
1868 MI_WRAM_SIZE_128KB : 128KB
1869 MI_WRAM_SIZE_160KB : 160KB
1870 MI_WRAM_SIZE_192KB : 192KB
1871 MI_WRAM_SIZE_224KB : 224KB
1872 MI_WRAM_SIZE_256KB : 256KB
1873
1874 proc : processor
1875 MI_WRAM_ARM9 : ARM9
1876 MI_WRAM_ARM7 : ARM7
1877 MI_WRAM_DSP : DSP
1878
1879 Returns: number of canceled blocks
1880 -1 means failure
1881 *---------------------------------------------------------------------------*/
MI_CancelWramSlot(MIWramPos wram,int slot,MIWramSize size,MIWramProc proc)1882 int MI_CancelWramSlot( MIWramPos wram, int slot, MIWramSize size, MIWramProc proc )
1883 {
1884 int result;
1885 u16 lockid;
1886
1887 OSIntrMode e = MIi_LockWramManagerDI( &lockid );
1888 result = MIi_DoCancelWramSlot( wram, slot, size, proc );
1889 MIi_UnlockWramManagerRI( lockid, e );
1890
1891 return result;
1892 }
1893
1894 //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MIi_DoCancelWramSlot(MIWramPos wram,int slot,MIWramSize size,MIWramProc proc)1895 static int MIi_DoCancelWramSlot( MIWramPos wram, int slot, MIWramSize size, MIWramProc proc )
1896 {
1897 #ifdef SDK_ARM9
1898 int blocks = (int)( (wram == MI_WRAM_A)? (size/2): size );
1899 int retval = 0;
1900 int n;
1901 int maxNum = (wram == MI_WRAM_A)? MI_WRAM_A_MAX_NUM: MI_WRAM_B_MAX_NUM;
1902
1903 for( n=slot; n<slot+blocks; n++ )
1904 {
1905 if (MIi_GetReservation(wram,n) == proc)
1906 {
1907 MIi_SetReservation(wram, n, MI_WRAM_FREE);
1908 retval ++;
1909 }
1910 }
1911 return retval;
1912
1913 #else
1914 volatile BOOL finished = FALSE;
1915 u32 result;
1916
1917 if ( ! MIi_LockForPxi( &finished, &result ) )
1918 {
1919 return -1;
1920 }
1921 else
1922 {
1923 u32 data = MIi_MakeData( MIi_PXI_COMMAND_CANCEL_SLOT, wram, proc, (u32)(slot<<8)|size );
1924 MIi_SendToPxi( MIi_SENDTYPE_COMMAND, data );
1925 MIi_WaitWhileBusy( &finished );
1926 }
1927 return (int)result;
1928 #endif
1929 }
1930
1931 /*---------------------------------------------------------------------------*
1932 Name: MI_LockWramSlot
1933
1934 Description: Locks WRAM slot
1935
1936 Arguments: wram wram position
1937 MI_WRAM_A : WRAM A
1938 MI_WRAM_B : WRAM B
1939 MI_WRAM_C : WRAM C
1940 slots: slot to lock
1941
1942 Returns: 0 if success
1943 -1 means filer
1944 *---------------------------------------------------------------------------*/
MI_LockWramSlots(MIWramPos wram,u32 slots)1945 int MI_LockWramSlots( MIWramPos wram, u32 slots )
1946 {
1947 int result;
1948 u16 lockid;
1949
1950 OSIntrMode e = MIi_LockWramManagerDI( &lockid );
1951 result = MIi_DoLockWramSlots( wram, slots );
1952 MIi_UnlockWramManagerRI( lockid, e );
1953
1954 return result;
1955 }
1956
1957 //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MIi_DoLockWramSlots(MIWramPos wram,u32 slots)1958 static int MIi_DoLockWramSlots( MIWramPos wram, u32 slots )
1959 {
1960 #ifdef SDK_ARM9
1961 u32 result;
1962 volatile BOOL finished = FALSE;
1963
1964 if ( ! MIi_LockForPxi( &finished, &result ) )
1965 {
1966 return -1;
1967 }
1968 else
1969 {
1970 u32 data = MIi_MakeData( MIi_PXI_COMMAND_LOCKWRAM, wram, (MIWramProc)0, slots );
1971 MIi_SendToPxi( MIi_SENDTYPE_COMMAND, data );
1972 MIi_WaitWhileBusy( &finished );
1973 }
1974 return (int)result;
1975
1976 #else
1977 switch( wram )
1978 {
1979 case MI_WRAM_A:
1980 reg_MI_MBK_A_LOCK |= slots;
1981 break;
1982 case MI_WRAM_B:
1983 reg_MI_MBK_B_LOCK |= slots;
1984 break;
1985 case MI_WRAM_C:
1986 reg_MI_MBK_C_LOCK |= slots;
1987 break;
1988 }
1989
1990 return 0;
1991 #endif
1992 }
1993
1994 /*---------------------------------------------------------------------------*
1995 Name: MI_UnlockWramSlot
1996
1997 Description: Unlocks WRAM slot
1998
1999 Arguments: wram wram position
2000 MI_WRAM_A : WRAM A
2001 MI_WRAM_B : WRAM B
2002 MI_WRAM_C : WRAM C
2003 slots: slot to unlock
2004
2005 Returns: 0 if success
2006 -1 means filer
2007 *---------------------------------------------------------------------------*/
MI_UnlockWramSlots(MIWramPos wram,u32 slots)2008 int MI_UnlockWramSlots( MIWramPos wram, u32 slots )
2009 {
2010 int result;
2011 u16 lockid;
2012
2013 OSIntrMode e = MIi_LockWramManagerDI( &lockid );
2014 result = MIi_DoUnlockWramSlots( wram, slots );
2015 MIi_UnlockWramManagerRI( lockid, e );
2016
2017 return result;
2018 }
2019
2020 //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MIi_DoUnlockWramSlots(MIWramPos wram,u32 slots)2021 static int MIi_DoUnlockWramSlots( MIWramPos wram, u32 slots )
2022 {
2023 #ifdef SDK_ARM9
2024 volatile BOOL finished = FALSE;
2025 u32 result;
2026
2027 if ( ! MIi_LockForPxi( &finished, &result ) )
2028 {
2029 return -1;
2030 }
2031 else
2032 {
2033 u32 data = MIi_MakeData( MIi_PXI_COMMAND_UNLOCKWRAM, wram, (MIWramProc)0, slots );
2034 MIi_SendToPxi( MIi_SENDTYPE_COMMAND, data );
2035 MIi_WaitWhileBusy( &finished );
2036 }
2037 return (int)result;
2038
2039 #else
2040 switch( wram )
2041 {
2042 case MI_WRAM_A:
2043 reg_MI_MBK_A_LOCK &= ~slots;
2044 break;
2045 case MI_WRAM_B:
2046 reg_MI_MBK_B_LOCK &= ~slots;
2047 break;
2048 case MI_WRAM_C:
2049 reg_MI_MBK_C_LOCK &= ~slots;
2050 break;
2051 }
2052 return 0;
2053 #endif
2054 }
2055
2056 /*---------------------------------------------------------------------------*
2057 Name: MI_GetWramReservation
2058
2059 Description: Gets which processor reserves the specified WRAM
2060
2061
2062 Arguments: wram wram position
2063 MI_WRAM_A : WRAM A
2064 MI_WRAM_B : WRAM B
2065 MI_WRAM_C : WRAM C
2066
2067 slot ; slot
2068 WRAM_A:0-3 WRAM_B:0-7 WRAM_C:0-7
2069
2070 Returns: MI_WRAM_ARM9 : ARM9
2071 MI_WRAM_ARM7 : ARM7
2072 MI_WRAM_DSP : DSP (only for WRAM_B and WRAM_C)
2073 *---------------------------------------------------------------------------*/
MI_GetWramReservation(MIWramPos wram,int slot)2074 MIWramProc MI_GetWramReservation( MIWramPos wram, int slot )
2075 {
2076 #ifdef SDK_ARM9
2077 return (MIWramProc)MIi_GetReservation( wram, slot );
2078
2079
2080 #else
2081 volatile BOOL finished = FALSE;
2082 u32 result;
2083
2084 if ( ! MIi_LockForPxi( &finished, &result ) )
2085 {
2086 // do nothing
2087 }
2088 else
2089 {
2090 u32 data = MIi_MakeData( MIi_PXI_COMMAND_GET_RESERVE, wram, (MIWramProc)0, (u32)slot );
2091 MIi_SendToPxi( MIi_SENDTYPE_COMMAND, data );
2092 MIi_WaitWhileBusy( &finished );
2093 }
2094 return (MIWramProc)result;
2095 #endif
2096 }
2097
2098 /*---------------------------------------------------------------------------*
2099 Name: MI_GetAllocatableWramSlot
2100
2101 Description: Gets allocatable WRAM slots by specifying the processor
2102
2103 Arguments: wram wram position
2104 MI_WRAM_A : WRAM A
2105 MI_WRAM_B : WRAM B
2106 MI_WRAM_C : WRAM C
2107
2108 proc : processor
2109 MI_WRAM_ARM9 : ARM9
2110 MI_WRAM_ARM7 : ARM7
2111 MI_WRAM_DSP : DSP
2112
2113 Returns: bit=1 slot is allocatable for the processor.
2114 bit=0 slot is used by other processors, so cannot allocate.
2115 WRAM_A : (1<<3)=slot3, (1<<2)=slot2, ... , (1<<0)=slot0
2116 WRAM_B : (1<<7)=slot7, (1<<6)=slot6, ... , (1<<0)=slot0
2117 WRAM_C : (1<<7)=slot7, (1<<6)=slot6, ... , (1<<0)=slot0
2118
2119 *---------------------------------------------------------------------------*/
MI_GetAllocatableWramSlot(MIWramPos wram,MIWramProc proc)2120 u8 MI_GetAllocatableWramSlot( MIWramPos wram, MIWramProc proc )
2121 {
2122 u8 result;
2123 u16 lockid;
2124
2125 OSIntrMode e = MIi_LockWramManagerDI( &lockid );
2126 result = (u8)MIi_DoGetAllocatableWramSlot( wram, proc );
2127 MIi_UnlockWramManagerRI( lockid, e );
2128
2129 return result;
2130 }
2131
2132 //- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MIi_DoGetAllocatableWramSlot(MIWramPos wram,MIWramProc proc)2133 static int MIi_DoGetAllocatableWramSlot( MIWramPos wram, MIWramProc proc )
2134 {
2135 #ifdef SDK_ARM9
2136 int retval = 0;
2137 int n;
2138 int maxNum = (wram == MI_WRAM_A)? MI_WRAM_A_MAX_NUM: MI_WRAM_B_MAX_NUM;
2139
2140 for( n=0; n<maxNum; n++ )
2141 {
2142 int master = MIi_GetMaster( wram, n );
2143 int reserve = MIi_GetReservation( wram, n );
2144
2145 if ( master == MI_WRAM_FREE && (reserve == proc || reserve == MI_WRAM_FREE) )
2146 {
2147 retval |= (1<<n);
2148 }
2149 }
2150 return retval;
2151
2152 #else
2153 volatile BOOL finished = FALSE;
2154 u32 result;
2155
2156 if ( ! MIi_LockForPxi( &finished, &result ) )
2157 {
2158 return -1;
2159 }
2160 else
2161 {
2162 u32 data = MIi_MakeData( MIi_PXI_COMMAND_GET_ALLOCATABLE, wram, proc, 0 );
2163 MIi_SendToPxi( MIi_SENDTYPE_COMMAND, data );
2164 MIi_WaitWhileBusy( &finished );
2165 }
2166 return (int)result;
2167 #endif
2168 }
2169
2170 #ifdef SDK_ARM9
2171 /*---------------------------------------------------------------------------*
2172 Name: MI_GetUsedWramSlot
2173
2174 Description: Gets used WRAM slots.
2175
2176 Arguments: wram wram position
2177 MI_WRAM_A : WRAM A
2178 MI_WRAM_B : WRAM B
2179 MI_WRAM_C : WRAM C
2180
2181 Returns: bit=1 slot is used by some processor.
2182 bit=0 slot is not used. (it may be reserved by some processor)
2183 WRAM_A : (1<<3)=slot3, (1<<2)=slot2, ... , (1<<0)=slot0
2184 WRAM_B : (1<<7)=slot7, (1<<6)=slot6, ... , (1<<0)=slot0
2185 WRAM_C : (1<<7)=slot7, (1<<6)=slot6, ... , (1<<0)=slot0
2186
2187 *---------------------------------------------------------------------------*/
MI_GetUsedWramSlot(MIWramPos wram)2188 u8 MI_GetUsedWramSlot( MIWramPos wram )
2189 {
2190 u16 lockid;
2191 OSIntrMode e = MIi_LockWramManagerDI( &lockid );
2192 int retval = 0;
2193 int n;
2194 int maxNum = (wram == MI_WRAM_A)? MI_WRAM_A_MAX_NUM: MI_WRAM_B_MAX_NUM;
2195
2196 for( n=0; n<maxNum; n++ )
2197 {
2198 if ( MIi_GetMaster( wram, n ) != MI_WRAM_FREE )
2199 {
2200 retval |= (1<<n);
2201 }
2202 }
2203 MIi_UnlockWramManagerRI( lockid, e );
2204 return (u8)retval;
2205 }
2206
2207 /*---------------------------------------------------------------------------*
2208 Name: MI_IsWramSlotUsed
2209
2210 Description: Checks if WRAM slot is used
2211
2212 Arguments: wram wram position
2213 MI_WRAM_A : WRAM A
2214 MI_WRAM_B : WRAM B
2215 MI_WRAM_C : WRAM C
2216
2217 slot ; slot
2218 WRAM_A:0-3 WRAM_B:0-7 WRAM_C:0-7
2219
2220 Returns: TRUE ... used
2221 FALSE ... not used
2222 *---------------------------------------------------------------------------*/
MI_IsWramSlotUsed(MIWramPos wram,int slot)2223 BOOL MI_IsWramSlotUsed( MIWramPos wram, int slot )
2224 {
2225 return (MIi_GetMaster(wram, slot) == MI_WRAM_FREE)? FALSE: TRUE;
2226 }
2227 #endif
2228
2229 //----------------------------------------------------------------
2230 // ARM9 / ARM7
2231 //----------------------------------------------------------------
2232 /*---------------------------------------------------------------------------*
2233 Name: (MIi_LockForPxi)
2234
2235 Description: Locks wram manager
2236
2237 Arguments: finishFlag : when unlocked, set TRUE.
2238 ptr: when unlocked, set data from ARM9
2239
2240 Returns: TRUE: Success.
2241 FALSE: Failure. The manager is already locked.
2242 *---------------------------------------------------------------------------*/
MIi_LockForPxi(volatile BOOL * finishFlag,u32 * ptr)2243 static int MIi_LockForPxi( volatile BOOL* finishFlag, u32* ptr )
2244 {
2245 OSIntrMode enabled = OS_DisableInterrupts();
2246 if (lock)
2247 {
2248 (void)OS_RestoreInterrupts(enabled);
2249 return FALSE;
2250 }
2251
2252 lock = TRUE;
2253 finishPtr = finishFlag;
2254 resultPtr = ptr;
2255
2256 (void)OS_RestoreInterrupts(enabled);
2257
2258 return TRUE;
2259 }
2260
2261 /*---------------------------------------------------------------------------*
2262 Name: (MIi_WaitWhileBusy)
2263
2264 Description: Waits while busy (=locked)
2265
2266 Arguments: finished : when unlocked, set TRUE.
2267
2268 Returns: None.
2269 *---------------------------------------------------------------------------*/
MIi_WaitWhileBusy(volatile BOOL * finished)2270 static void MIi_WaitWhileBusy( volatile BOOL* finished )
2271 {
2272 while( *finished == FALSE )
2273 {
2274 if (OS_GetCpsrIrq() == OS_INTRMODE_IRQ_DISABLE)
2275 {
2276 PXIi_HandlerRecvFifoNotEmpty();
2277 }
2278 SVC_WaitByLoop(1);
2279 }
2280 }
2281
2282 /*---------------------------------------------------------------------------*
2283 Name: (MIi_SendToPxi)
2284
2285 Description: send data via PXI
2286
2287 Arguments: data: data to send
2288
2289 Returns: None.
2290 *---------------------------------------------------------------------------*/
MIi_SendToPxi(BOOL sendType,u32 data)2291 static void MIi_SendToPxi(BOOL sendType, u32 data)
2292 {
2293 while( PXI_SendWordByFifo( PXI_FIFO_TAG_MI, data, sendType) != PXI_FIFO_SUCCESS )
2294 {
2295 SVC_WaitByLoop(1);
2296 }
2297 }
2298
2299 /*---------------------------------------------------------------------------*
2300 Name: (MIi_MakeData)
2301
2302 Description: Packs data to send via PXI
2303
2304 Arguments: command : command
2305 MI_WRAM_COMMAND_xxx
2306 wram wram position
2307 MI_WRAM_A : WRAM A
2308 MI_WRAM_B : WRAM B
2309 MI_WRAM_C : WRAM C
2310 proc : processor
2311 MI_WRAM_ARM9 : ARM9
2312 MI_WRAM_ARM7 : ARM7
2313 MI_WRAM_DSP : DSP
2314
2315 Returns: Data
2316 *---------------------------------------------------------------------------*/
MIi_MakeData(u32 command,MIWramPos wram,MIWramProc proc,u32 data)2317 static u32 MIi_MakeData( u32 command, MIWramPos wram, MIWramProc proc, u32 data )
2318 {
2319 return (command<<20) | (wram<<18) | (proc<<16) | data;
2320 }
2321
2322 /*---------------------------------------------------------------------------*
2323 Name: (MIi_TakeApartData)
2324
2325 Description: Takes apart data to several variables.
2326
2327 Arguments: pxiData : data to take apart
2328 command : pointer to store command
2329 wram pointer to store wram
2330 proc : pointer to store proc
2331 data: pointer to store data
2332
2333 Returns: None.
2334 *---------------------------------------------------------------------------*/
MIi_TakeApartData(u32 pxiData,u32 * command,MIWramPos * wram,MIWramProc * proc,u32 * data)2335 static void MIi_TakeApartData( u32 pxiData, u32* command, MIWramPos* wram, MIWramProc* proc, u32* data )
2336 {
2337 if ( command )
2338 {
2339 *command = (pxiData>>20) & 0xf;
2340 }
2341 if ( wram )
2342 {
2343 *wram = (MIWramPos)( (pxiData>>18) & 3 );
2344 }
2345 if ( proc )
2346 {
2347 *proc = (MIWramProc)( (pxiData>>16) & 3 );
2348 }
2349 if ( data )
2350 {
2351 *data = (pxiData) & 0xffff;
2352 }
2353 }
2354
2355
2356 //================================================================================
2357 /*---------------------------------------------------------------------------*
2358 Name: MI_LockWramManager
2359
2360 Description: Locks wram manager
2361
2362 Arguments: lockid : lockID
2363
2364 Returns: None.
2365 *---------------------------------------------------------------------------*/
MI_LockWramManager(u16 * lockid)2366 void MI_LockWramManager( u16* lockid )
2367 {
2368 *lockid = (u16)OS_GetLockID();
2369 (void)OS_LockByWord( *lockid, (OSLockWord *)(HW_WRAM_EX_LOCK_BUF), NULL );
2370 }
2371 /*---------------------------------------------------------------------------*
2372 Name: MI_UnlockWramManager
2373
2374 Description: Unlocks wram manager
2375
2376 Arguments: lockid : lockID
2377
2378 Returns: None.
2379 *---------------------------------------------------------------------------*/
MI_UnlockWramManager(u16 lockid)2380 void MI_UnlockWramManager( u16 lockid )
2381 {
2382 (void)OS_UnlockByWord( lockid, (OSLockWord *)(HW_WRAM_EX_LOCK_BUF), NULL );
2383 OS_ReleaseLockID( lockid );
2384 }
2385 /*---------------------------------------------------------------------------*
2386 Name: MI_TryLockWramManager
2387
2388 Description: Tries to lock wram manager
2389
2390 Arguments: lockid : lockID
2391
2392 Returns: >0 value: Previous locked id
2393 OS_LOCK_SUCCESS: Lock success.
2394 *---------------------------------------------------------------------------*/
MI_TryLockWramManager(u16 * lockid)2395 s32 MI_TryLockWramManager( u16* lockid )
2396 {
2397 *lockid = (u16)OS_GetLockID();
2398 return OS_TryLockByWord( *lockid, (OSLockWord *)(HW_WRAM_EX_LOCK_BUF), NULL );
2399 }
2400
2401 /*---------------------------------------------------------------------------*
2402 Name: (MIi_LockWramManagerDI)
2403
2404 Description: Disables interrupts and locks wram manager
2405
2406 Arguments: lockid : lockID
2407
2408 Returns: former interrupt mode
2409 *---------------------------------------------------------------------------*/
MIi_LockWramManagerDI(u16 * lockid)2410 static OSIntrMode MIi_LockWramManagerDI( u16* lockid )
2411 {
2412 OSIntrMode e = OS_DisableInterrupts();
2413 MI_LockWramManager( lockid );
2414 return e;
2415 }
2416 /*---------------------------------------------------------------------------*
2417 Name: (MIi_UnlockWramManagerRI)
2418
2419 Description: Unlocks wram manager and restores interrupts
2420
2421 Arguments: lockid : lockID
2422 e : interrupt mode
2423
2424 Returns: None.
2425 *---------------------------------------------------------------------------*/
MIi_UnlockWramManagerRI(u16 lockid,OSIntrMode e)2426 static void MIi_UnlockWramManagerRI( u16 lockid, OSIntrMode e )
2427 {
2428 MI_UnlockWramManager( lockid );
2429 (void)OS_RestoreInterrupts( e );
2430 }
2431 //================================================================================
2432 // for DEBUG
2433 //================================================================================
2434 static char* getMasterStr( MIWramProc m );
getMasterStr(MIWramProc m)2435 static char* getMasterStr( MIWramProc m )
2436 {
2437 static char strARM9[] = "ARM9";
2438 static char strARM7[] = "ARM7";
2439 static char strDSP[] = "DSP ";
2440 static char strNA[] = "----";
2441
2442 switch( m )
2443 {
2444 case MI_WRAM_ARM9: return strARM9;
2445 case MI_WRAM_ARM7: return strARM7;
2446 case MI_WRAM_DSP: return strDSP;
2447 }
2448 return strNA;
2449 }
2450
2451 /*---------------------------------------------------------------------------*
2452 Name: MI_DumpThreadList
2453
2454 Description: Dumps wram Status for WRAM-A/B/C
2455
2456 Arguments: wram wram position.
2457 MI_WRAM_A / MI_WRAM_B / MI_WRAM_C
2458
2459 Returns: None.
2460 *---------------------------------------------------------------------------*/
MI_DumpWramList(MIWramPos wram)2461 void MI_DumpWramList(MIWramPos wram)
2462 {
2463 #ifdef SDK_FINALROM
2464 #pragma unused( wram )
2465 #else
2466 int n;
2467 int maxNum = (wram == MI_WRAM_A)? MI_WRAM_A_MAX_NUM: MI_WRAM_B_MAX_NUM;
2468
2469 //---- wram address
2470 OS_Printf("----WRAM-%c (%x-%x)\n",
2471 'A'+(int)wram,
2472 MI_GetWramMapStart(wram), MI_GetWramMapEnd(wram) );
2473
2474 //---- explanatory
2475 OS_Printf(" ALLOC RESERVE\n");
2476
2477 //---- each slot info
2478 for( n=0; n<maxNum; n++ )
2479 {
2480 //---- slot num
2481 OS_Printf("slot%d ", n);
2482
2483 //---- allocated proc
2484 if ( MI_GetWramBankEnable( wram, n ) )
2485 {
2486 OS_Printf("%s ", getMasterStr( MI_GetWramBankMaster( wram, n ) ) );
2487 }
2488 else
2489 {
2490 OS_Printf("---- ");
2491 }
2492
2493 //---- reserved proc
2494 OS_Printf("%s\n", getMasterStr( MI_GetWramReservation( wram, n ) ) );
2495 }
2496 #endif
2497 }
2498
2499 /*---------------------------------------------------------------------------*
2500 Name: MI_DumpWramListAll
2501
2502 Description: Dumps all wram status
2503
2504 Arguments: None.
2505
2506 Returns: None.
2507 *---------------------------------------------------------------------------*/
MI_DumpWramListAll(void)2508 void MI_DumpWramListAll(void)
2509 {
2510 #ifndef SDK_FINALROM
2511 MI_DumpWramList( MI_WRAM_A );
2512 MI_DumpWramList( MI_WRAM_B );
2513 MI_DumpWramList( MI_WRAM_C );
2514 OS_Printf("\n");
2515 #endif // ifndef SDK_FINALROM
2516 }
2517
2518 #ifdef SDK_ARM9
2519 #include <twl/ltdmain_end.h>
2520 #endif
2521