1 /*---------------------------------------------------------------------------* 2 Project: TwlSDK - MI - include 3 File: dma.h 4 5 Copyright 2007-2008 Nintendo. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 $Date:: 2008-10-16#$ 14 $Rev: 8977 $ 15 $Author: yada $ 16 *---------------------------------------------------------------------------*/ 17 #ifndef TWL_MI_DMA_H_ 18 #define TWL_MI_DMA_H_ 19 20 #ifdef __cplusplus 21 extern "C" { 22 #endif 23 24 #include <twl/misc.h> 25 #include <twl/types.h> 26 #include <twl/memorymap.h> 27 28 #include <nitro/mi/dma.h> 29 30 //================================================================================ 31 // new-DMA control definition 32 //================================================================================ 33 //---- maximum new-DMA channel No. 34 #define MI_NDMA_MAX_NUM 3 35 36 //---------------- global control register 37 //---- arbitrament type 38 #define MI_NDMA_ARBITRAMENT_FIX (0UL << REG_MI_NDMAGCNT_ARBITER_SHIFT) 39 #define MI_NDMA_ARBITRAMENT_ROUND (1UL << REG_MI_NDMAGCNT_ARBITER_SHIFT) 40 41 //---- DSP-DMA & CPU Cycle select 42 #define MI_NDMA_RCYCLE_MASK (REG_MI_NDMAGCNT_CPUCYCLE_MASK) 43 #define MI_NDMA_RCYCLE_0 ( 0UL << REG_MI_NDMAGCNT_CPUCYCLE_SHIFT) 44 #define MI_NDMA_RCYCLE_1 ( 1UL << REG_MI_NDMAGCNT_CPUCYCLE_SHIFT) 45 #define MI_NDMA_RCYCLE_2 ( 2UL << REG_MI_NDMAGCNT_CPUCYCLE_SHIFT) 46 #define MI_NDMA_RCYCLE_4 ( 3UL << REG_MI_NDMAGCNT_CPUCYCLE_SHIFT) 47 #define MI_NDMA_RCYCLE_8 ( 4UL << REG_MI_NDMAGCNT_CPUCYCLE_SHIFT) 48 #define MI_NDMA_RCYCLE_16 ( 5UL << REG_MI_NDMAGCNT_CPUCYCLE_SHIFT) 49 #define MI_NDMA_RCYCLE_32 ( 6UL << REG_MI_NDMAGCNT_CPUCYCLE_SHIFT) 50 #define MI_NDMA_RCYCLE_64 ( 7UL << REG_MI_NDMAGCNT_CPUCYCLE_SHIFT) 51 #define MI_NDMA_RCYCLE_128 ( 8UL << REG_MI_NDMAGCNT_CPUCYCLE_SHIFT) 52 #define MI_NDMA_RCYCLE_256 ( 9UL << REG_MI_NDMAGCNT_CPUCYCLE_SHIFT) 53 #define MI_NDMA_RCYCLE_512 (10UL << REG_MI_NDMAGCNT_CPUCYCLE_SHIFT) 54 #define MI_NDMA_RCYCLE_1024 (11UL << REG_MI_NDMAGCNT_CPUCYCLE_SHIFT) 55 #define MI_NDMA_RCYCLE_2048 (12UL << REG_MI_NDMAGCNT_CPUCYCLE_SHIFT) 56 #define MI_NDMA_RCYCLE_4096 (13UL << REG_MI_NDMAGCNT_CPUCYCLE_SHIFT) 57 #define MI_NDMA_RCYCLE_8192 (14UL << REG_MI_NDMAGCNT_CPUCYCLE_SHIFT) 58 #define MI_NDMA_RCYCLE_16384 (15UL << REG_MI_NDMAGCNT_CPUCYCLE_SHIFT) 59 #ifdef SDK_ARM9 60 #define MI_NDMA_RCYCLE_DEFAULT MI_NDMA_RCYCLE_32 61 #else // SDK_ARM7 62 #define MI_NDMA_RCYCLE_DEFAULT MI_NDMA_RCYCLE_16 63 #endif // SDK_ARM7 64 65 //---------------- control register 66 //---- enable 67 #define MI_NDMA_ENABLE_MASK (1UL << REG_MI_NDMA0CNT_E_SHIFT) // DMA enable mask 68 #define MI_NDMA_ENABLE (1UL << REG_MI_NDMA0CNT_E_SHIFT) // DMA enable 69 #define MI_NDMA_DISABLE (0UL << REG_MI_NDMA0CNT_E_SHIFT) // DMA disable 70 71 //---- interrupt enable 72 #define MI_NDMA_IF_ENABLE (1UL << REG_MI_NDMA0CNT_I_SHIFT) // interrupt enable 73 #define MI_NDMA_IF_DISABLE (0UL << REG_MI_NDMA0CNT_I_SHIFT) // interrupt disable 74 75 //---- continuous mode 76 #define MI_NDMA_CONTINUOUS_ON (1UL << REG_MI_NDMA0CNT_CM_SHIFT) // continuous mode on 77 #define MI_NDMA_CONTINUOUS_OFF (0UL << REG_MI_NDMA0CNT_CM_SHIFT) // continuous mode off 78 79 //---- immidiate mode 80 #define MI_NDMA_IMM_MODE_ON (1UL << REG_MI_NDMA0CNT_IM_SHIFT) // immidiate mode on 81 #define MI_NDMA_IMM_MODE_OFF (0UL << REG_MI_NDMA0CNT_IM_SHIFT) // immidiate mode on 82 83 //---- dma timing 84 #define MI_NDMA_TIMING_MASK (REG_MI_NDMA0CNT_MODE_MASK) 85 #define MI_NDMA_TIMING_SHIFT (REG_MI_NDMA0CNT_MODE_SHIFT) 86 #define MI_NDMA_TIMING_TIMER0 ( 0UL << REG_MI_NDMA0CNT_MODE_SHIFT) // start by timer0 87 #define MI_NDMA_TIMING_TIMER1 ( 1UL << REG_MI_NDMA0CNT_MODE_SHIFT) // start by timer1 88 #define MI_NDMA_TIMING_TIMER2 ( 2UL << REG_MI_NDMA0CNT_MODE_SHIFT) // start by timer2 89 #define MI_NDMA_TIMING_TIMER3 ( 3UL << REG_MI_NDMA0CNT_MODE_SHIFT) // start by timer3 90 #define MI_NDMA_TIMING_CARD ( 4UL << REG_MI_NDMA0CNT_MODE_SHIFT) // start by card A 91 #define MI_NDMA_TIMING_CARD_A MI_NDMA_TIMING_CARD 92 #define MI_NDMA_TIMING_V_BLANK ( 6UL << REG_MI_NDMA0CNT_MODE_SHIFT) // start by VBlank 93 #ifdef SDK_ARM9 94 #define MI_NDMA_TIMING_H_BLANK ( 7UL << REG_MI_NDMA0CNT_MODE_SHIFT) // start by HBlank 95 #define MI_NDMA_TIMING_DISP ( 8UL << REG_MI_NDMA0CNT_MODE_SHIFT) // start by display sync 96 #define MI_NDMA_TIMING_DISP_MMEM ( 9UL << REG_MI_NDMA0CNT_MODE_SHIFT) // start by main memory display sync 97 #define MI_NDMA_TIMING_GXFIFO (10UL << REG_MI_NDMA0CNT_MODE_SHIFT) // start by geometry FIFO 98 #define MI_NDMA_TIMING_CAMERA (11UL << REG_MI_NDMA0CNT_MODE_SHIFT) // start by camera 99 #else // SDK_ARM7 100 #define MI_NDMA_TIMING_WIRELESS ( 7UL << REG_MI_NDMA0CNT_MODE_SHIFT) // start by 101 #define MI_NDMA_TIMING_SD_1 ( 8UL << REG_MI_NDMA0CNT_MODE_SHIFT) // start by SD I/F 1 102 #define MI_NDMA_TIMING_SD_2 ( 9UL << REG_MI_NDMA0CNT_MODE_SHIFT) // start by SD I/F 2 103 #define MI_NDMA_TIMING_AES_IN (10UL << REG_MI_NDMA0CNT_MODE_SHIFT) // start by AES in 104 #define MI_NDMA_TIMING_AES_OUT (11UL << REG_MI_NDMA0CNT_MODE_SHIFT) // start by AES out 105 #define MI_NDMA_TIMING_MIC (11UL << REG_MI_NDMA0CNT_MODE_SHIFT) // start by mic 106 #endif // SDK_ARM7 107 #define MIi_NDMA_TIMING_IMMIDIATE 0xffffffff // for internal use 108 109 //---- DMA block word count 110 #define MI_NDMA_BWORD_MASK (REG_MI_NDMA0CNT_WORDCNT_MASK) 111 #define MI_NDMA_BWORD_1 ( 0UL << REG_MI_NDMA0CNT_WORDCNT_SHIFT) // 1 word 112 #define MI_NDMA_BWORD_2 ( 1UL << REG_MI_NDMA0CNT_WORDCNT_SHIFT) // 2 words 113 #define MI_NDMA_BWORD_4 ( 2UL << REG_MI_NDMA0CNT_WORDCNT_SHIFT) // 4 words 114 #define MI_NDMA_BWORD_8 ( 3UL << REG_MI_NDMA0CNT_WORDCNT_SHIFT) // 8 words 115 #define MI_NDMA_BWORD_16 ( 4UL << REG_MI_NDMA0CNT_WORDCNT_SHIFT) // 16 words 116 #define MI_NDMA_BWORD_32 ( 5UL << REG_MI_NDMA0CNT_WORDCNT_SHIFT) // 32 words 117 #define MI_NDMA_BWORD_64 ( 6UL << REG_MI_NDMA0CNT_WORDCNT_SHIFT) // 64 words 118 #define MI_NDMA_BWORD_128 ( 7UL << REG_MI_NDMA0CNT_WORDCNT_SHIFT) // 128 words 119 #define MI_NDMA_BWORD_256 ( 8UL << REG_MI_NDMA0CNT_WORDCNT_SHIFT) // 256 words 120 #define MI_NDMA_BWORD_512 ( 9UL << REG_MI_NDMA0CNT_WORDCNT_SHIFT) // 512 words 121 #define MI_NDMA_BWORD_1024 (10UL << REG_MI_NDMA0CNT_WORDCNT_SHIFT) // 1024 words 122 #define MI_NDMA_BWORD_2048 (11UL << REG_MI_NDMA0CNT_WORDCNT_SHIFT) // 2048 words 123 #define MI_NDMA_BWORD_4096 (12UL << REG_MI_NDMA0CNT_WORDCNT_SHIFT) // 4096 words 124 #define MI_NDMA_BWORD_8192 (13UL << REG_MI_NDMA0CNT_WORDCNT_SHIFT) // 8192 words 125 #define MI_NDMA_BWORD_16384 (14UL << REG_MI_NDMA0CNT_WORDCNT_SHIFT) // 16384 words 126 #define MI_NDMA_BWORD_32768 (15UL << REG_MI_NDMA0CNT_WORDCNT_SHIFT) // 32768 words 127 128 //---- src address reload enable 129 #define MI_NDMA_SRC_RELOAD_ENABLE (1UL << REG_MI_NDMA0CNT_SRL_SHIFT) // reload after transferring specified words 130 #define MI_NDMA_SRC_RELOAD_DISABLE (0UL << REG_MI_NDMA0CNT_SRL_SHIFT) // not reload 131 132 //---- direction of src address 133 #define MI_NDMA_SRC_INC (0UL << REG_MI_NDMA0CNT_SAR_SHIFT) // increment 134 #define MI_NDMA_SRC_DEC (1UL << REG_MI_NDMA0CNT_SAR_SHIFT) // decrement 135 #define MI_NDMA_SRC_FIX (2UL << REG_MI_NDMA0CNT_SAR_SHIFT) // fix 136 #define MI_NDMA_SRC_FILLDATA (3UL << REG_MI_NDMA0CNT_SAR_SHIFT) // no address (= use fill data) 137 138 //---- src address reload enable 139 #define MI_NDMA_DEST_RELOAD_ENABLE (1UL << REG_MI_NDMA0CNT_DRL_SHIFT) // reload after transferring specified words 140 #define MI_NDMA_DEST_RELOAD_DISABLE (0UL << REG_MI_NDMA0CNT_DRL_SHIFT) // not reload 141 142 // direction of dest address 143 #define MI_NDMA_DEST_INC (0UL << REG_MI_NDMA0CNT_DAR_SHIFT) // increment 144 #define MI_NDMA_DEST_DEC (1UL << REG_MI_NDMA0CNT_DAR_SHIFT) // decrement 145 #define MI_NDMA_DEST_FIX (2UL << REG_MI_NDMA0CNT_DAR_SHIFT) // fix 146 147 //---------------- block transfer interval setting 148 #define MI_NDMA_INTERVAL_PS_1 (0UL << REG_MI_NDMA0BCNT_PS_SHIFT) // system clock (33.514MHz) 149 #define MI_NDMA_INTERVAL_PS_4 (1UL << REG_MI_NDMA0BCNT_PS_SHIFT) // system clock x 4 150 #define MI_NDMA_INTERVAL_PS_16 (2UL << REG_MI_NDMA0BCNT_PS_SHIFT) // system clock x 16 151 #define MI_NDMA_INTERVAL_PS_64 (3UL << REG_MI_NDMA0BCNT_PS_SHIFT) // system clock x 64 152 153 154 //================================================================ 155 // for convinience to access NDMA register 156 //================================================================ 157 #define MI_NDMA_NUM_WOFFSET(ndmaNo) (ndmaNo * 7) 158 #define MI_NDMA_REG_SAD_WOFFSET 0 159 #define MI_NDMA_REG_DAD_WOFFSET 1 160 #define MI_NDMA_REG_TCNT_WOFFSET 2 161 #define MI_NDMA_REG_WCNT_WOFFSET 3 162 #define MI_NDMA_REG_BCNT_WOFFSET 4 163 #define MI_NDMA_REG_FDATA_WOFFSET 5 164 #define MI_NDMA_REG_CNT_WOFFSET 6 165 166 #define MI_NDMA_REGADDR(ndmaNo, reg) (((vu32*)REG_NDMA0SAD_ADDR) + MI_NDMA_NUM_WOFFSET(ndmaNo) + reg ) 167 #define MI_NDMA_REG(ndmaNo, reg) ( *( MI_NDMA_REGADDR(ndmaNo, reg) ) ) 168 169 //---------------- for internal parameter 170 #define MI_NDMA_NO_INTERVAL 0 171 #define MI_NDMA_AT_A_TIME 0xffffffff 172 173 174 //---- NDMA config 175 typedef struct _MINDmaConfig 176 { 177 u32 intervalTimer; 178 u32 prescaler; 179 u32 blockWord; 180 u32 wordCount; 181 } 182 MINDmaConfig; 183 184 //---- NDMA callback 185 typedef void (*MINDmaCallback) (void *); 186 187 //---- NDMA device 188 typedef u32 MINDmaDevice; 189 190 191 //================================================================================ 192 // initialize NDMA 193 //================================================================================ 194 /*---------------------------------------------------------------------------* 195 Name: MI_InitNDma 196 197 Description: initialize NDMA. 198 199 Arguments: None 200 201 Returns: None 202 *---------------------------------------------------------------------------*/ 203 void MI_InitNDma( void ); 204 205 //================================================================ 206 // do Fill, Copy, Send, Recv, Pipe by using NDMA 207 // 208 // (1) MI_NDmaXXX imm 209 // (2) MI_NDmaXXXAsync async 210 // (3) MI_NDmaXXXEx useConfig imm 211 // (4) MI_NDmaXXXExAsync useConfig, async, 212 // (5) MI_NDmaXXX_Dev imm drivenByDevice 213 // (6) MI_NDmaXXXAsync_Dev async, drivenByDevice 214 // (7) MI_NDmaXXXEx_Dev useConfig, imm drivenByDevice 215 // (8) MI_NDmaXXXExAsync_Dev useConfig, async, drivenByDevice 216 // 217 //================================================================================ 218 /*---------------------------------------------------------------------------* 219 Name: MI_NDmaFill 220 221 Description: fill memory with specified data. 222 223 Arguments: dmaNo : NDMA channel No. 224 dest : destination address 225 data : fill data 226 size : size (byte) 227 228 Returns: None 229 230 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 231 Name: MI_NDmaCopy 232 233 Description: copy memory with NDMA. 234 235 Arguments: dmaNo : NDMA channel No. 236 src : source address 237 dest : destination address 238 size : size (byte) 239 240 Returns: None 241 242 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 243 Name: MI_NDmaSend 244 245 Description: send data to fixed address. 246 247 Arguments: dmaNo : NDMA channel No. 248 src : source address 249 dest : destination address 250 size : size (byte) 251 252 Returns: None 253 254 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 255 Name: MI_NDmaRecv 256 257 Description: receive data from fixed address. 258 259 Arguments: dmaNo : NDMA channel No. 260 src : source address 261 dest : destination address 262 size : size (byte) 263 264 Returns: None 265 266 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 267 Name: MI_NDmaPipe 268 269 Description: pipe data from fixed address to fixed address. 270 271 Arguments: dmaNo : NDMA channel No. 272 src : source address 273 dest : destination address 274 size : size (byte) 275 276 Returns: None 277 278 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 279 Name: MI_NDmaClear 280 281 Description: fill memory with 0 282 (define of MI_NDmaFill) 283 284 Arguments: dmaNo : NDMA channel No. 285 dest : destination address 286 size : size (byte) 287 288 Returns: None 289 290 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 291 (Common) 292 Arguments: callback : callback which will be called at NDMA finish 293 arg : argument of callback 294 config : pointer to NDMA config struct 295 dev : device which causes NDMA (MI_NDMA_TIMING_xxxx) 296 297 *---------------------------------------------------------------------------*/ 298 // (1) 299 void MI_NDmaFill (u32 ndmaNo, 300 void *dest, u32 data, u32 size ); 301 void MI_NDmaFill_SetUp (u32 ndmaNo, 302 void *dest, u32 data, u32 size ); 303 void MI_NDmaCopy (u32 ndmaNo, 304 const void *src, void *dest, u32 size ); 305 void MI_NDmaCopy_SetUp (u32 ndmaNo, 306 const void *src, void *dest, u32 size ); 307 void MI_NDmaSend (u32 ndmaNo, 308 const void *src, volatile void *dest, u32 size ); 309 void MI_NDmaSend_SetUp (u32 ndmaNo, 310 const void *src, volatile void *dest, u32 size ); 311 void MI_NDmaRecv (u32 ndmaNo, 312 volatile const void *src, void *dest, u32 size ); 313 void MI_NDmaRecv_SetUp (u32 ndmaNo, 314 volatile const void *src, void *dest, u32 size ); 315 void MI_NDmaPipe (u32 ndmaNo, 316 volatile const void *src, volatile void *dest, u32 size ); 317 void MI_NDmaPipe_SetUp (u32 ndmaNo, 318 volatile const void *src, volatile void *dest, u32 size ); 319 #define MI_NDmaClear(ndmaNo, dest, size) \ 320 MI_NDmaFill((ndmaNo), (dest), 0, (size)) 321 #define MI_NDmaClear_SetUp(ndmaNo, dest, size) \ 322 MI_NDmaFill_SetUp((ndmaNo), (dest), 0, (size)) 323 324 // (2) 325 void MI_NDmaFillAsync (u32 ndmaNo, 326 void *dest, u32 data, u32 size, 327 MINDmaCallback callback, void *arg ); 328 void MI_NDmaFillAsync_SetUp (u32 ndmaNo, 329 void *dest, u32 data, u32 size, 330 MINDmaCallback callback, void *arg ); 331 void MI_NDmaCopyAsync (u32 ndmaNo, 332 const void *src, void *dest, u32 size, 333 MINDmaCallback callback, void* arg ); 334 void MI_NDmaCopyAsync_SetUp (u32 ndmaNo, 335 const void *src, void *dest, u32 size, 336 MINDmaCallback callback, void* arg ); 337 void MI_NDmaSendAsync (u32 ndmaNo, 338 const void *src, volatile void *dest, u32 size, 339 MINDmaCallback callback, void* arg ); 340 void MI_NDmaSendAsync_SetUp (u32 ndmaNo, 341 const void *src, volatile void *dest, u32 size, 342 MINDmaCallback callback, void* arg ); 343 void MI_NDmaRecvAsync (u32 ndmaNo, 344 volatile const void *src, void *dest, u32 size, 345 MINDmaCallback callback, void* arg ); 346 void MI_NDmaRecvAsync_SetUp (u32 ndmaNo, 347 volatile const void *src, void *dest, u32 size, 348 MINDmaCallback callback, void* arg ); 349 void MI_NDmaPipeAsync (u32 ndmaNo, 350 volatile const void *src, volatile void *dest, u32 size, 351 MINDmaCallback callback, void* arg ); 352 void MI_NDmaPipeAsync_SetUp (u32 ndmaNo, 353 volatile const void *src, volatile void *dest, u32 size, 354 MINDmaCallback callback, void* arg ); 355 #define MI_NDmaClearAsync(ndmaNo, dest, size, callback, arg) \ 356 MI_NDmaFillAsync((ndmaNo), (dest), 0, (size), (callback), (arg)) 357 #define MI_NDmaClearAsync_SetUp(ndmaNo, dest, size, callback, arg) \ 358 MI_NDmaFillAsync_SetUp((ndmaNo), (dest), 0, (size), (callback), (arg)) 359 360 // (3) 361 void MI_NDmaFillEx (u32 ndmaNo, 362 void *dest, u32 data, u32 size, 363 const MINDmaConfig *config); 364 void MI_NDmaFillEx_SetUp (u32 ndmaNo, 365 void *dest, u32 data, u32 size, 366 const MINDmaConfig *config); 367 void MI_NDmaCopyEx (u32 ndmaNo, 368 const void *src, void *dest, u32 size, 369 const MINDmaConfig *config ); 370 void MI_NDmaCopyEx_SetUp (u32 ndmaNo, 371 const void *src, void *dest, u32 size, 372 const MINDmaConfig *config ); 373 void MI_NDmaSendEx (u32 ndmaNo, 374 const void *src, volatile void *dest, u32 size, 375 const MINDmaConfig *config ); 376 void MI_NDmaSendEx_SetUp (u32 ndmaNo, 377 const void *src, volatile void *dest, u32 size, 378 const MINDmaConfig *config ); 379 void MI_NDmaRecvEx (u32 ndmaNo, 380 volatile const void *src, void *dest, u32 size, 381 const MINDmaConfig *config ); 382 void MI_NDmaRecvEx_SetUp (u32 ndmaNo, 383 volatile const void *src, void *dest, u32 size, 384 const MINDmaConfig *config ); 385 void MI_NDmaPipeEx (u32 ndmaNo, 386 volatile const void *src, volatile void *dest, u32 size, 387 const MINDmaConfig *config ); 388 void MI_NDmaPipeEx_SetUp (u32 ndmaNo, 389 volatile const void *src, volatile void *dest, u32 size, 390 const MINDmaConfig *config ); 391 #define MI_NDmaClearEx(ndmaNo, dest, size, config) \ 392 MI_NDmaFillEx((ndmaNo), (dest), 0, (size), (config)) 393 #define MI_NDmaClearEx_SetUp(ndmaNo, dest, size, config) \ 394 MI_NDmaFillEx_SetUp((ndmaNo), (dest), 0, (size), (config)) 395 396 // (4) 397 void MI_NDmaFillExAsync (u32 ndmaNo, 398 void *dest, u32 data, u32 size, 399 MINDmaCallback callback, void *arg, const MINDmaConfig *config); 400 void MI_NDmaFillExAsync_SetUp(u32 ndmaNo, 401 void *dest, u32 data, u32 size, 402 MINDmaCallback callback, void *arg, const MINDmaConfig *config); 403 void MI_NDmaCopyExAsync (u32 ndmaNo, 404 const void *src, void *dest, u32 size, 405 MINDmaCallback callback, void* arg, const MINDmaConfig *config ); 406 void MI_NDmaCopyExAsync_SetUp(u32 ndmaNo, 407 const void *src, void *dest, u32 size, 408 MINDmaCallback callback, void* arg, const MINDmaConfig *config ); 409 void MI_NDmaSendExAsync (u32 ndmaNo, 410 const void *src, volatile void *dest, u32 size, 411 MINDmaCallback callback, void* arg, const MINDmaConfig *config); 412 void MI_NDmaSendExAsync_SetUp(u32 ndmaNo, 413 const void *src, volatile void *dest, u32 size, 414 MINDmaCallback callback, void* arg, const MINDmaConfig *config); 415 void MI_NDmaRecvExAsync (u32 ndmaNo, 416 volatile const void *src, void *dest, u32 size, 417 MINDmaCallback callback, void* arg, const MINDmaConfig *config); 418 void MI_NDmaRecvExAsync_SetUp(u32 ndmaNo, 419 volatile const void *src, void *dest, u32 size, 420 MINDmaCallback callback, void* arg, const MINDmaConfig *config); 421 void MI_NDmaPipeExAsync (u32 ndmaNo, 422 volatile const void *src, volatile void *dest, u32 size, 423 MINDmaCallback callback, void* arg, const MINDmaConfig *config); 424 void MI_NDmaPipeExAsync_SetUp(u32 ndmaNo, 425 volatile const void *src, volatile void *dest, u32 size, 426 MINDmaCallback callback, void* arg, const MINDmaConfig *config); 427 #define MI_NDmaClearExAsync(ndmaNo, dest, size, callback, arg, config) \ 428 MI_NDmaFillExAsync((ndmaNo), (dest), 0, (size), (callback), (arg), (config)) 429 #define MI_NDmaClearExAsync_SetUp(ndmaNo, dest, size, callback, arg, config) \ 430 MI_NDmaFillExAsync_SetUp((ndmaNo), (dest), 0, (size), (callback), (arg), (config)) 431 432 // (5) 433 void MI_NDmaFill_Dev (u32 ndmaNo, 434 void *dest, u32 data, u32 size, 435 MINDmaDevice dev ); 436 void MI_NDmaFill_Dev_SetUp (u32 ndmaNo, 437 void *dest, u32 data, u32 size, 438 MINDmaDevice dev ); 439 void MI_NDmaCopy_Dev (u32 ndmaNo, 440 const void *src, void *dest, u32 size, 441 MINDmaDevice dev ); 442 void MI_NDmaCopy_Dev_SetUp (u32 ndmaNo, 443 const void *src, void *dest, u32 size, 444 MINDmaDevice dev ); 445 void MI_NDmaSend_Dev (u32 ndmaNo, 446 const void *src, volatile void *dest, u32 size, 447 MINDmaDevice dev ); 448 void MI_NDmaSend_Dev_SetUp (u32 ndmaNo, 449 const void *src, volatile void *dest, u32 size, 450 MINDmaDevice dev ); 451 void MI_NDmaRecv_Dev (u32 ndmaNo, 452 volatile const void *src, void *dest, u32 size, 453 MINDmaDevice dev ); 454 void MI_NDmaRecv_Dev_SetUp (u32 ndmaNo, 455 volatile const void *src, void *dest, u32 size, 456 MINDmaDevice dev ); 457 void MI_NDmaPipe_Dev (u32 ndmaNo, 458 volatile const void *src, volatile void *dest, u32 size, 459 MINDmaDevice dev ); 460 void MI_NDmaPipe_Dev_SetUp (u32 ndmaNo, 461 volatile const void *src, volatile void *dest, u32 size, 462 MINDmaDevice dev ); 463 #define MI_NDmaClear_Dev(ndmaNo, dest, size, dev) \ 464 MI_NDmaFill_Dev((ndmaNo), (dest), 0, (size), (dev)) 465 #define MI_NDmaClear_Dev_SetUp(ndmaNo, dest, size, dev) \ 466 MI_NDmaFill_Dev_SetUp((ndmaNo), (dest), 0, (size), (dev)) 467 468 // (6) 469 void MI_NDmaFillAsync_Dev (u32 ndmaNo, 470 void *dest, u32 data, u32 size, 471 MINDmaCallback callback, void* arg, MINDmaDevice dev); 472 void MI_NDmaFillAsync_Dev_SetUp(u32 ndmaNo, 473 void *dest, u32 data, u32 size, 474 MINDmaCallback callback, void* arg, MINDmaDevice dev); 475 void MI_NDmaCopyAsync_Dev (u32 ndmaNo, 476 const void *src, void *dest, u32 size, 477 MINDmaCallback callback, void* arg, MINDmaDevice dev ); 478 void MI_NDmaCopyAsync_Dev_SetUp(u32 ndmaNo, 479 const void *src, void *dest, u32 size, 480 MINDmaCallback callback, void* arg, MINDmaDevice dev ); 481 void MI_NDmaSendAsync_Dev (u32 ndmaNo, 482 const void *src, volatile void *dest, u32 size, 483 MINDmaCallback callback, void* arg, MINDmaDevice dev ); 484 void MI_NDmaSendAsync_Dev_SetUp(u32 ndmaNo, 485 const void *src, volatile void *dest, u32 size, 486 MINDmaCallback callback, void* arg, MINDmaDevice dev ); 487 void MI_NDmaRecvAsync_Dev (u32 ndmaNo, 488 volatile const void *src, void *dest, u32 size, 489 MINDmaCallback callback, void* arg, MINDmaDevice dev ); 490 void MI_NDmaRecvAsync_Dev_SetUp(u32 ndmaNo, 491 volatile const void *src, void *dest, u32 size, 492 MINDmaCallback callback, void* arg, MINDmaDevice dev ); 493 void MI_NDmaPipeAsync_Dev (u32 ndmaNo, 494 volatile const void *src, volatile void *dest, u32 size, 495 MINDmaCallback callback, void* arg, MINDmaDevice dev ); 496 void MI_NDmaPipeAsync_Dev_SetUp(u32 ndmaNo, 497 volatile const void *src, volatile void *dest, u32 size, 498 MINDmaCallback callback, void* arg, MINDmaDevice dev ); 499 #define MI_NDmaClearAsync_Dev(ndmaNo, dest, size, callback, arg, dev) \ 500 MI_NDmaFillAsync_Dev((ndmaNo), (dest), 0, (size), (callback), (arg), (dev)) 501 #define MI_NDmaClearAsync_Dev_SetUp(ndmaNo, dest, size, callback, arg, dev) \ 502 MI_NDmaFillAsync_Dev_SetUp((ndmaNo), (dest), 0, (size), (callback), (arg), (dev)) 503 504 // (7) 505 void MI_NDmaFillEx_Dev (u32 ndmaNo, 506 void *dest, u32 data, u32 size, 507 const MINDmaConfig *config, MINDmaDevice dev); 508 void MI_NDmaFillEx_Dev_SetUp(u32 ndmaNo, 509 void *dest, u32 data, u32 size, 510 const MINDmaConfig *config, MINDmaDevice dev); 511 void MI_NDmaCopyEx_Dev (u32 ndmaNo, 512 const void *src, void *dest, u32 size, 513 const MINDmaConfig *config, MINDmaDevice dev ); 514 void MI_NDmaCopyEx_Dev_SetUp(u32 ndmaNo, 515 const void *src, void *dest, u32 size, 516 const MINDmaConfig *config, MINDmaDevice dev ); 517 void MI_NDmaSendEx_Dev (u32 ndmaNo, 518 const void *src, volatile void *dest, u32 size, 519 const MINDmaConfig *config, MINDmaDevice dev ); 520 void MI_NDmaSendEx_Dev_SetUp(u32 ndmaNo, 521 const void *src, volatile void *dest, u32 size, 522 const MINDmaConfig *config, MINDmaDevice dev ); 523 void MI_NDmaRecvEx_Dev (u32 ndmaNo, 524 volatile const void *src, void *dest, u32 size, 525 const MINDmaConfig *config, MINDmaDevice dev ); 526 void MI_NDmaRecvEx_Dev_SetUp(u32 ndmaNo, 527 volatile const void *src, void *dest, u32 size, 528 const MINDmaConfig *config, MINDmaDevice dev ); 529 void MI_NDmaPipeEx_Dev (u32 ndmaNo, 530 volatile const void *src, volatile void *dest, u32 size, 531 const MINDmaConfig *config, MINDmaDevice dev ); 532 void MI_NDmaPipeEx_Dev_SetUp(u32 ndmaNo, 533 volatile const void *src, volatile void *dest, u32 size, 534 const MINDmaConfig *config, MINDmaDevice dev ); 535 #define MI_NDmaClearEx_Dev(ndmaNo, dest, size, config, dev) \ 536 MI_NDmaFillEx_Dev((ndmaNo), (dest), 0, (size), (config), (dev)) 537 #define MI_NDmaClearEx_Dev_SetUp(ndmaNo, dest, size, config, dev) \ 538 MI_NDmaFillEx_Dev_SetUp((ndmaNo), (dest), 0, (size), (config), (dev)) 539 540 // (8) 541 void MI_NDmaFillExAsync_Dev (u32 ndmaNo, 542 void *dest, u32 data, u32 size, 543 MINDmaCallback callback, void* arg, const MINDmaConfig *config, MINDmaDevice dev); 544 void MI_NDmaFillExAsync_Dev_SetUp(u32 ndmaNo, 545 void *dest, u32 data, u32 size, 546 MINDmaCallback callback, void* arg, const MINDmaConfig *config, MINDmaDevice dev); 547 void MI_NDmaCopyExAsync_Dev (u32 ndmaNo, 548 const void *src, void *dest, u32 size, 549 MINDmaCallback callback, void* arg, const MINDmaConfig *config, MINDmaDevice dev ); 550 void MI_NDmaCopyExAsync_Dev_SetUp(u32 ndmaNo, 551 const void *src, void *dest, u32 size, 552 MINDmaCallback callback, void* arg, const MINDmaConfig *config, MINDmaDevice dev ); 553 void MI_NDmaSendExAsync_Dev (u32 ndmaNo, 554 const void *src, volatile void *dest, u32 size, 555 MINDmaCallback callback, void* arg, const MINDmaConfig *config, MINDmaDevice dev ); 556 void MI_NDmaSendExAsync_Dev_SetUp(u32 ndmaNo, 557 const void *src, volatile void *dest, u32 size, 558 MINDmaCallback callback, void* arg, const MINDmaConfig *config, MINDmaDevice dev ); 559 void MI_NDmaRecvExAsync_Dev (u32 ndmaNo, 560 volatile const void *src, void *dest, u32 size, 561 MINDmaCallback callback, void* arg, const MINDmaConfig *config, MINDmaDevice dev ); 562 void MI_NDmaRecvExAsync_Dev_SetUp(u32 ndmaNo, 563 volatile const void *src, void *dest, u32 size, 564 MINDmaCallback callback, void* arg, const MINDmaConfig *config, MINDmaDevice dev ); 565 void MI_NDmaPipeExAsync_Dev (u32 ndmaNo, 566 volatile const void *src, volatile void *dest, u32 size, 567 MINDmaCallback callback, void* arg, const MINDmaConfig *config, MINDmaDevice dev ); 568 void MI_NDmaPipeExAsync_Dev_SetUp(u32 ndmaNo, 569 volatile const void *src, volatile void *dest, u32 size, 570 MINDmaCallback callback, void* arg, const MINDmaConfig *config, MINDmaDevice dev ); 571 #define MI_NDmaClearExAsync_Dev(ndmaNo, dest, size, callback, arg, config, dev) \ 572 MI_NDmaFillExAsync_Dev((ndmaNo), (dest), 0, (size), (callback), (arg), (config), (dev)) 573 #define MI_NDmaClearExAsync_Dev_SetUp(ndmaNo, dest, size, callback, arg, config, dev) \ 574 MI_NDmaFillExAsync_Dev_SetUp((ndmaNo), (dest), 0, (size), (callback), (arg), (config), (dev)) 575 576 577 //================================================================================ 578 // DMA WAIT 579 //================================================================================ 580 /*---------------------------------------------------------------------------* 581 Name: MI_IsNDmaBusy 582 583 Description: check whether DMA is busy or not 584 585 Arguments: ndmaNo : DMA channel No. 586 587 Returns: TRUE if DMA is busy, FALSE if not 588 *---------------------------------------------------------------------------*/ 589 BOOL MI_IsNDmaBusy(u32 ndmaNo); 590 591 /*---------------------------------------------------------------------------* 592 Name: MI_WaitNDma 593 594 Description: wait while DMA is busy 595 596 Arguments: ndmaNo : DMA channel No. 597 598 Returns: None 599 *---------------------------------------------------------------------------*/ 600 void MI_WaitNDma(u32 ndmaNo); 601 602 /*---------------------------------------------------------------------------* 603 Name: MI_StopNDma 604 605 Description: stop DMA 606 607 Arguments: ndmaNo : DMA channel No. 608 609 Returns: None 610 *---------------------------------------------------------------------------*/ 611 void MI_StopNDma(u32 ndmaNo); 612 613 614 /*---------------------------------------------------------------------------* 615 Name: MI_StopAllNDma 616 617 Description: stop all DMA 618 619 Arguments: None 620 621 Returns: None 622 *---------------------------------------------------------------------------*/ 623 void MI_StopAllNDma(void); 624 625 //================================================================================ 626 // restart NDMA 627 //================================================================================ 628 /*---------------------------------------------------------------------------* 629 Name: MI_NDmaRestart 630 631 Description: restart DMA 632 Just set the enable bit. 633 634 Arguments: ndmaNo : DMA channel No. 635 636 Returns: None 637 *---------------------------------------------------------------------------*/ 638 void MI_NDmaRestart(u32 ndmaNo); 639 640 //================================================================================ 641 // NDMA configure 642 //================================================================================ 643 /*---------------------------------------------------------------------------* 644 Name: MI_SetNDmaArbitrament 645 646 Description: set arbittament mode and cycle for DSP and CPU access to AHB 647 648 Arguments: mode : Arbittament mode 649 650 MI_NDMA_ARBITRAMENT_FIX fix 651 MI_NDMA_ARBITRAMENT_ROUND round robin 652 653 cycle : Cycles for DSP and CPU access to AHB 654 This parameter is available only when mode is round robin. 655 656 MI_NDMA_RCYCLE_n 657 (n = 0, 1, 2, 4, 8, ..., 8192, 16384) 658 659 Returns: None 660 *---------------------------------------------------------------------------*/ 661 void MI_SetNDmaArbitrament( u32 mode, u32 cycle ); 662 663 /*---------------------------------------------------------------------------* 664 Name: MI_GetNDmaArbitramentMode 665 666 Description: get NDMA arbitrament mode setting 667 668 Arguments: None 669 670 Returns: value which is set 671 672 MI_NDMA_ARBITRAMENT_FIX fix 673 MI_NDMA_ARBITRAMENT_ROUND round robin 674 675 *---------------------------------------------------------------------------*/ 676 u32 MI_GetNDmaArbitramentMode(void); 677 678 /*---------------------------------------------------------------------------* 679 Name: MI_GetNDmaArbitramentRoundRobinCycle 680 681 Description: get cycle setting for DSP and CPU access to AHB 682 683 Arguments: None 684 685 Returns: value which is set 686 687 MI_NDMA_RCYCLE_n (n = 0, 1, 2, 4, 8, ..., 16384) 688 689 *---------------------------------------------------------------------------*/ 690 u32 MI_GetNDmaArbitramentRoundRobinCycle(void); 691 692 /*---------------------------------------------------------------------------* 693 Name: MI_SetNDmaInterval 694 695 Description: set interval time and prescaler 696 697 Arguments: ndmaNo : NDMA number. (0-3) 698 intervalTime : interval time. (0-0xffff) 699 prescaler : prescaler. (MI_NDMA_INTERVAL_PS_n (n=1,4,16,64)) 700 701 Returns: None 702 *---------------------------------------------------------------------------*/ 703 void MI_SetNDmaInterval( u32 ndmaNo, u32 intervalTime, u32 prescaler ); 704 705 /*---------------------------------------------------------------------------* 706 Name: MI_GetNDmaIntervalTimer 707 708 Description: get interval time which is set 709 710 Arguments: ndmaNo : NDMA number. (0-3) 711 712 Returns: interval time (0-0xffff) 713 *---------------------------------------------------------------------------*/ 714 u32 MI_GetNDmaIntervalTimer( u32 ndmaNo ); 715 716 /*---------------------------------------------------------------------------* 717 Name: MI_GetNDmaIntervalPrescaler 718 719 Description: get prescaler setting which is set 720 721 Arguments: ndmaNo : NDMA number. (0-3) 722 723 Returns: prescaler 724 MI_NDMA_INTERVAL_PS_n (n=1,4,16,64) 725 *---------------------------------------------------------------------------*/ 726 u32 MI_GetNDmaIntervalPrescaler( u32 ndmaNo ); 727 728 /*---------------------------------------------------------------------------* 729 Name: MI_SetNDmaBlockWord 730 731 Description: set block word which is transferred by DMA at a time 732 733 Arguments: ndmaNo : NDMA number. (0-3) 734 word ; block word 735 736 MI_NDMA_WORD_n (n=1,2,4,8,...,32768) 737 738 Returns: None 739 740 *---------------------------------------------------------------------------*/ 741 void MI_SetNDmaBlockWord( u32 ndmaNo, u32 word ); 742 743 /*---------------------------------------------------------------------------* 744 Name: MI_GetNDmaBlockWord 745 746 Description: get block word which is transferrd by DMA at a time 747 748 Arguments: ndmaNo 749 750 Returns: value which is set 751 752 MI_NDMA_RCYCLE_n 753 (n = 0, 1, 2, 4, 8, ..., 8192, 16384) 754 755 *---------------------------------------------------------------------------*/ 756 u32 MI_GetNDmaBlockWord( u32 ndmaNo ); 757 758 /*---------------------------------------------------------------------------* 759 Name: MI_SetNDmaWordCount 760 761 Description: set word count for each DMA request to start 762 763 Arguments: ndmaNo : NDMA number. (0-3) 764 wordCount : word count for each DMA request to start 765 766 0 - 0xffff 767 (0 means 0x100000000) 768 769 Returns: None 770 771 *---------------------------------------------------------------------------*/ 772 void MI_SetNDmaWordCount( u32 ndmaNo, u32 wordCount ); 773 774 /*---------------------------------------------------------------------------* 775 Name: MI_GetNDmaWordCount 776 777 Description: get word count for each DMA request to start 778 779 Arguments: ndmaNo 780 781 Returns: value which is set 782 783 0 - 0xffff 784 (0 means 0x100000000) 785 786 *---------------------------------------------------------------------------*/ 787 u32 MI_GetNDmaWordCount( u32 ndmaNo ); 788 789 /*---------------------------------------------------------------------------* 790 Name: MI_InitNDmaConfig 791 792 Description: initialize NDMA config. 793 794 Arguments: None 795 796 Returns: None 797 *---------------------------------------------------------------------------*/ 798 void MI_InitNDmaConfig( void ); 799 800 801 /*---------------------------------------------------------------------------* 802 Name: MI_GetNDmaConfig 803 804 Description: copy NDMA config data to local variable 805 806 Arguments: ndmaNo : NDMA channel No. 807 config : pointer to NDMA config struct 808 809 Returns: None 810 *---------------------------------------------------------------------------*/ 811 void MI_GetNDmaConfig( u32 ndmaNo, MINDmaConfig *config ); 812 813 /*---------------------------------------------------------------------------* 814 Name: MI_SetNDmaConfig 815 816 Description: copy NDMA config data from local variable 817 818 Arguments: ndmaNo : NDMA channel No. 819 config : pointer to NDMA config struct 820 821 Returns: None 822 *---------------------------------------------------------------------------*/ 823 void MI_SetNDmaConfig( u32 ndmaNo, const MINDmaConfig *config ); 824 825 826 //================================================================================ 827 // Timer DMA 828 //================================================================================ 829 void MI_TimerNDmaCopy(u32 ndmaNo, u32 timerNo, const void *src, void *dest, u32 size); 830 831 //================================================================================ 832 // HBlank DMA 833 //================================================================================ 834 #ifdef SDK_ARM9 835 void MI_HBlankNDmaCopy(u32 ndmaNo, const void *src, void *dest, u32 size); 836 void MI_HBlankNDmaCopyIf(u32 ndmaNo, const void *src, void *dest, u32 size); 837 #endif 838 839 //================================================================================ 840 // VBlank DMA 841 //================================================================================ 842 void MI_VBlankNDmaCopy(u32 dmaNo, const void *src, void *dest, u32 size); 843 void MI_VBlankNDmaCopyAsync(u32 dmaNo, const void *src, void *dest, u32 size, 844 MINDmaCallback callback, void *arg); 845 //================================================================================ 846 // CARD DMA 847 //================================================================================ 848 void MI_Card_NDmaCopy(u32 dmaNo, const void *src, void *dest, u32 size); 849 #define MI_Card_A_NDmaCopy MI_Card_NDmaCopy 850 851 //================================================================================ 852 // main memory display DMA 853 //================================================================================ 854 //void MI_DispMemDmaCopy(u32 dmaNo, const void *src); 855 856 //================================================================================ 857 // geometry FIFO DMA 858 //================================================================================ 859 #ifdef SDK_ARM9 860 void MI_SendNDmaGXCommand(u32 dmaNo, const void *src, u32 commandLength); 861 void MI_SendNDmaGXCommandAsync(u32 dmaNo, const void *src, u32 commandLength, MINDmaCallback callback, void *arg); 862 void MI_SendNDmaGXCommandFast(u32 ndmaNo, const void *src, u32 commandLength); 863 void MI_SendNDmaGXCommandAsyncFast(u32 ndmaNo, const void *src, u32 commandLength, MINDmaCallback callback, void *arg); 864 #endif 865 866 //================================================================================ 867 // Camera DMA 868 //================================================================================ 869 #ifdef SDK_ARM9 870 void MI_Camera_NDmaRecv(u32 ndmaNo, void *dest, u32 unit, u32 size, BOOL contSw ); 871 void MI_Camera_NDmaRecvEx(u32 ndmaNo, void *dest, u32 size, BOOL contSw, const MINDmaConfig *config ); 872 void MI_Camera_NDmaRecvAsync(u32 ndmaNo, void *dest, u32 unit, u32 size, BOOL contSw, MINDmaCallback callback, void* arg ); 873 void MI_Camera_NDmaRecvAsyncEx(u32 ndmaNo, void *dest, u32 size, BOOL contSw, MINDmaCallback callback, void* arg, const MINDmaConfig *config ); 874 #endif 875 876 //================================================================================ 877 // AES DMA 878 //================================================================================ 879 #ifndef SDK_ARM9 880 void MIi_Aes_NDmaSend(u32 ndmaNo, const void *src, u32 size, MINDmaCallback callback, void* arg, const MINDmaConfig* pConfig); 881 void MIi_Aes_NDmaRecv(u32 ndmaNo, void *dst, u32 size, MINDmaCallback callback, void* arg, const MINDmaConfig* pConfig); 882 #endif 883 884 //================================================================================ 885 // setting each register directly (internal) 886 //================================================================================ 887 void MIi_SetNDmaSrc( u32 ndmaNo, void *src ); 888 void MIi_SetNDmaDest( u32 ndmaNo, void *dest ); 889 void MIi_SetNDmaTotalWordCount( u32 ndmaNo, u32 size ); 890 void MIi_SetNDmaWordCount( u32 ndmaNo, u32 size ); 891 void MIi_SetNDmaInterval( u32 ndmaNo, u32 intervalTimer, u32 prescaler ); 892 893 //-------------------------------------------------------------------------------- 894 #ifdef __cplusplus 895 } /* extern "C" */ 896 #endif 897 898 /* TWL_MI_DMA_H_ */ 899 #endif 900