1 /*---------------------------------------------------------------------------* 2 Project: TwlSDK - include - twl - HW - common 3 File: mmap_wramEnv.h 4 5 Copyright 2007-2008 Nintendo. All rights reserved. 6 7 These coded instructions, statements, and computer programs contain 8 proprietary information of Nintendo of America Inc. and/or Nintendo 9 Company Ltd., and are protected by Federal copyright law. They may 10 not be disclosed to third parties or copied or duplicated in any form, 11 in whole or in part, without the prior written consent of Nintendo. 12 13 $Date:: 2008-09-17#$ 14 $Rev: 8556 $ 15 $Author: okubata_ryoma $ 16 *---------------------------------------------------------------------------*/ 17 18 #ifndef TWL_HW_COMMON_WRAMENV_H_ 19 #define TWL_HW_COMMON_WRAMENV_H_ 20 21 #ifdef __cplusplus 22 extern "C" { 23 #endif 24 25 //---- 26 //HW_PRV_WRAM_SYSRV+4: SCFG_EXT 4Byte -> 4Byte 27 28 #define HWi_WSYS04_SIZE 4 29 #define HWi_WSYS04_OFFSET 0 30 #define HWi_WSYS04_WRAMOFFSET (HWi_WSYS04_OFFSET+4) 31 #define HWi_WSYS04_ADDR (HW_PRV_WRAM_SYSRV + HWi_WSYS04_WRAMOFFSET) 32 33 //bit:31 34 #define HWi_WSYS04_EXT_CFG_SHIFT REG_SCFG_EXT_CFG_SHIFT 35 #define HWi_WSYS04_EXT_CFG_SIZE REG_SCFG_EXT_CFG_SIZE 36 #define HWi_WSYS04_EXT_CFG_MASK REG_SCFG_EXT_CFG_MASK 37 //bit:28 38 #define HWi_WSYS04_EXT_PUENABLE_SHIFT REG_SCFG_EXT_PUENABLE_SHIFT 39 #define HWi_WSYS04_EXT_PUENABLE_SIZE REG_SCFG_EXT_PUENABLE_SIZE 40 #define HWi_WSYS04_EXT_PUENABLE_MASK REG_SCFG_EXT_PUENABLE_MASK 41 //bit:28 42 #define HWi_WSYS04_EXT_SD20_SHIFT REG_SCFG_EXT_SD20_SHIFT 43 #define HWi_WSYS04_EXT_SD20_SIZE REG_SCFG_EXT_SD20_SIZE 44 #define HWi_WSYS04_EXT_SD20_MASK REG_SCFG_EXT_SD20_MASK 45 //bit:25-16 46 #define HWi_WSYS04_EXT_NEWB_ACCESS_E_SHIFT REG_SCFG_EXT_NEWB_ACCESS_E_SHIFT 47 #define HWi_WSYS04_EXT_NEWB_ACCESS_E_SIZE REG_SCFG_EXT_NEWB_ACCESS_E_SIZE 48 #define HWi_WSYS04_EXT_NEWB_ACCESS_E_MASK REG_SCFG_EXT_NEWB_ACCESS_E_MASK 49 //bit:25 50 #define HWi_WSYS04_EXT_WRAM_SHIFT REG_SCFG_EXT_WRAM_SHIFT 51 #define HWi_WSYS04_EXT_WRAM_SIZE REG_SCFG_EXT_WRAM_SIZE 52 #define HWi_WSYS04_EXT_WRAM_MASK REG_SCFG_EXT_WRAM_MASK 53 //bit:24 54 #define HWi_WSYS04_EXT_MC_B_SHIFT REG_SCFG_EXT_MC_B_SHIFT 55 #define HWi_WSYS04_EXT_MC_B_SIZE REG_SCFG_EXT_MC_B_SIZE 56 #define HWi_WSYS04_EXT_MC_B_MASK REG_SCFG_EXT_MC_B_MASK 57 //bit:23 58 #define HWi_WSYS04_EXT_GPIO_SHIFT REG_SCFG_EXT_GPIO_SHIFT 59 #define HWi_WSYS04_EXT_GPIO_SIZE REG_SCFG_EXT_GPIO_SIZE 60 #define HWi_WSYS04_EXT_GPIO_MASK REG_SCFG_EXT_GPIO_MASK 61 //bit:22 62 #define HWi_WSYS04_EXT_I2C_SHIFT REG_SCFG_EXT_I2C_SHIFT 63 #define HWi_WSYS04_EXT_I2C_SIZE REG_SCFG_EXT_I2C_SIZE 64 #define HWi_WSYS04_EXT_I2C_MASK REG_SCFG_EXT_I2C_MASK 65 //bit:21 66 #define HWi_WSYS04_EXT_I2S_SHIFT REG_SCFG_EXT_I2S_SHIFT 67 #define HWi_WSYS04_EXT_I2S_SIZE REG_SCFG_EXT_I2S_SIZE 68 #define HWi_WSYS04_EXT_I2S_MASK REG_SCFG_EXT_I2S_MASK 69 //bit:20 70 #define HWi_WSYS04_EXT_MIC_SHIFT REG_SCFG_EXT_MIC_SHIFT 71 #define HWi_WSYS04_EXT_MIC_SIZE REG_SCFG_EXT_MIC_SIZE 72 #define HWi_WSYS04_EXT_MIC_MASK REG_SCFG_EXT_MIC_MASK 73 //bit:19 74 #define HWi_WSYS04_EXT_SD2_SHIFT REG_SCFG_EXT_SD2_SHIFT 75 #define HWi_WSYS04_EXT_SD2_SIZE REG_SCFG_EXT_SD2_SIZE 76 #define HWi_WSYS04_EXT_SD2_MASK REG_SCFG_EXT_SD2_MASK 77 //bit:18 78 #define HWi_WSYS04_EXT_SD1_SHIFT REG_SCFG_EXT_SD1_SHIFT 79 #define HWi_WSYS04_EXT_SD1_SIZE REG_SCFG_EXT_SD1_SIZE 80 #define HWi_WSYS04_EXT_SD1_MASK REG_SCFG_EXT_SD1_MASK 81 //bit:17 82 #define HWi_WSYS04_EXT_AES_SHIFT REG_SCFG_EXT_AES_SHIFT 83 #define HWi_WSYS04_EXT_AES_SIZE REG_SCFG_EXT_AES_SIZE 84 #define HWi_WSYS04_EXT_AES_MASK REG_SCFG_EXT_AES_MASK 85 //bit:16 86 #define HWi_WSYS04_EXT_DMAC_SHIFT REG_SCFG_EXT_DMAC_SHIFT 87 #define HWi_WSYS04_EXT_DMAC_SIZE REG_SCFG_EXT_DMAC_SIZE 88 #define HWi_WSYS04_EXT_DMAC_MASK REG_SCFG_EXT_DMAC_MASK 89 //bit:15-8 90 #define HWi_WSYS04_EXT_NITROB_EX_E_SHIFT REG_SCFG_EXT_NITROB_EX_E_SHIFT 91 #define HWi_WSYS04_EXT_NITROB_EX_E_SIZE REG_SCFG_EXT_NITROB_EX_E_SIZE 92 #define HWi_WSYS04_EXT_NITROB_EX_E_MASK REG_SCFG_EXT_NITROB_EX_E_MASK 93 //bit:15-14 94 #define HWi_WSYS04_EXT_PSRAM_SHIFT REG_SCFG_EXT_PSRAM_SHIFT 95 #define HWi_WSYS04_EXT_PSRAM_SIZE REG_SCFG_EXT_PSRAM_SIZE 96 #define HWi_WSYS04_EXT_PSRAM_MASK REG_SCFG_EXT_PSRAM_MASK 97 //bit:13 98 #define HWi_WSYS04_EXT_VRAM_SHIFT REG_SCFG_EXT_VRAM_SHIFT 99 #define HWi_WSYS04_EXT_VRAM_SIZE REG_SCFG_EXT_VRAM_SIZE 100 #define HWi_WSYS04_EXT_VRAM_MASK REG_SCFG_EXT_VRAM_MASK 101 //bit:12 102 #define HWi_WSYS04_EXT_LCDC_SHIFT REG_SCFG_EXT_LCDC_SHIFT 103 #define HWi_WSYS04_EXT_LCDC_SIZE REG_SCFG_EXT_LCDC_SIZE 104 #define HWi_WSYS04_EXT_LCDC_MASK REG_SCFG_EXT_LCDC_MASK 105 //bit:11 106 #define HWi_WSYS04_EXT_SIO_SHIFT REG_SCFG_EXT_SIO_SHIFT 107 #define HWi_WSYS04_EXT_SIO_SIZE REG_SCFG_EXT_SIO_SIZE 108 #define HWi_WSYS04_EXT_SIO_MASK REG_SCFG_EXT_SIO_MASK 109 //bit:10 110 #define HWi_WSYS04_EXT_DSEL_SHIFT REG_SCFG_EXT_DSEL_SHIFT 111 #define HWi_WSYS04_EXT_DSEL_SIZE REG_SCFG_EXT_DSEL_SIZE 112 #define HWi_WSYS04_EXT_DSEL_MASK REG_SCFG_EXT_DSEL_MASK 113 //bit:9 114 #define HWi_WSYS04_EXT_SPI_SHIFT REG_SCFG_EXT_SPI_SHIFT 115 #define HWi_WSYS04_EXT_SPI_SIZE REG_SCFG_EXT_SPI_SIZE 116 #define HWi_WSYS04_EXT_SPI_MASK REG_SCFG_EXT_SPI_MASK 117 //bit:8 118 #define HWi_WSYS04_EXT_INTC_SHIFT REG_SCFG_EXT_INTC_SHIFT 119 #define HWi_WSYS04_EXT_INTC_SIZE REG_SCFG_EXT_INTC_SIZE 120 #define HWi_WSYS04_EXT_INTC_MASK REG_SCFG_EXT_INTC_MASK 121 //bit:7-0 122 #define HWi_WSYS04_EXT_NITROB_MOD_E_SHIFT REG_SCFG_EXT_NITROB_MOD_E_SHIFT 123 #define HWi_WSYS04_EXT_NITROB_MOD_E_SIZE REG_SCFG_EXT_NITROB_MOD_E_SIZE 124 #define HWi_WSYS04_EXT_NITROB_MOD_E_MASK REG_SCFG_EXT_NITROB_MOD_E_MASK 125 //bit:7 126 #define HWi_WSYS04_EXT_MC_SHIFT REG_SCFG_EXT_MC_SHIFT 127 #define HWi_WSYS04_EXT_MC_SIZE REG_SCFG_EXT_MC_SIZE 128 #define HWi_WSYS04_EXT_MC_MASK REG_SCFG_EXT_MC_MASK 129 //bit:2 130 #define HWi_WSYS04_EXT_SND_SHIFT REG_SCFG_EXT_SND_SHIFT 131 #define HWi_WSYS04_EXT_SND_SIZE REG_SCFG_EXT_SND_SIZE 132 #define HWi_WSYS04_EXT_SND_MASK REG_SCFG_EXT_SND_MASK 133 //bit:1 134 #define HWi_WSYS04_EXT_SDMA_SHIFT REG_SCFG_EXT_SDMA_SHIFT 135 #define HWi_WSYS04_EXT_SDMA_SIZE REG_SCFG_EXT_SDMA_SIZE 136 #define HWi_WSYS04_EXT_SDMA_MASK REG_SCFG_EXT_SDMA_MASK 137 //bit:0 138 #define HWi_WSYS04_EXT_DMA_SHIFT REG_SCFG_EXT_DMA_SHIFT 139 #define HWi_WSYS04_EXT_DMA_SIZE REG_SCFG_EXT_DMA_SIZE 140 #define HWi_WSYS04_EXT_DMA_MASK REG_SCFG_EXT_DMA_MASK 141 142 //---------------------------------------------------------------- 143 //HW_PRV_WRAM_SYSRV+8: SCFG_OP & SCFG_ROM(L) & SCFG_WL 4Byte -> 1Byte 144 145 #define HWi_WSYS08_SIZE 1 146 #define HWi_WSYS08_OFFSET 4 147 #define HWi_WSYS08_WRAMOFFSET (HWi_WSYS08_OFFSET+4) 148 #define HWi_WSYS08_ADDR (HW_PRV_WRAM_SYSRV + HWi_WSYS08_WRAMOFFSET) 149 150 //bit:7 151 #define HWi_WSYS08_WL_OFFB_SHIFT 7 152 #define HWi_WSYS08_WL_OFFB_SIZE 1 153 #define HWi_WSYS08_WL_OFFB_MASK 0x80 154 //bit:6 155 #define HWi_WSYS08_ROM_ARM7FUSE_SHIFT 6 156 #define HWi_WSYS08_ROM_ARM7FUSE_SIZE 1 157 #define HWi_WSYS08_ROM_ARM7FUSE_MASK 0x40 158 //bit:5 159 #define HWi_WSYS08_ROM_ARM7RSEL_SHIFT 5 160 #define HWi_WSYS08_ROM_ARM7RSEL_SIZE 1 161 #define HWi_WSYS08_ROM_ARM7RSEL_MASK 0x20 162 //bit:3 163 #define HWi_WSYS08_ROM_ARM9RSEL_SHIFT 3 164 #define HWi_WSYS08_ROM_ARM9RSEL_SIZE 1 165 #define HWi_WSYS08_ROM_ARM9RSEL_MASK 0x08 166 //bit:2 167 #define HWi_WSYS08_ROM_ARM9SEC_SHIFT 2 168 #define HWi_WSYS08_ROM_ARM9SEC_SIZE 1 169 #define HWi_WSYS08_ROM_ARM9SEC_MASK 0x04 170 //bit:1 171 #define HWi_WSYS08_OP_OP1_SHIFT 1 172 #define HWi_WSYS08_OP_OP1_SIZE 1 173 #define HWi_WSYS08_OP_OP1_MASK 0x02 174 //bit:0 175 #define HWi_WSYS08_OP_OP0_SHIFT 0 176 #define HWi_WSYS08_OP_OP0_SIZE 1 177 #define HWi_WSYS08_OP_OP0_MASK 0x01 178 //bit:1-0 179 #define HWi_WSYS08_OP_OPT_SHIFT 0 180 #define HWi_WSYS08_OP_OPT_SIZE 2 181 #define HWi_WSYS08_OP_OPT_MASK 0x03 182 183 //---------------------------------------------------------------- 184 //HW_PRV_WRAM_SYSRV+9: SCFG_JTAG & SCFG_CLK 2Byte -> 1Byte 185 186 #define HWi_WSYS09_SIZE 1 187 #define HWi_WSYS09_OFFSET 5 188 #define HWi_WSYS09_WRAMOFFSET (HWi_WSYS09_OFFSET+4) 189 #define HWi_WSYS09_ADDR (HW_PRV_WRAM_SYSRV + HWi_WSYS09_WRAMOFFSET) 190 191 //bit:7 192 #define HWi_WSYS09_CLK_SNDMCLK_SHIFT 7 193 #define HWi_WSYS09_CLK_SNDMCLK_SIZE 1 194 #define HWi_WSYS09_CLK_SNDMCLK_MASK 0x80 195 //bit:6 196 #define HWi_WSYS09_CLK_WRAMHCLK_SHIFT 6 197 #define HWi_WSYS09_CLK_WRAMHCLK_SIZE 1 198 #define HWi_WSYS09_CLK_WRAMHCLK_MASK 0x40 199 //bit:5 200 #define HWi_WSYS09_CLK_AESHCLK_SHIFT 5 201 #define HWi_WSYS09_CLK_AESHCLK_SIZE 1 202 #define HWi_WSYS09_CLK_AESHCLK_MASK 0x20 203 //bit:4 204 #define HWi_WSYS09_CLK_SD2HCLK_SHIFT 4 205 #define HWi_WSYS09_CLK_SD2HCLK_SIZE 1 206 #define HWi_WSYS09_CLK_SD2HCLK_MASK 0x10 207 //bit:3 208 #define HWi_WSYS09_CLK_SD1HCLK_SHIFT 3 209 #define HWi_WSYS09_CLK_SD1HCLK_SIZE 1 210 #define HWi_WSYS09_CLK_SD1HCLK_MASK 0x08 211 //bit:2 212 #define HWi_WSYS09_JTAG_DSPJE_SHIFT 2 213 #define HWi_WSYS09_JTAG_DSPJE_SIZE 1 214 #define HWi_WSYS09_JTAG_DSPJE_MASK 0x04 215 //bit:1 216 #define HWi_WSYS09_JTAG_CPUJE_SHIFT 1 217 #define HWi_WSYS09_JTAG_CPUJE_SIZE 1 218 #define HWi_WSYS09_JTAG_CPUJE_MASK 0x02 219 //bit:0 220 #define HWi_WSYS09_JTAG_ARM7SEL_SHIFT 0 221 #define HWi_WSYS09_JTAG_ARM7SEL_SIZE 1 222 #define HWi_WSYS09_JTAG_ARM7SEL_MASK 0x01 223 224 //---------------------------------------------------------------- 225 #ifdef __cplusplus 226 } /* extern "C" */ 227 #endif 228 229 /* TWL_HW_COMMON_WRAMENV_H_ */ 230 #endif 231