1 /*---------------------------------------------------------------------------* 2 3 Copyright (C) 2010-2011 Nintendo. All rights reserved. 4 5 These coded instructions, statements, and computer programs contain 6 proprietary information of Nintendo of America Inc. and/or Nintendo 7 Company Ltd., and are protected by Federal copyright law. They may 8 not be disclosed to third parties or copied or duplicated in any form, 9 in whole or in part, without the prior written consent of Nintendo. 10 11 *---------------------------------------------------------------------------*/ 12 13 // gx2PerfEnum.h 14 // 15 // Declares performance enums for gx2 library. 16 17 #ifndef _CAFE_GX2_PERF_ENUM_H_ 18 #define _CAFE_GX2_PERF_ENUM_H_ 19 20 #ifdef __cplusplus 21 extern "C" 22 { 23 #endif // __cplusplus 24 25 #if defined _WIN32 || defined _WIN64 26 #include <assert.h> 27 #include <string.h> 28 #ifndef ASSERT 29 #define ASSERT assert 30 #endif // ASSERT 31 #endif 32 33 #define GX2_CHECK_ENUM_RANGE(value, type) \ 34 ASSERT(value>=type##_FIRST && value<=type##_LAST); 35 36 /// @addtogroup GX2PerfEnumGroup 37 /// @{ 38 39 /// \brief Indicates a set of counters in a GPU block 40 /// 41 /// 42 typedef enum __GX2CounterId { 43 GX2_COUNTER_CP_0 = 0x00, 44 GX2_COUNTER_GRBM_0 = 0x01, 45 GX2_COUNTER_GRBM_1 = 0x02, 46 GX2_COUNTER_PA_SU_0 = 0x03, 47 GX2_COUNTER_PA_SU_1 = 0x04, 48 GX2_COUNTER_PA_SU_2 = 0x05, 49 GX2_COUNTER_PA_SU_3 = 0x06, 50 GX2_COUNTER_PA_SC_0 = 0x07, 51 GX2_COUNTER_PA_SC_1 = 0x08, 52 GX2_COUNTER_PA_SC_2 = 0x09, 53 GX2_COUNTER_PA_SC_3 = 0x0a, 54 GX2_COUNTER_VGT_0 = 0x0b, 55 GX2_COUNTER_VGT_1 = 0x0c, 56 GX2_COUNTER_VGT_2 = 0x0d, 57 GX2_COUNTER_VGT_3 = 0x0e, 58 GX2_COUNTER_SQ_0 = 0x0f, 59 GX2_COUNTER_SQ_1 = 0x10, 60 GX2_COUNTER_SQ_2 = 0x11, 61 GX2_COUNTER_SQ_3 = 0x12, 62 GX2_COUNTER_SPI_0 = 0x13, 63 GX2_COUNTER_SPI_1 = 0x14, 64 GX2_COUNTER_SPI_2 = 0x15, 65 GX2_COUNTER_SPI_3 = 0x16, 66 GX2_COUNTER_SX_0 = 0x17, 67 GX2_COUNTER_SX_1 = 0x18, 68 GX2_COUNTER_SX_2 = 0x19, 69 GX2_COUNTER_SX_3 = 0x1a, 70 GX2_COUNTER_SMX_0 = 0x1b, 71 GX2_COUNTER_SMX_1 = 0x1c, 72 GX2_COUNTER_SMX_2 = 0x1d, 73 GX2_COUNTER_SMX_3 = 0x1e, 74 75 /// \brief TD instance 0. When configuring counters, this controls what TD_0_0 and TD_0_1 count. When getting results, this holds the result from TD instance 0. 76 GX2_COUNTER_TD_0_0 = 0x1f, 77 /// \brief TD instance 1. When configuring counters, this is ignored. It is controlled by TD_0_0. When getting results, this holds the result from TD instance 1. 78 GX2_COUNTER_TD_0_1 = 0x20, 79 /// \brief TA counter 0, instance 0. When configuring counters, this controls what TA_0_0 and TA_0_1 count. When getting results, this holds the result from TA instance 0. 80 GX2_COUNTER_TA_0_0 = 0x21, 81 /// \brief TA counter 0, instance 1. When configuring counters, this is ignored. It is controlled by TA_0_0. When getting results, this holds the result from TA instance 1. 82 GX2_COUNTER_TA_0_1 = 0x22, 83 /// \brief TA counter 1, instance 0. When configuring counters, this controls what TA_1_0 and TA_1_1 count. When getting results, this holds the result from TA instance 0. 84 GX2_COUNTER_TA_1_0 = 0x23, 85 /// \brief TA counter 1, instance 1. When configuring counters, this is ignored. It is controlled by TA_1_0. When getting results, this holds the result from TA instance 1. 86 GX2_COUNTER_TA_1_1 = 0x24, 87 /// \brief TCP counter 0, instance 0. When configuring counters, this controls what TCP_0_0 and TCP_0_1 count. When getting results, this holds the result from TCP instance 0. 88 GX2_COUNTER_TCP_0_0 = 0x25, 89 /// \brief TCP counter 0, instance 1. When configuring counters, this is ignored. It is controlled by TCP_0_0. When getting results, this holds the result from TCP instance 1. 90 GX2_COUNTER_TCP_0_1 = 0x26, 91 /// \brief TCP counter 1, instance 0. When configuring counters, this controls what TCP_1_0 and TCP_1_1 count. When getting results, this holds the result from TCP instance 0. 92 GX2_COUNTER_TCP_1_0 = 0x27, 93 /// \brief TCP counter 1, instance 1. When configuring counters, this is ignored. It is controlled by TCP_1_0. When getting results, this holds the result from TCP instance 1. 94 GX2_COUNTER_TCP_1_1 = 0x28, 95 /// \brief TCP counter 2, instance 0. When configuring counters, this controls what TCP_2_0 and TCP_2_1 count. When getting results, this holds the result from TCP instance 0. 96 GX2_COUNTER_TCP_2_0 = 0x29, 97 /// \brief TCP counter 2, instance 1. When configuring counters, this is ignored. It is controlled by TCP_2_0. When getting results, this holds the result from TCP instance 1. 98 GX2_COUNTER_TCP_2_1 = 0x2a, 99 /// \brief TCP counter 3, instance 0. When configuring counters, this controls what TCP_3_0 and TCP_3_1 count. When getting results, this holds the result from TCP instance 0. 100 GX2_COUNTER_TCP_3_0 = 0x2b, 101 /// \brief TCP counter 3, instance 1. When configuring counters, this is ignored. It is controlled by TCP_3_0. When getting results, this holds the result from TCP instance 1. 102 GX2_COUNTER_TCP_3_1 = 0x2c, 103 /// \brief TCC counter 0, instance 0. When configuring counters, this controls what TCC_0_0 and TCC_0_1 count. When getting results, this holds the result from TCC instance 0. 104 GX2_COUNTER_TCC_0_0 = 0x2d, 105 /// \brief TCC counter 0, instance 1. When configuring counters, this is ignored. It is controlled by TCC_0_0. When getting results, this holds the result from TCC instance 1. 106 GX2_COUNTER_TCC_0_1 = 0x2e, 107 /// \brief TCC counter 1, instance 0. When configuring counters, this controls what TCC_1_0 and TCC_1_1 count. When getting results, this holds the result from TCC instance 0. 108 GX2_COUNTER_TCC_1_0 = 0x2f, 109 /// \brief TCC counter 1, instance 1. When configuring counters, this is ignored. It is controlled by TCC_1_0. When getting results, this holds the result from TCC instance 1. 110 GX2_COUNTER_TCC_1_1 = 0x30, 111 /// \brief TCC counter 2, instance 0. When configuring counters, this controls what TCC_2_0 and TCC_2_1 count. When getting results, this holds the result from TCC instance 0. 112 GX2_COUNTER_TCC_2_0 = 0x31, 113 /// \brief TCC counter 2, instance 1. When configuring counters, this is ignored. It is controlled by TCC_2_0. When getting results, this holds the result from TCC instance 1. 114 GX2_COUNTER_TCC_2_1 = 0x32, 115 /// \brief TCC counter 3, instance 0. When configuring counters, this controls what TCC_3_0 and TCC_3_1 count. When getting results, this holds the result from TCC instance 0. 116 GX2_COUNTER_TCC_3_0 = 0x33, 117 /// \brief TCC counter 3, instance 1. When configuring counters, this is ignored. It is controlled by TCC_3_0. When getting results, this holds the result from TCC instance 1. 118 GX2_COUNTER_TCC_3_1 = 0x34, 119 120 /// \brief CB counter 0, instance 0. When configuring counters, this controls what CB_0_0 and CB_0_1 count. When getting results, this holds the result from CB instance 0. 121 GX2_COUNTER_CB_0_0 = 0x3d, 122 /// \brief CB counter 0, instance 1. When configuring counters, this is ignored. It is controlled by CB_0_0. When getting results, this holds the result from CB instance 1. 123 GX2_COUNTER_CB_0_1 = 0x3e, 124 /// \brief CB counter 1, instance 0. When configuring counters, this controls what CB_1_0 and CB_1_1 count. When getting results, this holds the result from CB instance 0. 125 GX2_COUNTER_CB_1_0 = 0x3f, 126 /// \brief CB counter 1, instance 1. When configuring counters, this is ignored. It is controlled by CB_1_0. When getting results, this holds the result from CB instance 1. 127 GX2_COUNTER_CB_1_1 = 0x40, 128 /// \brief CB counter 2, instance 0. When configuring counters, this controls what CB_2_0 and CB_2_1 count. When getting results, this holds the result from CB instance 0. 129 GX2_COUNTER_CB_2_0 = 0x41, 130 /// \brief CB counter 2, instance 1. When configuring counters, this is ignored. It is controlled by CB_2_0. When getting results, this holds the result from CB instance 1. 131 GX2_COUNTER_CB_2_1 = 0x42, 132 /// \brief CB counter 3, instance 0. When configuring counters, this controls what CB_3_0 and CB_3_1 count. When getting results, this holds the result from CB instance 0. 133 GX2_COUNTER_CB_3_0 = 0x43, 134 /// \brief CB counter 3, instance 1. When configuring counters, this is ignored. It is controlled by CB_3_0. When getting results, this holds the result from CB instance 1. 135 GX2_COUNTER_CB_3_1 = 0x44, 136 137 /// \brief DB counter 0, instance 0. When configuring counters, this controls what DB_0_0 and DB_0_1 count. When getting results, this holds the result from DB instance 0. 138 GX2_COUNTER_DB_0_0 = 0x35, 139 /// \brief DB counter 0, instance 1. When configuring counters, this is ignored. It is controlled by DB_0_0. When getting results, this holds the result from DB instance 1. 140 GX2_COUNTER_DB_0_1 = 0x36, 141 /// \brief DB counter 1, instance 0. When configuring counters, this controls what DB_1_0 and DB_1_1 count. When getting results, this holds the result from DB instance 0. 142 GX2_COUNTER_DB_1_0 = 0x37, 143 /// \brief DB counter 1, instance 1. When configuring counters, this is ignored. It is controlled by DB_1_0. When getting results, this holds the result from DB instance 1. 144 GX2_COUNTER_DB_1_1 = 0x38, 145 /// \brief DB counter 2, instance 0. When configuring counters, this controls what DB_2_0 and DB_2_1 count. When getting results, this holds the result from DB instance 0. 146 GX2_COUNTER_DB_2_0 = 0x39, 147 /// \brief DB counter 2, instance 1. When configuring counters, this is ignored. It is controlled by DB_2_0. When getting results, this holds the result from DB instance 1. 148 GX2_COUNTER_DB_2_1 = 0x3a, 149 /// \brief DB counter 3, instance 0. When configuring counters, this controls what DB_3_0 and DB_3_1 count. When getting results, this holds the result from DB instance 0. 150 GX2_COUNTER_DB_3_0 = 0x3b, 151 /// \brief DB counter 3, instance 1. When configuring counters, this is ignored. It is controlled by DB_3_0. When getting results, this holds the result from DB instance 1. 152 GX2_COUNTER_DB_3_1 = 0x3c, 153 154 GX2_COUNTER_PIPELINE = 0x45, 155 156 GX2_COUNTER_FIRST = GX2_COUNTER_CP_0, 157 GX2_COUNTER_LAST = GX2_COUNTER_PIPELINE 158 } _GX2CounterId; 159 160 /// \brief Indicates shader type for sq counter 161 /// 162 typedef enum __GX2SqType { 163 GX2_SQ_PS = 0x00000100, 164 GX2_SQ_VS = 0x00000200, 165 GX2_SQ_GS = 0x00000400, 166 GX2_SQ_ES = 0x00000800, 167 GX2_SQ_FIRST = GX2_SQ_ES, 168 GX2_SQ_LAST = GX2_SQ_PS 169 } _GX2SqType; 170 171 /// \brief Indicate a specific statistic in a GPU counter block 172 /// 173 typedef enum __GX2StatId { 174 /// Always Count. 175 GX2_STAT_CP_CP_COUNT = 0x00000000, 176 /// RBIU Transaction FIFO FUll. 177 GX2_STAT_CP_RBIU_FIFO_FULL = 0x00000001, 178 /// CSF is Ready to Send data but the MIU is not Ready to Receive it. 179 GX2_STAT_CP_CSF_RTS_BUT_MIU_NOT_RTR = 0x00000002, 180 /// PFP to CSF I1 Request FIFO is FUll. 181 GX2_STAT_CP_CSF_I1_BASE_SIZE_FIFO_FULL_6XX = 0x00000003, 182 /// PFP to CSF I2 Request FIFO is FUll. 183 GX2_STAT_CP_CSF_I2_BASE_SIZE_FIFO_FULL_6XX = 0x00000004, 184 /// PFP to CSF State Request FIFO is FUll. 185 GX2_STAT_CP_CSF_ST_BASE_SIZE_FIFO_FULL = 0x00000005, 186 /// Ring Reorder Queue is Full. 187 GX2_STAT_CP_RING_REORDER_QUEUE_FULL = 0x00000006, 188 GX2_STAT_CP_I1_REORDER_QUEUE_FULL = 0x00000007, 189 GX2_STAT_CP_I2_REORDER_QUEUE_FULL = 0x00000008, 190 GX2_STAT_CP_ST_REORDER_QUEUE_FULL = 0x00000009, 191 GX2_STAT_CP_CSF_RB_WPTR_NEQ_RPTR = 0x0000000A, 192 GX2_STAT_CP_CSF_I1_SIZE_NEQ_ZERO = 0x0000000B, 193 GX2_STAT_CP_CSF_I2_SIZE_NEQ_ZERO = 0x0000000C, 194 GX2_STAT_CP_BRUSH_WR_CONFIRM_FIFO_FULL_6XX = 0x0000000D, 195 GX2_STAT_CP_CP_GRBM_DWORDS_SENT = 0x0000000E, 196 GX2_STAT_CP_ME_PARSER_BUSY = 0x0000000F, 197 GX2_STAT_CP_COUNT_TYPE0_PACKETS = 0x00000010, 198 GX2_STAT_CP_COUNT_TYPE3_PACKETS = 0x00000011, 199 GX2_STAT_CP_CSF_RBI1I2_FETCHING = 0x00000012, 200 GX2_STAT_CP_ME_STALLED_FOR_DATA_FROM_PFP = 0x00000013, 201 GX2_STAT_CP_CP_GRBM_OUT_OF_CREDITS = 0x00000014, 202 GX2_STAT_CP_CP_PFP_GRBM_OUT_OF_CREDITS = 0x00000015, 203 GX2_STAT_CP_RCIU_STALLED_ON_ME_READ = 0x00000016, 204 GX2_STAT_CP_RCIU_STALLED_ON_DMA_READ = 0x00000017, 205 GX2_STAT_CP_MIU_STALLED_ON_RDREQ_CREDITS_6XX = 0x00000018, 206 GX2_STAT_CP_MIU_STALLED_ON_WRREQ_CREDITS_6XX = 0x00000019, 207 GX2_STAT_CP_MIU_STALLED_ON_WRCLEAN_PHASE_6XX = 0x0000001A, 208 GX2_STAT_CP_SSU_STALLED_ON_ACTIVE_CNTX = 0x0000001B, 209 GX2_STAT_CP_SSU_STALLED_ON_CLEAN_SIGNALS = 0x0000001C, 210 GX2_STAT_CP_QU_STALLED_ON_RECT_DONE_PULSE_6XX = 0x0000001D, 211 GX2_STAT_CP_QU_STALLED_ON_RECT_DONE_WR_CONFIRM_6XX = 0x0000001E, 212 GX2_STAT_CP_QU_STALLED_ON_SC_EOP_DONE_PULSE = 0x0000001F, 213 GX2_STAT_CP_QU_STALLED_ON_SX_EOP_DONE_PULSE = 0x00000020, 214 GX2_STAT_CP_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x00000021, 215 GX2_STAT_CP_QU_STALLED_ON_SIGNAL_SEMAPHORE = 0x00000022, 216 GX2_STAT_CP_QU_STALLED_ON_STREAMOUT_ADDRESS = 0x00000023, 217 GX2_STAT_CP_QU_STALLED_ON_STREAMOUT_DATA = 0x00000024, 218 GX2_STAT_CP_QU_STALLED_ON_PIPELINE_STATISTICS = 0x00000025, 219 GX2_STAT_CP_PFP_STALLED_ON_CSF_READY = 0x00000026, 220 GX2_STAT_CP_PFP_STALLED_ON_MEQ_READY = 0x00000027, 221 GX2_STAT_CP_PFP_STALLED_ON_VGT_READY = 0x00000028, 222 GX2_STAT_CP_PFP_STALLED_ON_PENDING_MULTIPASS = 0x00000029, 223 GX2_STAT_CP_ME_STALLED_ON_BRUSH_WR_CONFIRM_6XX = 0x0000002A, 224 GX2_STAT_CP_ME_STALLED_ON_BUSY_BRUSH_LOGIC_6XX = 0x0000002B, 225 GX2_STAT_CP_ME_STALLED_ON_NO_AVAIL_CR_CNTX_6XX = 0x0000002C, 226 GX2_STAT_CP_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x0000002D, 227 GX2_STAT_CP_ME_STALLED_WRITING_TO_RCIU = 0x0000002E, 228 GX2_STAT_CP_ME_STALLED_WRITING_CONSTANTS = 0x0000002F, 229 GX2_STAT_CP_RBIU_STALLED_WRITING_DMA_REGS = 0x00000030, 230 GX2_STAT_CP_RBIU_STALLED_WRITING_SEM_REGS = 0x00000031, 231 GX2_STAT_CP_RBIU_STALLED_WRITING_MC_WR_ADDR = 0x00000032, 232 GX2_STAT_CP_RBIU_STALLED_WRITING_MC_RD_ADDR_6XX = 0x00000033, 233 GX2_STAT_CP_RBIU_STALLED_WRITING_EOPDONE_FIFO_600 = 0x00000034, 234 GX2_STAT_CP_RBIU_STALLED_WRITING_RECTDONE_FIFO_6XX = 0x00000035, 235 GX2_STAT_CP_RBIU_STALLED_WRITING_STREAMOUT_FIFO_600 = 0x00000036, 236 GX2_STAT_CP_RBIU_STALLED_WRITING_PIPESTATS_FIFO_600 = 0x00000037, 237 GX2_STAT_CP_SEMAPHORE_BUSY_POLLING_FOR_PASS = 0x00000038, 238 GX2_STAT_CP_LOAD_STALLED_ON_SET_COHERENCY = 0x00000039, 239 GX2_STAT_CP_ME_STALLED_ON_PARTIAL_FLUSH = 0x0000003A, 240 GX2_STAT_CP_CSF_IDLE_CONFIRM_TO_ACTIVE_6XX = 0x0000003B, 241 GX2_STAT_CP_DYNAMIC_CLK_VALID = 0x0000003C, 242 GX2_STAT_CP_REGISTER_CLK_VALID = 0x0000003D, 243 GX2_STAT_CP_FIRST = GX2_STAT_CP_CP_COUNT, 244 GX2_STAT_CP_LAST = GX2_STAT_CP_REGISTER_CLK_VALID, 245 GX2_STAT_GRBM_COUNT = 0x00001000, 246 GX2_STAT_GRBM_GUI_ACTIVE = 0x00001001, 247 GX2_STAT_GRBM_VGT_NO_DMA_BUSY = 0x00001002, 248 GX2_STAT_GRBM_VGT_DMA_BUSY = 0x00001003, 249 GX2_STAT_GRBM_TA0_BUSY = 0x00001004, 250 GX2_STAT_GRBM_TA1_BUSY = 0x00001005, 251 GX2_STAT_GRBM_TA2_BUSY = 0x00001006, 252 GX2_STAT_GRBM_TA3_BUSY = 0x00001007, 253 GX2_STAT_GRBM_TC_BUSY_R6XX = 0x00001008, 254 GX2_STAT_GRBM_SX_BUSY = 0x00001009, 255 GX2_STAT_GRBM_SH_BUSY = 0x0000100A, 256 GX2_STAT_GRBM_SPI_BUSY = 0x0000100B, 257 GX2_STAT_GRBM_SMX_BUSY_R6XX = 0x0000100C, 258 GX2_STAT_GRBM_SC_BUSY = 0x0000100D, 259 GX2_STAT_GRBM_DRMDMA_BUSY_R6XX = 0x0000100E, 260 GX2_STAT_GRBM_PA_BUSY = 0x0000100F, 261 GX2_STAT_GRBM_DB0_BUSY = 0x00001010, 262 GX2_STAT_GRBM_DB1_BUSY = 0x00001011, 263 GX2_STAT_GRBM_DB2_BUSY = 0x00001012, 264 GX2_STAT_GRBM_DB3_BUSY = 0x00001013, 265 GX2_STAT_GRBM_CR_BUSY_R6XX = 0x00001014, 266 GX2_STAT_GRBM_CP_COHER_BUSY = 0x00001015, 267 GX2_STAT_GRBM_CP_BUSY = 0x00001016, 268 GX2_STAT_GRBM_CP_DMA_BUSY = 0x00001017, 269 GX2_STAT_GRBM_CB0_BUSY = 0x00001018, 270 GX2_STAT_GRBM_CB1_BUSY = 0x00001019, 271 GX2_STAT_GRBM_CB2_BUSY = 0x0000101A, 272 GX2_STAT_GRBM_CB3_BUSY = 0x0000101B, 273 GX2_STAT_GRBM_VC_BUSY_R6XX = 0x0000101C, 274 GX2_STAT_GRBM_EXTERN_STALL = 0x0000101D, 275 GX2_STAT_GRBM_CP_DMA_IDLE_STALL = 0x0000101E, 276 GX2_STAT_GRBM_GFX_IDLE_STALL = 0x0000101F, 277 GX2_STAT_GRBM_GFX_IDLE_CLEAN_STALL = 0x00001020, 278 GX2_STAT_GRBM_GFX_IDLE_STALL_R600 = 0x00001021, 279 GX2_STAT_GRBM_GFX_IDLE_CLEAN_STALL_R600 = 0x00001022, 280 GX2_STAT_GRBM_TA4_BUSY = 0x00001023, 281 GX2_STAT_GRBM_TA5_BUSY = 0x00001024, 282 GX2_STAT_GRBM_TA6_BUSY = 0x00001025, 283 GX2_STAT_GRBM_TA7_BUSY = 0x00001026, 284 GX2_STAT_GRBM_TA8_BUSY = 0x00001027, 285 GX2_STAT_GRBM_TA9_BUSY = 0x00001028, 286 GX2_STAT_GRBM_TA10_BUSY = 0x00001029, 287 GX2_STAT_GRBM_TA11_BUSY = 0x0000102A, 288 GX2_STAT_GRBM_TA12_BUSY = 0x0000102B, 289 GX2_STAT_GRBM_TA13_BUSY = 0x0000102C, 290 GX2_STAT_GRBM_TA14_BUSY = 0x0000102D, 291 GX2_STAT_GRBM_TA15_BUSY = 0x0000102E, 292 GX2_STAT_GRBM_RESERVED0 = 0x0000102F, 293 GX2_STAT_GRBM_RESERVED1 = 0x00001030, 294 GX2_STAT_GRBM_RESERVED2 = 0x00001031, 295 GX2_STAT_GRBM_RESERVED3 = 0x00001032, 296 GX2_STAT_GRBM_RESERVED4 = 0x00001033, 297 GX2_STAT_GRBM_RESERVED5 = 0x00001034, 298 GX2_STAT_GRBM_RESERVED6 = 0x00001035, 299 GX2_STAT_GRBM_RESERVED7 = 0x00001036, 300 GX2_STAT_GRBM_RESERVED8 = 0x00001037, 301 GX2_STAT_GRBM_RESERVED9 = 0x00001038, 302 GX2_STAT_GRBM_RESERVED10 = 0x00001039, 303 GX2_STAT_GRBM_RESERVED11 = 0x0000103A, 304 GX2_STAT_GRBM_RESERVED12 = 0x0000103B, 305 GX2_STAT_GRBM_RESERVED13 = 0x0000103C, 306 GX2_STAT_GRBM_RESERVED14 = 0x0000103D, 307 GX2_STAT_GRBM_RESERVED15 = 0x0000103E, 308 GX2_STAT_GRBM_USER_DEFINED_BUSY = 0x0000103F, 309 GX2_STAT_GRBM_FIRST = GX2_STAT_GRBM_COUNT, 310 GX2_STAT_GRBM_LAST = GX2_STAT_GRBM_USER_DEFINED_BUSY, 311 GX2_STAT_PA_SU_PASX_REQ = 0x00002000, 312 GX2_STAT_PA_SU_PASX_DISABLE_PIPE = 0x00002001, 313 GX2_STAT_PA_SU_PASX_FIRST_VECTOR = 0x00002002, 314 GX2_STAT_PA_SU_PASX_SECOND_VECTOR = 0x00002003, 315 GX2_STAT_PA_SU_PASX_FIRST_DEAD = 0x00002004, 316 GX2_STAT_PA_SU_PASX_SECOND_DEAD = 0x00002005, 317 GX2_STAT_PA_SU_PASX_VTX_KILL_DISCARD = 0x00002006, 318 GX2_STAT_PA_SU_PASX_VTX_NAN_DISCARD = 0x00002007, 319 GX2_STAT_PA_SU_PA_INPUT_PRIM = 0x00002008, 320 GX2_STAT_PA_SU_PA_INPUT_NULL_PRIM = 0x00002009, 321 GX2_STAT_PA_SU_PA_INPUT_EVENT_FLAG = 0x0000200A, 322 GX2_STAT_PA_SU_PA_INPUT_FIRST_PRIM_SLOT = 0x0000200B, 323 GX2_STAT_PA_SU_PA_INPUT_END_OF_PACKET = 0x0000200C, 324 GX2_STAT_PA_SU_PA_INPUT_EXTENDED_EVENT = 0x0000200D, 325 GX2_STAT_PA_SU_CLPR_CULL_PRIM = 0x0000200E, 326 GX2_STAT_PA_SU_CLPR_VVUCP_CULL_PRIM = 0x0000200F, 327 GX2_STAT_PA_SU_CLPR_VV_CULL_PRIM = 0x00002010, 328 GX2_STAT_PA_SU_CLPR_UCP_CULL_PRIM = 0x00002011, 329 GX2_STAT_PA_SU_CLPR_VTX_KILL_CULL_PRIM = 0x00002012, 330 GX2_STAT_PA_SU_CLPR_VTX_NAN_CULL_PRIM = 0x00002013, 331 GX2_STAT_PA_SU_CLPR_CULL_TO_NULL_PRIM = 0x00002014, 332 GX2_STAT_PA_SU_CLPR_VVUCP_CLIP_PRIM = 0x00002015, 333 GX2_STAT_PA_SU_CLPR_VV_CLIP_PRIM = 0x00002016, 334 GX2_STAT_PA_SU_CLPR_UCP_CLIP_PRIM = 0x00002017, 335 GX2_STAT_PA_SU_CLPR_POINT_CLIP_CANDIDATE = 0x00002018, 336 GX2_STAT_PA_SU_CLPR_CLIP_PLANE_CNT_1 = 0x00002019, 337 GX2_STAT_PA_SU_CLPR_CLIP_PLANE_CNT_2 = 0x0000201A, 338 GX2_STAT_PA_SU_CLPR_CLIP_PLANE_CNT_3 = 0x0000201B, 339 GX2_STAT_PA_SU_CLPR_CLIP_PLANE_CNT_4 = 0x0000201C, 340 GX2_STAT_PA_SU_CLPR_CLIP_PLANE_CNT_5_8 = 0x0000201D, 341 GX2_STAT_PA_SU_CLPR_CLIP_PLANE_CNT_9_12 = 0x0000201E, 342 GX2_STAT_PA_SU_CLPR_CLIP_PLANE_NEAR = 0x0000201F, 343 GX2_STAT_PA_SU_CLPR_CLIP_PLANE_FAR = 0x00002020, 344 GX2_STAT_PA_SU_CLPR_CLIP_PLANE_LEFT = 0x00002021, 345 GX2_STAT_PA_SU_CLPR_CLIP_PLANE_RIGHT = 0x00002022, 346 GX2_STAT_PA_SU_CLPR_CLIP_PLANE_TOP = 0x00002023, 347 GX2_STAT_PA_SU_CLPR_CLIP_PLANE_BOTTOM = 0x00002024, 348 GX2_STAT_PA_SU_CLPR_GSC_KILL_CULL_PRIM = 0x00002025, 349 GX2_STAT_PA_SU_CLPR_RASTER_KILL_CULL_PRIM = 0x00002026, 350 GX2_STAT_PA_SU_CLSM_NULL_PRIM = 0x00002027, 351 GX2_STAT_PA_SU_CLSM_TOTALLY_VISIBLE_PRIM = 0x00002028, 352 GX2_STAT_PA_SU_CLSM_CULL_TO_NULL_PRIM = 0x00002029, 353 GX2_STAT_PA_SU_CLSM_OUT_PRIM_CNT_1 = 0x0000202A, 354 GX2_STAT_PA_SU_CLSM_OUT_PRIM_CNT_2 = 0x0000202B, 355 GX2_STAT_PA_SU_CLSM_OUT_PRIM_CNT_3 = 0x0000202C, 356 GX2_STAT_PA_SU_CLSM_OUT_PRIM_CNT_4 = 0x0000202D, 357 GX2_STAT_PA_SU_CLSM_OUT_PRIM_CNT_5_8 = 0x0000202E, 358 GX2_STAT_PA_SU_CLSM_OUT_PRIM_CNT_9_13 = 0x0000202F, 359 GX2_STAT_PA_SU_CLIPGA_VTE_KILL_PRIM = 0x00002030, 360 GX2_STAT_PA_SU_SU_INPUT_PRIM = 0x00002031, 361 GX2_STAT_PA_SU_SU_INPUT_CLIP_PRIM = 0x00002032, 362 GX2_STAT_PA_SU_SU_INPUT_NULL_PRIM = 0x00002033, 363 GX2_STAT_PA_SU_SU_INPUT_PRIM_DUAL = 0x00002034, 364 GX2_STAT_PA_SU_SU_INPUT_CLIP_PRIM_DUAL = 0x00002035, 365 GX2_STAT_PA_SU_SU_ZERO_AREA_CULL_PRIM = 0x00002036, 366 GX2_STAT_PA_SU_SU_BACK_FACE_CULL_PRIM = 0x00002037, 367 GX2_STAT_PA_SU_SU_FRONT_FACE_CULL_PRIM = 0x00002038, 368 GX2_STAT_PA_SU_SU_POLYMODE_FACE_CULL = 0x00002039, 369 GX2_STAT_PA_SU_SU_POLYMODE_BACK_CULL = 0x0000203A, 370 GX2_STAT_PA_SU_SU_POLYMODE_FRONT_CULL = 0x0000203B, 371 GX2_STAT_PA_SU_SU_POLYMODE_INVALID_FILL = 0x0000203C, 372 GX2_STAT_PA_SU_SU_OUTPUT_PRIM = 0x0000203D, 373 GX2_STAT_PA_SU_SU_OUTPUT_CLIP_PRIM = 0x0000203E, 374 GX2_STAT_PA_SU_SU_OUTPUT_NULL_PRIM = 0x0000203F, 375 GX2_STAT_PA_SU_SU_OUTPUT_EVENT_FLAG = 0x00002040, 376 GX2_STAT_PA_SU_SU_OUTPUT_FIRST_PRIM_SLOT = 0x00002041, 377 GX2_STAT_PA_SU_SU_OUTPUT_END_OF_PACKET = 0x00002042, 378 GX2_STAT_PA_SU_SU_OUTPUT_POLYMODE_FACE = 0x00002043, 379 GX2_STAT_PA_SU_SU_OUTPUT_POLYMODE_BACK = 0x00002044, 380 GX2_STAT_PA_SU_SU_OUTPUT_POLYMODE_FRONT = 0x00002045, 381 GX2_STAT_PA_SU_SU_OUT_CLIP_POLYMODE_FACE = 0x00002046, 382 GX2_STAT_PA_SU_SU_OUT_CLIP_POLYMODE_BACK = 0x00002047, 383 GX2_STAT_PA_SU_SU_OUT_CLIP_POLYMODE_FRONT = 0x00002048, 384 GX2_STAT_PA_SU_SU_OUTPUT_PRIM_DUAL = 0x00002049, 385 GX2_STAT_PA_SU_SU_OUTPUT_CLIP_PRIM_DUAL = 0x0000204A, 386 GX2_STAT_PA_SU_SU_OUTPUT_POLYMODE_DUAL = 0x0000204B, 387 GX2_STAT_PA_SU_SU_OUTPUT_CLIP_POLYMODE_DUAL = 0x0000204C, 388 GX2_STAT_PA_SU_PASX_REQ_IDLE = 0x0000204D, 389 GX2_STAT_PA_SU_PASX_REQ_BUSY = 0x0000204E, 390 GX2_STAT_PA_SU_PASX_REQ_STALLED = 0x0000204F, 391 GX2_STAT_PA_SU_PASX_REC_IDLE = 0x00002050, 392 GX2_STAT_PA_SU_PASX_REC_BUSY = 0x00002051, 393 GX2_STAT_PA_SU_PASX_REC_STARVED_SX = 0x00002052, 394 GX2_STAT_PA_SU_PASX_REC_STALLED = 0x00002053, 395 GX2_STAT_PA_SU_PASX_REC_STALLED_POS_MEM = 0x00002054, 396 GX2_STAT_PA_SU_PASX_REC_STALLED_CCGSM_IN = 0x00002055, 397 GX2_STAT_PA_SU_CCGSM_IDLE = 0x00002056, 398 GX2_STAT_PA_SU_CCGSM_BUSY = 0x00002057, 399 GX2_STAT_PA_SU_CCGSM_STALLED = 0x00002058, 400 GX2_STAT_PA_SU_CLPRIM_IDLE = 0x00002059, 401 GX2_STAT_PA_SU_CLPRIM_BUSY = 0x0000205A, 402 GX2_STAT_PA_SU_CLPRIM_STALLED = 0x0000205B, 403 GX2_STAT_PA_SU_CLPRIM_STARVED_CCGSM = 0x0000205C, 404 GX2_STAT_PA_SU_CLIPSM_IDLE = 0x0000205D, 405 GX2_STAT_PA_SU_CLIPSM_BUSY = 0x0000205E, 406 GX2_STAT_PA_SU_CLIPSM_WAIT_CLIP_VERT_ENGH = 0x0000205F, 407 GX2_STAT_PA_SU_CLIPSM_WAIT_HIGH_PRI_SEQ = 0x00002060, 408 GX2_STAT_PA_SU_CLIPSM_WAIT_CLIPGA = 0x00002061, 409 GX2_STAT_PA_SU_CLIPSM_WAIT_AVAIL_VTE_CLIP = 0x00002062, 410 GX2_STAT_PA_SU_CLIPSM_WAIT_CLIP_OUTSM = 0x00002063, 411 GX2_STAT_PA_SU_CLIPGA_IDLE = 0x00002064, 412 GX2_STAT_PA_SU_CLIPGA_BUSY = 0x00002065, 413 GX2_STAT_PA_SU_CLIPGA_STARVED_VTE_CLIP = 0x00002066, 414 GX2_STAT_PA_SU_CLIPGA_STALLED = 0x00002067, 415 GX2_STAT_PA_SU_CLIP_IDLE = 0x00002068, 416 GX2_STAT_PA_SU_CLIP_BUSY = 0x00002069, 417 GX2_STAT_PA_SU_SU_IDLE = 0x0000206A, 418 GX2_STAT_PA_SU_SU_BUSY = 0x0000206B, 419 GX2_STAT_PA_SU_SU_STARVED_CLIP = 0x0000206C, 420 GX2_STAT_PA_SU_SU_STALLED_SC = 0x0000206D, 421 GX2_STAT_PA_SU_PA_DYN_SCLK_VLD = 0x0000206E, 422 GX2_STAT_PA_SU_PA_REG_SCLK_VLD = 0x0000206F, 423 GX2_STAT_PA_SU_FIRST = GX2_STAT_PA_SU_PASX_REQ, 424 GX2_STAT_PA_SU_LAST = GX2_STAT_PA_SU_PA_REG_SCLK_VLD, 425 /// Number of clocks event-window is valid at stage register/primitive setup 426 GX2_STAT_PA_SC_SRPS_WINDOW_VALID = 0x00003000, 427 /// Number of clocks event-window is valid at primitive setup/supertile walker 428 GX2_STAT_PA_SC_PSSW_WINDOW_VALID = 0x00003001, 429 /// Number of clocks event-window is valid at tile picker/quad-z 430 GX2_STAT_PA_SC_TPQZ_WINDOW_VALID = 0x00003002, 431 /// Number of clocks event-window is valid at quad-z/quad processor 432 GX2_STAT_PA_SC_QZQP_WINDOW_VALID = 0x00003003, 433 /// Number of clocks event-window is valid at tile reorder/packer 434 GX2_STAT_PA_SC_TRPK_WINDOW_VALID = 0x00003004, 435 /// Number of clocks event-window is valid at stage register/primitive setup with SC busy 436 GX2_STAT_PA_SC_SRPS_WINDOW_VALID_BUSY = 0x00003005, 437 /// Number of clocks event-window is valid at primitive setup/supertile walker with SC busy 438 GX2_STAT_PA_SC_PSSW_WINDOW_VALID_BUSY = 0x00003006, 439 /// Number of clocks event-window is valid at tile picker/quad-z with SC busy 440 GX2_STAT_PA_SC_TPQZ_WINDOW_VALID_BUSY = 0x00003007, 441 GX2_STAT_PA_SC_QZQP_WINDOW_VALID_BUSY = 0x00003008, 442 GX2_STAT_PA_SC_TRPK_WINDOW_VALID_BUSY = 0x00003009, 443 GX2_STAT_PA_SC_STARVED_BY_PA = 0x0000300A, 444 GX2_STAT_PA_SC_STALLED_BY_PRIMFIFO = 0x0000300B, 445 GX2_STAT_PA_SC_STARVED_BY_DB_TILE = 0x0000300C, 446 GX2_STAT_PA_SC_STARVED_BY_DB_QUAD = 0x0000300D, 447 GX2_STAT_PA_SC_STALLED_BY_TILEORDERFIFO = 0x0000300E, 448 GX2_STAT_PA_SC_STALLED_BY_TILEFIFO = 0x0000300F, 449 GX2_STAT_PA_SC_STALLED_BY_QUADFIFO = 0x00003010, 450 GX2_STAT_PA_SC_STALLED_BY_DB_TILE = 0x00003011, 451 GX2_STAT_PA_SC_STALLED_BY_DB_QUAD = 0x00003012, 452 GX2_STAT_PA_SC_STALLED_BY_SX = 0x00003013, 453 GX2_STAT_PA_SC_STALLED_BY_SPI = 0x00003014, 454 GX2_STAT_PA_SC_SCISSOR_DISCARD = 0x00003015, 455 GX2_STAT_PA_SC_BB_DISCARD = 0x00003016, 456 GX2_STAT_PA_SC_MULTICHIP_PRIM_DISCARD = 0x00003017, 457 GX2_STAT_PA_SC_SUPERTILE_COUNT = 0x00003018, 458 GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H0 = 0x00003019, 459 GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H1 = 0x0000301A, 460 GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H2 = 0x0000301B, 461 GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H3 = 0x0000301C, 462 GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H4 = 0x0000301D, 463 GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H5 = 0x0000301E, 464 GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H6 = 0x0000301F, 465 GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H7 = 0x00003020, 466 GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H8 = 0x00003021, 467 GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H9 = 0x00003022, 468 GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H10 = 0x00003023, 469 GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H11 = 0x00003024, 470 GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H12 = 0x00003025, 471 GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H13 = 0x00003026, 472 GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H14 = 0x00003027, 473 GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H15 = 0x00003028, 474 GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H16 = 0x00003029, 475 GX2_STAT_PA_SC_TILE_PER_PRIM_H0 = 0x0000302A, 476 GX2_STAT_PA_SC_TILE_PER_PRIM_H1 = 0x0000302B, 477 GX2_STAT_PA_SC_TILE_PER_PRIM_H2 = 0x0000302C, 478 GX2_STAT_PA_SC_TILE_PER_PRIM_H3 = 0x0000302D, 479 GX2_STAT_PA_SC_TILE_PER_PRIM_H4 = 0x0000302E, 480 GX2_STAT_PA_SC_TILE_PER_PRIM_H5 = 0x0000302F, 481 GX2_STAT_PA_SC_TILE_PER_PRIM_H6 = 0x00003030, 482 GX2_STAT_PA_SC_TILE_PER_PRIM_H7 = 0x00003031, 483 GX2_STAT_PA_SC_TILE_PER_PRIM_H8 = 0x00003032, 484 GX2_STAT_PA_SC_TILE_PER_PRIM_H9 = 0x00003033, 485 GX2_STAT_PA_SC_TILE_PER_PRIM_H10 = 0x00003034, 486 GX2_STAT_PA_SC_TILE_PER_PRIM_H11 = 0x00003035, 487 GX2_STAT_PA_SC_TILE_PER_PRIM_H12 = 0x00003036, 488 GX2_STAT_PA_SC_TILE_PER_PRIM_H13 = 0x00003037, 489 GX2_STAT_PA_SC_TILE_PER_PRIM_H14 = 0x00003038, 490 GX2_STAT_PA_SC_TILE_PER_PRIM_H15 = 0x00003039, 491 GX2_STAT_PA_SC_TILE_PER_PRIM_H16 = 0x0000303A, 492 GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H0 = 0x0000303B, 493 GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H1 = 0x0000303C, 494 GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H2 = 0x0000303D, 495 GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H3 = 0x0000303E, 496 GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H4 = 0x0000303F, 497 GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H5 = 0x00003040, 498 GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H6 = 0x00003041, 499 GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H7 = 0x00003042, 500 GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H8 = 0x00003043, 501 GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H9 = 0x00003044, 502 GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H10 = 0x00003045, 503 GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H11 = 0x00003046, 504 GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H12 = 0x00003047, 505 GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H13 = 0x00003048, 506 GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H14 = 0x00003049, 507 GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H15 = 0x0000304A, 508 GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H16 = 0x0000304B, 509 GX2_STAT_PA_SC_TILE_PICKED_H1 = 0x0000304C, 510 GX2_STAT_PA_SC_TILE_PICKED_H2 = 0x0000304D, 511 GX2_STAT_PA_SC_TILE_PICKED_CONFLICT = 0x0000304E, 512 GX2_STAT_PA_SC_QZ0_MULTICHIP_TILE_DISCARD = 0x0000304F, 513 GX2_STAT_PA_SC_QZ1_MULTICHIP_TILE_DISCARD = 0x00003050, 514 GX2_STAT_PA_SC_QZ0_TILE_COUNT = 0x00003051, 515 GX2_STAT_PA_SC_QZ1_TILE_COUNT = 0x00003052, 516 GX2_STAT_PA_SC_QZ0_TILE_COVERED_COUNT = 0x00003053, 517 GX2_STAT_PA_SC_QZ1_TILE_COVERED_COUNT = 0x00003054, 518 GX2_STAT_PA_SC_QZ0_TILE_NOT_COVERED_COUNT = 0x00003055, 519 GX2_STAT_PA_SC_QZ1_TILE_NOT_COVERED_COUNT = 0x00003056, 520 GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H0 = 0x00003057, 521 GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H1 = 0x00003058, 522 GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H2 = 0x00003059, 523 GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H3 = 0x0000305A, 524 GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H4 = 0x0000305B, 525 GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H5 = 0x0000305C, 526 GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H6 = 0x0000305D, 527 GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H7 = 0x0000305E, 528 GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H8 = 0x0000305F, 529 GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H9 = 0x00003060, 530 GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H10 = 0x00003061, 531 GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H11 = 0x00003062, 532 GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H12 = 0x00003063, 533 GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H13 = 0x00003064, 534 GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H14 = 0x00003065, 535 GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H15 = 0x00003066, 536 GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H16 = 0x00003067, 537 GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H0 = 0x00003068, 538 GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H1 = 0x00003069, 539 GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H2 = 0x0000306A, 540 GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H3 = 0x0000306B, 541 GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H4 = 0x0000306C, 542 GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H5 = 0x0000306D, 543 GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H6 = 0x0000306E, 544 GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H7 = 0x0000306F, 545 GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H8 = 0x00003070, 546 GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H9 = 0x00003071, 547 GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H10 = 0x00003072, 548 GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H11 = 0x00003073, 549 GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H12 = 0x00003074, 550 GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H13 = 0x00003075, 551 GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H14 = 0x00003076, 552 GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H15 = 0x00003077, 553 GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H16 = 0x00003078, 554 GX2_STAT_PA_SC_QZ0_QUAD_COUNT = 0x00003079, 555 GX2_STAT_PA_SC_QZ1_QUAD_COUNT = 0x0000307A, 556 GX2_STAT_PA_SC_QUAD0_NOT_PICKED_TB_R6XX = 0x0000307B, 557 GX2_STAT_PA_SC_QUAD1_NOT_PICKED_TB_R6XX = 0x0000307C, 558 GX2_STAT_PA_SC_QUAD2_NOT_PICKED_TB_R6XX = 0x0000307D, 559 GX2_STAT_PA_SC_QUAD3_NOT_PICKED_TB_R6XX = 0x0000307E, 560 GX2_STAT_PA_SC_P0_HIZ_TILE_COUNT = 0x0000307F, 561 GX2_STAT_PA_SC_P1_HIZ_TILE_COUNT = 0x00003080, 562 GX2_STAT_PA_SC_P2_HIZ_TILE_COUNT = 0x00003081, 563 GX2_STAT_PA_SC_P3_HIZ_TILE_COUNT = 0x00003082, 564 GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H0 = 0x00003083, 565 GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H1 = 0x00003084, 566 GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H2 = 0x00003085, 567 GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H3 = 0x00003086, 568 GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H4 = 0x00003087, 569 GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H5 = 0x00003088, 570 GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H6 = 0x00003089, 571 GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H7 = 0x0000308A, 572 GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H8 = 0x0000308B, 573 GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H9 = 0x0000308C, 574 GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H10 = 0x0000308D, 575 GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H11 = 0x0000308E, 576 GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H12 = 0x0000308F, 577 GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H13 = 0x00003090, 578 GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H14 = 0x00003091, 579 GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H15 = 0x00003092, 580 GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H16 = 0x00003093, 581 GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H0 = 0x00003094, 582 GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H1 = 0x00003095, 583 GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H2 = 0x00003096, 584 GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H3 = 0x00003097, 585 GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H4 = 0x00003098, 586 GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H5 = 0x00003099, 587 GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H6 = 0x0000309A, 588 GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H7 = 0x0000309B, 589 GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H8 = 0x0000309C, 590 GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H9 = 0x0000309D, 591 GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H10 = 0x0000309E, 592 GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H11 = 0x0000309F, 593 GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H12 = 0x000030A0, 594 GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H13 = 0x000030A1, 595 GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H14 = 0x000030A2, 596 GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H15 = 0x000030A3, 597 GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H16 = 0x000030A4, 598 GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H0 = 0x000030A5, 599 GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H1 = 0x000030A6, 600 GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H2 = 0x000030A7, 601 GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H3 = 0x000030A8, 602 GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H4 = 0x000030A9, 603 GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H5 = 0x000030AA, 604 GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H6 = 0x000030AB, 605 GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H7 = 0x000030AC, 606 GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H8 = 0x000030AD, 607 GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H9 = 0x000030AE, 608 GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H10 = 0x000030AF, 609 GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H11 = 0x000030B0, 610 GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H12 = 0x000030B1, 611 GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H13 = 0x000030B2, 612 GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H14 = 0x000030B3, 613 GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H15 = 0x000030B4, 614 GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H16 = 0x000030B5, 615 GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H0 = 0x000030B6, 616 GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H1 = 0x000030B7, 617 GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H2 = 0x000030B8, 618 GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H3 = 0x000030B9, 619 GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H4 = 0x000030BA, 620 GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H5 = 0x000030BB, 621 GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H6 = 0x000030BC, 622 GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H7 = 0x000030BD, 623 GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H8 = 0x000030BE, 624 GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H9 = 0x000030BF, 625 GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H10 = 0x000030C0, 626 GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H11 = 0x000030C1, 627 GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H12 = 0x000030C2, 628 GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H13 = 0x000030C3, 629 GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H14 = 0x000030C4, 630 GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H15 = 0x000030C5, 631 GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H16 = 0x000030C6, 632 GX2_STAT_PA_SC_P0_HIZ_QUAD_COUNT = 0x000030C7, 633 GX2_STAT_PA_SC_P1_HIZ_QUAD_COUNT = 0x000030C8, 634 GX2_STAT_PA_SC_P2_HIZ_QUAD_COUNT = 0x000030C9, 635 GX2_STAT_PA_SC_P3_HIZ_QUAD_COUNT = 0x000030CA, 636 GX2_STAT_PA_SC_P0_DETAIL_QUAD_COUNT = 0x000030CB, 637 GX2_STAT_PA_SC_P1_DETAIL_QUAD_COUNT = 0x000030CC, 638 GX2_STAT_PA_SC_P2_DETAIL_QUAD_COUNT = 0x000030CD, 639 GX2_STAT_PA_SC_P3_DETAIL_QUAD_COUNT = 0x000030CE, 640 GX2_STAT_PA_SC_P0_DETAIL_QUAD_WITH_1_PIX = 0x000030CF, 641 GX2_STAT_PA_SC_P0_DETAIL_QUAD_WITH_2_PIX = 0x000030D0, 642 GX2_STAT_PA_SC_P0_DETAIL_QUAD_WITH_3_PIX = 0x000030D1, 643 GX2_STAT_PA_SC_P0_DETAIL_QUAD_WITH_4_PIX = 0x000030D2, 644 GX2_STAT_PA_SC_P1_DETAIL_QUAD_WITH_1_PIX = 0x000030D3, 645 GX2_STAT_PA_SC_P1_DETAIL_QUAD_WITH_2_PIX = 0x000030D4, 646 GX2_STAT_PA_SC_P1_DETAIL_QUAD_WITH_3_PIX = 0x000030D5, 647 GX2_STAT_PA_SC_P1_DETAIL_QUAD_WITH_4_PIX = 0x000030D6, 648 GX2_STAT_PA_SC_P2_DETAIL_QUAD_WITH_1_PIX = 0x000030D7, 649 GX2_STAT_PA_SC_P2_DETAIL_QUAD_WITH_2_PIX = 0x000030D8, 650 GX2_STAT_PA_SC_P2_DETAIL_QUAD_WITH_3_PIX = 0x000030D9, 651 GX2_STAT_PA_SC_P2_DETAIL_QUAD_WITH_4_PIX = 0x000030DA, 652 GX2_STAT_PA_SC_P3_DETAIL_QUAD_WITH_1_PIX = 0x000030DB, 653 GX2_STAT_PA_SC_P3_DETAIL_QUAD_WITH_2_PIX = 0x000030DC, 654 GX2_STAT_PA_SC_P3_DETAIL_QUAD_WITH_3_PIX = 0x000030DD, 655 GX2_STAT_PA_SC_P3_DETAIL_QUAD_WITH_4_PIX = 0x000030DE, 656 GX2_STAT_PA_SC_EARLYZ_QUAD_COUNT = 0x000030DF, 657 GX2_STAT_PA_SC_EARLYZ_QUAD_WITH_1_PIX = 0x000030E0, 658 GX2_STAT_PA_SC_EARLYZ_QUAD_WITH_2_PIX = 0x000030E1, 659 GX2_STAT_PA_SC_EARLYZ_QUAD_WITH_3_PIX = 0x000030E2, 660 GX2_STAT_PA_SC_EARLYZ_QUAD_WITH_4_PIX = 0x000030E3, 661 GX2_STAT_PA_SC_TILE_REORDER_DB_CONFLICT_R6XX = 0x000030E4, 662 GX2_STAT_PA_SC_PKR_QUAD_PER_ROW_H1 = 0x000030E5, 663 GX2_STAT_PA_SC_PKR_QUAD_PER_ROW_H2 = 0x000030E6, 664 GX2_STAT_PA_SC_PKR_QUAD_PER_ROW_H3 = 0x000030E7, 665 GX2_STAT_PA_SC_PKR_QUAD_PER_ROW_H4 = 0x000030E8, 666 GX2_STAT_PA_SC_PKR_END_OF_VECTOR = 0x000030E9, 667 GX2_STAT_PA_SC_PKR_CONTROL_XFER = 0x000030EA, 668 GX2_STAT_PA_SC_PKR_DBHANG_FORCE_EOV = 0x000030EB, 669 GX2_STAT_PA_SC_REG_SCLK_BUSY = 0x000030EC, 670 GX2_STAT_PA_SC_GRP0_DYN_SCLK_BUSY = 0x000030ED, 671 GX2_STAT_PA_SC_GRP1_DYN_SCLK_BUSY = 0x000030EE, 672 GX2_STAT_PA_SC_GRP2_DYN_SCLK_BUSY = 0x000030EF, 673 GX2_STAT_PA_SC_GRP3_DYN_SCLK_BUSY = 0x000030F0, 674 GX2_STAT_PA_SC_GRP4_DYN_SCLK_BUSY = 0x000030F1, 675 GX2_STAT_PA_SC_FIRST = GX2_STAT_PA_SC_SRPS_WINDOW_VALID, 676 GX2_STAT_PA_SC_LAST = GX2_STAT_PA_SC_GRP4_DYN_SCLK_BUSY, 677 GX2_STAT_VGT_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE = 0x00004000, 678 GX2_STAT_VGT_VGT_SPI_ESVERT_VALID = 0x00004001, 679 GX2_STAT_VGT_VGT_SPI_ESVERT_EOV = 0x00004002, 680 GX2_STAT_VGT_VGT_SPI_ESVERT_STALLED = 0x00004003, 681 GX2_STAT_VGT_VGT_SPI_ESVERT_STARVED_BUSY = 0x00004004, 682 GX2_STAT_VGT_VGT_SPI_ESVERT_STARVED_IDLE = 0x00004005, 683 GX2_STAT_VGT_VGT_SPI_ESVERT_STATIC = 0x00004006, 684 GX2_STAT_VGT_VGT_SPI_ESTHREAD_IS_EVENT = 0x00004007, 685 GX2_STAT_VGT_VGT_SPI_ESTHREAD_SEND = 0x00004008, 686 GX2_STAT_VGT_VGT_SPI_GSPRIM_VALID = 0x00004009, 687 GX2_STAT_VGT_VGT_SPI_GSPRIM_EOV = 0x0000400A, 688 GX2_STAT_VGT_VGT_SPI_GSPRIM_CONT = 0x0000400B, 689 GX2_STAT_VGT_VGT_SPI_GSPRIM_STALLED = 0x0000400C, 690 GX2_STAT_VGT_VGT_SPI_GSPRIM_STARVED_BUSY = 0x0000400D, 691 GX2_STAT_VGT_VGT_SPI_GSPRIM_STARVED_IDLE = 0x0000400E, 692 GX2_STAT_VGT_VGT_SPI_GSPRIM_STATIC = 0x0000400F, 693 GX2_STAT_VGT_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE = 0x00004010, 694 GX2_STAT_VGT_VGT_SPI_GSTHREAD_IS_EVENT = 0x00004011, 695 GX2_STAT_VGT_VGT_SPI_GSTHREAD_SEND = 0x00004012, 696 GX2_STAT_VGT_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE = 0x00004013, 697 GX2_STAT_VGT_VGT_SPI_VSVERT_SEND = 0x00004014, 698 GX2_STAT_VGT_VGT_SPI_VSVERT_EOV = 0x00004015, 699 GX2_STAT_VGT_VGT_SPI_VSVERT_STALLED = 0x00004016, 700 GX2_STAT_VGT_VGT_SPI_VSVERT_STARVED_BUSY = 0x00004017, 701 GX2_STAT_VGT_VGT_SPI_VSVERT_STARVED_IDLE = 0x00004018, 702 GX2_STAT_VGT_VGT_SPI_VSVERT_STATIC = 0x00004019, 703 GX2_STAT_VGT_VGT_SPI_VSTHREAD_IS_EVENT = 0x0000401A, 704 GX2_STAT_VGT_VGT_SPI_VSTHREAD_SEND = 0x0000401B, 705 GX2_STAT_VGT_VGT_PA_EVENT_WINDOW_ACTIVE = 0x0000401C, 706 GX2_STAT_VGT_VGT_PA_CLIPV_SEND = 0x0000401D, 707 GX2_STAT_VGT_VGT_PA_CLIPV_FIRSTVERT = 0x0000401E, 708 GX2_STAT_VGT_VGT_PA_CLIPV_STALLED = 0x0000401F, 709 GX2_STAT_VGT_VGT_PA_CLIPV_STARVED_BUSY = 0x00004020, 710 GX2_STAT_VGT_VGT_PA_CLIPV_STARVED_IDLE = 0x00004021, 711 GX2_STAT_VGT_VGT_PA_CLIPV_STATIC = 0x00004022, 712 GX2_STAT_VGT_VGT_PA_CLIPP_SEND = 0x00004023, 713 GX2_STAT_VGT_VGT_PA_CLIPP_EOP = 0x00004024, 714 GX2_STAT_VGT_VGT_PA_CLIPP_IS_EVENT = 0x00004025, 715 GX2_STAT_VGT_VGT_PA_CLIPP_NULL_PRIM = 0x00004026, 716 GX2_STAT_VGT_VGT_PA_CLIPP_NEW_VTX_VECT = 0x00004027, 717 GX2_STAT_VGT_VGT_PA_CLIPP_STALLED = 0x00004028, 718 GX2_STAT_VGT_VGT_PA_CLIPP_STARVED_BUSY = 0x00004029, 719 GX2_STAT_VGT_VGT_PA_CLIPP_STARVED_IDLE = 0x0000402A, 720 GX2_STAT_VGT_VGT_PA_CLIPP_STATIC = 0x0000402B, 721 GX2_STAT_VGT_VGT_PA_CLIPS_SEND = 0x0000402C, 722 GX2_STAT_VGT_VGT_PA_CLIPS_STALLED = 0x0000402D, 723 GX2_STAT_VGT_VGT_PA_CLIPS_STARVED_BUSY = 0x0000402E, 724 GX2_STAT_VGT_VGT_PA_CLIPS_STARVED_IDLE = 0x0000402F, 725 GX2_STAT_VGT_VGT_PA_CLIPS_STATIC = 0x00004030, 726 GX2_STAT_VGT_RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 0x00004031, 727 GX2_STAT_VGT_RBIU_IM_FIFO_STARVED = 0x00004032, 728 GX2_STAT_VGT_RBIU_IM_FIFO_STALLED = 0x00004033, 729 GX2_STAT_VGT_RBIU_DR_FIFO_STARVED = 0x00004034, 730 GX2_STAT_VGT_RBIU_DR_FIFO_STALLED = 0x00004035, 731 GX2_STAT_VGT_RBIU_DI_FIFO_STARVED = 0x00004036, 732 GX2_STAT_VGT_RBIU_DI_FIFO_STALLED = 0x00004037, 733 GX2_STAT_VGT_MC_LAT_BIN_0 = 0x00004038, 734 GX2_STAT_VGT_MC_LAT_BIN_1 = 0x00004039, 735 GX2_STAT_VGT_MC_LAT_BIN_2 = 0x0000403A, 736 GX2_STAT_VGT_MC_LAT_BIN_3 = 0x0000403B, 737 GX2_STAT_VGT_MC_LAT_BIN_4 = 0x0000403C, 738 GX2_STAT_VGT_MC_LAT_BIN_5 = 0x0000403D, 739 GX2_STAT_VGT_MC_LAT_BIN_6 = 0x0000403E, 740 GX2_STAT_VGT_MC_LAT_BIN_7 = 0x0000403F, 741 GX2_STAT_VGT_VGT_BUSY = 0x00004040, 742 GX2_STAT_VGT_VGT_GS_BUSY = 0x00004041, 743 GX2_STAT_VGT_ESVERT_STALLED_ES_TBL = 0x00004042, 744 GX2_STAT_VGT_ESVERT_STALLED_GS_TBL = 0x00004043, 745 GX2_STAT_VGT_ESVERT_STALLED_GS_EVENT = 0x00004044, 746 GX2_STAT_VGT_ESVERT_STALLED_GSPRIM = 0x00004045, 747 GX2_STAT_VGT_GSPRIM_STALLED_ES_TBL = 0x00004046, 748 GX2_STAT_VGT_GSPRIM_STALLED_GS_TBL = 0x00004047, 749 GX2_STAT_VGT_GSPRIM_STALLED_GS_EVENT = 0x00004048, 750 GX2_STAT_VGT_GSPRIM_STALLED_ESVERT = 0x00004049, 751 GX2_STAT_VGT_ESTHREAD_STALLED_ES_RB_FULL = 0x0000404A, 752 GX2_STAT_VGT_ESTHREAD_STALLED_SPI_BP = 0x0000404B, 753 GX2_STAT_VGT_COUNTERS_AVAIL_STALLED = 0x0000404C, 754 GX2_STAT_VGT_GS_RB_SPACE_AVAIL_STALLED = 0x0000404D, 755 GX2_STAT_VGT_GS_ISSUE_RTR_STALLED = 0x0000404E, 756 GX2_STAT_VGT_GSTHREAD_STALLED = 0x0000404F, 757 GX2_STAT_VGT_ES_CACHE_INVLD_STALLED = 0x00004050, 758 GX2_STAT_VGT_WAIT_FOR_ES_DONE_STALLED = 0x00004051, 759 GX2_STAT_VGT_CM_STALLED_BY_GOG = 0x00004052, 760 GX2_STAT_VGT_CM_READING_STALLED = 0x00004053, 761 GX2_STAT_VGT_CM_STALLED_BY_GSFETCH_DONE = 0x00004054, 762 GX2_STAT_VGT_GOG_VS_TBL_STALLED = 0x00004055, 763 GX2_STAT_VGT_GOG_OUT_INDX_STALLED = 0x00004056, 764 GX2_STAT_VGT_GOG_OUT_PRIM_STALLED = 0x00004057, 765 GX2_STAT_VGT_GS_RB_INVLD_STALLED = 0x00004058, 766 GX2_STAT_VGT_GOG_BUSY = 0x00004059, 767 GX2_STAT_VGT_REUSED_VS_INDICES = 0x0000405A, 768 GX2_STAT_VGT_SCLK_REG_VLD_EVENT = 0x0000405B, 769 GX2_STAT_VGT_SCLK_INPUT_VLD_EVENT = 0x0000405C, 770 GX2_STAT_VGT_SCLK_CORE_VLD_EVENT = 0x0000405D, 771 GX2_STAT_VGT_SCLK_INVAL_VLD_EVENT = 0x0000405E, 772 GX2_STAT_VGT_SCLK_GS_VLD_EVENT = 0x0000405F, 773 GX2_STAT_VGT_FIRST = GX2_STAT_VGT_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE, 774 GX2_STAT_VGT_LAST = GX2_STAT_VGT_SCLK_GS_VLD_EVENT, 775 GX2_STAT_SQ_NONE = 0x00005000, 776 /// Clock cycles. Thread-type independent. 777 GX2_STAT_SQ_CYCLES = 0x00005001, 778 /// Clock cycles while SQ is reporting that it is busy. Thread-type independent. 779 GX2_STAT_SQ_BUSY_CYCLES = 0x00005002, 780 /// Number of cycles we have a thread or an event. Thread-type dependent. 781 GX2_STAT_SQ_ANY_BUSY_PER_TYPE = 0x00005003, 782 /// Number of events. Thread-type dependent. Caveat: Event counts are slightly unpredictable because they don`t have an associated state and because we don`t count events when we don`t have acitve threads. 783 GX2_STAT_SQ_EVENTS_PER_TYPE = 0x00005004, 784 /// Number cycles we have an event. Thread-type dependent. 785 GX2_STAT_SQ_EVENTS_BUSY_PER_TYPE = 0x00005005, 786 /// Number of events in the pipeline per clock. 787 GX2_STAT_SQ_EVENT_LEVEL_PER_TYPE = 0x00005006, 788 /// Number of valid items per thread. Thread-type dependent. 789 GX2_STAT_SQ_ITEMS_PER_TYPE = 0x00005007, 790 /// Number of threads with a valid item in a position >= 48. Thread-type dependent. 791 GX2_STAT_SQ_ITEMS_GT_48_PER_TYPE = 0x00005008, 792 /// Number of threads with a valid item in a position >= 32. 793 GX2_STAT_SQ_ITEMS_GT_32_PER_TYPE = 0x00005009, 794 /// Number of threads with a valid item in a position >= 16. Thread-type dependent. 795 GX2_STAT_SQ_ITEMS_GT_16_PER_TYPE = 0x0000500A, 796 /// Number of valid pixel shader quads per thread. Deterministic. 797 GX2_STAT_SQ_QUADS = 0x0000500B, 798 /// Number cycles we have a thread. Thread-type dependent. 799 GX2_STAT_SQ_THREADS_BUSY_PER_TYPE = 0x0000500C, 800 /// Number of threads. Thread-type dependent. 801 GX2_STAT_SQ_THREADS_PER_TYPE = 0x0000500D, 802 /// Number of threads in the pipeline per clock. Thread-type dependent. 803 GX2_STAT_SQ_THREAD_LEVEL_PER_TYPE = 0x0000500E, 804 /// Number of threads waiting to be created. Thread-type dependent. 805 GX2_STAT_SQ_THREAD_LEVEL_WAIT_CREATE_PER_TYPE = 0x0000500F, 806 /// Number of threads with parameter cache unallocated. Thread-type dependent. 807 GX2_STAT_SQ_THREAD_LEVEL_UNALLOC_PARAM_PER_TYPE = 0x00005010, 808 /// Number of threads with pixel buffer unallocated. Thread-type dependent. 809 GX2_STAT_SQ_THREAD_LEVEL_UNALLOC_PIX_PER_TYPE = 0x00005011, 810 /// Number of threads with position buffer unallocated. 811 GX2_STAT_SQ_THREAD_LEVEL_UNALLOC_POS_PER_TYPE = 0x00005012, 812 /// Number of existing non-PS threads sharing the set of enabled thread-types with other selected NONPS counters. 813 GX2_STAT_SQ_THREADS_NONPS = 0x00005013, 814 /// Number of existing non-PS threads per cycle sharing the set of enabled thread-types with other selected NONPS counters. 815 GX2_STAT_SQ_THREAD_LEVEL_NONPS = 0x00005014, 816 /// Number of non-PS threads waiting for export space to be allocated. Must share the set of enabled thread-types with other selected NONPS counters. 817 GX2_STAT_SQ_THREAD_LEVEL_WAIT_ALLOC_NONPS = 0x00005015, 818 /// Number of non-PS threads waiting for instructions to be fetched or completed. Must share the set of enabled thread-types with other selected SHARED_TYPESET counters. 819 GX2_STAT_SQ_THREAD_LEVEL_WAIT_OTHER_NONPS = 0x00005016, 820 /// Number of PS threads waiting for pixel buffer to be allocated. 821 GX2_STAT_SQ_THREAD_LEVEL_WAIT_ALLOC_PS = 0x00005017, 822 /// Number of PS threads waiting for instructions to be fetched or completed. 823 GX2_STAT_SQ_THREAD_LEVEL_WAIT_OTHER_PS = 0x00005018, 824 /// Number of CF instruction issues. Thread-type dependent. Deterministic. 825 GX2_STAT_SQ_CF_INST_ISSUES_PER_TYPE = 0x00005019, 826 /// Number of times only a single instruction is issued on a cycle. 827 GX2_STAT_SQ_CF_INST_ISSUE_ONE = 0x0000501A, 828 /// Number of times two instructions are issued in a single cycle. Thread-type independent. 829 GX2_STAT_SQ_CF_INST_ISSUE_TWO = 0x0000501B, 830 /// Number of cycles when threads exist but no threads are ready to issue. Thread-type dependent. 831 GX2_STAT_SQ_CF_INST_ISSUE_IDLE_PER_TYPE = 0x0000501C, 832 /// Number of instructions executed in Fetch Shader Mode. Does not include initial CALL_FS instruction. Thread-type dependent. Deterministic. 833 GX2_STAT_SQ_CF_INST_ISSUE_FS_PER_TYPE = 0x0000501D, 834 /// Number of CF_ALU instructions issued.Thread-type dependent. 835 GX2_STAT_SQ_CF_INST_ISSUE_ALU_PER_TYPE = 0x0000501E, 836 /// Number of CF_TF instructions issued. Thread-type dependent. 837 GX2_STAT_SQ_CF_INST_ISSUE_TF_PER_TYPE = 0x0000501F, 838 /// Number of CF_VF instructions issued. Thread-type dependent. 839 GX2_STAT_SQ_CF_INST_ISSUE_VF_PER_TYPE = 0x00005020, 840 /// Number of Export instructions issued. Thread-type dependent. 841 GX2_STAT_SQ_CF_INST_ISSUE_EX_PER_TYPE = 0x00005021, 842 /// Number of SMX write instructions issued. Thread-type dependent. 843 GX2_STAT_SQ_CF_INST_ISSUE_SMX_WR_PER_TYPE = 0x00005022, 844 /// Number of SMX read instructions issued. Thread-type dependent. 845 GX2_STAT_SQ_CF_INST_ISSUE_SMX_RD_PER_TYPE = 0x00005023, 846 /// Number of geometry instructions issued. Thread-type dependent. 847 GX2_STAT_SQ_CF_INST_ISSUE_GF_PER_TYPE = 0x00005024, 848 /// Number of non-ALU/TF/VF/EX/SMX/GF instructions issued. Thread-type dependent. 849 GX2_STAT_SQ_CF_INST_ISSUE_OTHER_PER_TYPE = 0x00005025, 850 /// Number of ALU CF tags processed. Thread-type dependent. 851 GX2_STAT_SQ_CF_INST_ISSUE_ALU_CF_PER_TYPE = 0x00005026, 852 /// Number of OTHER and ALU CF tags processed. Thread-type dependent. 853 GX2_STAT_SQ_CF_INST_ISSUE_BL_PER_TYPE = 0x00005027, 854 /// Number of ALU instructions scheduled and trivially rejected. Thread-type dependent. 855 GX2_STAT_SQ_CF_INST_REJECT_ALU_PER_TYPE = 0x00005028, 856 /// Number of times a Texture Fetch instruction is scheduled and trivially rejected. Thread-type dependent. 857 GX2_STAT_SQ_CF_INST_REJECT_TF_PER_TYPE = 0x00005029, 858 /// Number of times a Vertex Fetch instruction is scheduled and trivially rejected. Thread-type dependent. 859 GX2_STAT_SQ_CF_INST_REJECT_VF_PER_TYPE = 0x0000502A, 860 /// Number of times an Export instruction is scheduled and trivially rejected. Thread-type dependent. 861 GX2_STAT_SQ_CF_INST_REJECT_EX_PER_TYPE = 0x0000502B, 862 /// Number of times a SMX write instruction is scheduled and trivially rejected. Thread-type dependent. 863 GX2_STAT_SQ_CF_INST_REJECT_SMX_WR_PER_TYPE = 0x0000502C, 864 /// Number of times a SMX read instruction is scheduled and trivially rejected. Thread-type dependent. 865 GX2_STAT_SQ_CF_INST_REJECT_SMX_RD_PER_TYPE = 0x0000502D, 866 /// Number of geometry instructions trivially rejected. Thread-type dependent. 867 GX2_STAT_SQ_CF_INST_REJECT_GF_PER_TYPE = 0x0000502E, 868 /// Number of non-ALU/TF/VF/EX/SMX/GF instructions rejected. Thread-type dependent. 869 GX2_STAT_SQ_CF_INST_REJECT_OTHER_PER_TYPE = 0x0000502F, 870 /// Number of instructions sent to ALU. Thread-type dependent. 871 GX2_STAT_SQ_CF_INST_FIFO_SEND_ALU_PER_TYPE = 0x00005030, 872 /// Number of instructions sent to Texture Fetch unit. Thread-type dependent. 873 GX2_STAT_SQ_CF_INST_FIFO_SEND_TF_PER_TYPE = 0x00005031, 874 /// Number of instructions sent to Vertex Fetch unit. Thread-type dependent. 875 GX2_STAT_SQ_CF_INST_FIFO_SEND_VF_PER_TYPE = 0x00005032, 876 /// Number of instructions sent to Export unit. Thread-type dependent. 877 GX2_STAT_SQ_CF_INST_FIFO_SEND_EX_PER_TYPE = 0x00005033, 878 /// Number of write instructions sent to SMX Export unit. Thread-type dependent. 879 GX2_STAT_SQ_CF_INST_FIFO_SEND_SMX_WR_PER_TYPE = 0x00005034, 880 /// Number of read instructions sent to SMX Export unit. Thread-type dependent. 881 GX2_STAT_SQ_CF_INST_FIFO_SEND_SMX_RD_PER_TYPE = 0x00005035, 882 /// Number of geometry instructions executed. Thread-type dependent. Deterministic. 883 GX2_STAT_SQ_CF_INST_FIFO_SEND_GF_PER_TYPE = 0x00005036, 884 /// Number of non-ALU/TF/VF/EX/SMX/GF instructions executed. Thread-type dependent. 885 GX2_STAT_SQ_CF_INST_FIFO_SEND_OTHER_PER_TYPE = 0x00005037, 886 /// Number of instructions sent to ALU with no kcache regions locked. Thread-type dependent. 887 GX2_STAT_SQ_CF_INST_FIFO_SEND_ALU_KCACHE_NONE_PER_TYPE = 0x00005038, 888 /// Number of instructions sent to ALU with one kcache regions locked. Thread-type dependent. 889 GX2_STAT_SQ_CF_INST_FIFO_SEND_ALU_KCACHE_ONE_PER_TYPE = 0x00005039, 890 /// Number of instructions sent to ALU with two kcache regions locked. Thread-type dependent. 891 GX2_STAT_SQ_CF_INST_FIFO_SEND_ALU_KCACHE_TWO_PER_TYPE = 0x0000503A, 892 /// Number of kcache region locks in instructions sent to ALU. Thread-type dependent. 893 GX2_STAT_SQ_CF_INST_FIFO_SEND_ALU_KCACHE_PER_TYPE = 0x0000503B, 894 /// Number of ALU units full on a cycle. Thread-type independent. 895 GX2_STAT_SQ_CF_INST_FIFO_FULL_ALU = 0x0000503C, 896 /// Number of cycles the Texture Fetch unit was full. Thread-type independent. 897 GX2_STAT_SQ_CF_INST_FIFO_FULL_TF = 0x0000503D, 898 /// Number of cycles the Vertex Fetch unit was full. Thread-type independent. 899 GX2_STAT_SQ_CF_INST_FIFO_FULL_VF = 0x0000503E, 900 /// Number of cycles the Export unit was full. Thread-type independent. 901 GX2_STAT_SQ_CF_INST_FIFO_FULL_EX = 0x0000503F, 902 /// Number of cycles the SMX Export unit was full. Thread-type independent. 903 GX2_STAT_SQ_CF_INST_FIFO_FULL_SMX = 0x00005040, 904 /// Number of cycles the Geometry Fifo was full. Thread-type independent. 905 GX2_STAT_SQ_CF_INST_FIFO_FULL_GF = 0x00005041, 906 GX2_STAT_SQ_CF_INST_FIFO_FULL_OTHER = 0x00005042, 907 /// Number of credits available for all ALU units. Thread-type independent. 908 GX2_STAT_SQ_CF_INST_FIFO_LEVEL_ALU = 0x00005043, 909 /// Number of credits available for TF unit. Thread-type independent. 910 GX2_STAT_SQ_CF_INST_FIFO_LEVEL_TF = 0x00005044, 911 /// Number of credits available for VF unit. Thread-type independent. 912 GX2_STAT_SQ_CF_INST_FIFO_LEVEL_VF = 0x00005045, 913 /// Number of credits available for EX unit. Thread-type independent. 914 GX2_STAT_SQ_CF_INST_FIFO_LEVEL_EX = 0x00005046, 915 /// Number of credits available for SMX unit. Thread-type independent. 916 GX2_STAT_SQ_CF_INST_FIFO_LEVEL_SMX = 0x00005047, 917 /// Number of credits available for Geometry Fifo. Thread-type independent. 918 GX2_STAT_SQ_CF_INST_FIFO_LEVEL_GF = 0x00005048, 919 GX2_STAT_SQ_CF_INST_FIFO_LEVEL_OTHER = 0x00005049, 920 /// Number of ALU units empty on a cycle. Thread-type independent. 921 GX2_STAT_SQ_CF_INST_FIFO_EMPTY_ALU = 0x0000504A, 922 /// Number of cycles the Texture Fetch unit was empty. Thread-type independent. 923 GX2_STAT_SQ_CF_INST_FIFO_EMPTY_TF = 0x0000504B, 924 /// Number of cycles the Vertex Fetch unit was empty. Thread-type independent. 925 GX2_STAT_SQ_CF_INST_FIFO_EMPTY_VF = 0x0000504C, 926 /// Number of cycles the Export unit was empty. Thread-type independent. 927 GX2_STAT_SQ_CF_INST_FIFO_EMPTY_EX = 0x0000504D, 928 /// Number of cycles the SMX unit was empty. Thread-type independent. 929 GX2_STAT_SQ_CF_INST_FIFO_EMPTY_SMX = 0x0000504E, 930 /// Number of cycles the Geometry fifo was empty. Thread-type independent. 931 GX2_STAT_SQ_CF_INST_FIFO_EMPTY_GF = 0x0000504F, 932 GX2_STAT_SQ_CF_INST_FIFO_EMPTY_OTHER = 0x00005050, 933 /// Number of instructions outstanding for all ALU units. Thread-type dependent. 934 GX2_STAT_SQ_CF_INST_ISSUE_LEVEL_ALU_PER_TYPE = 0x00005051, 935 /// Number of instructions outstanding for TF unit. Thread-type dependent. 936 GX2_STAT_SQ_CF_INST_ISSUE_LEVEL_TF_PER_TYPE = 0x00005052, 937 /// Number of instructions outstanding for VF unit. Thread-type ependent. 938 GX2_STAT_SQ_CF_INST_ISSUE_LEVEL_VF_PER_TYPE = 0x00005053, 939 /// Number of instructions outstanding for EX unit. Thread-type dependent. 940 GX2_STAT_SQ_CF_INST_ISSUE_LEVEL_EX_PER_TYPE = 0x00005054, 941 /// Number of write instructions outstanding for SMX unit. Thread-type dependent. 942 GX2_STAT_SQ_CF_INST_ISSUE_LEVEL_SMX_WR_PER_TYPE = 0x00005055, 943 /// Number of read instructions outstanding for SMX unit. Thread-type dependent. 944 GX2_STAT_SQ_CF_INST_ISSUE_LEVEL_SMX_RD_PER_TYPE = 0x00005056, 945 /// Number of instructions outstanding for Geometry Fifo. Thread-type dependent. 946 GX2_STAT_SQ_CF_INST_ISSUE_LEVEL_GF_PER_TYPE = 0x00005057, 947 /// Number of instructions outstanding for non-ALU/TF/VF/EX/SMX/GF. Thread-type dependent. 948 GX2_STAT_SQ_CF_INST_ISSUE_LEVEL_OTHER_PER_TYPE = 0x00005058, 949 /// Number of times user specified CF address is executed. Deterministic. 950 GX2_STAT_SQ_CF_INST_CHECKPOINT = 0x00005059, 951 /// Number of CF instructions executed including and after the specified CF address. 952 GX2_STAT_SQ_CF_INST_CHECKPOINT_BEFORE = 0x0000505A, 953 /// Number of items valid for execution of instruction at CF address. Deterministic. 954 GX2_STAT_SQ_CF_INST_CHECKPOINT_ITEMS_VALID = 0x0000505B, 955 /// Number of times no items are valid for execution of instruction at CF address. 956 GX2_STAT_SQ_CF_INST_CHECKPOINT_ITEMS_VALID_NONE = 0x0000505C, 957 /// Number of items active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). 958 GX2_STAT_SQ_CF_INST_CHECKPOINT_ITEMS_ACTIVE = 0x0000505D, 959 /// Number of times no items are active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). 960 GX2_STAT_SQ_CF_INST_CHECKPOINT_ITEMS_ACTIVE_NONE = 0x0000505E, 961 /// Number of pixel quads active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). 962 GX2_STAT_SQ_CF_INST_CHECKPOINT_QUADS_ACTIVE = 0x0000505F, 963 /// Number of pixel quads valid for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). 964 GX2_STAT_SQ_CF_INST_CHECKPOINT_QUADS_VALID = 0x00005060, 965 /// Number of times a thread first reaches the CF address. 966 GX2_STAT_SQ_CF_INST_CHECKPOINT_THREADS = 0x00005061, 967 /// Number of threads that have reached the CF address per cycle. 968 GX2_STAT_SQ_CF_INST_CHECKPOINT_THREAD_LEVEL = 0x00005062, 969 /// Number of CF fetch requests from cache. Thread-type dependent. 970 GX2_STAT_SQ_CF_INST_FETCH_PER_TYPE = 0x00005063, 971 /// Number of CF fetch return cycles from cache. Thread-type dependent. 972 GX2_STAT_SQ_CF_INST_FETCH_RETURNS_PER_TYPE = 0x00005064, 973 /// Number of CF instructions requested from cache. Thread-type dependent. 974 GX2_STAT_SQ_CF_INST_FETCH_INSTS_PER_TYPE = 0x00005065, 975 /// Number of CF level requested from cache. Thread-type dependent. 976 GX2_STAT_SQ_CF_INST_FETCH_LEVEL_PER_TYPE = 0x00005066, 977 /// Number of times we didn`t issue the second instruction in a pair. Does not include instructions after PROGRAM_END. Thread-type dependent. 978 GX2_STAT_SQ_CF_INST_FETCH_EXTRA_PER_TYPE = 0x00005067, 979 /// Number of requests passing through the fetch fifo. Thread-type independent. 980 GX2_STAT_SQ_CF_INST_FETCH_FIFO_SEND = 0x00005068, 981 /// Control Flow Fetch fifo entry level. Thread-type independent. 982 GX2_STAT_SQ_CF_INST_FETCH_FIFO_LEVEL = 0x00005069, 983 /// Number of cycles when the CF fetch fifo is stalling issues. Thread-type independent. 984 GX2_STAT_SQ_CF_INST_FETCH_FIFO_STALL = 0x0000506A, 985 /// Number of requests passing through the cache fifo. Thread-type independent. 986 GX2_STAT_SQ_CF_INST_CACHE_FIFO_SEND = 0x0000506B, 987 /// Number of credits in cache. Thread-type independent. 988 GX2_STAT_SQ_CF_INST_CACHE_FIFO_LEVEL = 0x0000506C, 989 /// Number of cycles when we have no cache credits. Thread-type independent. 990 GX2_STAT_SQ_CF_INST_CACHE_FIFO_FULL = 0x0000506D, 991 /// Number of issues that must be accounted for to avoid overflowing the done fifo. Thread-type independent. 992 GX2_STAT_SQ_CF_INST_ISSUE_DONES = 0x0000506E, 993 /// Number of issues pending at any given time that must be accounted for to avoid overflowing the done fifo. Thread-type independent. 994 GX2_STAT_SQ_CF_INST_ISSUE_DONE_LEVEL = 0x0000506F, 995 /// Stalls triggered to avoid overflowing the done fifo. Thread-type independent. 996 GX2_STAT_SQ_CF_INST_ISSUE_DONE_STALL = 0x00005070, 997 /// Number of items passing through the done fifo. Thread-type independent. 998 GX2_STAT_SQ_CF_INST_ISSUE_DONE_FIFO_SEND = 0x00005071, 999 /// Control Flow Done fifo entry level. Thread-type independent. 1000 GX2_STAT_SQ_CF_INST_ISSUE_DONE_FIFO_LEVEL = 0x00005072, 1001 /// Macro sequencer alu update fifo send. Thread-type independent. 1002 GX2_STAT_SQ_CF_INST_ALU_UPDATE_FIFO_SEND = 0x00005073, 1003 /// Macro sequencer alu update fifo level. Thread-type independent. 1004 GX2_STAT_SQ_CF_INST_ALU_UPDATE_FIFO_LEVEL = 0x00005074, 1005 /// Number of cycles when the MS alu update fifo is stalling issues and alu returns. Thread-type independent. 1006 GX2_STAT_SQ_CF_INST_ALU_UPDATE_FIFO_STALL = 0x00005075, 1007 /// Number of threads and events in the ofifo. Thread-type dependent. 1008 GX2_STAT_SQ_OFIFO_LEVEL_PER_TYPE = 0x00005076, 1009 /// Number of cycles the SX event fifo is full. Thread-type dependent. 1010 GX2_STAT_SQ_SX_EVENT_FIFO_FULL_PER_TYPE = 0x00005077, 1011 /// Number of ALU instruction groups executed. Thread-type dependent. 1012 GX2_STAT_SQ_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE = 0x00005078, 1013 /// Number of ALU individual alu instructions executed. Thread-type dependent. 1014 GX2_STAT_SQ_ALU_CLAUSE_INSTRS_PER_TYPE = 0x00005079, 1015 /// Number of ALU instruction groups which use const-waterfall. Thread-type dependent. 1016 GX2_STAT_SQ_ALU_KWATERFALL_PER_TYPE = 0x0000507A, 1017 /// Number of ALU instruction groups which use gpr-waterfall. Thread-type dependent. 1018 GX2_STAT_SQ_ALU_GPRWATERFALL_PER_TYPE = 0x0000507B, 1019 /// Number of ALU instructions which use one or more constant (literal, kcache, or kfile). Thread-type dependent. 1020 GX2_STAT_SQ_ALU_K_INSTR_PER_TYPE = 0x0000507C, 1021 /// Number of times ALU Icache read was denied - cache busy. Thread-type dependent. 1022 GX2_STAT_SQ_ALU_ICACHE_BUSY_PER_TYPE = 0x0000507D, 1023 /// Number of times ALU Kcache/Kfile read was denied - cache busy. Thread-type dependent. 1024 GX2_STAT_SQ_ALU_KCACHE_BUSY_PER_TYPE = 0x0000507E, 1025 /// Number of instruction cycles idle waiting for MOVA to complete. Thread-type dependent. 1026 GX2_STAT_SQ_ALU_MOVA_IDLE_WAIT_PER_TYPE = 0x0000507F, 1027 /// Number of times (1 every 4 clocks) ALU has clauses in input fifo but no clauses locked -- ALU is idle. Thread-type independent. 1028 GX2_STAT_SQ_ALU_LOCK_WAIT = 0x00005080, 1029 /// Number of read requests to the ALU I-cache. Thread-type dependent. Deterministic. 1030 GX2_STAT_SQ_ALU_ICACHE_READS_PER_TYPE = 0x00005081, 1031 /// Number of read requests to the ALU K-cache/K-file. Thread-type dependent. Deterministic. 1032 GX2_STAT_SQ_ALU_KCACHE_READS_PER_TYPE = 0x00005082, 1033 /// Number of times the done-fifo is full and that caused a stall. Thread-type independent. 1034 GX2_STAT_SQ_ALU_DONE_FIFO_FULL = 0x00005083, 1035 /// Number of times more than one SIMD tried to execute MOVA, and one was denied access. Thread-type dependent. 1036 GX2_STAT_SQ_ALU_MOVA_WAIT_PER_TYPE = 0x00005084, 1037 /// Number of threads waiting in the alu-seq`s input fifo each cycle, of the selected thread type. 1038 GX2_STAT_SQ_ALU_THREADS_IN_FIFO_PER_TYPE = 0x00005085, 1039 GX2_STAT_SQ_UNUSED_006 = 0x00005086, 1040 GX2_STAT_SQ_UNUSED_007 = 0x00005087, 1041 /// Number of cycles the Tex/Vtx Icache denied a read request (busy). Thread-type dependent. 1042 GX2_STAT_SQ_TV_ICACHE_WAIT_PER_TYPE = 0x00005088, 1043 GX2_STAT_SQ_UNUSED_010 = 0x00005089, 1044 GX2_STAT_SQ_UNUSED_001 = 0x0000508A, 1045 GX2_STAT_SQ_UNUSED_002 = 0x0000508B, 1046 /// Number of times the TF had data to send to TA, but the TA input fifo was full. Thread-type dependent. 1047 GX2_STAT_SQ_TF_TA_STALL_PER_TYPE = 0x0000508C, 1048 /// Number of times the VF had data to send to Wii U Virtual Console, but the Virtual Console instruction input fifo was full. Thread-type dependent. 1049 GX2_STAT_SQ_VF_VC_INSTR_STALL_PER_TYPE = 0x0000508D, 1050 /// SQ_PERF_SEL_VF_VC_INDEX_STALL_PER_TYPE: Number of times the VF had data to send to Wii U Virtual Console, but the Virtual Console index input fifo was full. Thread-type dependent. 1051 GX2_STAT_SQ_VF_VC_INDEX_STALL_PER_TYPE = 0x0000508E, 1052 GX2_STAT_SQ_UNUSED_003 = 0x0000508F, 1053 GX2_STAT_SQ_UNUSED_008 = 0x00005090, 1054 GX2_STAT_SQ_UNUSED_004 = 0x00005091, 1055 GX2_STAT_SQ_UNUSED_009 = 0x00005092, 1056 /// Number of exports (seen by export-seq). 1057 GX2_STAT_SQ_EXPORT_INSTR_PER_TYPE = 0x00005093, 1058 /// Number of clocks where export unit is idle. Thread-type independent. 1059 GX2_STAT_SQ_EXPORT_IDLE = 0x00005094, 1060 /// Number of clocks SMX export stalled waiting for alloc. Thread-type independent. 1061 GX2_STAT_SQ_EXPORT_SMX_AL_STALL = 0x00005095, 1062 /// Number of clocks Param.cache alloc was stalled. Thread-type independent. 1063 GX2_STAT_SQ_EXPORT_PC_AL_STALL = 0x00005096, 1064 /// Number of clocks Position export alloc was stalled. Thread-type independent. 1065 GX2_STAT_SQ_EXPORT_POS_AL_STALL = 0x00005097, 1066 /// Number of clocks Pixel export alloc was stalled. Thread-type independent. 1067 GX2_STAT_SQ_EXPORT_PIX_AL_STALL = 0x00005098, 1068 /// Number of position export cycles (4 clocks), * burst count). Thread-type independent. 1069 GX2_STAT_SQ_EXPORT_POS_CYCLE = 0x00005099, 1070 /// Number of pixel export cycles (4 clocks), * burst count). Thread-type independent. 1071 GX2_STAT_SQ_EXPORT_PIX_CYCLE = 0x0000509A, 1072 /// Number of param.cache export cycles (4 clocks), * burst count). Thread-type independent. 1073 GX2_STAT_SQ_EXPORT_PC_CYCLE = 0x0000509B, 1074 /// Number of smx export cycles (4 clocks), * burst count). Thread-type dependent. 1075 GX2_STAT_SQ_EXPORT_SMX_CYCLE_PER_TYPE = 0x0000509C, 1076 /// Number of cache invalidation (surface synchronization) operations of any kind. 1077 GX2_STAT_SQ_CACHE_INVAL_ANY = 0x0000509D, 1078 /// Number of cache invalidation (surface synchronization) operations that invalidate the whole cache (due to a large invalidation region). Thread-type independent. 1079 GX2_STAT_SQ_CACHE_INVAL_ALL = 0x0000509E, 1080 /// Number of cache invalidation (surface synchronization) cycles, not including full invalidations; indicates the size of the invalidation regions in 4 KB increments. Thread-type independent. 1081 GX2_STAT_SQ_CACHE_INVAL_CYCLES = 0x0000509F, 1082 /// Number of CF instruction cache hits (it was found in the cache). Thread-type independent. 1083 GX2_STAT_SQ_CF_ICACHE_HITS = 0x000050A0, 1084 /// Number of TV instruction cache hits (it was found in the cache). Thread-type independent. 1085 GX2_STAT_SQ_TF_ICACHE_HITS = 0x000050A1, 1086 GX2_STAT_SQ_VF_ICACHE_HITS = 0x000050A2, 1087 /// Number of ALU instruction cache hits (it was found in the cache). Thread-type independent. 1088 GX2_STAT_SQ_ALU_ICACHE_HITS = 0x000050A3, 1089 /// Number of ALU constant cache hits (it was found in the cache). Thread-type independent. 1090 GX2_STAT_SQ_ALU_KCACHE_HITS = 0x000050A4, 1091 /// Number of CF instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. 1092 GX2_STAT_SQ_CF_ICACHE_MISSES = 0x000050A5, 1093 /// Number of TV instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. 1094 GX2_STAT_SQ_TF_ICACHE_MISSES = 0x000050A6, 1095 GX2_STAT_SQ_VF_ICACHE_MISSES = 0x000050A7, 1096 /// Number of ALU instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. 1097 GX2_STAT_SQ_ALU_ICACHE_MISSES = 0x000050A8, 1098 /// Number of ALU constant cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. 1099 GX2_STAT_SQ_ALU_KCACHE_MISSES = 0x000050A9, 1100 /// Number of CF instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. 1101 GX2_STAT_SQ_CF_ICACHE_DUP_MISSES = 0x000050AA, 1102 /// Number of TV instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. 1103 GX2_STAT_SQ_TF_ICACHE_DUP_MISSES = 0x000050AB, 1104 GX2_STAT_SQ_VF_ICACHE_DUP_MISSES = 0x000050AC, 1105 /// Number of ALU instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. 1106 GX2_STAT_SQ_ALU_ICACHE_DUP_MISSES = 0x000050AD, 1107 /// Number of ALU constant cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. 1108 GX2_STAT_SQ_ALU_KCACHE_DUP_MISSES = 0x000050AE, 1109 /// Number of CF instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. 1110 GX2_STAT_SQ_CF_ICACHE_ACCESSES = 0x000050AF, 1111 /// Number of TV instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. 1112 GX2_STAT_SQ_TF_ICACHE_ACCESSES = 0x000050B0, 1113 GX2_STAT_SQ_VF_ICACHE_ACCESSES = 0x000050B1, 1114 /// Number of ALU instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. 1115 GX2_STAT_SQ_ALU_ICACHE_ACCESSES = 0x000050B2, 1116 /// Number of ALU constant cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. 1117 GX2_STAT_SQ_ALU_KCACHE_ACCESSES = 0x000050B3, 1118 /// Count of CF instruction cache requests stored in the input FIFO. Thread-type independent. 1119 GX2_STAT_SQ_CF_ICACHE_INPUT_FIFO_ENTRIES = 0x000050B4, 1120 /// Count of TV instruction cache requests stored in the input FIFO. Thread-type independent. 1121 GX2_STAT_SQ_TF_ICACHE_INPUT_FIFO_ENTRIES = 0x000050B5, 1122 GX2_STAT_SQ_VF_ICACHE_INPUT_FIFO_ENTRIES = 0x000050B6, 1123 /// Count of ALU instruction cache requests stored in the input FIFO. Thread-type independent. 1124 GX2_STAT_SQ_ALU_ICACHE_INPUT_FIFO_ENTRIES = 0x000050B7, 1125 /// Count of ALU constant cache requests stored in the input FIFO. Thread-type independent. 1126 GX2_STAT_SQ_ALU_KCACHE_INPUT_FIFO_ENTRIES = 0x000050B8, 1127 /// Number of CF instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. 1128 GX2_STAT_SQ_CF_ICACHE_MISS_MEM_STALL = 0x000050B9, 1129 /// Number of TV instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. 1130 GX2_STAT_SQ_TF_ICACHE_MISS_MEM_STALL = 0x000050BA, 1131 GX2_STAT_SQ_VF_ICACHE_MISS_MEM_STALL = 0x000050BB, 1132 /// Number of ALU instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. 1133 GX2_STAT_SQ_ALU_ICACHE_MISS_MEM_STALL = 0x000050BC, 1134 /// Number of ALU constant cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. 1135 GX2_STAT_SQ_ALU_KCACHE_MISS_MEM_STALL = 0x000050BD, 1136 /// Number of CF instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. 1137 GX2_STAT_SQ_CF_ICACHE_MISS_FIFO_STALL = 0x000050BE, 1138 /// Number of TV instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. 1139 GX2_STAT_SQ_TF_ICACHE_MISS_FIFO_STALL = 0x000050BF, 1140 GX2_STAT_SQ_VF_ICACHE_MISS_FIFO_STALL = 0x000050C0, 1141 /// Number of ALU instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. 1142 GX2_STAT_SQ_ALU_ICACHE_MISS_FIFO_STALL = 0x000050C1, 1143 /// Number of ALU constant cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. 1144 GX2_STAT_SQ_ALU_KCACHE_MISS_FIFO_STALL = 0x000050C2, 1145 /// Number of CF instruction cache cycles that are a cache hit but are stalled due to processing previous misses. Thread-type independent. 1146 GX2_STAT_SQ_CF_ICACHE_HIT_STALL = 0x000050C3, 1147 /// Number of CF instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. 1148 GX2_STAT_SQ_CF_ICACHE_MISS_LOCKED_STALL = 0x000050C4, 1149 /// Number of TV instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. 1150 GX2_STAT_SQ_TF_ICACHE_MISS_LOCKED_STALL = 0x000050C5, 1151 GX2_STAT_SQ_VF_ICACHE_MISS_LOCKED_STALL = 0x000050C6, 1152 /// Number of ALU instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. 1153 GX2_STAT_SQ_ALU_ICACHE_MISS_LOCKED_STALL = 0x000050C7, 1154 /// Number of ALU constant cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. 1155 GX2_STAT_SQ_ALU_KCACHE_MISS_LOCKED_STALL = 0x000050C8, 1156 /// Count of CF instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. 1157 GX2_STAT_SQ_CF_ICACHE_LOCKED_TAGS = 0x000050C9, 1158 /// Count of TV instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. 1159 GX2_STAT_SQ_TF_ICACHE_LOCKED_TAGS = 0x000050CA, 1160 GX2_STAT_SQ_VF_ICACHE_LOCKED_TAGS = 0x000050CB, 1161 /// Count of ALU instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. 1162 GX2_STAT_SQ_ALU_ICACHE_LOCKED_TAGS = 0x000050CC, 1163 /// Count of ALU constant cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. 1164 GX2_STAT_SQ_ALU_KCACHE_LOCKED_TAGS = 0x000050CD, 1165 /// Count of CF instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. 1166 GX2_STAT_SQ_CF_ICACHE_MISS_LOCKED_TAGS = 0x000050CE, 1167 /// Count of TV instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. 1168 GX2_STAT_SQ_TF_ICACHE_MISS_LOCKED_TAGS = 0x000050CF, 1169 GX2_STAT_SQ_VF_ICACHE_MISS_LOCKED_TAGS = 0x000050D0, 1170 /// Count of ALU instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. 1171 GX2_STAT_SQ_ALU_ICACHE_MISS_LOCKED_TAGS = 0x000050D1, 1172 /// Count of ALU constant cache tags that are currently locked during a cache miss cycle. Thread-type independent. 1173 GX2_STAT_SQ_ALU_KCACHE_MISS_LOCKED_TAGS = 0x000050D2, 1174 /// Number of cache to memory controller requests of any type. Thread-type independent. 1175 GX2_STAT_SQ_CACHE_MEM_REQUESTS = 0x000050D3, 1176 /// Number of CF instruction cache to memory controller requests. Thread-type independent. 1177 GX2_STAT_SQ_CF_ICACHE_MEM_REQUESTS = 0x000050D4, 1178 /// Number of TV instruction cache to memory controller requests. Thread-type independent. 1179 GX2_STAT_SQ_TV_ICACHE_MEM_REQUESTS = 0x000050D5, 1180 /// Number of ALU instruction cache to memory controller requests. Thread-type independent. 1181 GX2_STAT_SQ_ALU_ICACHE_MEM_REQUESTS = 0x000050D6, 1182 /// Number of ALU constant cache to memory controller requests. Thread-type independent. 1183 GX2_STAT_SQ_ALU_KCACHE_MEM_REQUESTS = 0x000050D7, 1184 /// Number of times a read to the CF icache memory was blocked by a write from a memory return. Thread-type independent. 1185 GX2_STAT_SQ_CF_ICACHE_RD_WR_COLLISION = 0x000050D8, 1186 /// Number of times processing a hit is stalled by processing a now-resident miss. Thread-type independent. 1187 GX2_STAT_SQ_CF_ICACHE_MISS_HIT_RD_COLLISION = 0x000050D9, 1188 /// Count of the number of outstanding CF instruction cache to memory controller requests of any type. Thread-type independent. 1189 GX2_STAT_SQ_CF_ICACHE_MEM_REQUESTS_IN_FLIGHT = 0x000050DA, 1190 /// Count of the number of outstanding TV instruction cache to memory controller requests of any type. Thread-type independent. 1191 GX2_STAT_SQ_TV_ICACHE_MEM_REQUESTS_IN_FLIGHT = 0x000050DB, 1192 /// Count of the number of outstanding ALU instruction cache to memory controller requests of any type. Thread-type independent. 1193 GX2_STAT_SQ_ALU_ICACHE_MEM_REQUESTS_IN_FLIGHT = 0x000050DC, 1194 /// Count of the number of outstanding ALU constant cache to memory controller requests of any type. Thread-type independent. 1195 GX2_STAT_SQ_ALU_KCACHE_MEM_REQUESTS_IN_FLIGHT = 0x000050DD, 1196 /// Count of the number of CF instruction cache misses waiting in the miss FIFO. Thread-type independent. 1197 GX2_STAT_SQ_CF_ICACHE_MISS_FIFO_MISSES = 0x000050DE, 1198 /// Count of the number of TV instruction cache misses waiting in the miss FIFO. Thread-type independent. 1199 GX2_STAT_SQ_TF_ICACHE_MISS_FIFO_MISSES = 0x000050DF, 1200 GX2_STAT_SQ_VF_ICACHE_MISS_FIFO_MISSES = 0x000050E0, 1201 /// Count of the number of ALU instruction cache misses waiting in the miss FIFO. Divided by 2. Thread-type independent. 1202 GX2_STAT_SQ_ALU_ICACHE_MISS_FIFO_MISSES = 0x000050E1, 1203 /// Count of the number of ALU constant cache misses waiting in the miss FIFO. Divided by 2. Thread-type independent. 1204 GX2_STAT_SQ_ALU_KCACHE_MISS_FIFO_MISSES = 0x000050E2, 1205 /// Count of the number of outstanding cache to memory controller requests of any type. Divided by 2. Thread-type independent. 1206 GX2_STAT_SQ_CACHE_MEM_REQUESTS_IN_FLIGHT = 0x000050E3, 1207 /// Number of cache to memory controller cycles that are stalled. Thread-type independent. 1208 GX2_STAT_SQ_CACHE_MEM_STALL = 0x000050E4, 1209 /// Clock cycles GRBM stalled due to time stamp-64 FIFO full. 1210 GX2_STAT_SQ_TM_TS64_STALL = 0x000050E5, 1211 /// Clock cycles GRBM stalled due to ALU constant overflow buffer full. 1212 GX2_STAT_SQ_TM_ALU_CONST_STALL = 0x000050E6, 1213 /// Clock cycles GRBM stalled due to Loop constant overflow buffer full. 1214 GX2_STAT_SQ_TM_LOOP_CONST_STALL = 0x000050E7, 1215 /// Clock cycles GRBM stalled due to VertexBase/InstantStart constant overflow buffer full. 1216 GX2_STAT_SQ_TM_TEX_BASE_CONST_STALL = 0x000050E8, 1217 /// Clock cycles GRBM stalled due to Texture Sampler constant overflow buffer full. 1218 GX2_STAT_SQ_TM_TEX_SAMPLER_STALL = 0x000050E9, 1219 /// Clock cycles GRBM stalled due to Texture Resource constant overflow buffer full. 1220 GX2_STAT_SQ_TM_TEX_RESOURCE_STALL = 0x000050EA, 1221 GX2_STAT_SQ_UNUSED_005 = 0x000050EB, 1222 /// Number of texture-fetch instructions executed by the Texture cache, including killed fetches. Thread-type dependent. 1223 GX2_STAT_SQ_TA_TEX_INSTRS_PER_TYPE = 0x000050EC, 1224 /// Number of vertex-fetch instructions executed by the Texture cache, including killed fetches. Thread-type dependent. 1225 GX2_STAT_SQ_TA_VTX_INSTRS_PER_TYPE = 0x000050ED, 1226 /// Number of instructions executed by the Vertex cache, including killed fetches. Thread-type dependent. 1227 GX2_STAT_SQ_VC_INSTRS_PER_TYPE = 0x000050EE, 1228 /// Number of cycles the TF input FIFO had clauses, none were locked. Thread-type independent 1229 GX2_STAT_SQ_TV_LOCK_WAIT = 0x000050EF, 1230 /// Number of times an TA fetch (16 pix or verts) was executed as a src-c export. 1231 GX2_STAT_SQ_TA_SRC_C = 0x000050F0, 1232 /// Number of times a Wii U Virtual Console fetch (16 pix or verts) was executed as a src-c export. 1233 GX2_STAT_SQ_VC_SRC_C = 0x000050F1, 1234 /// Number of fetch instructions killed (vertex semantic failed or gpr out of range). 1235 GX2_STAT_SQ_TV_KILLED_FETCH_PER_TYPE = 0x000050F2, 1236 /// Number of null fetchs issued (null = issue empty fetch at end of clause due to killed fetches). 1237 GX2_STAT_SQ_TV_NULL_FETCH_PER_TYPE = 0x000050F3, 1238 /// Number of threads waiting in the fetch-seq`s input fifo each cycle, of the selected thread type. 1239 GX2_STAT_SQ_TV_THREADS_IN_FIFO_PER_TYPE = 0x000050F4, 1240 /// Internal export per-quadpipe queue level average. 1241 GX2_STAT_SQ_EXPORT_SPQ_LEVEL = 0x000050F5, 1242 /// Internal export per-quadpipe stall cycles. 1243 GX2_STAT_SQ_EXPORT_SPQ_STALL = 0x000050F6, 1244 GX2_STAT_SQ_FIRST = GX2_STAT_SQ_NONE, 1245 GX2_STAT_SQ_LAST = GX2_STAT_SQ_EXPORT_SPQ_STALL, 1246 GX2_STAT_SPI_VS_WINDOW_VALID = 0x00006000, 1247 GX2_STAT_SPI_VS_BUSY = 0x00006001, 1248 GX2_STAT_SPI_VS_INPUT_STARVED = 0x00006002, 1249 GX2_STAT_SPI_VS_VSR_STALL = 0x00006003, 1250 GX2_STAT_SPI_VS_VSR_FULL = 0x00006004, 1251 GX2_STAT_SPI_VS_GPR_STALL = 0x00006005, 1252 GX2_STAT_SPI_VS_INPUT_STALL = 0x00006006, 1253 GX2_STAT_SPI_VS_MEM_STALL = 0x00006007, 1254 GX2_STAT_SPI_VS_TB_FULL = 0x00006008, 1255 GX2_STAT_SPI_VS_EV_FIFO_FULL = 0x00006009, 1256 GX2_STAT_SPI_VS_THREAD_STALL = 0x0000600A, 1257 GX2_STAT_SPI_VS_EVENT_VECTOR = 0x0000600B, 1258 GX2_STAT_SPI_VS_VECTOR = 0x0000600C, 1259 GX2_STAT_SPI_GS_WINDOW_VALID = 0x0000600D, 1260 GX2_STAT_SPI_GS_BUSY = 0x0000600E, 1261 GX2_STAT_SPI_GS_INPUT_STARVED = 0x0000600F, 1262 GX2_STAT_SPI_GS_GSR_STALL = 0x00006010, 1263 GX2_STAT_SPI_GS_GSR_FULL = 0x00006011, 1264 GX2_STAT_SPI_GS_GPR_STALL = 0x00006012, 1265 GX2_STAT_SPI_GS_INPUT_STALL = 0x00006013, 1266 GX2_STAT_SPI_GS_MEM_STALL = 0x00006014, 1267 GX2_STAT_SPI_GS_TB_FULL = 0x00006015, 1268 GX2_STAT_SPI_GS_EV_FIFO_FULL = 0x00006016, 1269 GX2_STAT_SPI_GS_THREAD_STALL = 0x00006017, 1270 GX2_STAT_SPI_GS_EVENT_VECTOR = 0x00006018, 1271 GX2_STAT_SPI_GS_VECTOR = 0x00006019, 1272 GX2_STAT_SPI_ES_WINDOW_VALID = 0x0000601A, 1273 GX2_STAT_SPI_ES_BUSY = 0x0000601B, 1274 GX2_STAT_SPI_ES_INPUT_STARVED = 0x0000601C, 1275 GX2_STAT_SPI_ES_ESR_STALL = 0x0000601D, 1276 GX2_STAT_SPI_ES_ESR_FULL = 0x0000601E, 1277 GX2_STAT_SPI_ES_GPR_STALL = 0x0000601F, 1278 GX2_STAT_SPI_ES_INPUT_STALL = 0x00006020, 1279 GX2_STAT_SPI_ES_MEM_STALL = 0x00006021, 1280 GX2_STAT_SPI_ES_TB_FULL = 0x00006022, 1281 GX2_STAT_SPI_ES_EV_FIFO_FULL = 0x00006023, 1282 GX2_STAT_SPI_ES_THREAD_STALL = 0x00006024, 1283 GX2_STAT_SPI_ES_EVENT_VECTOR = 0x00006025, 1284 GX2_STAT_SPI_ES_VECTOR = 0x00006026, 1285 GX2_STAT_SPI_ITER_CTRL_WINDOW_VALID = 0x00006027, 1286 GX2_STAT_SPI_ITER_CTRL_ACTIVE = 0x00006028, 1287 GX2_STAT_SPI_ITER_CTRL_FULL = 0x00006029, 1288 GX2_STAT_SPI_ITER_CTRL_STALL_PV = 0x0000602A, 1289 GX2_STAT_SPI_ITER_CTRL_STALL_EV = 0x0000602B, 1290 GX2_STAT_SPI_ITER_STARVED = 0x0000602C, 1291 GX2_STAT_SPI_ITER_ACTIVE = 0x0000602D, 1292 GX2_STAT_SPI_ITER_FULL = 0x0000602E, 1293 GX2_STAT_SPI_ITER_STALL = 0x0000602F, 1294 GX2_STAT_SPI_PTR_BUFF_WINDOW_VALID = 0x00006030, 1295 GX2_STAT_SPI_PTR_BUFF_BUSY = 0x00006031, 1296 GX2_STAT_SPI_PTR_BUFF_ACTIVE = 0x00006032, 1297 GX2_STAT_SPI_PTR_BUFF_STALL = 0x00006033, 1298 GX2_STAT_SPI_PTR_BUFF_GPR_STALL = 0x00006034, 1299 GX2_STAT_SPI_PTR_BUFF_MEM_STALL = 0x00006035, 1300 GX2_STAT_SPI_PTR_BUFF_IJ_STALL = 0x00006036, 1301 GX2_STAT_SPI_PTR_BUFF_CTL_STALL = 0x00006037, 1302 GX2_STAT_SPI_PTR_BUFF_EVENT_VECTOR = 0x00006038, 1303 GX2_STAT_SPI_PTR_BUFF_VECTOR = 0x00006039, 1304 GX2_STAT_SPI_PTR_BUFF_2_PASS_VEC = 0x0000603A, 1305 GX2_STAT_SPI_PTR_BUFF_3_PASS_VEC = 0x0000603B, 1306 GX2_STAT_SPI_PTR_BUFF_4_PASS_VEC = 0x0000603C, 1307 GX2_STAT_SPI_PCTL0_INPUT_STALL = 0x0000603D, 1308 GX2_STAT_SPI_PCTL0_PI_PPB_STALL = 0x0000603E, 1309 GX2_STAT_SPI_PCTL0_THREAD_STALL = 0x0000603F, 1310 GX2_STAT_SPI_PCTL0_PI_BUSY = 0x00006040, 1311 GX2_STAT_SPI_PCTL0_SX_VALID = 0x00006041, 1312 GX2_STAT_SPI_PCTL1_INPUT_STALL = 0x00006042, 1313 GX2_STAT_SPI_PCTL1_PI_PPB_STALL = 0x00006043, 1314 GX2_STAT_SPI_PCTL1_THREAD_STALL = 0x00006044, 1315 GX2_STAT_SPI_PCTL1_PI_BUSY = 0x00006045, 1316 GX2_STAT_SPI_PCTL1_SX_VALID = 0x00006046, 1317 GX2_STAT_SPI_PS_TB_FULL = 0x00006047, 1318 GX2_STAT_SPI_PS_EV_FIFO_FULL = 0x00006048, 1319 GX2_STAT_SPI_THREAD_CONFLICT = 0x00006049, 1320 GX2_STAT_SPI_VS_STK_STALL = 0x0000604A, 1321 GX2_STAT_SPI_VS_TMP_STALL = 0x0000604B, 1322 GX2_STAT_SPI_GS_STK_STALL = 0x0000604C, 1323 GX2_STAT_SPI_GS_TMP_STALL = 0x0000604D, 1324 GX2_STAT_SPI_ES_STK_STALL = 0x0000604E, 1325 GX2_STAT_SPI_ES_TMP_STALL = 0x0000604F, 1326 GX2_STAT_SPI_PS_STK_STALL = 0x00006050, 1327 GX2_STAT_SPI_PS_TMP_STALL = 0x00006051, 1328 GX2_STAT_SPI_PS_FBUF_STALL = 0x00006052, 1329 GX2_STAT_SPI_PTR_BUFF_FPOS = 0x00006053, 1330 GX2_STAT_SPI_PTR_BUFF_DEALLOC = 0x00006054, 1331 GX2_STAT_SPI_PTR_BUFF_0_CONFLICT_VEC = 0x00006055, 1332 GX2_STAT_SPI_PTR_BUFF_1_CONFLICT_VEC = 0x00006056, 1333 GX2_STAT_SPI_PTR_BUFF_2_CONFLICT_VEC = 0x00006057, 1334 GX2_STAT_SPI_PTR_BUFF_3_CONFLICT_VEC = 0x00006058, 1335 GX2_STAT_SPI_PTR_BUFF_4_CONFLICT_VEC = 0x00006059, 1336 GX2_STAT_SPI_PTR_BUFF_5_CONFLICT_VEC = 0x0000605A, 1337 GX2_STAT_SPI_DYN_GPR_PS_SKIP_SIMD = 0x0000605B, 1338 GX2_STAT_SPI_DYN_GPR_VS_SKIP_SIMD = 0x0000605C, 1339 GX2_STAT_SPI_DYN_GPR_GS_SKIP_SIMD = 0x0000605D, 1340 GX2_STAT_SPI_DYN_GPR_ES_SKIP_SIMD = 0x0000605E, 1341 GX2_STAT_SPI_DYN_GPR_PS_WRAP_SOONER = 0x0000605F, 1342 GX2_STAT_SPI_DYN_GPR_VS_WRAP_SOONER = 0x00006060, 1343 GX2_STAT_SPI_DYN_GPR_GS_WRAP_SOONER = 0x00006061, 1344 GX2_STAT_SPI_DYN_GPR_ES_WRAP_SOONER = 0x00006062, 1345 GX2_STAT_SPI_CLKGATE_BUSY_STALL = 0x00006063, 1346 GX2_STAT_SPI_CLKGATE_ACTIVE_STALL = 0x00006064, 1347 GX2_STAT_SPI_CLKGATE_ALL_CLOCKS_ON = 0x00006065, 1348 GX2_STAT_SPI_CLKGATE_SPI_CLOCKS_ON = 0x00006066, 1349 GX2_STAT_SPI_FIRST = GX2_STAT_SPI_VS_WINDOW_VALID, 1350 GX2_STAT_SPI_LAST = GX2_STAT_SPI_CLKGATE_SPI_CLOCKS_ON, 1351 GX2_STAT_SX_GS_FLUSH_EVENT_IN = 0x00007000, 1352 GX2_STAT_SX_ES_FLUSH_EVENT_IN = 0x00007001, 1353 GX2_STAT_SX_TS_EVENT_IN = 0x00007002, 1354 GX2_STAT_SX_CONTEXT_EVENT_IN = 0x00007003, 1355 GX2_STAT_SX_GS_FLUSH_EVENT_OUT = 0x00007004, 1356 GX2_STAT_SX_ES_FLUSH_EVENT_OUT = 0x00007005, 1357 GX2_STAT_SX_TS_EVENT_OUT = 0x00007006, 1358 GX2_STAT_SX_CONTEXT_EVENT_OUT = 0x00007007, 1359 GX2_STAT_SX_DB0_IDLE_CYCLES = 0x00007008, 1360 GX2_STAT_SX_DB0_STALL_CYCLES = 0x00007009, 1361 GX2_STAT_SX_DB0_HALF_QUADS = 0x0000700a, 1362 GX2_STAT_SX_DB0_PIXELS = 0x0000700b, 1363 GX2_STAT_SX_DB0_PRED_PIXELS = 0x0000700c, 1364 GX2_STAT_SX_DB1_IDLE_CYCLES = 0x0000700d, 1365 GX2_STAT_SX_DB1_STALL_CYCLES = 0x0000700e, 1366 GX2_STAT_SX_DB1_HALF_QUADS = 0x0000700f, 1367 GX2_STAT_SX_DB1_PIXELS = 0x00007010, 1368 GX2_STAT_SX_DB1_PRED_PIXELS = 0x00007011, 1369 GX2_STAT_SX_DB2_IDLE_CYCLES = 0x00007012, 1370 GX2_STAT_SX_DB2_STALL_CYCLES = 0x00007013, 1371 GX2_STAT_SX_DB2_HALF_QUADS = 0x00007014, 1372 GX2_STAT_SX_DB2_PIXELS = 0x00007015, 1373 GX2_STAT_SX_DB2_PRED_PIXELS = 0x00007016, 1374 GX2_STAT_SX_DB3_IDLE_CYCLES = 0x00007017, 1375 GX2_STAT_SX_DB3_STALL_CYCLES = 0x00007018, 1376 GX2_STAT_SX_DB3_HALF_QUADS = 0x00007019, 1377 GX2_STAT_SX_DB3_PIXELS = 0x0000701a, 1378 GX2_STAT_SX_DB3_PRED_PIXELS = 0x0000701b, 1379 GX2_STAT_SX_DB4_IDLE_CYCLES = 0x0000701c, 1380 GX2_STAT_SX_DB4_STALL_CYCLES = 0x0000701d, 1381 GX2_STAT_SX_DB4_HALF_QUADS = 0x0000701e, 1382 GX2_STAT_SX_DB4_PIXELS = 0x0000701f, 1383 GX2_STAT_SX_DB4_PRED_PIXELS = 0x00007020, 1384 GX2_STAT_SX_DB5_IDLE_CYCLES = 0x00007021, 1385 GX2_STAT_SX_DB5_STALL_CYCLES = 0x00007022, 1386 GX2_STAT_SX_DB5_HALF_QUADS = 0x00007023, 1387 GX2_STAT_SX_DB5_PIXELS = 0x00007024, 1388 GX2_STAT_SX_DB5_PRED_PIXELS = 0x00007025, 1389 GX2_STAT_SX_DB6_IDLE_CYCLES = 0x00007026, 1390 GX2_STAT_SX_DB6_STALL_CYCLES = 0x00007027, 1391 GX2_STAT_SX_DB6_HALF_QUADS = 0x00007028, 1392 GX2_STAT_SX_DB6_PIXELS = 0x00007029, 1393 GX2_STAT_SX_DB6_PRED_PIXELS = 0x0000702a, 1394 GX2_STAT_SX_DB7_IDLE_CYCLES = 0x0000702b, 1395 GX2_STAT_SX_DB7_STALL_CYCLES = 0x0000702c, 1396 GX2_STAT_SX_DB7_HALF_QUADS = 0x0000702d, 1397 GX2_STAT_SX_DB7_PIXELS = 0x0000702e, 1398 GX2_STAT_SX_DB7_PRED_PIXELS = 0x0000702f, 1399 GX2_STAT_SX_PA_IDLE_CYCLES = 0x00007030, 1400 GX2_STAT_SX_PA_REQ = 0x00007031, 1401 GX2_STAT_SX_PA_POS = 0x00007032, 1402 GX2_STAT_SX_SPI_REQ_0 = 0x00007033, 1403 GX2_STAT_SX_SPI_REQ_1 = 0x00007034, 1404 GX2_STAT_SX_CLOCK_PS = 0x00007035, 1405 GX2_STAT_SX_CLOCK_VS = 0x00007036, 1406 GX2_STAT_SX_CLOCK_GS = 0x00007037, 1407 GX2_STAT_SX_CLOCK_ES = 0x00007038, 1408 GX2_STAT_SX_CLOCK = 0x00007039, 1409 GX2_STAT_SX_DB0_ACK_REQUEST = 0x0000703a, 1410 GX2_STAT_SX_DB1_ACK_REQUEST = 0x0000703b, 1411 GX2_STAT_SX_DB2_ACK_REQUEST = 0x0000703c, 1412 GX2_STAT_SX_DB3_ACK_REQUEST = 0x0000703d, 1413 GX2_STAT_SX_DB4_ACK_REQUEST = 0x0000703e, 1414 GX2_STAT_SX_DB5_ACK_REQUEST = 0x0000703f, 1415 GX2_STAT_SX_DB6_ACK_REQUEST = 0x00007040, 1416 GX2_STAT_SX_DB7_ACK_REQUEST = 0x00007041, 1417 GX2_STAT_SX_SC_CLOCK = 0x00007042, 1418 GX2_STAT_SX_PS_ADJUSTED_CLOCK = 0x00007043, 1419 GX2_STAT_SX_DB0_ALPHA_KILLED_PIXELS = 0x00007044, 1420 GX2_STAT_SX_DB1_ALPHA_KILLED_PIXELS = 0x00007045, 1421 GX2_STAT_SX_DB2_ALPHA_KILLED_PIXELS = 0x00007046, 1422 GX2_STAT_SX_DB3_ALPHA_KILLED_PIXELS = 0x00007047, 1423 GX2_STAT_SX_GATE_EN1 = 0x00007048, 1424 GX2_STAT_SX_GATE_EN2 = 0x00007049, 1425 GX2_STAT_SX_GATE_EN3 = 0x0000704a, 1426 GX2_STAT_SX_GATE_EN4 = 0x0000704b, 1427 GX2_STAT_SX_GATE_EN5 = 0x0000704c, 1428 GX2_STAT_SX_PIX_CLK_VALID = 0x0000704d, 1429 GX2_STAT_SX_SC_CLK_VALID = 0x0000704e, 1430 GX2_STAT_SX_PA_CLK_VALID = 0x0000704f, 1431 GX2_STAT_SX_REG_CLK_VALID = 0x00007050, 1432 GX2_STAT_SX_SMX_CLK_VALID = 0x00007051, 1433 GX2_STAT_SX_ARB_QP0_COLLISION = 0x00007052, 1434 GX2_STAT_SX_ARB_QP1_COLLISION = 0x00007053, 1435 GX2_STAT_SX_ARB_QP2_COLLISION = 0x00007054, 1436 GX2_STAT_SX_ARB_QP3_COLLISION = 0x00007055, 1437 GX2_STAT_SX_FIRST = GX2_STAT_SX_GS_FLUSH_EVENT_IN, 1438 GX2_STAT_SX_LAST = GX2_STAT_SX_ARB_QP3_COLLISION, 1439 GX2_STAT_SMX_CACHE_IDLE_CYCLES = 0x00008000, 1440 GX2_STAT_SMX_CACHE_STALL_CYCLES = 0x00008001, 1441 GX2_STAT_SMX_WRITE_REQS = 0x00008002, 1442 GX2_STAT_SMX_WRITE_REQS_PS = 0x00008003, 1443 GX2_STAT_SMX_WRITE_REQS_VS = 0x00008004, 1444 GX2_STAT_SMX_WRITE_REQS_GS = 0x00008005, 1445 GX2_STAT_SMX_WRITE_REQS_ES = 0x00008006, 1446 GX2_STAT_SMX_WRITE_REQS_STREAM0 = 0x00008007, 1447 GX2_STAT_SMX_WRITE_REQS_STREAM1 = 0x00008008, 1448 GX2_STAT_SMX_WRITE_REQS_STREAM2 = 0x00008009, 1449 GX2_STAT_SMX_WRITE_REQS_STREAM3 = 0x0000800a, 1450 GX2_STAT_SMX_WRITE_REQS_SCRATCH = 0x0000800b, 1451 GX2_STAT_SMX_WRITE_REQS_REDUCTION = 0x0000800c, 1452 GX2_STAT_SMX_WRITE_REQS_RING = 0x0000800d, 1453 GX2_STAT_SMX_WRITE_REQS_FBUFFER = 0x0000800e, 1454 GX2_STAT_SMX_WRITE_REQS_SCATTER = 0x0000800f, 1455 GX2_STAT_SMX_VF_STALL = 0x00008010, 1456 GX2_STAT_SMX0_NUMBER_OF_PARTIAL_LINES = 0x00008011, 1457 GX2_STAT_SMX0_NUMBER_OF_ES_FLUSH = 0x00008012, 1458 GX2_STAT_SMX0_NUMBER_OF_GS_FLUSH = 0x00008013, 1459 GX2_STAT_SMX0_NUMBER_OF_SYNC_FLUSH = 0x00008014, 1460 GX2_STAT_SMX0_NUMBER_OF_ACK_FLUSH = 0x00008015, 1461 GX2_STAT_SMX0_NUMBER_OF_FLUSH = 0x00008016, 1462 GX2_STAT_SMX0_DW_WRITTEN = 0x00008017, 1463 GX2_STAT_SMX0_DW_MISS = 0x00008018, 1464 GX2_STAT_SMX0_DB_STALL = 0x00008019, 1465 GX2_STAT_SMX1_NUMBER_OF_PARTIAL_LINES = 0x0000801a, 1466 GX2_STAT_SMX1_NUMBER_OF_ES_FLUSH = 0x0000801b, 1467 GX2_STAT_SMX1_NUMBER_OF_GS_FLUSH = 0x0000801c, 1468 GX2_STAT_SMX1_NUMBER_OF_SYNC_FLUSH = 0x0000801d, 1469 GX2_STAT_SMX1_NUMBER_OF_ACK_FLUSH = 0x0000801e, 1470 GX2_STAT_SMX1_NUMBER_OF_FLUSH = 0x0000801f, 1471 GX2_STAT_SMX1_DW_WRITTEN = 0x00008020, 1472 GX2_STAT_SMX1_DW_MISS = 0x00008021, 1473 GX2_STAT_SMX1_DB_STALL = 0x00008022, 1474 GX2_STAT_SMX2_NUMBER_OF_PARTIAL_LINES = 0x00008023, 1475 GX2_STAT_SMX2_NUMBER_OF_ES_FLUSH = 0x00008024, 1476 GX2_STAT_SMX2_NUMBER_OF_GS_FLUSH = 0x00008025, 1477 GX2_STAT_SMX2_NUMBER_OF_SYNC_FLUSH = 0x00008026, 1478 GX2_STAT_SMX2_NUMBER_OF_ACK_FLUSH = 0x00008027, 1479 GX2_STAT_SMX2_NUMBER_OF_FLUSH = 0x00008028, 1480 GX2_STAT_SMX2_DW_WRITTEN = 0x00008029, 1481 GX2_STAT_SMX2_DW_MISS = 0x0000802a, 1482 GX2_STAT_SMX2_DB_STALL = 0x0000802b, 1483 GX2_STAT_SMX3_NUMBER_OF_PARTIAL_LINES = 0x0000802c, 1484 GX2_STAT_SMX3_NUMBER_OF_ES_FLUSH = 0x0000802d, 1485 GX2_STAT_SMX3_NUMBER_OF_GS_FLUSH = 0x0000802e, 1486 GX2_STAT_SMX3_NUMBER_OF_SYNC_FLUSH = 0x0000802f, 1487 GX2_STAT_SMX3_NUMBER_OF_ACK_FLUSH = 0x00008030, 1488 GX2_STAT_SMX3_NUMBER_OF_FLUSH = 0x00008031, 1489 GX2_STAT_SMX3_DW_WRITTEN = 0x00008032, 1490 GX2_STAT_SMX3_DW_MISS = 0x00008033, 1491 GX2_STAT_SMX3_DB_STALL = 0x00008034, 1492 GX2_STAT_SMX0_SET0_CNT = 0x00008035, 1493 GX2_STAT_SMX0_SET1_CNT = 0x00008036, 1494 GX2_STAT_SMX0_SET2_CNT = 0x00008037, 1495 GX2_STAT_SMX0_SET3_CNT = 0x00008038, 1496 GX2_STAT_SMX0_SET4_CNT = 0x00008039, 1497 GX2_STAT_SMX0_SET5_CNT = 0x0000803a, 1498 GX2_STAT_SMX0_SET6_CNT = 0x0000803b, 1499 GX2_STAT_SMX0_SET7_CNT = 0x0000803c, 1500 GX2_STAT_SMX1_SET0_CNT = 0x0000803d, 1501 GX2_STAT_SMX1_SET1_CNT = 0x0000803e, 1502 GX2_STAT_SMX1_SET2_CNT = 0x0000803f, 1503 GX2_STAT_SMX1_SET3_CNT = 0x00008040, 1504 GX2_STAT_SMX1_SET4_CNT = 0x00008041, 1505 GX2_STAT_SMX1_SET5_CNT = 0x00008042, 1506 GX2_STAT_SMX1_SET6_CNT = 0x00008043, 1507 GX2_STAT_SMX1_SET7_CNT = 0x00008044, 1508 GX2_STAT_SMX2_SET0_CNT = 0x00008045, 1509 GX2_STAT_SMX2_SET1_CNT = 0x00008046, 1510 GX2_STAT_SMX2_SET2_CNT = 0x00008047, 1511 GX2_STAT_SMX2_SET3_CNT = 0x00008048, 1512 GX2_STAT_SMX2_SET4_CNT = 0x00008049, 1513 GX2_STAT_SMX2_SET5_CNT = 0x0000804a, 1514 GX2_STAT_SMX2_SET6_CNT = 0x0000804b, 1515 GX2_STAT_SMX2_SET7_CNT = 0x0000804c, 1516 GX2_STAT_SMX3_SET0_CNT = 0x0000804d, 1517 GX2_STAT_SMX3_SET1_CNT = 0x0000804e, 1518 GX2_STAT_SMX3_SET2_CNT = 0x0000804f, 1519 GX2_STAT_SMX3_SET3_CNT = 0x00008050, 1520 GX2_STAT_SMX3_SET4_CNT = 0x00008051, 1521 GX2_STAT_SMX3_SET5_CNT = 0x00008052, 1522 GX2_STAT_SMX3_SET6_CNT = 0x00008053, 1523 GX2_STAT_SMX3_SET7_CNT = 0x00008054, 1524 GX2_STAT_SMX0_PROBE_COLLISION = 0x00008055, 1525 GX2_STAT_SMX1_PROBE_COLLISION = 0x00008056, 1526 GX2_STAT_SMX2_PROBE_COLLISION = 0x00008057, 1527 GX2_STAT_SMX3_PROBE_COLLISION = 0x00008058, 1528 GX2_STAT_SMX_FIRST = GX2_STAT_SMX_CACHE_IDLE_CYCLES, 1529 GX2_STAT_SMX_LAST = GX2_STAT_SMX3_PROBE_COLLISION, 1530 GX2_STAT_TD_TD_BUSY = 0x00009000, 1531 GX2_STAT_TD_INPUT_BUSY = 0x00009008, 1532 GX2_STAT_TD_OUTPUT_BUSY = 0x00009009, 1533 GX2_STAT_TD_SAMPLE_LATENCY_FIFO_BUSY = 0x0000900a, 1534 GX2_STAT_TD_CONSTANT_LATENCY_FIFO_BUSY = 0x0000900b, 1535 GX2_STAT_TD_FASTPATH_BUSY = 0x0000900c, 1536 GX2_STAT_TD_SH_FIFO_BUSY = 0x0000900d, 1537 GX2_STAT_TD_PHASE_SYNC_BUSY = 0x0000900e, 1538 GX2_STAT_TD_DATAOUT_FIFO_BUSY = 0x0000900f, 1539 GX2_STAT_TD_LATENCY_FIFO_BUSY_PIPE_IDLE = 0x00009010, 1540 GX2_STAT_TD_SYNC_PHASE_COUNT = 0x00009011, 1541 GX2_STAT_TD_VC_DATA_RETURN = 0x00009012, 1542 GX2_STAT_TD_STALL_DUE_TO_VC = 0x00009013, 1543 GX2_STAT_TD_STALL_DUE_TO_RSP = 0x00009014, 1544 GX2_STAT_TD_STALL_DUE_TO_VC_OR_RSP = 0x00009015, 1545 GX2_STAT_TD_TD_REG_SCLK_VLD = 0x00009016, 1546 GX2_STAT_TD_TD_LOCAL_CG_DYN_SCLK_GRP0_EN = 0x00009017, 1547 GX2_STAT_TD_TD_LOCAL_CG_DYN_SCLK_GRP1_EN = 0x00009018, 1548 GX2_STAT_TD_FIRST = GX2_STAT_TD_TD_BUSY, 1549 GX2_STAT_TD_LAST = GX2_STAT_TD_TD_LOCAL_CG_DYN_SCLK_GRP1_EN, 1550 GX2_STAT_TA_TA_BUSY = 0x0000a000, 1551 GX2_STAT_TA_GRADIENT_BUSY = 0x0000a001, 1552 GX2_STAT_TA_GRADIENT_FIFO_BUSY = 0x0000a002, 1553 GX2_STAT_TA_LOD_BUSY = 0x0000a003, 1554 GX2_STAT_TA_LOD_FIFO_BUSY = 0x0000a004, 1555 GX2_STAT_TA_ADDRESSER_BUSY = 0x0000a005, 1556 GX2_STAT_TA_ADDRESSER_FIFO_BUSY = 0x0000a006, 1557 GX2_STAT_TA_ALIGNER_BUSY = 0x0000a007, 1558 GX2_STAT_TA_PIX_0_QUAD = 0x0000a008, 1559 GX2_STAT_TA_PIX_1_QUAD = 0x0000a009, 1560 GX2_STAT_TA_PIX_2_QUAD = 0x0000a00a, 1561 GX2_STAT_TA_PIX_3_QUAD = 0x0000a00b, 1562 GX2_STAT_TA_PIX_4_QUAD = 0x0000a00c, 1563 GX2_STAT_TA_INPUT_CYCLES = 0x0000a010, 1564 GX2_STAT_TA_GRADIENT_BALANCING_CYCLES = 0x0000a011, 1565 GX2_STAT_TA_GRADIENT_CYCLES = 0x0000a012, 1566 GX2_STAT_TA_WALKER_BALANCING_CYCLES = 0x0000a013, 1567 GX2_STAT_TA_WALKER_CYCLES = 0x0000a014, 1568 GX2_STAT_TA_ALIGNER_BALANCING_CYCLES = 0x0000a015, 1569 GX2_STAT_TA_ALIGNER_CYCLES = 0x0000a016, 1570 GX2_STAT_TA_MIP_1_CYCLE_PIXELS = 0x0000a018, 1571 GX2_STAT_TA_MIP_2_CYCLE_PIXELS = 0x0000a019, 1572 GX2_STAT_TA_VOL_1_CYCLE_PIXELS = 0x0000a01a, 1573 GX2_STAT_TA_VOL_2_CYCLE_PIXELS = 0x0000a01b, 1574 GX2_STAT_TA_BILIN_POINT_1_CYCLE_PIXELS = 0x0000a01c, 1575 GX2_STAT_TA_BICUBIC_4_CYCLE_PIXELS = 0x0000a01d, 1576 GX2_STAT_TA_MIPMAP_LOD_0_SAMPLES = 0x0000a020, 1577 GX2_STAT_TA_MIPMAP_LOD_1_SAMPLES = 0x0000a021, 1578 GX2_STAT_TA_MIPMAP_LOD_2_SAMPLES = 0x0000a022, 1579 GX2_STAT_TA_MIPMAP_LOD_3_SAMPLES = 0x0000a023, 1580 GX2_STAT_TA_MIPMAP_LOD_4_SAMPLES = 0x0000a024, 1581 GX2_STAT_TA_MIPMAP_LOD_5_SAMPLES = 0x0000a025, 1582 GX2_STAT_TA_MIPMAP_LOD_6_SAMPLES = 0x0000a026, 1583 GX2_STAT_TA_MIPMAP_LOD_7_SAMPLES = 0x0000a027, 1584 GX2_STAT_TA_MIPMAP_LOD_8_SAMPLES = 0x0000a028, 1585 GX2_STAT_TA_MIPMAP_LOD_9_SAMPLES = 0x0000a029, 1586 GX2_STAT_TA_MIPMAP_LOD_10_SAMPLES = 0x0000a02a, 1587 GX2_STAT_TA_MIPMAP_LOD_11_SAMPLES = 0x0000a02b, 1588 GX2_STAT_TA_MIPMAP_LOD_12_SAMPLES = 0x0000a02c, 1589 GX2_STAT_TA_MIPMAP_LOD_13_SAMPLES = 0x0000a02d, 1590 GX2_STAT_TA_MIPMAP_LOD_14_SAMPLES = 0x0000a02e, 1591 GX2_STAT_TA_ANISO_1_1_QUADS = 0x0000a030, 1592 GX2_STAT_TA_ANISO_2_1_QUADS = 0x0000a031, 1593 GX2_STAT_TA_ANISO_3_1_QUADS = 0x0000a032, 1594 GX2_STAT_TA_ANISO_4_1_QUADS = 0x0000a033, 1595 GX2_STAT_TA_ANISO_5_1_QUADS = 0x0000a034, 1596 GX2_STAT_TA_ANISO_6_1_QUADS = 0x0000a035, 1597 GX2_STAT_TA_ANISO_7_1_QUADS = 0x0000a036, 1598 GX2_STAT_TA_ANISO_8_1_QUADS = 0x0000a037, 1599 GX2_STAT_TA_ANISO_9_1_QUADS = 0x0000a038, 1600 GX2_STAT_TA_ANISO_10_1_QUADS = 0x0000a039, 1601 GX2_STAT_TA_ANISO_11_1_QUADS = 0x0000a03a, 1602 GX2_STAT_TA_ANISO_12_1_QUADS = 0x0000a03b, 1603 GX2_STAT_TA_ANISO_13_1_QUADS = 0x0000a03c, 1604 GX2_STAT_TA_ANISO_14_1_QUADS = 0x0000a03d, 1605 GX2_STAT_TA_ANISO_15_1_QUADS = 0x0000a03e, 1606 GX2_STAT_TA_ANISO_16_1_QUADS = 0x0000a03f, 1607 GX2_STAT_TA_TA_REG_SCLK_VLD = 0x0000a040, 1608 GX2_STAT_TA_TA_LOCAL_CG_DYN_SCLK_GRP0_EN = 0x0000a041, 1609 GX2_STAT_TA_TA_LOCAL_CG_DYN_SCLK_GRP1_EN = 0x0000a042, 1610 GX2_STAT_TA_TA_LOCAL_CG_DYN_SCLK_GRP1_MEMS_EN = 0x0000a043, 1611 GX2_STAT_TA_FIRST = GX2_STAT_TA_TA_BUSY, 1612 GX2_STAT_TA_LAST = GX2_STAT_TA_TA_LOCAL_CG_DYN_SCLK_GRP1_MEMS_EN, 1613 GX2_STAT_TCP_TA_TCP_STARVE_CYCLES = 0x0000b000, 1614 GX2_STAT_TCP_TCP_TA_STALL_CYCLES = 0x0000b001, 1615 GX2_STAT_TCP_TD_TCP_STALL_CYCLES = 0x0000b002, 1616 GX2_STAT_TCP_TCC_TCP_STALL_CYCLES = 0x0000b003, 1617 GX2_STAT_TCP_TCC0_TCP_STALL_CYCLES = 0x0000b004, 1618 GX2_STAT_TCP_TCC1_TCP_STALL_CYCLES = 0x0000b005, 1619 GX2_STAT_TCP_TCC2_TCP_STALL_CYCLES = 0x0000b006, 1620 GX2_STAT_TCP_TCC3_TCP_STALL_CYCLES = 0x0000b007, 1621 GX2_STAT_TCP_TCC4_TCP_STALL_CYCLES = 0x0000b008, 1622 GX2_STAT_TCP_TCC5_TCP_STALL_CYCLES = 0x0000b009, 1623 GX2_STAT_TCP_TCC6_TCP_STALL_CYCLES = 0x0000b00a, 1624 GX2_STAT_TCP_TCC7_TCP_STALL_CYCLES = 0x0000b00b, 1625 GX2_STAT_TCP_TCP_LOD_STALL_CYCLES = 0x0000b00c, 1626 GX2_STAT_TCP_TCP_TAGCONFLICT_STALL_CYCLES = 0x0000b00d, 1627 GX2_STAT_TCP_TCP_ALLOC_STALL_CYCLES = 0x0000b00e, 1628 GX2_STAT_TCP_TCP_LFIFO_STALL_CYCLES = 0x0000b00f, 1629 GX2_STAT_TCP_TCP_RFIFO_STALL_CYCLES = 0x0000b010, 1630 GX2_STAT_TCP_TCP_FFIFO_STALL_CYCLES = 0x0000b011, 1631 GX2_STAT_TCP_TCP_CFIFO_STALL_CYCLES = 0x0000b012, 1632 GX2_STAT_TCP_TCP_READCONFLICT_STALL_CYCLES = 0x0000b013, 1633 GX2_STAT_TCP_TCP_PENDING_STALL_CYCLES = 0x0000b014, 1634 GX2_STAT_TCP_TCP_READFIFO_STALL_CYCLES = 0x0000b015, 1635 GX2_STAT_TCP_TCP_LATENCY = 0x0000b016, 1636 GX2_STAT_TCP_TCC_REQ_LATENCY = 0x0000b017, 1637 GX2_STAT_TCP_TCC0_REQ_LATENCY = 0x0000b018, 1638 GX2_STAT_TCP_TCC1_REQ_LATENCY = 0x0000b019, 1639 GX2_STAT_TCP_TCC2_REQ_LATENCY = 0x0000b01a, 1640 GX2_STAT_TCP_TCC3_REQ_LATENCY = 0x0000b01b, 1641 GX2_STAT_TCP_TCC4_REQ_LATENCY = 0x0000b01c, 1642 GX2_STAT_TCP_TCC5_REQ_LATENCY = 0x0000b01d, 1643 GX2_STAT_TCP_TCC6_REQ_LATENCY = 0x0000b01e, 1644 GX2_STAT_TCP_TCC7_REQ_LATENCY = 0x0000b01f, 1645 GX2_STAT_TCP_TCC_FREE_LATENCY = 0x0000b020, 1646 GX2_STAT_TCP_TCC0_FREE_LATENCY = 0x0000b021, 1647 GX2_STAT_TCP_TCC1_FREE_LATENCY = 0x0000b022, 1648 GX2_STAT_TCP_TCC2_FREE_LATENCY = 0x0000b023, 1649 GX2_STAT_TCP_TCC3_FREE_LATENCY = 0x0000b024, 1650 GX2_STAT_TCP_TCC4_FREE_LATENCY = 0x0000b025, 1651 GX2_STAT_TCP_TCC5_FREE_LATENCY = 0x0000b026, 1652 GX2_STAT_TCP_TCC6_FREE_LATENCY = 0x0000b027, 1653 GX2_STAT_TCP_TCC7_FREE_LATENCY = 0x0000b028, 1654 GX2_STAT_TCP_TCP_TCC_REQ = 0x0000b029, 1655 GX2_STAT_TCP_TCP_TCC0_REQ = 0x0000b02a, 1656 GX2_STAT_TCP_TCP_TCC1_REQ = 0x0000b02b, 1657 GX2_STAT_TCP_TCP_TCC2_REQ = 0x0000b02c, 1658 GX2_STAT_TCP_TCP_TCC3_REQ = 0x0000b02d, 1659 GX2_STAT_TCP_TCP_TCC4_REQ = 0x0000b02e, 1660 GX2_STAT_TCP_TCP_TCC5_REQ = 0x0000b02f, 1661 GX2_STAT_TCP_TCP_TCC6_REQ = 0x0000b030, 1662 GX2_STAT_TCP_TCP_TCC7_REQ = 0x0000b031, 1663 GX2_STAT_TCP_TCC_TCP_RDRET = 0x0000b032, 1664 GX2_STAT_TCP_TCC0_TCP_RDRET = 0x0000b033, 1665 GX2_STAT_TCP_TCC1_TCP_RDRET = 0x0000b034, 1666 GX2_STAT_TCP_TCC2_TCP_RDRET = 0x0000b035, 1667 GX2_STAT_TCP_TCC3_TCP_RDRET = 0x0000b036, 1668 GX2_STAT_TCP_TCC4_TCP_RDRET = 0x0000b037, 1669 GX2_STAT_TCP_TCC5_TCP_RDRET = 0x0000b038, 1670 GX2_STAT_TCP_TCC6_TCP_RDRET = 0x0000b039, 1671 GX2_STAT_TCP_TCC7_TCP_RDRET = 0x0000b03a, 1672 GX2_STAT_TCP_TOTAL_PIXELS = 0x0000b03b, 1673 GX2_STAT_TCP_UNCACHED_PIXELS = 0x0000b03c, 1674 GX2_STAT_TCP_FMT_1_PIXELS = 0x0000b03d, 1675 GX2_STAT_TCP_FMT_8_PIXELS = 0x0000b03e, 1676 GX2_STAT_TCP_FMT_16_PIXELS = 0x0000b03f, 1677 GX2_STAT_TCP_FMT_32_PIXELS = 0x0000b040, 1678 GX2_STAT_TCP_FMT_32_AS_8_PIXELS = 0x0000b041, 1679 GX2_STAT_TCP_FMT_32_AS_16_PIXELS = 0x0000b042, 1680 GX2_STAT_TCP_FMT_64_2_CYCLE_PIXELS = 0x0000b043, 1681 GX2_STAT_TCP_FMT_64_1_CYCLE_PIXELS = 0x0000b044, 1682 GX2_STAT_TCP_FMT_96_PIXELS = 0x0000b045, 1683 GX2_STAT_TCP_FMT_128_4_CYCLE_PIXELS = 0x0000b046, 1684 GX2_STAT_TCP_FMT_128_1_CYCLE_PIXELS = 0x0000b047, 1685 GX2_STAT_TCP_FMT_BC1_PIXELS = 0x0000b048, 1686 GX2_STAT_TCP_FMT_BC2_PIXELS = 0x0000b049, 1687 GX2_STAT_TCP_FMT_BC3_PIXELS = 0x0000b04a, 1688 GX2_STAT_TCP_FMT_BC4_PIXELS = 0x0000b04b, 1689 GX2_STAT_TCP_FMT_BC5_PIXELS = 0x0000b04c, 1690 GX2_STAT_TCP_FMT_I8_PIXELS = 0x0000b04d, 1691 GX2_STAT_TCP_FMT_I16_PIXELS = 0x0000b04e, 1692 GX2_STAT_TCP_FMT_I32_PIXELS = 0x0000b04f, 1693 GX2_STAT_TCP_FMT_I32_AS_8_PIXELS = 0x0000b050, 1694 GX2_STAT_TCP_FMT_I32_AS_16_PIXELS = 0x0000b051, 1695 GX2_STAT_TCP_FMT_D16_PIXELS = 0x0000b052, 1696 GX2_STAT_TCP_FMT_D32_PIXELS = 0x0000b053, 1697 GX2_STAT_TCP_FMT_V8_PIXELS = 0x0000b054, 1698 GX2_STAT_TCP_FMT_V16_PIXELS = 0x0000b055, 1699 GX2_STAT_TCP_FMT_V32_PIXELS = 0x0000b056, 1700 GX2_STAT_TCP_FMT_V64_2_CYCLE_PIXELS = 0x0000b057, 1701 GX2_STAT_TCP_FMT_V64_1_CYCLE_PIXELS = 0x0000b058, 1702 GX2_STAT_TCP_FMT_V128_4_CYCLE_PIXELS = 0x0000b059, 1703 GX2_STAT_TCP_FMT_V128_2_CYCLE_PIXELS = 0x0000b05a, 1704 GX2_STAT_TCP_FMT_V128_1_CYCLE_PIXELS = 0x0000b05b, 1705 GX2_STAT_TCP_ARR_LINEAR_GENERAL_PIXELS = 0x0000b05c, 1706 GX2_STAT_TCP_ARR_LINEAR_ALIGNED_PIXELS = 0x0000b05d, 1707 GX2_STAT_TCP_ARR_1D_THIN1_PIXELS = 0x0000b05e, 1708 GX2_STAT_TCP_ARR_1D_THICK_PIXELS = 0x0000b05f, 1709 GX2_STAT_TCP_ARR_2D_THIN1_PIXELS = 0x0000b060, 1710 GX2_STAT_TCP_ARR_2D_THIN2_PIXELS = 0x0000b061, 1711 GX2_STAT_TCP_ARR_2D_THIN4_PIXELS = 0x0000b062, 1712 GX2_STAT_TCP_ARR_2D_THICK_PIXELS = 0x0000b063, 1713 GX2_STAT_TCP_ARR_2B_THIN1_PIXELS = 0x0000b064, 1714 GX2_STAT_TCP_ARR_2B_THIN2_PIXELS = 0x0000b065, 1715 GX2_STAT_TCP_ARR_2B_THIN4_PIXELS = 0x0000b066, 1716 GX2_STAT_TCP_ARR_2B_THICK_PIXELS = 0x0000b067, 1717 GX2_STAT_TCP_ARR_3D_THIN1_PIXELS = 0x0000b068, 1718 GX2_STAT_TCP_ARR_3D_THICK_PIXELS = 0x0000b069, 1719 GX2_STAT_TCP_ARR_3B_THIN1_PIXELS = 0x0000b06a, 1720 GX2_STAT_TCP_ARR_3B_THICK_PIXELS = 0x0000b06b, 1721 GX2_STAT_TCP_DIM_1D_PIXELS = 0x0000b06c, 1722 GX2_STAT_TCP_DIM_2D_PIXELS = 0x0000b06d, 1723 GX2_STAT_TCP_DIM_3D_PIXELS = 0x0000b06e, 1724 GX2_STAT_TCP_DIM_CUBE_PIXELS = 0x0000b06f, 1725 GX2_STAT_TCP_DIM_1D_ARRAY_PIXELS = 0x0000b070, 1726 GX2_STAT_TCP_DIM_2D_ARRAY_PIXELS = 0x0000b071, 1727 GX2_STAT_TCP_DIM_2D_MSAA_PIXELS = 0x0000b072, 1728 GX2_STAT_TCP_DIM_2D_ARRAY_MSAA_PIXELS = 0x0000b073, 1729 GX2_STAT_TCP_DIM_CUBE_ARRAY_PIXELS = 0x0000b074, 1730 GX2_STAT_TCP_VGT_TCP_INVALIDATE = 0x0000b075, 1731 GX2_STAT_TCP_TA_TCP_STATE_READ = 0x0000b076, 1732 GX2_STAT_TCP_TCP_TAGRAM0_REQ = 0x0000b077, 1733 GX2_STAT_TCP_TCP_TAGRAM1_REQ = 0x0000b078, 1734 GX2_STAT_TCP_TCP_TAGRAM2_REQ = 0x0000b079, 1735 GX2_STAT_TCP_TCP_TAGRAM3_REQ = 0x0000b07a, 1736 GX2_STAT_TCP_TCP_GATE_EN1 = 0x0000b07b, 1737 GX2_STAT_TCP_TCP_GATE_EN2 = 0x0000b07c, 1738 GX2_STAT_TCP_TCP_CORE_REG_SCLK_VLD = 0x0000b07d, 1739 GX2_STAT_TCP_FMT_V96_PIXELS = 0x0000b07e, 1740 GX2_STAT_TCP_FIRST = GX2_STAT_TCP_TA_TCP_STARVE_CYCLES, 1741 GX2_STAT_TCP_LAST = GX2_STAT_TCP_FMT_V96_PIXELS, 1742 GX2_STAT_TCC_NONE = 0x0000C000, 1743 GX2_STAT_TCC_CYCLES = 0x0000C001, 1744 GX2_STAT_TCC_BUSY = 0x0000C002, 1745 GX2_STAT_TCC_BUSY_TC_TF = 0x0000C003, 1746 GX2_STAT_TCC_BUSY_TC_VF = 0x0000C004, 1747 GX2_STAT_TCC_BUSY_VC_VF = 0x0000C005, 1748 GX2_STAT_TCC_REQS = 0x0000C006, 1749 GX2_STAT_TCC_REQS_HIT = 0x0000C007, 1750 GX2_STAT_TCC_REQS_MISS = 0x0000C008, 1751 GX2_STAT_TCC_REQS_UNCACHED = 0x0000C009, 1752 GX2_STAT_TCC_REQS_CLIENT_0 = 0x0000C00A, 1753 GX2_STAT_TCC_REQS_CLIENT_1 = 0x0000C00B, 1754 GX2_STAT_TCC_REQS_CLIENT_2 = 0x0000C00C, 1755 GX2_STAT_TCC_REQS_CLIENT_3 = 0x0000C00D, 1756 GX2_STAT_TCC_REQS_CLIENT_4 = 0x0000C00E, 1757 GX2_STAT_TCC_REQS_CLIENT_5 = 0x0000C00F, 1758 GX2_STAT_TCC_REQS_CLIENT_6 = 0x0000C010, 1759 GX2_STAT_TCC_REQS_CLIENT_7 = 0x0000C011, 1760 GX2_STAT_TCC_REQS_CLIENT_8 = 0x0000C012, 1761 GX2_STAT_TCC_REQS_CLIENT_9 = 0x0000C013, 1762 GX2_STAT_TCC_REQS_CLIENT_10 = 0x0000C014, 1763 GX2_STAT_TCC_REQS_CLIENT_11 = 0x0000C015, 1764 GX2_STAT_TCC_REQS_CLIENT_12 = 0x0000C016, 1765 GX2_STAT_TCC_REQS_CLIENT_13 = 0x0000C017, 1766 GX2_STAT_TCC_REQS_CLIENT_14 = 0x0000C018, 1767 GX2_STAT_TCC_REQS_CLIENT_15 = 0x0000C019, 1768 GX2_STAT_TCC_REQS_CLIENT_16 = 0x0000C01A, 1769 GX2_STAT_TCC_REQS_CLIENT_17 = 0x0000C01B, 1770 GX2_STAT_TCC_REQS_CLIENT_18 = 0x0000C01C, 1771 GX2_STAT_TCC_REQS_CLIENT_19 = 0x0000C01D, 1772 GX2_STAT_TCC_REQS_CLIENT_20 = 0x0000C01E, 1773 GX2_STAT_TCC_REQS_CLIENT_21 = 0x0000C01F, 1774 GX2_STAT_TCC_REQS_CLIENT_22 = 0x0000C020, 1775 GX2_STAT_TCC_REQS_CLIENT_23 = 0x0000C021, 1776 GX2_STAT_TCC_REQS_TC_TF = 0x0000C022, 1777 GX2_STAT_TCC_REQS_TC_TF_HIT = 0x0000C023, 1778 GX2_STAT_TCC_REQS_TC_TF_MISS = 0x0000C024, 1779 GX2_STAT_TCC_REQS_TC_VF = 0x0000C025, 1780 GX2_STAT_TCC_REQS_TC_VF_HIT = 0x0000C026, 1781 GX2_STAT_TCC_REQS_TC_VF_MISS = 0x0000C027, 1782 GX2_STAT_TCC_REQS_VC_VF = 0x0000C028, 1783 GX2_STAT_TCC_REQS_VC_VF_HIT = 0x0000C029, 1784 GX2_STAT_TCC_REQS_VC_VF_MISS = 0x0000C02A, 1785 GX2_STAT_TCC_REQ_LEVEL_TC_TF = 0x0000C02B, 1786 GX2_STAT_TCC_REQ_LEVEL_TC_VF = 0x0000C02C, 1787 GX2_STAT_TCC_REQ_LEVEL_VC_VF = 0x0000C02D, 1788 GX2_STAT_TCC_REQ_LEVEL_CLIENT_0 = 0x0000C02E, 1789 GX2_STAT_TCC_REQ_LEVEL_CLIENT_1 = 0x0000C02F, 1790 GX2_STAT_TCC_REQ_LEVEL_CLIENT_2 = 0x0000C030, 1791 GX2_STAT_TCC_REQ_LEVEL_CLIENT_3 = 0x0000C031, 1792 GX2_STAT_TCC_REQ_LEVEL_CLIENT_4 = 0x0000C032, 1793 GX2_STAT_TCC_REQ_LEVEL_CLIENT_5 = 0x0000C033, 1794 GX2_STAT_TCC_REQ_LEVEL_CLIENT_6 = 0x0000C034, 1795 GX2_STAT_TCC_REQ_LEVEL_CLIENT_7 = 0x0000C035, 1796 GX2_STAT_TCC_REQ_LEVEL_CLIENT_8 = 0x0000C036, 1797 GX2_STAT_TCC_REQ_LEVEL_CLIENT_9 = 0x0000C037, 1798 GX2_STAT_TCC_REQ_LEVEL_CLIENT_10 = 0x0000C038, 1799 GX2_STAT_TCC_REQ_LEVEL_CLIENT_11 = 0x0000C039, 1800 GX2_STAT_TCC_REQ_LEVEL_CLIENT_12 = 0x0000C03A, 1801 GX2_STAT_TCC_REQ_LEVEL_CLIENT_13 = 0x0000C03B, 1802 GX2_STAT_TCC_REQ_LEVEL_CLIENT_14 = 0x0000C03C, 1803 GX2_STAT_TCC_REQ_LEVEL_CLIENT_15 = 0x0000C03D, 1804 GX2_STAT_TCC_REQ_LEVEL_CLIENT_16 = 0x0000C03E, 1805 GX2_STAT_TCC_REQ_LEVEL_CLIENT_17 = 0x0000C03F, 1806 GX2_STAT_TCC_REQ_LEVEL_CLIENT_18 = 0x0000C040, 1807 GX2_STAT_TCC_REQ_LEVEL_CLIENT_19 = 0x0000C041, 1808 GX2_STAT_TCC_REQ_LEVEL_CLIENT_20 = 0x0000C042, 1809 GX2_STAT_TCC_REQ_LEVEL_CLIENT_21 = 0x0000C043, 1810 GX2_STAT_TCC_REQ_LEVEL_CLIENT_22 = 0x0000C044, 1811 GX2_STAT_TCC_REQ_LEVEL_CLIENT_23 = 0x0000C045, 1812 GX2_STAT_TCC_MC_REQS = 0x0000C046, 1813 GX2_STAT_TCC_MC_REQS_TC_TF = 0x0000C047, 1814 GX2_STAT_TCC_MC_REQS_TC_VF = 0x0000C048, 1815 GX2_STAT_TCC_MC_REQS_VC_VF = 0x0000C049, 1816 GX2_STAT_TCC_MC_FULL = 0x0000C04A, 1817 GX2_STAT_TCC_MC_REQ_LEVEL = 0x0000C04B, 1818 GX2_STAT_TCC_MC_REQ_LEVEL_TC_TF = 0x0000C04C, 1819 GX2_STAT_TCC_MC_REQ_LEVEL_TC_VF = 0x0000C04D, 1820 GX2_STAT_TCC_MC_REQ_LEVEL_VC_VF = 0x0000C04E, 1821 GX2_STAT_TCC_MC_CREDIT_LEVEL = 0x0000C04F, 1822 GX2_STAT_TCC_CG_CORE_ENABLED = 0x0000C050, 1823 GX2_STAT_TCC_CG_BLOCK_ENABLED = 0x0000C051, 1824 GX2_STAT_TCC_LF_FULL = 0x0000C052, 1825 GX2_STAT_TCC_LF_FULL_VC = 0x0000C053, 1826 GX2_STAT_TCC_LF_FULL_TC = 0x0000C054, 1827 GX2_STAT_TCC_LF_FULL_CLIENT_VC = 0x0000C055, 1828 GX2_STAT_TCC_LF_FULL_CLIENT_TC = 0x0000C056, 1829 GX2_STAT_TCC_LF_LEVEL = 0x0000C057, 1830 GX2_STAT_TCC_LF_LEVEL_VC_VF = 0x0000C058, 1831 GX2_STAT_TCC_LF_LEVEL_TC_VF = 0x0000C059, 1832 GX2_STAT_TCC_LF_LEVEL_TC_TF = 0x0000C05A, 1833 GX2_STAT_TCC_LF_BLOCK_LEVEL = 0x0000C05B, 1834 GX2_STAT_TCC_LF_BLOCK_LEVEL_VC = 0x0000C05C, 1835 GX2_STAT_TCC_LF_BLOCK_LEVEL_TC = 0x0000C05D, 1836 GX2_STAT_TCC_OF_LEVEL = 0x0000C05E, 1837 GX2_STAT_TCC_OF_LEVEL_VC_VF = 0x0000C05F, 1838 GX2_STAT_TCC_OF_LEVEL_TC_VF = 0x0000C060, 1839 GX2_STAT_TCC_OF_LEVEL_TC_TF = 0x0000C061, 1840 GX2_STAT_TCC_TCA_LEVEL = 0x0000C062, 1841 GX2_STAT_TCC_TCA_LEVEL_VC_VF = 0x0000C063, 1842 GX2_STAT_TCC_TCA_LEVEL_TC_VF = 0x0000C064, 1843 GX2_STAT_TCC_TCA_LEVEL_TC_TF = 0x0000C065, 1844 GX2_STAT_TCC_TCA_LEVEL_CLIENT_0 = 0x0000C066, 1845 GX2_STAT_TCC_TCA_LEVEL_CLIENT_1 = 0x0000C067, 1846 GX2_STAT_TCC_TCA_LEVEL_CLIENT_2 = 0x0000C068, 1847 GX2_STAT_TCC_TCA_LEVEL_CLIENT_3 = 0x0000C069, 1848 GX2_STAT_TCC_TCA_LEVEL_CLIENT_4 = 0x0000C06A, 1849 GX2_STAT_TCC_TCA_LEVEL_CLIENT_5 = 0x0000C06B, 1850 GX2_STAT_TCC_TCA_LEVEL_CLIENT_6 = 0x0000C06C, 1851 GX2_STAT_TCC_TCA_LEVEL_CLIENT_7 = 0x0000C06D, 1852 GX2_STAT_TCC_TCA_LEVEL_CLIENT_8 = 0x0000C06E, 1853 GX2_STAT_TCC_TCA_LEVEL_CLIENT_9 = 0x0000C06F, 1854 GX2_STAT_TCC_TCA_LEVEL_CLIENT_10 = 0x0000C070, 1855 GX2_STAT_TCC_TCA_LEVEL_CLIENT_11 = 0x0000C071, 1856 GX2_STAT_TCC_TCA_LEVEL_CLIENT_12 = 0x0000C072, 1857 GX2_STAT_TCC_TCA_LEVEL_CLIENT_13 = 0x0000C073, 1858 GX2_STAT_TCC_TCA_LEVEL_CLIENT_14 = 0x0000C074, 1859 GX2_STAT_TCC_TCA_LEVEL_CLIENT_15 = 0x0000C075, 1860 GX2_STAT_TCC_TCA_LEVEL_CLIENT_16 = 0x0000C076, 1861 GX2_STAT_TCC_TCA_LEVEL_CLIENT_17 = 0x0000C077, 1862 GX2_STAT_TCC_TCA_LEVEL_CLIENT_18 = 0x0000C078, 1863 GX2_STAT_TCC_TCA_LEVEL_CLIENT_19 = 0x0000C079, 1864 GX2_STAT_TCC_TCA_LEVEL_CLIENT_20 = 0x0000C07A, 1865 GX2_STAT_TCC_TCA_LEVEL_CLIENT_21 = 0x0000C07B, 1866 GX2_STAT_TCC_TCA_LEVEL_CLIENT_22 = 0x0000C07C, 1867 GX2_STAT_TCC_TCA_LEVEL_CLIENT_23 = 0x0000C07D, 1868 GX2_STAT_TCC_CLIENTS_FULL = 0x0000C07E, 1869 GX2_STAT_TCC_CLIENTS_FULL_VC = 0x0000C07F, 1870 GX2_STAT_TCC_CLIENTS_FULL_TC = 0x0000C080, 1871 GX2_STAT_TCC_ARB_BURST = 0x0000C081, 1872 GX2_STAT_TCC_ARB_BURST_VC = 0x0000C082, 1873 GX2_STAT_TCC_ARB_BURST_TC = 0x0000C083, 1874 GX2_STAT_TCC_CACHE_TAG_STALL_TC_TF = 0x0000C084, 1875 GX2_STAT_TCC_CACHE_TAG_RENAME_TC_TF = 0x0000C085, 1876 GX2_STAT_TCC_CACHE_TAG_STALL_TC_VF = 0x0000C086, 1877 GX2_STAT_TCC_CACHE_TAG_RENAME_TC_VF = 0x0000C087, 1878 GX2_STAT_TCC_CACHE_TAG_STALL_VC_VF = 0x0000C088, 1879 GX2_STAT_TCC_CACHE_TAG_RENAME_VC_VF = 0x0000C089, 1880 GX2_STAT_TCC_CACHE_STALL = 0x0000C08A, 1881 GX2_STAT_TCC_DEALLOC = 0x0000C08B, 1882 GX2_STAT_TCC_DEALLOC_ALL = 0x0000C08C, 1883 GX2_STAT_TCC_DEALLOC_LINES = 0x0000C08D, 1884 GX2_STAT_TCC_DEALLOC_CYCLES = 0x0000C08E, 1885 GX2_STAT_TCC_REG_WRITES = 0x0000C08F, 1886 GX2_STAT_TCC_REG_READS = 0x0000C090, 1887 GX2_STAT_TCC_DEBUG_BUS = 0x0000C091, 1888 GX2_STAT_TCC_DUMMY_LAST = 0x0000C092, 1889 GX2_STAT_TCC_FIRST = GX2_STAT_TCC_NONE, 1890 GX2_STAT_TCC_LAST = GX2_STAT_TCC_DUMMY_LAST, 1891 /// Number of busy cycles 1892 GX2_STAT_CB_BUSY = 0x0000D000, 1893 /// Number of cycles the DB to CB tile interface is valid and ready. This is measured after the input fifo. 1894 GX2_STAT_CB_DB_CB_TILE_VALID_READY = 0x0000D001, 1895 /// Number of cycles the DB to CB tile interface is valid and not ready. This is measured after the input fifo. 1896 GX2_STAT_CB_DB_CB_TILE_VALID_READYB = 0x0000D002, 1897 /// Number of cycles the DB to CB tile interface is not valid and ready. This is measured after the input fifo. 1898 GX2_STAT_CB_DB_CB_TILE_VALIDB_READY = 0x0000D003, 1899 /// Number of cycles the DB to CB tile interface is not valid and not ready. This is measured after the input fifo. 1900 GX2_STAT_CB_DB_CB_TILE_VALIDB_READYB = 0x0000D004, 1901 /// Number of cycles the DB to CB lquad interface is valid and ready. This is measured after the input fifo 1902 GX2_STAT_CB_DB_CB_LQUAD_VALID_READY = 0x0000D005, 1903 /// Number of cycles the DB to CB lquad interface is valid and not ready. This is measured after the input fifo 1904 GX2_STAT_CB_DB_CB_LQUAD_VALID_READYB = 0x0000D006, 1905 /// Number of cycles the DB to CB lquad interface is not valid and ready. This is measured after the input fifo 1906 GX2_STAT_CB_DB_CB_LQUAD_VALIDB_READY = 0x0000D007, 1907 /// Number of cycles the DB to CB lquad interface is not valid and not ready. This is measured after the input fifo 1908 GX2_STAT_CB_DB_CB_LQUAD_VALIDB_READYB = 0x0000D008, 1909 /// Number of cycles the CB to TAP write request interface is valid and ready. This is measured at the interface converter rather than directly on the interface. 1910 GX2_STAT_CB_CB_TAP_WRREQ_VALID_READY = 0x0000D009, 1911 /// Number of cycles the CB to TAP write request interface is valid and not ready. This is measured at the interface converter rather than directly on the interface. 1912 GX2_STAT_CB_CB_TAP_WRREQ_VALID_READYB = 0x0000D00A, 1913 /// Number of cycles the CB to TAP write request interface is valid and ready. This is measured at the interface converter rather than directly on the interface. 1914 GX2_STAT_CB_CB_TAP_WRREQ_VALIDB_READY = 0x0000D00B, 1915 /// Number of cycles the CB to TAP write request interface is not valid and not ready. This is measured at the interface converter rather than directly on the interface. 1916 GX2_STAT_CB_CB_TAP_WRREQ_VALIDB_READYB = 0x0000D00C, 1917 /// Number of cycles the CB to TAP read request interface is valid and ready. This is measured at the interface converter rather than directly on the interface. 1918 GX2_STAT_CB_CB_TAP_RDREQ_VALID_READY = 0x0000D00D, 1919 /// Number of cycles the CB to TAP read request interface is valid and not ready. This is measured at the interface converter rather than directly on the interface. 1920 GX2_STAT_CB_CB_TAP_RDREQ_VALID_READYB = 0x0000D00E, 1921 /// Number of cycles the CB to TAP read request interface is not valid and ready. This is measured at the interface converter rather than directly on the interface. 1922 GX2_STAT_CB_CB_TAP_RDREQ_VALIDB_READY = 0x0000D00F, 1923 /// Number of cycles the CB to TAP read request interface is not valid and not ready. This is measured at the interface converter rather than directly on the interface. 1924 GX2_STAT_CB_CB_TAP_RDREQ_VALIDB_READYB = 0x0000D010, 1925 /// Number of cycles the cmask to fmask tile interface is valid and ready 1926 GX2_STAT_CB_CM_FC_TILE_VALID_READY = 0x0000D011, 1927 /// Number of cycles the cmask to fmask tile interface is valid and not ready 1928 GX2_STAT_CB_CM_FC_TILE_VALID_READYB = 0x0000D012, 1929 /// Number of cycles the cmask to fmask tile interface is not valid and ready 1930 GX2_STAT_CB_CM_FC_TILE_VALIDB_READY = 0x0000D013, 1931 /// Number of cycles the cmask to fmask tile interface is not valid and not ready 1932 GX2_STAT_CB_CM_FC_TILE_VALIDB_READYB = 0x0000D014, 1933 /// Number of cycles the fmask to color cache interface is valid and ready 1934 GX2_STAT_CB_FC_CC_QUADFRAG_VALID_READY = 0x0000D015, 1935 /// Number of cycles the fmask to color cache interface is valid and not ready 1936 GX2_STAT_CB_FC_CC_QUADFRAG_VALID_READYB = 0x0000D016, 1937 /// Number of cycles the fmask to color cache interface is not valid and ready 1938 GX2_STAT_CB_FC_CC_QUADFRAG_VALIDB_READY = 0x0000D017, 1939 /// Number of cycles the fmask to color cache interface is not valid and not ready 1940 GX2_STAT_CB_FC_CC_QUADFRAG_VALIDB_READYB = 0x0000D018, 1941 /// Number of cycles the fragop unit input interface is valid and ready 1942 GX2_STAT_CB_FOP_IN_VALID_READY = 0x0000D019, 1943 /// Number of cycles the fragop unit input interface is valid and not ready 1944 GX2_STAT_CB_FOP_IN_VALID_READYB = 0x0000D01A, 1945 /// Number of cycles the fragop unit input interface is not valid and ready 1946 GX2_STAT_CB_FOP_IN_VALIDB_READY = 0x0000D01B, 1947 /// Number of cycles the fragop unit input interface is not valid and not ready 1948 GX2_STAT_CB_FOP_IN_VALIDB_READYB = 0x0000D01C, 1949 /// Number of cycles the color cache input block to tag block interface is valid and ready 1950 GX2_STAT_CB_CC_IB_TB_FRAG_VALID_READY = 0x0000D01D, 1951 /// Number of cycles the color cache input block to tag block interface is valid and not ready 1952 GX2_STAT_CB_CC_IB_TB_FRAG_VALID_READYB = 0x0000D01E, 1953 /// Number of cycles the color cache input block to tag block interface is not valid and ready 1954 GX2_STAT_CB_CC_IB_TB_FRAG_VALIDB_READY = 0x0000D01F, 1955 /// Number of cycles the color cache input block to tag block interface is not valid and not ready 1956 GX2_STAT_CB_CC_IB_TB_FRAG_VALIDB_READYB = 0x0000D020, 1957 /// The color cache source fifo is full 1958 GX2_STAT_CB_CC_SF_FULL = 0x0000D021, 1959 /// The color cache reorder buffer is full 1960 GX2_STAT_CB_CC_RB_FULL = 0x0000D022, 1961 /// The fmask read latency fifo is full 1962 GX2_STAT_CB_FC_RDLAT_FIFO_FULL = 0x0000D023, 1963 /// The cmask tile queue is full 1964 GX2_STAT_CB_CM_TQ_FULL = 0x0000D024, 1965 /// A quad has arrived over the lquad interface but the corresponding tile has not arrive yet. 1966 GX2_STAT_CB_LQUAD_NO_TILE = 0x0000D025, 1967 /// Number of cmask cache hits 1968 GX2_STAT_CB_CM_CACHE_HIT = 0x0000D026, 1969 /// Number of cmask cache tag misses. A tag miss is when there isn`t a tag that matches the input. Because of sectoring, a tag hit does not imply that the required data is in the cache. 1970 GX2_STAT_CB_CM_CACHE_TAG_MISS = 0x0000D027, 1971 /// Number of cmask cache sector misses. A sector miss is when the required sector is not in the cache. Tag misses are included in this count because a sector cannot be in the cache if there is no tag for it. 1972 GX2_STAT_CB_CM_CACHE_SECTOR_MISS = 0x0000D028, 1973 /// The cmask cache is stalled because it is trying to evict a line that already has a pending evict 1974 GX2_STAT_CB_CM_CACHE_REEVICTION_STALL = 0x0000D029, 1975 /// The cmask cache is stalled because it is trying to evict a line that has a nonzero inflight count. This is usually a sign that the cache is unable to withstand the memory read latency. 1976 GX2_STAT_CB_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x0000D02A, 1977 /// The cmask cache is stalled because it is trying to evict a line that does not yet have resident data. 1978 GX2_STAT_CB_CM_CACHE_EVICT_NONRESIDENT_STALL = 0x0000D02B, 1979 /// The cmask cache is stalled because the line being replaced has a pending evict. This is usually a sign that the cache is unable to withstand the memory write latency. 1980 GX2_STAT_CB_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x0000D02C, 1981 /// The cmask cache is stalled because one of the inflight counters has reached the maximum value. 1982 GX2_STAT_CB_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x0000D02D, 1983 /// The cmask cache is stalled because the read request output path is stalled. 1984 GX2_STAT_CB_CM_CACHE_READ_OUTPUT_STALL = 0x0000D02E, 1985 /// The cmask cache is stalled because the write request output path is stalled. 1986 GX2_STAT_CB_CM_CACHE_WRITE_OUTPUT_STALL = 0x0000D02F, 1987 /// The cmask cache is stalled because the acknowledge output path is stalled. 1988 GX2_STAT_CB_CM_CACHE_ACK_OUTPUT_STALL = 0x0000D030, 1989 /// This is the number of cmask cache flushes. 1990 GX2_STAT_CB_CM_CACHE_FLUSH = 0x0000D031, 1991 /// Number of fmask cache hits 1992 GX2_STAT_CB_FC_CACHE_HIT = 0x0000D032, 1993 /// Number of fmask cache tag misses. A tag miss is when there isn`t a tag that matches the input. Because of sectoring, a tag hit does not imply that the required data is in the cache. 1994 GX2_STAT_CB_FC_CACHE_TAG_MISS = 0x0000D033, 1995 /// Number of fmask cache sector misses. A sector miss is when the required sector is not in the cache. Tag misses are included in this count because a sector cannot be in the cache if there is no tag for it. 1996 GX2_STAT_CB_FC_CACHE_SECTOR_MISS = 0x0000D034, 1997 /// The fmask cache is stalled because it is trying to evict a line that already has a pending evict 1998 GX2_STAT_CB_FC_CACHE_REEVICTION_STALL = 0x0000D035, 1999 /// The fmask cache is stalled because it is trying to evict a line that has a nonzero inflight count. This is usually a sign that the cache is unable to withstand the memory read latency. 2000 GX2_STAT_CB_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x0000D036, 2001 /// The fmask cache is stalled because it is trying to evict a line that does not yet have resident data. 2002 GX2_STAT_CB_FC_CACHE_EVICT_NONRESIDENT_STALL = 0x0000D037, 2003 /// The fmask cache is stalled because the line being replaced has a pending evict. This is usually a sign that the cache is unable to withstand the memory write latency. 2004 GX2_STAT_CB_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x0000D038, 2005 /// The fmask cache is stalled because one of the inflight counters has reached the maximum value. 2006 GX2_STAT_CB_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x0000D039, 2007 /// The fmask cache is stalled because the read request output path is stalled. 2008 GX2_STAT_CB_FC_CACHE_READ_OUTPUT_STALL = 0x0000D03A, 2009 /// The fmask cache is stalled because the write request output path is stalled. 2010 GX2_STAT_CB_FC_CACHE_WRITE_OUTPUT_STALL = 0x0000D03B, 2011 /// The fmask cache is stalled because the acknowledge output path is stalled. 2012 GX2_STAT_CB_FC_CACHE_ACK_OUTPUT_STALL = 0x0000D03C, 2013 /// This is the number of fmask cache flushes. 2014 GX2_STAT_CB_FC_CACHE_FLUSH = 0x0000D03D, 2015 /// Number of fmask cache hits 2016 GX2_STAT_CB_CC_CACHE_HIT = 0x0000D03E, 2017 /// Number of color cache tag misses. A tag miss is when there isn`t a tag that matches the input. Because of sectoring, a tag hit does not imply that the required data is in the cache. 2018 GX2_STAT_CB_CC_CACHE_TAG_MISS = 0x0000D03F, 2019 /// Number of color cache sector misses. A sector miss is when the required sector is not in the cache. Tag misses are included in this count because a sector cannot be in the cache if there is no tag for it. 2020 GX2_STAT_CB_CC_CACHE_SECTOR_MISS = 0x0000D040, 2021 /// The color cache is stalled because it is trying to evict a line that already has a pending evict 2022 GX2_STAT_CB_CC_CACHE_REEVICTION_STALL = 0x0000D041, 2023 /// The color cache is stalled because it is trying to evict a line that has a nonzero inflight count. This is usually a sign that the cache is unable to withstand the memory read latency. 2024 GX2_STAT_CB_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x0000D042, 2025 /// The color cache is stalled because it is trying to evict a line that does not yet have resident data. 2026 GX2_STAT_CB_CC_CACHE_EVICT_NONRESIDENT_STALL = 0x0000D043, 2027 /// The color cache is stalled because the line being replaced has a pending evict. This is usually a sign that the cache is unable to withstand the memory write latency. 2028 GX2_STAT_CB_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x0000D044, 2029 /// The color cache is stalled because one of the inflight counters has reached the maximum value. 2030 GX2_STAT_CB_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x0000D045, 2031 /// The color cache is stalled because the read request output path is stalled. 2032 GX2_STAT_CB_CC_CACHE_READ_OUTPUT_STALL = 0x0000D046, 2033 /// The color cache is stalled because the write request output path is stalled. 2034 GX2_STAT_CB_CC_CACHE_WRITE_OUTPUT_STALL = 0x0000D047, 2035 /// The color cache is stalled because the acknowledge output path is stalled. 2036 GX2_STAT_CB_CC_CACHE_ACK_OUTPUT_STALL = 0x0000D048, 2037 /// The number of times a write allocate cache line is converted to a read-modify-write cache line. 2038 GX2_STAT_CB_CC_CACHE_WA_TO_RMW_CONVERSION = 0x0000D049, 2039 /// This is the number of color cache flushes. This is includes surface sync flushes. 2040 GX2_STAT_CB_CC_CACHE_FLUSH = 0x0000D04A, 2041 /// Number of 32-byte cmask mc read requests. Cmask does not make 32-byte requests, so the counter will report the equivalent number of 32-byte requests. 2042 GX2_STAT_CB_CM_MC_READ_REQUEST = 0x0000D04B, 2043 /// Number of 32-byte fmask mc read requests. 2044 GX2_STAT_CB_FC_MC_READ_REQUEST = 0x0000D04C, 2045 /// Number of 32-byte color mc read requests. Color does not make 32-byte requests, so the counter will report the equivalent number of 32-byte requests. 2046 GX2_STAT_CB_CC_MC_READ_REQUEST = 0x0000D04D, 2047 /// Number of 32-byte cmask mc write requests. 2048 GX2_STAT_CB_CM_MC_WRITE_REQUEST = 0x0000D04E, 2049 /// Number of 32-byte fmask mc write requests. 2050 GX2_STAT_CB_FC_MC_WRITE_REQUEST = 0x0000D04F, 2051 /// Number of 32-byte color mc write requests. 2052 GX2_STAT_CB_CC_MC_WRITE_REQUEST = 0x0000D050, 2053 /// Number of 32-byte cmask mc read requests in flight. Cmask does not make 32-byte requests, so the counter will report the equivalent number of 32-byte requests. Dividing this number by the cmask read request count produces the average latency. 2054 GX2_STAT_CB_CM_MC_READ_REQUESTS_IN_FLIGHT = 0x0000D051, 2055 /// Number of 32-byte fmask mc read requests in flight. Dividing this number by the fmask read request count produces the average latency. 2056 GX2_STAT_CB_FC_MC_READ_REQUESTS_IN_FLIGHT = 0x0000D052, 2057 /// Number of 32-byte color mc read requests in flight. Color does not make 32-byte requests, so the counter will report the equivalent number of 32-byte requests. Dividing this number by the color read request count produces the average latency. 2058 GX2_STAT_CB_CC_MC_READ_REQUESTS_IN_FLIGHT = 0x0000D053, 2059 /// Number of 32-byte cmask mc write requests in flight. Dividing this number by the cmask write request count produces the average latency. 2060 GX2_STAT_CB_CM_MC_WRITE_REQUESTS_IN_FLIGHT = 0x0000D054, 2061 /// Number of 32-byte fmask mc write requests in flight. Dividing this number by the fmask write request count produces the average latency. 2062 GX2_STAT_CB_FC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x0000D055, 2063 /// Number of 32-byte color mc write requests in flight. Dividing this number by the color write request count produces the average latency. 2064 GX2_STAT_CB_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x0000D056, 2065 /// Number of surface syncs 2066 GX2_STAT_CB_CC_SURFACE_SYNC = 0x0000D057, 2067 /// Number of quad fragments that require two cache probes. AA blending can create these when the read fragment does not match the write fragment. 2068 GX2_STAT_CB_TWO_PROBE_QUAD_FRAGMENT = 0x0000D058, 2069 /// Number of slow mode quad fragments. 2070 GX2_STAT_CB_SLOW_MODE_QUAD_FRAGMENT = 0x0000D059, 2071 /// This is the number of dual source color quad fragments 2072 GX2_STAT_CB_DUAL_SOURCE_COLOR_QUAD_FRAGMENT = 0x0000D05A, 2073 /// This is the number of drawn quads. Filtering has an effect in this mode. 2074 GX2_STAT_CB_DRAWN_QUAD = 0x0000D05B, 2075 /// This is the number of drawn pixels. Filtering has an effect in this mode. 2076 GX2_STAT_CB_DRAWN_PIXEL = 0x0000D05C, 2077 /// This is the number of drawn quad fragments. Filtering has an effect in this mode. 2078 GX2_STAT_CB_DRAWN_QUAD_FRAGMENT = 0x0000D05D, 2079 /// This is the number of times the blend pipeline is stalled to handle read after write hazards. 2080 GX2_STAT_CB_BLENDER_RAW_HAZARD_STALL = 0x0000D05E, 2081 /// Total number of events reaching the CB. This includes events that the CB does not process. 2082 GX2_STAT_CB_EVENT = 0x0000D05F, 2083 /// Number of CACHE_FLUSH_TS events 2084 GX2_STAT_CB_EVENT_CACHE_FLUSH_TS = 0x0000D060, 2085 /// Number of CONTEXT_DONE events 2086 GX2_STAT_CB_EVENT_CONTEXT_DONE = 0x0000D061, 2087 /// Number of CACHE_FLUSH events 2088 GX2_STAT_CB_EVENT_CACHE_FLUSH = 0x0000D062, 2089 /// Number of CACHE_FLUSH_AND_INV_TS_EVENT events 2090 GX2_STAT_CB_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 0x0000D063, 2091 /// Number of_CACHE_FLUSH_AND_INV_EVENTevents 2092 GX2_STAT_CB_EVENT_CACHE_FLUSH_AND_INV_EVENT = 0x0000D064, 2093 /// Number of FLUSH_AND_INV_CB_DATA_TS events 2094 GX2_STAT_CB_EVENT_FLUSH_AND_INV_CB_DATA_TS = 0x0000D065, 2095 /// Number of FLUSH_AND_INV_CB_META events 2096 GX2_STAT_CB_EVENT_FLUSH_AND_INV_CB_META = 0x0000D066, 2097 /// Number of times a value of 0xC was read from cmask. Cmask reads only occur on fmask cache misses. A value of 0xC means that a fmask tile requires 0 bit planes. 2098 GX2_STAT_CB_CMASK_READ_DATA_0XC = 0x0000D067, 2099 /// Number of times a value of 0xD was read from cmask. Cmask reads only occur on fmask cache misses. A value of 0xD means that a fmask tile requires 1 bit planes. 2100 GX2_STAT_CB_CMASK_READ_DATA_0XD = 0x0000D068, 2101 /// Number of times a value of 0xE was read from cmask. Cmask reads only occur on fmask cache misses. A value of 0xE means that a fmask tile requires 2 bit planes. 2102 GX2_STAT_CB_CMASK_READ_DATA_0XE = 0x0000D069, 2103 /// Number of times a value of 0xF was read from cmask. Cmask reads only occur on fmask cache misses. A value of 0xF means that a fmask tile requires 3 bit planes. 2104 GX2_STAT_CB_CMASK_READ_DATA_0XF = 0x0000D06A, 2105 /// Number of times a value of 0xC was written to cmask. Cmask writes occur at the end of a tile. The hardware does not perform the write if fmask has not changed, but the counter will update as if regardless of whether the hardware wrote or not. A value of 0xC means that a fmask tile requires 0 bit planes. 2106 GX2_STAT_CB_CMASK_WRITE_DATA_0XC = 0x0000D06B, 2107 /// Number of times a value of 0xD was written to cmask. Cmask writes occur at the end of a tile. The hardware does not perform the write if fmask has not changed, but the counter will update as if regardless of whether the hardware wrote or not. A value of 0xD means that a fmask tile requires 1 bit planes. 2108 GX2_STAT_CB_CMASK_WRITE_DATA_0XD = 0x0000D06C, 2109 /// Number of times a value of 0xE was written to cmask. Cmask writes occur at the end of a tile. The hardware does not perform the write if fmask has not changed, but the counter will update as if regardless of whether the hardware wrote or not. A value of 0xE means that a fmask tile requires 2 bit planes. 2110 GX2_STAT_CB_CMASK_WRITE_DATA_0XE = 0x0000D06D, 2111 /// Number of times a value of 0xF was written to cmask. Cmask writes occur at the end of a tile. The hardware does not perform the write if fmask has not changed, but the counter will update as if regardless of whether the hardware wrote or not. A value of 0xF means that a fmask tile requires 3 bit planes. 2112 GX2_STAT_CB_CMASK_WRITE_DATA_0XF = 0x0000D06E, 2113 /// Number of cycles that the core clock is enabled. 2114 GX2_STAT_CB_CORE_SCLK_VLD = 0x0000D06F, 2115 /// Number of cycles that the register clock is enabled. 2116 GX2_STAT_CB_REG_SCLK_VLD = 0x0000D070, 2117 GX2_STAT_CB_FIRST = GX2_STAT_CB_BUSY, 2118 GX2_STAT_CB_LAST = GX2_STAT_CB_REG_SCLK_VLD, 2119 /// Cycles Interface is sending 2120 GX2_STAT_DB_SC_DB_TILE_SENDS = 0x0000E000, 2121 /// Cycles Interface is busy 2122 GX2_STAT_DB_SC_DB_TILE_BUSY = 0x0000E001, 2123 /// Cycles Interface is stalled 2124 GX2_STAT_DB_SC_DB_TILE_STALLS = 0x0000E002, 2125 /// Events sent over interface 2126 GX2_STAT_DB_SC_DB_TILE_EVENTS = 0x0000E003, 2127 /// Tiles sent over interface 2128 GX2_STAT_DB_SC_DB_TILE_TILES = 0x0000E004, 2129 /// Fully covered tiles 2130 GX2_STAT_DB_SC_DB_TILE_COVERED = 0x0000E005, 2131 /// HiZ starved waiting for htile data from cache 2132 GX2_STAT_DB_HIZ_TC_READ_STARVED = 0x0000E006, 2133 /// HiZ stalled writing to htile cache 2134 GX2_STAT_DB_HIZ_TC_WRITE_STALL = 0x0000E007, 2135 /// Quarter tiles culled by hiZ 2136 GX2_STAT_DB_HIZ_QTILES_CULLED = 0x0000E008, 2137 /// Quarter tiles culled by HiS 2138 GX2_STAT_DB_HIS_QTILES_CULLED = 0x0000E009, 2139 /// Cycles Interface is sending 2140 GX2_STAT_DB_DB_SC_TILE_SENDS = 0x0000E00A, 2141 /// Cycles Interface is busy 2142 GX2_STAT_DB_DB_SC_TILE_BUSY = 0x0000E00B, 2143 /// Cycles Interface is stalled by SC 2144 GX2_STAT_DB_DB_SC_TILE_STALLS = 0x0000E00C, 2145 /// Cycles Interface is stalled by detail walk tile fifo 2146 GX2_STAT_DB_DB_SC_TILE_DF_STALLS = 0x0000E00D, 2147 /// Tiles sent over interface 2148 GX2_STAT_DB_DB_SC_TILE_TILES = 0x0000E00E, 2149 /// Tiles culled in total 2150 GX2_STAT_DB_DB_SC_TILE_CULLED = 0x0000E00F, 2151 /// Tiles culled due to a hierarchical fail test 2152 GX2_STAT_DB_DB_SC_TILE_HIER_KILL = 0x0000E010, 2153 /// Tiles culled because they were accerated fast tile ops. 2154 GX2_STAT_DB_DB_SC_TILE_FAST_OPS = 0x0000E011, 2155 /// Tiles culled because they would not do anything 2156 GX2_STAT_DB_DB_SC_TILE_NO_OPS = 0x0000E012, 2157 /// Tiles run at pixel rate as opposed to sample rate tile 2158 GX2_STAT_DB_DB_SC_TILE_PIXEL_RATE = 0x0000E013, 2159 /// Tiles culled because they were supersample tiles that are merged into a fast tile op 2160 GX2_STAT_DB_DB_SC_TILE_SSAA_KILL = 0x0000E014, 2161 /// Tiles that operate on Z in 1 clock. Can be inside a slow, pixel rate, or fast tile op 2162 GX2_STAT_DB_DB_SC_TILE_FAST_Z_OPS = 0x0000E015, 2163 /// Tiles that operate on stencil in 1 clock. Can be inside a slow, pixel rate, or fast tile op 2164 GX2_STAT_DB_DB_SC_TILE_FAST_STENCIL_OPS = 0x0000E016, 2165 /// Cycles Interface is sending 2166 GX2_STAT_DB_SC_DB_QUAD_SENDS = 0x0000E017, 2167 /// Cycles Interface is busy 2168 GX2_STAT_DB_SC_DB_QUAD_BUSY = 0x0000E018, 2169 /// Squads transferred over interface 2170 GX2_STAT_DB_SC_DB_QUAD_SQUADS = 0x0000E019, 2171 /// Tiles sent over interface 2172 GX2_STAT_DB_SC_DB_QUAD_TILES = 0x0000E01A, 2173 /// Pixels transferred over interface 2174 GX2_STAT_DB_SC_DB_QUAD_PIXELS = 0x0000E01B, 2175 /// Number of detail killed tiles 2176 GX2_STAT_DB_SC_DB_QUAD_KILLED_TILES = 0x0000E01C, 2177 /// Interface is sending 2178 GX2_STAT_DB_DB_SC_QUAD_SENDS = 0x0000E01D, 2179 /// Cycles Interface is busy 2180 GX2_STAT_DB_DB_SC_QUAD_BUSY = 0x0000E01E, 2181 /// Cycles Interface is stalled 2182 GX2_STAT_DB_DB_SC_QUAD_STALLS = 0x0000E01F, 2183 /// Squads sent over interface 2184 GX2_STAT_DB_DB_SC_QUAD_SQUADS = 0x0000E020, 2185 /// Tiles sent over interface 2186 GX2_STAT_DB_DB_SC_QUAD_TILES = 0x0000E021, 2187 /// Quads transferred over the DB_SC_quad interface 2188 GX2_STAT_DB_DB_SC_QUAD_QUADS = 0x0000E022, 2189 /// Cycles sending tiles/events to CB. Tiles not shaded or needed by the CB are not sent. 2190 GX2_STAT_DB_DB_CB_TILE_SENDS = 0x0000E023, 2191 GX2_STAT_DB_DB_CB_TILE_BUSY = 0x0000E024, 2192 GX2_STAT_DB_DB_CB_TILE_STALLS = 0x0000E025, 2193 /// Cycles Interface is sending 2194 GX2_STAT_DB_SX_DB_QUAD_SENDS = 0x0000E026, 2195 /// Cycles Interface is busy 2196 GX2_STAT_DB_SX_DB_QUAD_BUSY = 0x0000E027, 2197 /// Cycles Interface is stalled 2198 GX2_STAT_DB_SX_DB_QUAD_STALLS = 0x0000E028, 2199 /// Quads sent over interface 2200 GX2_STAT_DB_SX_DB_QUAD_QUADS = 0x0000E029, 2201 /// Pixels sent over interface 2202 GX2_STAT_DB_SX_DB_QUAD_PIXELS = 0x0000E02A, 2203 /// Each MRT of a quad sent over interface 2204 GX2_STAT_DB_SX_DB_QUAD_EXPORTS = 0x0000E02B, 2205 /// Divide by DB_SC_quad_quads to get PS latency. 2206 GX2_STAT_DB_SH_QUADS_OUTSTANDING_SUM = 0x0000E02C, 2207 /// Cycles Interface is sending 2208 GX2_STAT_DB_DB_CB_LQUAD_SENDS = 0x0000E02D, 2209 /// Cycles Interface is busy 2210 GX2_STAT_DB_DB_CB_LQUAD_BUSY = 0x0000E02E, 2211 /// Cycles Interface is stalled 2212 GX2_STAT_DB_DB_CB_LQUAD_STALLS = 0x0000E02F, 2213 /// Quads sent over interface 2214 GX2_STAT_DB_DB_CB_LQUAD_QUADS = 0x0000E030, 2215 /// HTile reads. Each is 256B 2216 GX2_STAT_DB_TILE_RD_SENDS = 0x0000E031, 2217 /// Divide by tile_rd_sends*8 to get htile memory latency 2218 GX2_STAT_DB_MI_TILE_RD_OUTSTANDING_SUM = 0x0000E032, 2219 /// Quad read reqs. Each is 32B to 256B 2220 GX2_STAT_DB_QUAD_RD_SENDS = 0x0000E033, 2221 /// Cycles quad read interface is trying to send requests 2222 GX2_STAT_DB_QUAD_RD_BUSY = 0x0000E034, 2223 /// Cycles quad read interface is stalled by the memory interface 2224 GX2_STAT_DB_QUAD_RD_MI_STALL = 0x0000E035, 2225 /// Cycles a quad read is stalled waiting for a write to finish 2226 GX2_STAT_DB_QUAD_RD_RW_COLLISION = 0x0000E036, 2227 /// Cycles a quad read is stalled because the read latency hiding fifo is full. 2228 GX2_STAT_DB_QUAD_RD_TAG_STALL = 0x0000E037, 2229 /// Number of 32 Byte quad read requests 2230 GX2_STAT_DB_QUAD_RD_32BYTE_REQS = 0x0000E038, 2231 /// Cycles DB is panicing for quad read data 2232 GX2_STAT_DB_QUAD_RD_PANIC = 0x0000E039, 2233 /// Divide by quad_rd_32byte_reqs to get depth buffer memory latency 2234 GX2_STAT_DB_MI_QUAD_RD_OUTSTANDING_SUM = 0x0000E03A, 2235 /// Number of 32 byte quad read returns 2236 GX2_STAT_DB_QUAD_RDRET_SENDS = 0x0000E03B, 2237 /// Cycles the quad read data is returning 2238 GX2_STAT_DB_QUAD_RDRET_BUSY = 0x0000E03C, 2239 /// 32 Byte HTile writes 2240 GX2_STAT_DB_TILE_WR_SENDS = 0x0000E03D, 2241 /// 32 Byte Htile write acks 2242 GX2_STAT_DB_TILE_WR_ACKS = 0x0000E03E, 2243 /// Divide by tile_wr_sends to get tile write memory latency 2244 GX2_STAT_DB_MI_TILE_WR_OUTSTANDING_SUM = 0x0000E03F, 2245 /// Cycles quad is sending write requests to the memory interface block of the DB 2246 GX2_STAT_DB_QUAD_WR_SENDS = 0x0000E040, 2247 /// Cycles quad is trying to write to the memory interface 2248 GX2_STAT_DB_QUAD_WR_BUSY = 0x0000E041, 2249 /// Cycles quad is stalled while writing to the memory interface 2250 GX2_STAT_DB_QUAD_WR_MI_STALL = 0x0000E042, 2251 /// Cycles quad write is stalled waiting for a previous write to finish on the same address 2252 GX2_STAT_DB_QUAD_WR_COHERENCY_STALL = 0x0000E043, 2253 /// Number of 32 Byte quad write acks 2254 GX2_STAT_DB_QUAD_WR_ACKS = 0x0000E044, 2255 /// Divide by the quad_wr_sends to get quad memory write latency 2256 GX2_STAT_DB_MI_QUAD_WR_OUTSTANDING_SUM = 0x0000E045, 2257 /// Htile Cache misses 2258 GX2_STAT_DB_TILE_CACHE_MISSES = 0x0000E046, 2259 /// Htile Cache hits 2260 GX2_STAT_DB_TILE_CACHE_HITS = 0x0000E047, 2261 /// Htile Cache flushes 2262 GX2_STAT_DB_TILE_CACHE_FLUSHES = 0x0000E048, 2263 /// Tile stalls waiting for an htile surface to flush and free 2264 GX2_STAT_DB_TILE_CACHE_SURFACE_STALL = 0x0000E049, 2265 /// Tile stalls waiting for an htile cacheline to free 2266 GX2_STAT_DB_TILE_CACHE_STARVES = 0x0000E04A, 2267 /// Tile stalls waiting for an htile memory read to return 2268 GX2_STAT_DB_TILE_CACHE_MEM_RETURN_STARVE = 0x0000E04B, 2269 /// Number of htile cachelines fetched by the normal tile stream 2270 GX2_STAT_DB_TCP_DISPATCHER_READS = 0x0000E04C, 2271 /// Number of htile cachelines fetched by the prefetcher 2272 GX2_STAT_DB_TCP_PREFETCHER_READS = 0x0000E04D, 2273 /// Number of htile cachelines fetched by the preloader 2274 GX2_STAT_DB_TCP_PRELOADER_READS = 0x0000E04E, 2275 /// Number of htile flushes caused byt the normal tile stream 2276 GX2_STAT_DB_TCP_DISPATCHER_FLUSHES = 0x0000E04F, 2277 /// Number of htile flushes caused byt the normal prefetcher 2278 GX2_STAT_DB_TCP_PREFETCHER_FLUSHES = 0x0000E050, 2279 /// Number of htile flushes caused byt the normal preloader 2280 GX2_STAT_DB_TCP_PRELOADER_FLUSHES = 0x0000E051, 2281 /// Tiles/Events through the Depth Tile Cache 2282 GX2_STAT_DB_DEPTH_TILE_CACHE_SENDS = 0x0000E052, 2283 /// Cycles the Depth Tile Cache is busy testing hit/miss on tiles/events 2284 GX2_STAT_DB_DEPTH_TILE_CACHE_BUSY = 0x0000E053, 2285 /// Cycles starved waiting for a depth surface tile tag to free up 2286 GX2_STAT_DB_DEPTH_TILE_CACHE_STARVES = 0x0000E054, 2287 /// Cycles stalled waiting for a forced flush or invalidate to finish 2288 GX2_STAT_DB_DEPTH_TILE_CACHE_DTILE_LOCKED = 0x0000E055, 2289 /// Cycles depth tile stalled while allocating data 2290 GX2_STAT_DB_DEPTH_TILE_CACHE_ALLOC_STALL = 0x0000E056, 2291 /// Depth/Stencil Cache tile misses 2292 GX2_STAT_DB_DEPTH_TILE_CACHE_MISSES = 0x0000E057, 2293 /// Depth/Stencil Cache tile hits 2294 GX2_STAT_DB_DEPTH_TILE_CACHE_HITS = 0x0000E058, 2295 /// Depth/Stencil Cache tile flushes 2296 GX2_STAT_DB_DEPTH_TILE_CACHE_FLUSHES = 0x0000E059, 2297 /// Noop tiles through the depth tile cache 2298 GX2_STAT_DB_DEPTH_TILE_CACHE_NOOP_TILE = 0x0000E05A, 2299 /// Detail walked noops though the depth tile cache 2300 GX2_STAT_DB_DEPTH_TILE_CACHE_DETAILED_NOOP = 0x0000E05B, 2301 /// Events 2302 GX2_STAT_DB_DEPTH_TILE_CACHE_EVENT = 0x0000E05C, 2303 /// Depth tile frees 2304 GX2_STAT_DB_DEPTH_TILE_CACHE_TILE_FREES = 0x0000E05D, 2305 /// Depth tile data frees (may free data without freeing the dtile) 2306 GX2_STAT_DB_DEPTH_TILE_CACHE_DATA_FREES = 0x0000E05E, 2307 /// Cycles depth/stencil cache is waiting for memory to return 2308 GX2_STAT_DB_DEPTH_TILE_CACHE_MEM_RETURN_STARVE = 0x0000E05F, 2309 /// 512 bit allocation 2310 GX2_STAT_DB_STENCIL_CACHE_MISSES = 0x0000E060, 2311 GX2_STAT_DB_STENCIL_CACHE_HITS = 0x0000E061, 2312 /// 256 bit flushes. Two per cacheline unless it is compressed, in which case it is 1. 2313 GX2_STAT_DB_STENCIL_CACHE_FLUSHES = 0x0000E062, 2314 /// Cache starves when the cache wants to miss but is out of cachelines to allocate 2315 GX2_STAT_DB_STENCIL_CACHE_STARVES = 0x0000E063, 2316 GX2_STAT_DB_STENCIL_CACHE_FREES = 0x0000E064, 2317 GX2_STAT_DB_Z_CACHE_SEPARATE_Z_MISSES = 0x0000E065, 2318 GX2_STAT_DB_Z_CACHE_SEPARATE_Z_HITS = 0x0000E066, 2319 GX2_STAT_DB_Z_CACHE_SEPARATE_Z_FLUSHES = 0x0000E067, 2320 /// Cache starves when the cache wants to miss but is out of cachelines to allocate 2321 GX2_STAT_DB_Z_CACHE_SEPARATE_Z_STARVES = 0x0000E068, 2322 GX2_STAT_DB_Z_CACHE_PMASK_MISSES = 0x0000E069, 2323 GX2_STAT_DB_Z_CACHE_PMASK_HITS = 0x0000E06A, 2324 GX2_STAT_DB_Z_CACHE_PMASK_FLUSHES = 0x0000E06B, 2325 /// Cache starves when the cache wants to miss but is out of cachelines to allocate 2326 GX2_STAT_DB_Z_CACHE_PMASK_STARVES = 0x0000E06C, 2327 GX2_STAT_DB_Z_CACHE_FREES = 0x0000E06D, 2328 GX2_STAT_DB_PLANE_CACHE_MISSES = 0x0000E06E, 2329 GX2_STAT_DB_PLANE_CACHE_HITS = 0x0000E06F, 2330 GX2_STAT_DB_PLANE_CACHE_FLUSHES = 0x0000E070, 2331 /// Cache starves when the cache wants to miss but is out of cachelines to allocate 2332 GX2_STAT_DB_PLANE_CACHE_STARVES = 0x0000E071, 2333 GX2_STAT_DB_PLANE_CACHE_FREES = 0x0000E072, 2334 /// Tiles flushed with with expanded stencil 2335 GX2_STAT_DB_FLUSH_EXPANDED_STENCIL = 0x0000E073, 2336 /// Tiles flushed with with compressed stencil 2337 GX2_STAT_DB_FLUSH_COMPRESSED_STENCIL = 0x0000E074, 2338 /// Tiles flushed with with single stencil 2339 GX2_STAT_DB_FLUSH_SINGLE_STENCIL = 0x0000E075, 2340 /// Tiles flushed with 1 ZPlane 2341 GX2_STAT_DB_FLUSH_1PLANE = 0x0000E076, 2342 /// Tiles flushed with 2 ZPlane 2343 GX2_STAT_DB_FLUSH_2PLANE = 0x0000E077, 2344 /// Tiles flushed with 3 ZPlane 2345 GX2_STAT_DB_FLUSH_3PLANE = 0x0000E078, 2346 /// Tiles flushed with 4 ZPlane 2347 GX2_STAT_DB_FLUSH_4PLANE = 0x0000E079, 2348 /// Tiles flushed with 5 ZPlane 2349 GX2_STAT_DB_FLUSH_5PLANE = 0x0000E07A, 2350 /// Tiles flushed with 6 ZPlane 2351 GX2_STAT_DB_FLUSH_6PLANE = 0x0000E07B, 2352 /// Tiles flushed with 7 ZPlane 2353 GX2_STAT_DB_FLUSH_7PLANE = 0x0000E07C, 2354 /// Tiles flushed with 8 ZPlane 2355 GX2_STAT_DB_FLUSH_8PLANE = 0x0000E07D, 2356 /// Tiles flushed with 9 ZPlane 2357 GX2_STAT_DB_FLUSH_9PLANE = 0x0000E07E, 2358 /// Tiles flushed with 10 ZPlane 2359 GX2_STAT_DB_FLUSH_10PLANE = 0x0000E07F, 2360 /// Tiles flushed with 11 ZPlane 2361 GX2_STAT_DB_FLUSH_11PLANE = 0x0000E080, 2362 /// Tiles flushed with 12 ZPlane 2363 GX2_STAT_DB_FLUSH_12PLANE = 0x0000E081, 2364 /// Tiles flushed with 13 ZPlane 2365 GX2_STAT_DB_FLUSH_13PLANE = 0x0000E082, 2366 /// Tiles flushed with 14 ZPlane 2367 GX2_STAT_DB_FLUSH_14PLANE = 0x0000E083, 2368 /// Tiles flushed with 15 ZPlane 2369 GX2_STAT_DB_FLUSH_15PLANE = 0x0000E084, 2370 /// Tiles flushed with 16 ZPlane 2371 GX2_STAT_DB_FLUSH_16PLANE = 0x0000E085, 2372 /// Tiles flushed with expanded Z 2373 GX2_STAT_DB_FLUSH_EXPANDED_Z = 0x0000E086, 2374 /// Cycles stalled while transitioning from Late/ReZ to EarlyZ 2375 GX2_STAT_DB_EARLYZ_WAITING_FOR_POSTZ_DONE = 0x0000E087, 2376 /// Cycles stalled while transitioning to ReZ from an incompatible Z mode/func/etc. 2377 GX2_STAT_DB_REZ_WAITING_FOR_POSTZ_DONE = 0x0000E088, 2378 /// Detail kill block tiles/squads/events sent 2379 GX2_STAT_DB_DK_TILE_SENDS = 0x0000E089, 2380 /// Cycles Detail Kill block busy 2381 GX2_STAT_DB_DK_TILE_BUSY = 0x0000E08A, 2382 /// Cycles Detail Kill has tile, but no quads from the SC_DB_quad 2383 GX2_STAT_DB_DK_TILE_QUAD_STARVES = 0x0000E08B, 2384 /// Cycles Detail Kill is stalled from below 2385 GX2_STAT_DB_DK_TILE_STALLS = 0x0000E08C, 2386 /// Detail Kill squads 2387 GX2_STAT_DB_DK_SQUAD_SENDS = 0x0000E08D, 2388 /// Cycles the squad Detail Kill input is busy 2389 GX2_STAT_DB_DK_SQUAD_BUSY = 0x0000E08E, 2390 /// Cycles squads are stalled from below. 2391 GX2_STAT_DB_DK_SQUAD_STALLS = 0x0000E08F, 2392 /// Cycles the quad OP pipe of the DB is busy (including memory fetches, but not initial startup) 2393 GX2_STAT_DB_OP_PIPE_BUSY = 0x0000E090, 2394 /// Cycles the Op Pipe is waiting for memory to return (ignoring initial startup) 2395 GX2_STAT_DB_OP_PIPE_MC_READ_STALL = 0x0000E091, 2396 GX2_STAT_DB_QC_BUSY = 0x0000E092, 2397 GX2_STAT_DB_QC_XFC = 0x0000E093, 2398 GX2_STAT_DB_QC_CONFLICTS = 0x0000E094, 2399 GX2_STAT_DB_QC_FULL_STALL = 0x0000E095, 2400 GX2_STAT_DB_QC_IN_PREZ_TILE_STALLS_POSTZ = 0x0000E096, 2401 GX2_STAT_DB_QC_IN_POSTZ_TILE_STALLS_PREZ = 0x0000E097, 2402 GX2_STAT_DB_TSC_INSERT_SUMMARIZE_STALL = 0x0000E098, 2403 GX2_STAT_DB_TL_BUSY = 0x0000E099, 2404 GX2_STAT_DB_TL_DTC_READ_STARVED = 0x0000E09A, 2405 GX2_STAT_DB_TL_Z_FETCH_STALL = 0x0000E09B, 2406 GX2_STAT_DB_TL_STENCIL_STALL = 0x0000E09C, 2407 GX2_STAT_DB_TL_Z_DECOMPRESS_STALL = 0x0000E09D, 2408 GX2_STAT_DB_TL_STENCIL_LOCKED_STALL = 0x0000E09E, 2409 GX2_STAT_DB_TL_EVENTS = 0x0000E09F, 2410 GX2_STAT_DB_TL_SUMMARIZE_SQUADS = 0x0000E0A0, 2411 GX2_STAT_DB_TL_FLUSH_EXPAND_SQUADS = 0x0000E0A1, 2412 GX2_STAT_DB_TL_EXPAND_SQUADS = 0x0000E0A2, 2413 GX2_STAT_DB_TL_PREZ_SQUADS = 0x0000E0A3, 2414 GX2_STAT_DB_TL_POSTZ_SQUADS = 0x0000E0A4, 2415 GX2_STAT_DB_TL_PREZ_NOOP_SQUADS = 0x0000E0A5, 2416 GX2_STAT_DB_TL_POSTZ_NOOP_SQUADS = 0x0000E0A6, 2417 GX2_STAT_DB_TL_GETZ_SQUADS = 0x0000E0A7, 2418 GX2_STAT_DB_TL_TILE_OPS = 0x0000E0A8, 2419 GX2_STAT_DB_TL_IN_XFC = 0x0000E0A9, 2420 GX2_STAT_DB_TL_IN_SINGLE_STENCIL_EXPAND_STALL = 0x0000E0AA, 2421 GX2_STAT_DB_TL_IN_CONSTANT_STENCIL_WALK_STALL = 0x0000E0AB, 2422 GX2_STAT_DB_TL_IN_FAST_Z_STALL = 0x0000E0AC, 2423 GX2_STAT_DB_TL_OUT_XFC = 0x0000E0AD, 2424 GX2_STAT_DB_TL_OUT_SQUADS = 0x0000E0AE, 2425 GX2_STAT_DB_ZF_PLANE_MULTICYCLE = 0x0000E0AF, 2426 GX2_STAT_DB_POSTZ_SAMPLES_PASSING_Z = 0x0000E0B0, 2427 GX2_STAT_DB_POSTZ_SAMPLES_FAILING_Z = 0x0000E0B1, 2428 GX2_STAT_DB_POSTZ_SAMPLES_FAILING_S = 0x0000E0B2, 2429 GX2_STAT_DB_PREZ_SAMPLES_PASSING_Z = 0x0000E0B3, 2430 GX2_STAT_DB_PREZ_SAMPLES_FAILING_Z = 0x0000E0B4, 2431 GX2_STAT_DB_PREZ_SAMPLES_FAILING_S = 0x0000E0B5, 2432 GX2_STAT_DB_TS_TC_UPDATE_STALL = 0x0000E0B6, 2433 GX2_STAT_DB_SC_KICK_START = 0x0000E0B7, 2434 GX2_STAT_DB_SC_KICK_END = 0x0000E0B8, 2435 GX2_STAT_DB_SX_DB_MEM_EXPORTS = 0x0000E0B9, 2436 GX2_STAT_DB_SX_DB_MEM_EXPORTS_ACKED = 0x0000E0BA, 2437 GX2_STAT_DB_SX_DB_ACK_MEM_EXPORTS = 0x0000E0BB, 2438 GX2_STAT_DB_SX_DB_ACK_MEM_EXPORTS_ACKED = 0x0000E0BC, 2439 GX2_STAT_DB_MEM_EXPORT_BUSY = 0x0000E0BD, 2440 GX2_STAT_DB_MEM_EXPORT_MI_STALL = 0x0000E0BE, 2441 GX2_STAT_DB_MEM_EXPORT_TAG_STALL = 0x0000E0BF, 2442 GX2_STAT_DB_CLOCK_REG_ACTIVE = 0x0000E0C0, 2443 GX2_STAT_DB_CLOCK_MAIN_ACTIVE = 0x0000E0C1, 2444 GX2_STAT_DB_CLOCK_MEM_EXPORT_ACTIVE = 0x0000E0C2, 2445 GX2_STAT_DB_ESR_OUT_BUSY = 0x0000E0C3, 2446 GX2_STAT_DB_ESR_OUT_SC_STALL = 0x0000E0C4, 2447 GX2_STAT_DB_ESR_OUT_LQUAD_FIFO_FULL_STALL = 0x0000E0C5, 2448 GX2_STAT_DB_ETR_OUT_SEND = 0x0000E0C6, 2449 GX2_STAT_DB_ETR_OUT_BUSY = 0x0000E0C7, 2450 GX2_STAT_DB_ETR_OUT_LTILE_PROBE_FIFO_FULL_STALL = 0x0000E0C8, 2451 GX2_STAT_DB_ETR_OUT_CB_TILE_STALL = 0x0000E0C9, 2452 GX2_STAT_DB_ETR_OUT_ESR_STALL = 0x0000E0CA, 2453 GX2_STAT_DB_FIRST = GX2_STAT_DB_SC_DB_TILE_SENDS, 2454 GX2_STAT_DB_LAST = GX2_STAT_DB_ETR_OUT_ESR_STALL, 2455 GX2_STAT_PIPELINE = 0x0000F000, 2456 GX2_STAT_PIPELINE_FIRST = GX2_STAT_PIPELINE, 2457 GX2_STAT_PIPELINE_LAST = GX2_STAT_PIPELINE 2458 } _GX2StatId; 2459 2460 /// \brief Indicates desired high-level performance metric to gather. 2461 typedef enum _GX2PerfMetric 2462 { 2463 /// Time this API call took to execute on the CPU+GPU in microseconds. 2464 /// Does not include time that draw calls are processed in parallel 2465 /// (GX2_STAT_GRBM_COUNT / 550.0f) 2466 GX2_PERF_U64_TIME, 2467 /// Time this API call took to execute on the GPU in microseconds. 2468 /// Does not include time that draw calls are processed in parallel 2469 /// (GX2_STAT_GRBM_GUI_ACTIVE / 550.0f) 2470 GX2_PERF_U64_GPU_TIME, 2471 /// Percentage of time GPU was busy 2472 /// (GX2_STAT_GRBM_GUI_ACTIVE / GX2_STAT_GRBM_COUNT) * 100.0f 2473 GX2_PERF_F32_GPU_BUSY, 2474 /// Percentage of GPU time that the shader unit is busy. 2475 /// (GX2_STAT_GRBM_SH_BUSY / GX2_STAT_GRBM_GUI_ACTIVE) * 100.0f 2476 GX2_PERF_F32_SHADER_BUSY, 2477 /// The number of reused indices, excluding geometry shader scenario 2478 /// (GX2_STAT_VGT_REUSED_VS_INDICES) 2479 GX2_PERF_U64_REUSED_INDICES_VS, 2480 /// The percentage of work done by the shader unit for the VS. 2481 /// ( GX2_STAT_SQ_THREAD_LEVEL_PER_TYPE[VS|ES] / 2482 /// GX2_STAT_SQ_THREAD_LEVEL_PER_TYPE[VS|ES|GS|PS] ) * 100.0f 2483 GX2_PERF_F32_SHADER_BUSY_VS, 2484 /// The percentage of work done by the shader unit for the GS. 2485 /// ( GX2_STAT_SQ_THREAD_LEVEL_PER_TYPE[GS] / 2486 /// GX2_STAT_SQ_THREAD_LEVEL_PER_TYPE[VS|ES|GS|PS] ) * 100.0f 2487 GX2_PERF_F32_SHADER_BUSY_GS, 2488 /// The percentage of work done by the shader unit for the PS. 2489 /// ( GX2_STAT_SQ_THREAD_LEVEL_PER_TYPE[PS] / 2490 /// GX2_STAT_SQ_THREAD_LEVEL_PER_TYPE[VS|ES|GS|PS] ) * 100.0f 2491 GX2_PERF_F32_SHADER_BUSY_PS, 2492 /// Average number of ALU instructions executed. 2493 /// ( GX2_STAT_SQ_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE[VS|ES|GS|PS] / 2494 /// GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f * 2.0f 2495 GX2_PERF_F32_ALU_BUSY, 2496 /// The percentage of GPUTime texture instructions are being processed. 2497 /// ( GX2_STAT_SQ_TA_TEX_INSTRS_PER_TYPE[VS|ES|GS|PS] / 2498 /// GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f * 8.0f 2499 GX2_PERF_F32_TEX_BUSY, 2500 /// The number of vertices processed by the VS. 2501 /// ( GX2_STAT_SQ_ITEMS_PER_TYPE[VS|ES] ) 2502 GX2_PERF_U64_VS_VERTICES_IN, 2503 /// Average number of texture instructions executed in VS. Affected by flow control. 2504 /// ( GX2_STAT_SQ_TA_TEX_INSTRS_PER_TYPE[VS|ES] / 2505 /// GX2_STAT_SQ_THREADS_PER_TYPE[VS|ES] ) 2506 GX2_PERF_F32_VS_TEX_INST_COUNT, 2507 /// The percentage of GPUTime texture instructions are being processed by the VS. 2508 /// ( GX2_STAT_SQ_TA_TEX_INSTRS_PER_TYPE[VS|ES] / 2509 /// GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f * 8.0f 2510 GX2_PERF_F32_VS_TEX_BUSY, 2511 /// Average number of ALU instructions executed in the VS. Affected by flow control. 2512 /// ( GX2_STAT_SQ_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE[VS|ES] / 2513 /// GX2_STAT_SQ_THREADS_PER_TYPE[VS|ES] ) 2514 GX2_PERF_F32_VS_ALU_INST_COUNT, 2515 /// The percentage of GPUTime ALU instructions are being processed by the VS. 2516 /// ( GX2_STAT_SQ_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE[VS|ES] / 2517 /// GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f * 2.0f 2518 GX2_PERF_F32_VS_ALU_BUSY, 2519 /// ALU vector packing efficiency. Values below 70 percent indicate that ALU dependency chains may be preventing full utilization of the processor. 2520 /// ( GX2_STAT_SQ_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE[VS|ES] / 2521 /// GX2_STAT_SQ_ALU_CLAUSE_INSTRS_PER_TYPE[VS|ES] ) * 100.0f 2522 GX2_PERF_F32_VS_ALU_EFFICIENCY, 2523 /// The ratio of ALU to texture instructions in the VS. This can be tuned appropriately to match the target hardware.When there are no texture instructions, it shows the number of ALU instructions. 2524 /// Apps built with SDK versions prior to 2.10.01 multiply the numerator by an additional 100.0f. 2525 /// ( GX2_STAT_SQ_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE[VS|ES] / 2526 /// GX2_STAT_SQ_TA_TEX_INSTRS_PER_TYPE[VS|ES] ) 2527 GX2_PERF_F32_VS_ALU_TEX_RATIO, 2528 // Number of bytes read from memory due to vertex cache miss. 2529 // Note: only 32-byte or 128-byte vertices are accepted by the runtime version 2530 // GX2_PERF_VS_VERTEX_MEM_FETCHED, 2531 /// Average number of texture instructions executed in GS. 2532 /// Affected by flow control. 2533 /// ( GX2_STAT_SQ_TA_TEX_INSTRS_PER_TYPE[GS] / 2534 /// GX2_STAT_SQ_THREADS_PER_TYPE[GS] ) 2535 GX2_PERF_F32_GS_TEX_INST_COUNT, 2536 /// The percentage of GPUTime texture instructions are being processed 2537 /// by the GS. 2538 /// ( GX2_STAT_SQ_TA_TEX_INSTRS_PER_TYPE[GS] / 2539 /// GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f * 8.0f 2540 GX2_PERF_F32_GS_TEX_BUSY, 2541 /// Average number of ALU instructions executed in the GS. 2542 /// Affected by flow control. 2543 /// ( GX2_STAT_SQ_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE[GS] / 2544 /// GX2_STAT_SQ_THREADS_PER_TYPE[GS] ) 2545 GX2_PERF_F32_GS_ALU_INST_COUNT, 2546 /// The percentage of GPUTime ALU instructions are being processed 2547 /// by the GS. 2548 /// ( GX2_STAT_SQ_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE[GS] / 2549 /// GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f * 2.0f 2550 GX2_PERF_F32_GS_ALU_BUSY, 2551 /// ALU vector packing efficiency. Values below 70 percent indicate that 2552 /// ALU dependency chains may be preventing full utilization of 2553 /// the processor. 2554 /// ( GX2_STAT_SQ_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE[GS] / 2555 /// GX2_STAT_SQ_ALU_CLAUSE_INSTRS_PER_TYPE[GS]] ) * 100.0f 2556 GX2_PERF_F32_GS_ALU_EFFICIENCY, 2557 /// The ratio of ALU to texture instructions in the GS. 2558 /// This can be tuned appropriately to match the target hardware. 2559 /// When there are no texture instructions, 2560 /// it shows the number of ALU instructions. 2561 /// Apps built with SDK versions prior to 2.10.01 multiply the numerator by an additional 100.0f. 2562 /// ( GX2_STAT_SQ_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE[GS] / 2563 /// GX2_STAT_SQ_TA_TEX_INSTRS_PER_TYPE[GS] ) 2564 GX2_PERF_F32_GS_ALU_TEX_RATIO, 2565 /// Percentage of GPUTime that clipping and culling is busy. 2566 /// TODO : not accurate calculation. Do not use this metric yet. 2567 /// ( GX2_STAT_PA_SU_CLIP_BUSY / GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f 2568 GX2_PERF_F32_PRIMITIVE_ASSEMBLY_BUSY, 2569 /// The number of primitives received by the hardware. 2570 /// ( GX2_STAT_VGT_VGT_PA_CLIPP_SEND - GX2_STAT_VGT_VGT_PA_CLIPP_IS_EVENT ) 2571 GX2_PERF_U64_PRIMITIVES_IN, 2572 // The number of culled primitives. Typical reasons include scissor, 2573 // the primitive having zero area, and back or front face culling. 2574 // GX2_PERF_CULLED_PRIMS, 2575 // The number of primitives that required one or more clipping operations 2576 // due to intersecting the view volume or user clip planes. 2577 // GX2_PERF_CLIPPED_PRIMS, 2578 /// Percentage of GPUTime that primitive assembly waits for rasterization 2579 /// to be ready to accept data. This roughly indicates for what percentage 2580 /// of time the pipeline is bottlenecked by pixel operations. 2581 /// ( GX2_STAT_PA_SU_SU_STALLED_SC / GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f 2582 GX2_PERF_F32_PA_STALLED_ON_RASTERIZER, 2583 /// Percentage of GPU time that the interpolator is busy. 2584 /// ( max (GX2_STAT_SPI_PCTL0_PI_BUSY, GX2_STAT_SPI_PCTL1_PI_BUSY) 2585 /// / GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f 2586 GX2_PERF_F32_INTERP_BUSY, 2587 /// The number of pixels processed by the PS. 2588 /// Does not count pixels culled by early Z or stencil tests. 2589 /// ( GX2_STAT_SQ_ITEMS_PER_TYPE[PS] ) 2590 GX2_PERF_U64_PS_PIXELS_IN, 2591 /// Average number of texture instructions executed in PS. Affected by flow control. 2592 /// ( GX2_STAT_SQ_TA_TEX_INSTRS_PER_TYPE[PS] / 2593 /// GX2_STAT_SQ_THREADS_PER_TYPE[PS] ) * 100.0f 2594 GX2_PERF_F32_PS_TEX_INST_COUNT, 2595 /// The percentage of GPUTime texture instructions are being processed by the PS. 2596 /// ( GX2_STAT_SQ_TA_TEX_INSTRS_PER_TYPE[PS] / 2597 /// GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f * 8.0f 2598 GX2_PERF_F32_PS_TEX_BUSY, 2599 /// Average number of ALU instructions executed in the PS. Affected by flow control. 2600 /// ( GX2_STAT_SQ_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE[PS] / 2601 /// GX2_STAT_SQ_THREADS_PER_TYPE[PS] ) 2602 GX2_PERF_F32_PS_ALU_INST_COUNT, 2603 /// The percentage of GPU time ALU instructions are processed by the PS. 2604 /// ( GX2_STAT_SQ_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE[PS] / 2605 /// GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f * 2.0f 2606 GX2_PERF_F32_PS_ALU_BUSY, 2607 /// ALU vector packing efficiency. Values below 70 percent indicate that ALU dependency chains may be preventing full utilization of the processor. 2608 /// ( GX2_STAT_SQ_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE[PS] / 2609 /// GX2_STAT_SQ_ALU_CLAUSE_INSTRS_PER_TYPE[PS]] ) * 100.0f 2610 GX2_PERF_F32_PS_ALU_EFFICIENCY, 2611 /// The ratio of ALU to texture instructions in the PS. This can be tuned appropriately to match the target hardware.When there are no texture instructions, it shows the number of ALU instructions. 4.0 is best balanced number. 2612 /// Apps built with SDK versions prior to 2.10.01 multiply the numerator by an additional 100.0f. 2613 /// ( GX2_STAT_SQ_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE[PS] / 2614 /// GX2_STAT_SQ_TA_TEX_INSTRS_PER_TYPE[PS] ) 2615 GX2_PERF_F32_PS_ALU_TEX_RATIO, 2616 /// Pixels exported from shader to colour buffers. Does not include killed 2617 /// or alpha tested pixels; if there are multiple rendertargets, 2618 /// each rendertarget receives one export, so this will be 2 for 1 pixel 2619 /// written to two RTs. 2620 /// ( GX2_STAT_SX_DB0_PIXELS + GX2_STAT_SX_DB1_PIXELS ) 2621 GX2_PERF_U64_PS_PIXELS_OUT, 2622 /// Percentage of GPUTime that PS output is stalled. 2623 /// Should be zero for PS or further upstream limited cases; 2624 /// if not zero, indicates a bottleneck in late z testing 2625 /// or in the colour buffer. 2626 /// ( max( GX2_STAT_SX_DB0_STALL_CYCLES, GX2_STAT_SX_DB1_STALL_CYCLES ) / 2627 /// GX2_STAT_GRBM_GUI_ACTIVE ) 2628 GX2_PERF_F32_PS_EXPORT_STALLS, 2629 /// Percentage of GPU time the texture unit is active. 2630 /// This is measured with all extra fetches and any cache or 2631 /// memory effects taken into account. 2632 /// ( (GX2_STAT_TA_ALIGNER_CYCLES + GX2_STAT_TCP_TCP_TA_STALL_CYCLES ) / 2633 /// GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f 2634 GX2_PERF_F32_TEX_UNIT_BUSY, 2635 /// The total number of texels and index/vertex data fetched. 2636 /// This includes all shader types and any extra fetches caused by 2637 /// trilinear filtering, anisotropic filtering, color formats, 2638 /// and volume textures. 2639 /// ( GX2_STAT_TA_ALIGNER_CYCLES ) * 4.0f 2640 GX2_PERF_U64_TEXEL_FETCH_COUNT, 2641 /// Percentage of GPU time the texture cache is stalled. 2642 /// Try reducing the number of textures or reducing the number of bits 2643 /// per pixel (that is, use compressed textures) if possible. 2644 /// ( GX2_STAT_TCP_TCP_TAGCONFLICT_STALL_CYCLES / 2645 /// GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f 2646 GX2_PERF_F32_TEX_CACHE_STALLED, 2647 /// Texture miss rate (bytes/texel). 2648 /// A normal value for mipmapped textures is approximately 2649 /// (texture_bpp / 4). For 1:1 mapping, it will be texture_bpp. 2650 /// ( GX2_STAT_TCC_REQS_TC_TF_MISS * 64.0 / 2651 /// GX2_STAT_TCP_TOTAL_PIXELS ) * 100.0f 2652 GX2_PERF_F32_TEX_MISS_RATE, 2653 /// Texture memory read in bytes. 2654 /// ( GX2_STAT_TCC_REQS_TC_TF_MISS * 64.0 ) 2655 GX2_PERF_U64_TEX_MEM_BYTES_READ, 2656 /// Percentage of GPU time spent performing depth and stencil tests. 2657 /// ( GX2_STAT_DB_OP_PIPE_BUSY / GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f 2658 GX2_PERF_F32_DEPTH_STENCIL_TEST_BUSY, 2659 /// Percentage of tiles that can be accepted by HiZ 2660 /// without doing per-pixel Z tests. 2661 /// ( (GX2_STAT_DB_DB_SC_TILE_NO_OPS + GX2_STAT_DB_DB_SC_TILE_PIXEL_RATE + GX2_STAT_DB_DB_SC_TILE_FAST_OPS) / GX2_STAT_DB_SC_DB_TILE_TILES) * 100.0f 2662 GX2_PERF_F32_HIZ_TRIVIAL_ACCEPT, 2663 /// Percentage of tiles that are rejected by HiZ. 2664 /// GX2_STAT_DB_DB_SC_TILE_HIER_KILL / GX2_STAT_DB_DB_SC_TILE_CULLED * 100.0f 2665 GX2_PERF_F32_HIZ_REJECT, 2666 /// Number of samples tested for Z before shading and passed. 2667 /// ( GX2_STAT_DB_PREZ_SAMPLES_PASSING_Z ) 2668 GX2_PERF_U64_PRE_Z_SAMPLES_PASSING, 2669 /// Number of samples tested for Z before shading and failed stencil test. 2670 /// ( GX2_STAT_DB_PREZ_SAMPLES_FAILING_S ) 2671 GX2_PERF_U64_PRE_Z_SAMPLES_FAILING_S, 2672 /// Number of samples tested for Z before shading and failed Z test. 2673 /// ( GX2_PERF_U64_PRE_Z_SAMPLES_FAILING_Z ) 2674 GX2_PERF_U64_PRE_Z_SAMPLES_FAILING_Z, 2675 /// Number of samples tested for Z after shading and passed. 2676 /// ( GX2_PERF_U64_POST_Z_SAMPLES_PASSING ) 2677 GX2_PERF_U64_POST_Z_SAMPLES_PASSING, 2678 /// Number of samples tested for Z after shading and failed stencil test. 2679 /// ( GX2_STAT_DB_POSTZ_SAMPLES_FAILING_S ) 2680 GX2_PERF_U64_POST_Z_SAMPLES_FAILING_S, 2681 /// Number of samples tested for Z after shading and failed Z test. 2682 /// ( GX2_PERF_U64_POST_Z_SAMPLES_FAILING_Z ) 2683 GX2_PERF_U64_POST_Z_SAMPLES_FAILING_Z, 2684 /// Percentage of GPUTime the depth buffer spends waiting for 2685 /// the color buffer to be ready to accept data. High figures here 2686 /// indicate a bottleneck in color buffer operations. 2687 /// ( GX2_STAT_DB_DB_CB_LQUAD_STALLS / GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f 2688 GX2_PERF_F32_Z_UNIT_STALLED, 2689 /// Number of pixels drawn into the color buffer. 2690 /// ( GX2_STAT_CB_DRAWN_PIXEL ) 2691 GX2_PERF_U64_PIXELS_AT_CB, 2692 /// Number of bytes written to the color buffer. 2693 /// ( GX2_STAT_CB_CC_MC_WRITE_REQUEST ) 2694 GX2_PERF_U64_PIXELS_CB_MEM_WRITTEN, 2695 /// The number of input assembler (IA, or fetch shader) vertices. 2696 GX2_PERF_U64_IA_VERTICES, 2697 /// The number of input assembler (IA, just after FS) primitives. 2698 GX2_PERF_U64_IA_PRIMITIVES, 2699 /// The number of vertex shader (VS) invocations. 2700 /// This may be less than GX2_PERF_U64_IA_VERTICES if the index buffer reuses vertices. 2701 GX2_PERF_U64_VS_INVOCATIONS, 2702 /// The number of geometry shader (GS) invocations. 2703 GX2_PERF_U64_GS_INVOCATIONS, 2704 /// The number of geometry shader (GS) primitives. 2705 GX2_PERF_U64_GS_PRIMITIVES, 2706 /// The number of clipper invocations. 2707 GX2_PERF_U64_C_INVOCATIONS, 2708 /// The number of clipped primitives rendered. This may be larger or smaller than clipper invocations(C_INVOCATIONS) or 2709 /// GX2_PERF_U64_IA_PRIMITIVES because after a primitive is clipped sometimes it is either broken up into more than one 2710 /// primitive or completely culled. 2711 GX2_PERF_U64_C_PRIMITIVES, 2712 /// The number of pixel shader (PS) invocations. 2713 GX2_PERF_U64_PS_INVOCATIONS, 2714 /// Number of Primitives input to PA 2715 GX2_PERF_U64_PA_INPUT_PRIM, 2716 GX2_PERF_LAST = GX2_PERF_U64_PA_INPUT_PRIM, 2717 GX2_PERF_FIRST = 0x0 2718 } GX2PerfMetric; 2719 2720 /// \brief Collection Method 2721 /// 2722 typedef enum _GX2PerfCollectionMethod { 2723 GX2_PERF_COLLECT_NONE, ///< turn off collection, minimize API run-time effect 2724 GX2_PERF_COLLECT_TAGS_ACCUMULATE, ///< collect accumulated results of all enabled tags in a pass 2725 GX2_PERF_COLLECT_TAGS_INDIVIDUAL ///< collect results at each tag start/end occurrence 2726 } GX2PerfCollectionMethod; 2727 2728 /// \brief Type of perf metric/stat 2729 /// 2730 typedef enum _GX2PerfType { 2731 GX2_PERF_TYPE_GPU_METRIC, ///< high-level GPU metric 2732 GX2_PERF_TYPE_GPU_STAT, ///< low-level GPU stat 2733 GX2_PERF_TYPE_MEM_STAT ///< MEM stat 2734 } GX2PerfType; 2735 2736 /// @} 2737 2738 #ifdef __cplusplus 2739 } 2740 #endif // __cplusplus 2741 2742 #endif // _CAFE_GX2_ENUM_H_ 2743