1 /*---------------------------------------------------------------------------* 2 Project: Architecture level definitions 3 File: PPCArch.h 4 Programmers: Tian 5 OKASAKA, Shiki 6 HIROSE KAZUKI 7 HIRATSU Daisuke 8 9 Copyright 1998-2006 Nintendo. All rights reserved. 10 11 These coded instructions, statements, and computer programs contain 12 proprietary information of Nintendo of America Inc. and/or Nintendo 13 Company Ltd., and are protected by Federal copyright law. They may 14 not be disclosed to third parties or copied or duplicated in any form, 15 in whole or in part, without the prior written consent of Nintendo. 16 17 $Log: PPCArch.h,v $ 18 Revision 1.4 2006/02/04 11:56:45 hashida 19 (none) 20 21 Revision 1.3 02/01/2006 04:49:40 hirose 22 Added definition for new BAT registers. 23 24 25 15 8/27/02 8:51 Shiki 26 Defined FPSCR_*_BIT. 27 28 14 8/19/02 21:43 Shiki 29 Fixed FPSCR_VXIDI define names. 30 31 13 6/05/02 11:33 Shiki 32 Added FPSCR bit define names. 33 34 12 02/03/25 13:22 Hirose 35 Added SPD/IEEE Fp mode control functions. 36 37 11 11/05/01 14:23 Shiki 38 Added PPCMffpscr() and PPCMtfpscr(). 39 40 10 6/01/01 5:03p Tian 41 Removed PMC counter options that are not supported by GEKKO. 42 43 9 11/28/00 7:29p Tian 44 Added PPCMfpvr 45 46 8 11/01/00 3:43p Shiki 47 Fixed #ifdef around L2CR bit define names. 48 49 7 12/15/99 3:48p Tian 50 Fixed error in Gekko SRR1 bits 51 52 6 12/02/99 7:44p Tian 53 Additional SRR1 fields 54 55 5 11/29/99 6:14p Tian 56 HID_G -> HID2 57 58 4 11/29/99 2:31p Tian 59 Added HID2 alias for HID_G per Gekko user manual. 60 61 3 11/24/99 5:27p Shiki 62 Updated PMCn event defines according to "MPC750_Errata.pdf". 63 64 2 11/23/99 5:46p Tian 65 Added basic Gekko register information and accessors. 66 67 11 9/09/99 1:07p Tian 68 Added PPCAndCMsr 69 70 10 8/24/99 1:58p Shiki 71 Fixed PMCn bits. 72 73 9 8/23/99 5:03p Shiki 74 Added SPR defs. 75 76 8 99/07/26 8:52p Shiki 77 Fixed spelling. 78 79 7 99/07/26 8:43p Shiki 80 Added performance monitor SPR bit definitions. 81 82 6 99/07/26 4:42p Shiki 83 Added L2CR_ prefixes for L2CR bit definitions. 84 85 5 99/07/22 6:28p Shiki 86 Added four HID0_*_BIT definitions. 87 Added performance monitor SPR access functions. 88 89 4 99/07/13 9:32p Shiki 90 Added MSR_*_BIT definitions. 91 92 3 5/11/99 4:42p Shiki 93 Refreshed include tree. 94 95 1 4/30/99 12:49p Tianli01 96 97 2 4/23/99 5:30p Tianli01 98 Fixed include 99 100 1 4/13/99 3:33p Tianli01 101 Minor mods. Moved to base. 102 103 2 4/13/99 3:27p Tianli01 104 Minor mods. Moved to base. 105 106 1 4/12/99 7:47p Tianli01 107 Low level PPC architecture definitions and accessories. 108 109 $NoKeywords: $ 110 *---------------------------------------------------------------------------*/ 111 112 #ifndef __PPCARCH_H__ 113 #define __PPCARCH_H__ 114 115 #ifndef EPPC 116 #define EPPC // embedded PowerPC 117 #endif // EPPC 118 119 #ifdef __cplusplus 120 extern "C" { 121 #endif 122 123 #include <revolution/types.h> 124 125 /*---------------------------------------------------------------------------* 126 SPR 127 *---------------------------------------------------------------------------*/ 128 129 #define CTR 9 130 #define XER 1 131 #define LR 8 132 133 #define UPMC1 937 134 #define UPMC2 938 135 #define UPMC3 941 136 #define UPMC4 942 137 138 #define USIA 939 139 140 #define UMMCR0 936 141 #define UMMCR1 940 142 143 #define HID0 1008 144 #define HID1 1009 145 146 #define PVR 287 147 148 #define IBAT0U 528 149 #define IBAT0L 529 150 #define IBAT1U 530 151 #define IBAT1L 531 152 #define IBAT2U 532 153 #define IBAT2L 533 154 #define IBAT3U 534 155 #define IBAT3L 535 156 157 #define DBAT0U 536 158 #define DBAT0L 537 159 #define DBAT1U 538 160 #define DBAT1L 539 161 #define DBAT2U 540 162 #define DBAT2L 541 163 #define DBAT3U 542 164 #define DBAT3L 543 165 166 #define SDR1 25 167 168 #define SPRG0 272 169 #define SPRG1 273 170 #define SPRG2 274 171 #define SPRG3 275 172 173 #define DAR 19 174 #define DSISR 18 175 176 #define SRR0 26 177 #define SRR1 27 178 179 #define EAR 282 180 181 #define DABR 1013 182 183 #define TBL 284 184 #define TBU 285 185 186 #define L2CR 1017 187 188 #define DEC 22 189 190 #define IABR 1010 191 192 #define PMC1 953 193 #define PMC2 954 194 #define PMC3 957 195 #define PMC4 958 196 197 #define SIA 955 198 199 #define MMCR0 952 200 #define MMCR1 956 201 202 #define THRM1 1020 203 #define THRM2 1021 204 #define THRM3 1022 205 206 #define ICTC 1019 207 208 #ifdef GEKKO 209 // GEKKO Registers 210 #define GQR0 912 211 #define GQR1 913 212 #define GQR2 914 213 #define GQR3 915 214 #define GQR4 916 215 #define GQR5 917 216 #define GQR6 918 217 #define GQR7 919 218 219 #define HID2 920 220 221 #define WPAR 921 222 223 #define DMA_U 922 224 #define DMA_L 923 225 // end of GEKKO Registers 226 #endif 227 228 #ifdef BROADWAY_REV 229 // Broadway additional Registers 230 #define IBAT4U 560 231 #define IBAT4L 561 232 #define IBAT5U 562 233 #define IBAT5L 563 234 #define IBAT6U 564 235 #define IBAT6L 565 236 #define IBAT7U 566 237 #define IBAT7L 567 238 239 #define DBAT4U 568 240 #define DBAT4L 569 241 #define DBAT5U 570 242 #define DBAT5L 571 243 #define DBAT6U 572 244 #define DBAT6L 573 245 #define DBAT7U 574 246 #define DBAT7L 575 247 // end of Broadway Registers 248 #endif // BROADWAY_REV 249 250 /*---------------------------------------------------------------------------* 251 MSR bits 252 *---------------------------------------------------------------------------*/ 253 #define MSR_POW 0x00040000 // Power Management 254 #define MSR_ILE 0x00010000 // Interrupt Little Endian 255 #define MSR_EE 0x00008000 // external interrupt 256 #define MSR_PR 0x00004000 // privilege level(should be 0) 257 #define MSR_FP 0x00002000 // floating point available 258 #define MSR_ME 0x00001000 // machine check enable 259 #define MSR_FE0 0x00000800 // floating point exception enable 260 #define MSR_SE 0x00000400 // single step trace enable 261 #define MSR_BE 0x00000200 // branch trace enable 262 #define MSR_FE1 0x00000100 // floating point exception enable 263 #define MSR_IP 0x00000040 // Exception prefix 264 #define MSR_IR 0x00000020 // instruction relocate 265 #define MSR_DR 0x00000010 // data relocate 266 #define MSR_PM 0x00000004 // Performance monitor marked mode 267 #define MSR_RI 0x00000002 // Recoverable interrupt 268 #define MSR_LE 0x00000001 // Little Endian 269 270 #define MSR_POW_BIT 13 // Power Management 271 #define MSR_ILE_BIT 15 // Interrupt Little Endian 272 #define MSR_EE_BIT 16 // external interrupt 273 #define MSR_PR_BIT 17 // privilege level(should be 0) 274 #define MSR_FP_BIT 18 // floating point available 275 #define MSR_ME_BIT 19 // machine check enable 276 #define MSR_FE0_BIT 20 // floating point exception enable 277 #define MSR_SE_BIT 21 // single step trace enable 278 #define MSR_BE_BIT 22 // branch trace enable 279 #define MSR_FE1_BIT 23 // floating point exception enable 280 #define MSR_IP_BIT 25 // Exception prefix 281 #define MSR_IR_BIT 26 // instruction relocate 282 #define MSR_DR_BIT 27 // data relocate 283 #define MSR_PM_BIT 29 // Performance monitor marked mode 284 #define MSR_RI_BIT 30 // Recoverable interrupt 285 #define MSR_LE_BIT 31 // Little Endian 286 287 /*---------------------------------------------------------------------------* 288 HID0 bits 289 *---------------------------------------------------------------------------*/ 290 #define HID0_EMCP 0x80000000 // Enable MCP 291 #define HID0_DBP 0x40000000 // Enable 60x bus address and data parity check 292 #define HID0_EBA 0x20000000 // Enable 60x address parity checking 293 #define HID0_EBD 0x10000000 // Enable 60x data parity checking 294 #define HID0_BCLK 0x08000000 // CLK_OUT output enable and clk selection 295 #define HID0_ECLK 0x02000000 // CLK_OUT output enable and clk selection 296 #define HID0_PAR 0x01000000 // Disable !ARTRY precharge 297 #define HID0_DOZE 0x00800000 // Doze mode enable 298 #define HID0_NAP 0x00400000 // Nap mode enable 299 #define HID0_SLEEP 0x00200000 // Sleep mode enable 300 #define HID0_DPM 0x00100000 // Dynamic power management enable 301 #define HID0_NHR 0x00010000 // Not hard reset (0 hard reset if s/w set it) 302 #define HID0_ICE 0x00008000 // Instruction cache enable 303 #define HID0_DCE 0x00004000 // Data cache enable 304 #define HID0_ILOCK 0x00002000 // ICache lock 305 #define HID0_DLOCK 0x00001000 // DCache lock 306 #define HID0_ICFI 0x00000800 // ICache flash invalidate 307 #define HID0_DCFI 0x00000400 // DCache flash invalidate 308 #define HID0_SPD 0x00000200 // Speculative cache access enable (0 enable) 309 #define HID0_IFEM 0x00000100 // Enable M bit on bus for Ifetch 310 #define HID0_SGE 0x00000080 // Store gathering enable 311 #define HID0_DCFA 0x00000040 // DCache flush assist - set before a flush 312 #define HID0_BTIC 0x00000020 // Branch target icache enable 313 #define HID0_ABE 0x00000008 // Address bcast enable 314 #define HID0_BHT 0x00000004 // Branch history table enable 315 #define HID0_NOOPTI 0x00000001 // No-op Dcache touch instructions 316 317 #define HID0_ICE_BIT 16 // Instruction cache enable 318 #define HID0_DCE_BIT 17 // Data cache enable 319 #define HID0_ILOCK_BIT 18 // ICache lock 320 #define HID0_DLOCK_BIT 19 // DCache lock 321 322 /*---------------------------------------------------------------------------* 323 HID2 bits. GEKKO ONLY 324 *---------------------------------------------------------------------------*/ 325 #ifdef GEKKO 326 #define HID2_LSQE 0x80000000 // L/S quantize enable 327 #define HID2_WPE 0x40000000 // Write pipe enable 328 #define HID2_PSE 0x20000000 // Paired single enable 329 #define HID2_LCE 0x10000000 // Locked cache enable 330 331 #define HID2_DCHERR 0x00800000 // ERROR: dcbz_l cache hit 332 #define HID2_DNCERR 0x00400000 // ERROR: DMA access to normal cache 333 #define HID2_DCMERR 0x00200000 // ERROR: DMA cache miss error 334 #define HID2_DQOERR 0x00100000 // ERROR: DMA queue overflow 335 #define HID2_DCHEE 0x00080000 // dcbz_l cache hit error enable 336 #define HID2_DNCEE 0x00040000 // DMA access to normal cache error enable 337 #define HID2_DCMEE 0x00020000 // DMA cache miss error error enable 338 #define HID2_DQOEE 0x00010000 // DMA queue overflow error enable 339 340 #define HID2_DMAQL_MASK 0x0F000000 // DMA queue length mask 341 #define HID2_DMAQL_SHIFT 24 // DMA queue shift 342 343 #define HID2_LSQE_BIT 0 344 #define HID2_WPE_BIT 1 345 #define HID2_PSE_BIT 2 346 #define HID2_LCE_BIT 3 347 348 #define HID2_DCHERR_BIT 8 349 #define HID2_DNCERR_BIT 9 350 #define HID2_DCMERR_BIT 10 351 #define HID2_DQOERR_BIT 11 352 #define HID2_DCHEE_BIT 12 353 #define HID2_DNCEE_BIT 13 354 #define HID2_DCMEE_BIT 14 355 #define HID2_DQOEE_BIT 15 356 357 358 #endif // GEKKO 359 360 /*---------------------------------------------------------------------------* 361 GQR fields. GEKKO ONLY 362 *---------------------------------------------------------------------------*/ 363 #ifdef GEKKO 364 #define GQR_LOAD_SCALE_MASK 0x3F000000 // load scale field 365 #define GQR_LOAD_TYPE_MASK 0x00070000 // load type field 366 #define GQR_STORE_SCALE_MASK 0x00003F00 // store scale field 367 #define GQR_STORE_TYPE_MASK 0x00000007 // store type field 368 369 typedef struct 370 { 371 u32 _pad0 :2; 372 u32 loadScale :6; 373 u32 _pad1 :5; 374 u32 loadType :3; 375 u32 _pad2 :2; 376 u32 storeScale :6; 377 u32 _pad3 :5; 378 u32 storeType :3; 379 } PPC_GQR_t; 380 381 typedef union 382 { 383 u32 val; 384 PPC_GQR_t f; 385 } PPC_GQR_u; 386 387 388 #endif // GEKKO 389 390 /*---------------------------------------------------------------------------* 391 DMA fields 392 *---------------------------------------------------------------------------*/ 393 #ifdef GEKKO 394 #define DMA_U_ADDR_MASK 0xFFFFFFE0 // Start addr in memory 395 #define DMA_U_LEN_U_MASK 0x0000001F // lines to transfer (U) 396 397 #define DMA_L_LC_ADDR_MASK 0xFFFFFFE0 // Start addr in LC 398 #define DMA_L_LOAD 0x00000010 // 0 - store, 1 - load 399 #define DMA_L_STORE 0x00000000 // 0 - store, 1 - load 400 #define DMA_L_LEN_MASK 0x0000000C // lines to transfer (L) 401 #define DMA_L_TRIGGER 0x00000002 // 0 - cmd inactive, 1 - cmd rdy 402 #define DMA_L_FLUSH 0x00000001 // 1 - Flush DMA queue 403 404 typedef struct 405 { 406 u32 memAddr :27; 407 u32 dmaLenU :5; 408 } PPC_DMA_U_t; 409 410 typedef union 411 { 412 u32 val; 413 PPC_DMA_U_t f; 414 } PPC_DMA_U_u; 415 416 417 typedef struct 418 { 419 u32 lcAddr :27; 420 u32 dmaLd :1; 421 u32 dmaLenL :2; 422 u32 dmaTrigger :1; 423 u32 dmaFlush :1; 424 } PPC_DMA_L_t; 425 426 427 typedef union 428 { 429 u32 val; 430 PPC_DMA_L_t f; 431 } PPC_DMA_L_u; 432 433 434 435 #endif // GEKKO 436 437 /*---------------------------------------------------------------------------* 438 WPAR fields 439 *---------------------------------------------------------------------------*/ 440 #ifdef GEKKO 441 #define WPAR_ADDR 0xFFFFFFE0 // 32byte gather address 442 #define WPAR_BNE 0x00000001 // Buffer not empty (R) 443 #endif // GEKKO 444 445 /*---------------------------------------------------------------------------* 446 Additional SRR1 fields 447 *---------------------------------------------------------------------------*/ 448 #ifdef GEKKO 449 #define SRR1_DMA_BIT 0x00200000 450 #define SRR1_L2DP_BIT 0x00100000 451 #endif // GEKKO 452 453 /*---------------------------------------------------------------------------* 454 L2CR bits 455 *---------------------------------------------------------------------------*/ 456 457 #ifndef GEKKO // i.e. 750 (ARTHUR) 458 459 #define L2CR_L2E 0x80000000 // L2 Enable 460 #define L2CR_L2PE 0x40000000 // L2 data parity generation and checking enable 461 462 #define L2CR_L2SIZ_256K 0x10000000 // L2 size 256K 463 #define L2CR_L2SIZ_512K 0x20000000 // L2 size 512 464 #define L2CR_L2SIZ_1M 0x30000000 // L2 size 1M 465 466 #define L2CR_L2CLK_1_0 0x02000000 // L2 clock ratio 1 467 #define L2CR_L2CLK_1_5 0x04000000 // L2 clock ratio 1.5 468 #define L2CR_L2CLK_2_0 0x08000000 // L2 clock ratio 2 469 #define L2CR_L2CLK_2_5 0x0A000000 // L2 clock ratio 2.5 470 #define L2CR_L2CLK_3_0 0x0C000000 // L2 clock ratio 3 471 472 #define L2CR_RAM_FLOW_THRU_BURST 0x00000000 // L2 RAM type flow-through sync. burst SRAM 473 #define L2CR_RAM_PIPELINE_BURST 0x01000000 // L2 RAM type pipelined sync. burst SRAM 474 #define L2CR_RAM_PIPELINE_LATE 0x01800000 // L2 RAM type pipelined sync. late-write SRAM 475 476 #define L2CR_L2DO 0x00400000 // Data only 477 #define L2CR_L2I 0x00200000 // Global invalidate 478 #define L2CR_L2CTL 0x00100000 // ZZ enable 479 #define L2CR_L2WT 0x00080000 // L2 write through 480 #define L2CR_L2TS 0x00040000 // L2 test support 481 482 #define L2CR_L2OH_0_5 0x00000000 // L2 output hold 0.5 ns 483 #define L2CR_L2OH_1_0 0x00010000 // L2 output hold 1.0 ns 484 485 #define L2CR_L2SL 0x00008000 // L2 DLL slow 486 #define L2CR_L2DF 0x00004000 // L2 differential clock 487 #define L2CR_L2BYP 0x00002000 // L2 DLL bypass 488 #define L2CR_L2CS 0x00000200 // L2 clock stop 489 #define L2CR_L2DRO 0x00000100 // L2 DLL rollover checkstop enable 490 #define L2CR_L2CTR_MASK 0x000000FE // L2 counter value mask 491 #define L2CR_L2IP 0x00000001 // L2 global invalidate in progress 492 493 #else // GEKKO 494 495 #define L2CR_L2E 0x80000000 // L2 Enable 496 #define L2CR_L2CE 0x40000000 // L2 checkstop enable 497 #define L2CR_L2DO 0x00400000 // Data only 498 #define L2CR_L2I 0x00200000 // Global invalidate 499 #define L2CR_L2WT 0x00080000 // L2 write through 500 #define L2CR_L2TS 0x00040000 // L2 test support 501 #define L2CR_L2IP 0x00000001 // L2 global invalidate in progress 502 503 #endif // GEKKO 504 505 /*---------------------------------------------------------------------------* 506 MMCR0 bits 507 *---------------------------------------------------------------------------*/ 508 #define MMCR0_DIS 0x80000000 // Disables counting unconditionally 509 #define MMCR0_DP 0x40000000 // Disables counting while in supervisor mode 510 #define MMCR0_DU 0x20000000 // Disables counting while in user mode 511 #define MMCR0_DMS 0x10000000 // Disables counting while MSR[PM] is set 512 #define MMCR0_DMR 0x08000000 // Disables counting while MSR[PM] is zero 513 #define MMCR0_ENINT 0x04000000 // Enables performance monitor interrupt signaling 514 #define MMCR0_DISCOUNT 0x02000000 // Disables counting of PMCn when a performance monitor interrupt is signaled or... 515 #define MMCR0_RTCSELECT_MASK 0x01800000 // 64-bit time base, bit selection enable 516 #define MMCR0_RTCSELECT_63 0x00000000 // Pick bit 63 to count 517 #define MMCR0_RTCSELECT_55 0x00800000 // Pick bit 55 to count 518 #define MMCR0_RTCSELECT_51 0x01000000 // Pick bit 51 to count 519 #define MMCR0_RTCSELECT_47 0x01800000 // Pick bit 47 to count 520 #define MMCR0_INTONBITTRANS 0x00400000 // Causes interrupt signaling on bit transition from off to on 521 #define MMCR0_THRESHOLD_MASK 0x003F0000 // Threshold value 522 #define MMCR0_THRESHOLD(n) ((n) << 16) // Threshold value (0 - 63) 523 #define MMCR0_PMC1INTCONTROL 0x00008000 // Enables interrupt signaling due to PMC1 counter overflow 524 #define MMCR0_PMC2INTCONTROL 0x00004000 // Enables interrupt signaling due to PMC2-PMC4 counter overflow 525 #define MMCR0_PMCTRIGGER 0x00002000 // Can be used to trigger counting of PMC2-PMC4 after PMC1 has overflowed or... 526 #define MMCR0_PMC1SELECT_MASK 0x00001FC0 // PMC1 input selector 527 #define MMCR0_PMC2SELECT_MASK 0x0000003F // PMC2 input selector 528 529 /*---------------------------------------------------------------------------* 530 MMCR1 bits 531 *---------------------------------------------------------------------------*/ 532 #define MMCR1_PMC3SELECT_MASK 0xF8000000 // PMC3 input selector 533 #define MMCR1_PMC4SELECT_MASK 0x07C00000 // PMC4 input selector 534 535 /*---------------------------------------------------------------------------* 536 PMCn bits 537 *---------------------------------------------------------------------------*/ 538 #define PMC1_OV 0x80000000 // Overflow 539 #define PMC1_COUNTER 0x7FFFFFFF // Counter value 540 #define PMC2_OV 0x80000000 // Overflow 541 #define PMC2_COUNTER 0x7FFFFFFF // Counter value 542 #define PMC3_OV 0x80000000 // Overflow 543 #define PMC3_COUNTER 0x7FFFFFFF // Counter value 544 #define PMC4_OV 0x80000000 // Overflow 545 #define PMC4_COUNTER 0x7FFFFFFF // Counter value 546 547 /*---------------------------------------------------------------------------* 548 PMC1 Events 549 *---------------------------------------------------------------------------*/ 550 #define MMCR0_PMC1_HOLD 0x00000000 // Register holds current value 551 #define MMCR0_PMC1_CYCLE 0x00000040 // Processor cycles 552 #define MMCR0_PMC1_INSTRUCTION 0x00000080 // # of instructions completed. 553 #define MMCR0_PMC1_TRANSITION 0x000000C0 // # of transitions for 0 to 1 554 #define MMCR0_PMC1_DISPATCHED 0x00000100 // # of instructions dispatched 555 #define MMCR0_PMC1_EIEIO 0x00000140 // # of eieio instructions completed 556 #define MMCR0_PMC1_ITLB_CYCLE 0x00000180 // # of cycles spent performing table search op. for the ITLB 557 #define MMCR0_PMC1_L2_HIT 0x000001C0 // # of access that hit the L2. 558 #define MMCR0_PMC1_EA 0x00000200 // # of valid instruction EAs delivered to the memory subsystem 559 #define MMCR0_PMC1_IABR 0x00000240 // # of time the address of an instruction matches the IABR 560 #define MMCR0_PMC1_L1_MISS 0x00000280 // # of loads that miss the L1 561 #define MMCR0_PMC1_Bx_UNRESOLVED 0x000002C0 // # of branches that are unresolved when processed 562 #define MMCR0_PMC1_Bx_STALL_CYCLE 0x00000300 // # of cycles that dispatcher stalls due to a second 563 // unresolved branch in the instruction stream 564 #ifndef GEKKO 565 #define MMCR0_PMC1_IC_FETCH_MISS 0x00000340 // # of times an instruction fetch missed the L1 Icache 566 #endif 567 /*---------------------------------------------------------------------------* 568 PMC2 Events 569 *---------------------------------------------------------------------------*/ 570 #define MMCR0_PMC2_HOLD 0x00000000 // Register holds current value 571 #define MMCR0_PMC2_CYCLE 0x00000001 // Processor cycles 572 #define MMCR0_PMC2_INSTRUCTION 0x00000002 // # of instructions completed 573 #define MMCR0_PMC2_TRANSITION 0x00000003 // # of time-base (lower) bit transitions 574 #define MMCR0_PMC2_DISPATCHED 0x00000004 // # of instructions dispatched 575 #define MMCR0_PMC2_IC_MISS 0x00000005 // # of L1 instruction cache misses 576 #define MMCR0_PMC2_ITLB_MISS 0x00000006 // # of ITLB misses 577 #define MMCR0_PMC2_L2_I_MISS 0x00000007 // # of L2 instruction misses 578 #define MMCR0_PMC2_Bx_FALL_TROUGH 0x00000008 // # of fall-through branches 579 #ifndef GEKKO 580 #define MMCR0_PMC2_PR_SWITCH 0x00000009 // # of MSR[PR] bit toggles 581 #endif 582 #define MMCR0_PMC2_RESERVED_LOAD 0x0000000A // # of reserved loads completed 583 #define MMCR0_PMC2_LOAD_STORE 0x0000000B // # of completed loads and stores 584 #define MMCR0_PMC2_SNOOP 0x0000000C // # of snoops 585 #define MMCR0_PMC2_L1_CASTOUT 0x0000000D // # of L1 castouts to L2 586 #define MMCR0_PMC2_SYSTEM 0x0000000E // # of completed system unit instructions 587 #define MMCR0_PMC2_IC_FETCH_MISS 0x0000000F // # of instruction fetch misses in the L1 588 #define MMCR0_PMC2_Bx_OUT_OF_ORDER 0x00000010 // # of branches allowing out-of-order execution 589 590 /*---------------------------------------------------------------------------* 591 PMC3 Events 592 *---------------------------------------------------------------------------*/ 593 #define MMCR1_PMC3_HOLD 0x00000000 // Register holds current value 594 #define MMCR1_PMC3_CYCLE 0x08000000 // Processor cycles 595 #define MMCR1_PMC3_INSTRUCTION 0x10000000 // # of instructions completed 596 #define MMCR1_PMC3_TRANSITION 0x18000000 // # of time-base (lower) bit transitions 597 #define MMCR1_PMC3_DISPATCHED 0x20000000 // # of instructions dispatched 598 #define MMCR1_PMC3_DC_MISS 0x28000000 // # of L1 data cache misses 599 #define MMCR1_PMC3_DTLB_MISS 0x30000000 // # of DTLB misses 600 #define MMCR1_PMC3_L2_D_MISS 0x38000000 // # of L2 data misses 601 #define MMCR1_PMC3_Bx_TAKEN 0x40000000 // # predicted branches that were taken 602 #ifndef GEKKO 603 #define MMCR1_PMC3_PM_SWITCH 0x48000000 // # of transitions between marked and unmarked processes 604 #endif 605 #define MMCR1_PMC3_COND_STORE 0x50000000 // # of store conditional instructions completed 606 #define MMCR1_PMC3_FPU 0x58000000 // # of instructions completed from the FPU 607 #define MMCR1_PMC3_L2_SNOOP_CASTOUT 0x60000000 // # of L2 castouts caused by snoops to modified lines 608 #define MMCR1_PMC3_L2_HIT 0x68000000 // # of cache operations that hit in the L2 cache 609 #define MMCR1_PMC3_L1_MISS_CYCLE 0x78000000 // # of cycles generated by L1 load misses 610 #define MMCR1_PMC3_Bx_SECOND 0x80000000 // # of branches in the second speculative branch 611 // resolved correctly 612 #define MMCR1_PMC3_BPU_LR_CR 0x88000000 // # of cycles the BPU stalls due to LR or CR unresolved 613 // dependencies 614 615 /*---------------------------------------------------------------------------* 616 PMC4 Events 617 *---------------------------------------------------------------------------*/ 618 #define MMCR1_PMC4_HOLD 0x00000000 // Register holds current value 619 #define MMCR1_PMC4_CYCLE 0x00400000 // Processor cycles 620 #define MMCR1_PMC4_INSTRUCTION 0x00800000 // # of instructions completed 621 #define MMCR1_PMC4_TRANSITION 0x00C00000 // # of time-base (lower) bit transitions 622 #define MMCR1_PMC4_DISPATCHED 0x01000000 // # of instructions dispatched 623 #define MMCR1_PMC4_L2_CASTOUT 0x01400000 // # of L2 castouts 624 #define MMCR1_PMC4_DTLB_CYCLE 0x01800000 // # of cycles spent performing table searches for DTLB accesses 625 #define MMCR1_PMC4_Bx_MISSED 0x02000000 // # of mispredicted branches 626 #define MMCR1_PMC4_COND_STORE_INT 0x02800000 // # of store conditional instructions completed 627 // with reservation intact 628 #define MMCR1_PMC4_SYNC 0x02C00000 // # of completed sync instructions 629 #define MMCR1_PMC4_SNOOP_RETRY 0x03000000 // # of snoop request retries 630 #define MMCR1_PMC4_INTEGER 0x03400000 // # of completed integer operations 631 #define MMCR1_PMC4_BPU_THIRD 0x03800000 // # of cycles the BPU cannot process new branches 632 // due to having two unresolved branches 633 #ifndef GEKKO 634 #define MMCR1_PMC4_DC_MISS 0x07C00000 // # of L1 data cache misses 635 #endif 636 637 /*---------------------------------------------------------------------------* 638 FPSCR bits 639 *---------------------------------------------------------------------------*/ 640 #ifndef FPSCR_FX 641 #define FPSCR_FX 0x80000000 // Exception summary 642 #define FPSCR_FEX 0x40000000 // Enabled exception summary 643 #define FPSCR_VX 0x20000000 // Invalid operation 644 #define FPSCR_OX 0x10000000 // Overflow exception 645 #define FPSCR_UX 0x08000000 // Underflow exception 646 #define FPSCR_ZX 0x04000000 // Zero divide exception 647 #define FPSCR_XX 0x02000000 // Inexact exception 648 #define FPSCR_VXSNAN 0x01000000 // SNaN 649 #define FPSCR_VXISI 0x00800000 // Infinity - Infinity 650 #define FPSCR_VXIDI 0x00400000 // Infinity / Infinity 651 #define FPSCR_VXZDZ 0x00200000 // 0 / 0 652 #define FPSCR_VXIMZ 0x00100000 // Infinity * 0 653 #define FPSCR_VXVC 0x00080000 // Invalid compare 654 #define FPSCR_FR 0x00040000 // Fraction rounded 655 #define FPSCR_FI 0x00020000 // Fraction inexact 656 #define FPSCR_VXSOFT 0x00000400 // Software request 657 #define FPSCR_VXSQRT 0x00000200 // Invalid square root 658 #define FPSCR_VXCVI 0x00000100 // Invalid integer convert 659 #define FPSCR_VE 0x00000080 // Invalid operation exception enable 660 #define FPSCR_OE 0x00000040 // Overflow exception enable 661 #define FPSCR_UE 0x00000020 // Underflow exception enable 662 #define FPSCR_ZE 0x00000010 // Zero divide exception enable 663 #define FPSCR_XE 0x00000008 // Inexact exception enable 664 #define FPSCR_NI 0x00000004 // Non-IEEE mode 665 #endif 666 667 #ifndef FPSCR_FX_BIT 668 #define FPSCR_FX_BIT 0 // Exception summary 669 #define FPSCR_FEX_BIT 1 // Enabled exception summary 670 #define FPSCR_VX_BIT 2 // Invalid operation 671 #define FPSCR_OX_BIT 3 // Overflow exception 672 #define FPSCR_UX_BIT 4 // Underflow exception 673 #define FPSCR_ZX_BIT 5 // Zero divide exception 674 #define FPSCR_XX_BIT 6 // Inexact exception 675 #define FPSCR_VXSNAN_BIT 7 // SNaN 676 #define FPSCR_VXISI_BIT 8 // Infinity - Infinity 677 #define FPSCR_VXIDI_BIT 9 // Infinity / Infinity 678 #define FPSCR_VXZDZ_BIT 10 // 0 / 0 679 #define FPSCR_VXIMZ_BIT 11 // Infinity * 0 680 #define FPSCR_VXVC_BIT 12 // Invalid compare 681 #define FPSCR_FR_BIT 13 // Fraction rounded 682 #define FPSCR_FI_BIT 14 // Fraction inexact 683 #define FPSCR_VXSOFT_BIT 21 // Software request 684 #define FPSCR_VXSQRT_BIT 22 // Invalid square root 685 #define FPSCR_VXCVI_BIT 23 // Invalid integer convert 686 #define FPSCR_VE_BIT 24 // Invalid operation exception enable 687 #define FPSCR_OE_BIT 25 // Overflow exception enable 688 #define FPSCR_UE_BIT 26 // Underflow exception enable 689 #define FPSCR_ZE_BIT 27 // Zero divide exception enable 690 #define FPSCR_XE_BIT 28 // Inexact exception enable 691 #define FPSCR_NI_BIT 29 // Non-IEEE mode 692 #endif 693 694 /*---------------------------------------------------------------------------* 695 PPC instructions 696 *---------------------------------------------------------------------------*/ 697 u32 PPCMfmsr ( void ); 698 void PPCMtmsr ( u32 newMSR ); 699 u32 PPCOrMsr ( u32 value ); 700 u32 PPCAndMsr ( u32 value ); 701 u32 PPCAndCMsr( u32 value ); 702 703 u32 PPCMfhid0 ( void ); 704 void PPCMthid0 ( u32 newHID0 ); 705 706 u32 PPCMfhid1 ( void ); 707 708 #ifdef GEKKO 709 u32 PPCMfhid2 ( void ); 710 void PPCMthid2 ( u32 newhid2 ); 711 712 u32 PPCMfwpar ( void ); 713 // Note: this will flush the write pipe 714 void PPCMtwpar ( u32 newwpar ); 715 716 u32 PPCMfdmaU ( void ); 717 u32 PPCMfdmaL ( void ); 718 719 void PPCMtdmaU ( u32 newdmau ); 720 void PPCMtdmaL ( u32 newdmal ); 721 #endif // GEKKO 722 723 u32 PPCMfl2cr ( void ); 724 void PPCMtl2cr ( u32 newL2cr ); 725 726 void PPCMtdec ( u32 newDec ); 727 u32 PPCMfdec ( void ); 728 729 void PPCSync ( void ); 730 void PPCEieio ( void ); 731 732 void PPCHalt ( void ); 733 734 u32 PPCMfmmcr0( void ); 735 void PPCMtmmcr0( u32 newMmcr0 ); 736 u32 PPCMfmmcr1( void ); 737 void PPCMtmmcr1( u32 newMmcr1 ); 738 u32 PPCMfpmc1 ( void ); 739 void PPCMtpmc1 ( u32 newPmc1 ); 740 u32 PPCMfpmc2 ( void ); 741 void PPCMtpmc2 ( u32 newPmc2 ); 742 u32 PPCMfpmc3 ( void ); 743 void PPCMtpmc3 ( u32 newPmc3 ); 744 u32 PPCMfpmc4 ( void ); 745 void PPCMtpmc4 ( u32 newPmc4 ); 746 u32 PPCMfsia ( void ); 747 void PPCMtsia ( u32 newSia ); 748 749 u32 PPCMfpvr ( void ); 750 751 u32 PPCMffpscr( void ); 752 void PPCMtfpscr( u32 newFPSCR ); 753 754 /*---------------------------------------------------------------------------* 755 PPC mode functions 756 *---------------------------------------------------------------------------*/ 757 void PPCEnableSpeculation ( void ); 758 void PPCDisableSpeculation ( void ); 759 760 void PPCSetFpIEEEMode ( void ); 761 void PPCSetFpNonIEEEMode ( void ); 762 763 764 /*---------------------------------------------------------------------------* 765 BROADWAY SPECIFIC CODE 766 *---------------------------------------------------------------------------*/ 767 #ifdef BROADWAY_REV 768 #define HID4 1011 769 #define HID4_H4A 0x80000000 // HID4 access 770 #define HID4_L2FM_MASK 0x60000000 // L2 fetch mode 771 #define HID4_L2FM_32B 0x00000000 772 #define HID4_L2FM_64B 0x20000000 773 #define HID4_L2FM_128B 0x40000000 774 #define HID4_BPD_MASK 0x18000000 // Bus pipeline depth 775 #define HID4_BPD_2 0x00000000 776 #define HID4_BPD_3 0x08000000 777 #define HID4_BPD_4 0x10000000 778 #define HID4_BCO 0x04000000 // Bus castout buffers 779 #define HID4_SBE 0x02000000 // Secondary BAT enable 780 #define HID4_ST0 0x01000000 // Store 0 enable 781 #define HID4_LPE 0x00800000 // Little endian and paired-singles exception mode 782 #define HID4_DBP 0x00400000 // Data bus parking 783 #define HID4_L2MUM 0x00200000 // L2 MUM enable 784 #define HID4_L2CFI 0x00100000 // L2 castout complete prior to L2 flash invalidate 785 #endif 786 787 #if defined(BROADWAY_REV) || defined(BROADWAY_EMU) 788 u32 PPCMfhid4 ( void ); 789 void PPCMthid4 ( register u32 newhid4 ); 790 #endif // BROADWAY_REV || BROADWAY_EMU 791 792 #ifdef __cplusplus 793 } 794 #endif 795 796 #endif //__PPCARCH_H__ 797 798