/*---------------------------------------------------------------------------* Copyright (C) Nintendo. All rights reserved. These coded instructions, statements, and computer programs contain proprietary information of Nintendo of America Inc. and/or Nintendo Company Ltd., and are protected by Federal copyright law. They may not be disclosed to third parties or copied or duplicated in any form, in whole or in part, without the prior written consent of Nintendo. *---------------------------------------------------------------------------*/ // gx2PerfEnum.h // // Declares performance enums for gx2 library. #ifndef _CAFE_GX2_PERF_ENUM_H_ #define _CAFE_GX2_PERF_ENUM_H_ #ifdef __cplusplus extern "C" { #endif // __cplusplus #if defined _WIN32 || defined _WIN64 #include #include #ifndef ASSERT #define ASSERT assert #endif // ASSERT #endif #define GX2_CHECK_ENUM_RANGE(value, type) \ ASSERT(value>=type##_FIRST && value<=type##_LAST); /// @addtogroup GX2PerfEnumGroup /// @{ /// \brief Indicates a set of counters in a GPU block /// /// typedef enum __GX2CounterId { GX2_COUNTER_CP_0 = 0x00, GX2_COUNTER_GRBM_0 = 0x01, GX2_COUNTER_GRBM_1 = 0x02, GX2_COUNTER_PA_SU_0 = 0x03, GX2_COUNTER_PA_SU_1 = 0x04, GX2_COUNTER_PA_SU_2 = 0x05, GX2_COUNTER_PA_SU_3 = 0x06, GX2_COUNTER_PA_SC_0 = 0x07, GX2_COUNTER_PA_SC_1 = 0x08, GX2_COUNTER_PA_SC_2 = 0x09, GX2_COUNTER_PA_SC_3 = 0x0a, GX2_COUNTER_VGT_0 = 0x0b, GX2_COUNTER_VGT_1 = 0x0c, GX2_COUNTER_VGT_2 = 0x0d, GX2_COUNTER_VGT_3 = 0x0e, GX2_COUNTER_SQ_0 = 0x0f, GX2_COUNTER_SQ_1 = 0x10, GX2_COUNTER_SQ_2 = 0x11, GX2_COUNTER_SQ_3 = 0x12, GX2_COUNTER_SPI_0 = 0x13, GX2_COUNTER_SPI_1 = 0x14, GX2_COUNTER_SPI_2 = 0x15, GX2_COUNTER_SPI_3 = 0x16, GX2_COUNTER_SX_0 = 0x17, GX2_COUNTER_SX_1 = 0x18, GX2_COUNTER_SX_2 = 0x19, GX2_COUNTER_SX_3 = 0x1a, GX2_COUNTER_SMX_0 = 0x1b, GX2_COUNTER_SMX_1 = 0x1c, GX2_COUNTER_SMX_2 = 0x1d, GX2_COUNTER_SMX_3 = 0x1e, /// \brief TD instance 0. When configuring counters, this controls what TD_0_0 and TD_0_1 count. When getting results, this holds the result from TD instance 0. GX2_COUNTER_TD_0_0 = 0x1f, /// \brief TD instance 1. When configuring counters, this is ignored. It is controlled by TD_0_0. When getting results, this holds the result from TD instance 1. GX2_COUNTER_TD_0_1 = 0x20, /// \brief TA counter 0, instance 0. When configuring counters, this controls what TA_0_0 and TA_0_1 count. When getting results, this holds the result from TA instance 0. GX2_COUNTER_TA_0_0 = 0x21, /// \brief TA counter 0, instance 1. When configuring counters, this is ignored. It is controlled by TA_0_0. When getting results, this holds the result from TA instance 1. GX2_COUNTER_TA_0_1 = 0x22, /// \brief TA counter 1, instance 0. When configuring counters, this controls what TA_1_0 and TA_1_1 count. When getting results, this holds the result from TA instance 0. GX2_COUNTER_TA_1_0 = 0x23, /// \brief TA counter 1, instance 1. When configuring counters, this is ignored. It is controlled by TA_1_0. When getting results, this holds the result from TA instance 1. GX2_COUNTER_TA_1_1 = 0x24, /// \brief TCP counter 0, instance 0. When configuring counters, this controls what TCP_0_0 and TCP_0_1 count. When getting results, this holds the result from TCP instance 0. GX2_COUNTER_TCP_0_0 = 0x25, /// \brief TCP counter 0, instance 1. When configuring counters, this is ignored. It is controlled by TCP_0_0. When getting results, this holds the result from TCP instance 1. GX2_COUNTER_TCP_0_1 = 0x26, /// \brief TCP counter 1, instance 0. When configuring counters, this controls what TCP_1_0 and TCP_1_1 count. When getting results, this holds the result from TCP instance 0. GX2_COUNTER_TCP_1_0 = 0x27, /// \brief TCP counter 1, instance 1. When configuring counters, this is ignored. It is controlled by TCP_1_0. When getting results, this holds the result from TCP instance 1. GX2_COUNTER_TCP_1_1 = 0x28, /// \brief TCP counter 2, instance 0. When configuring counters, this controls what TCP_2_0 and TCP_2_1 count. When getting results, this holds the result from TCP instance 0. GX2_COUNTER_TCP_2_0 = 0x29, /// \brief TCP counter 2, instance 1. When configuring counters, this is ignored. It is controlled by TCP_2_0. When getting results, this holds the result from TCP instance 1. GX2_COUNTER_TCP_2_1 = 0x2a, /// \brief TCP counter 3, instance 0. When configuring counters, this controls what TCP_3_0 and TCP_3_1 count. When getting results, this holds the result from TCP instance 0. GX2_COUNTER_TCP_3_0 = 0x2b, /// \brief TCP counter 3, instance 1. When configuring counters, this is ignored. It is controlled by TCP_3_0. When getting results, this holds the result from TCP instance 1. GX2_COUNTER_TCP_3_1 = 0x2c, /// \brief TCC counter 0, instance 0. When configuring counters, this controls what TCC_0_0 and TCC_0_1 count. When getting results, this holds the result from TCC instance 0. GX2_COUNTER_TCC_0_0 = 0x2d, /// \brief TCC counter 0, instance 1. When configuring counters, this is ignored. It is controlled by TCC_0_0. When getting results, this holds the result from TCC instance 1. GX2_COUNTER_TCC_0_1 = 0x2e, /// \brief TCC counter 1, instance 0. When configuring counters, this controls what TCC_1_0 and TCC_1_1 count. When getting results, this holds the result from TCC instance 0. GX2_COUNTER_TCC_1_0 = 0x2f, /// \brief TCC counter 1, instance 1. When configuring counters, this is ignored. It is controlled by TCC_1_0. When getting results, this holds the result from TCC instance 1. GX2_COUNTER_TCC_1_1 = 0x30, /// \brief TCC counter 2, instance 0. When configuring counters, this controls what TCC_2_0 and TCC_2_1 count. When getting results, this holds the result from TCC instance 0. GX2_COUNTER_TCC_2_0 = 0x31, /// \brief TCC counter 2, instance 1. When configuring counters, this is ignored. It is controlled by TCC_2_0. When getting results, this holds the result from TCC instance 1. GX2_COUNTER_TCC_2_1 = 0x32, /// \brief TCC counter 3, instance 0. When configuring counters, this controls what TCC_3_0 and TCC_3_1 count. When getting results, this holds the result from TCC instance 0. GX2_COUNTER_TCC_3_0 = 0x33, /// \brief TCC counter 3, instance 1. When configuring counters, this is ignored. It is controlled by TCC_3_0. When getting results, this holds the result from TCC instance 1. GX2_COUNTER_TCC_3_1 = 0x34, /// \brief CB counter 0, instance 0. When configuring counters, this controls what CB_0_0 and CB_0_1 count. When getting results, this holds the result from CB instance 0. GX2_COUNTER_CB_0_0 = 0x3d, /// \brief CB counter 0, instance 1. When configuring counters, this is ignored. It is controlled by CB_0_0. When getting results, this holds the result from CB instance 1. GX2_COUNTER_CB_0_1 = 0x3e, /// \brief CB counter 1, instance 0. When configuring counters, this controls what CB_1_0 and CB_1_1 count. When getting results, this holds the result from CB instance 0. GX2_COUNTER_CB_1_0 = 0x3f, /// \brief CB counter 1, instance 1. When configuring counters, this is ignored. It is controlled by CB_1_0. When getting results, this holds the result from CB instance 1. GX2_COUNTER_CB_1_1 = 0x40, /// \brief CB counter 2, instance 0. When configuring counters, this controls what CB_2_0 and CB_2_1 count. When getting results, this holds the result from CB instance 0. GX2_COUNTER_CB_2_0 = 0x41, /// \brief CB counter 2, instance 1. When configuring counters, this is ignored. It is controlled by CB_2_0. When getting results, this holds the result from CB instance 1. GX2_COUNTER_CB_2_1 = 0x42, /// \brief CB counter 3, instance 0. When configuring counters, this controls what CB_3_0 and CB_3_1 count. When getting results, this holds the result from CB instance 0. GX2_COUNTER_CB_3_0 = 0x43, /// \brief CB counter 3, instance 1. When configuring counters, this is ignored. It is controlled by CB_3_0. When getting results, this holds the result from CB instance 1. GX2_COUNTER_CB_3_1 = 0x44, /// \brief DB counter 0, instance 0. When configuring counters, this controls what DB_0_0 and DB_0_1 count. When getting results, this holds the result from DB instance 0. GX2_COUNTER_DB_0_0 = 0x35, /// \brief DB counter 0, instance 1. When configuring counters, this is ignored. It is controlled by DB_0_0. When getting results, this holds the result from DB instance 1. GX2_COUNTER_DB_0_1 = 0x36, /// \brief DB counter 1, instance 0. When configuring counters, this controls what DB_1_0 and DB_1_1 count. When getting results, this holds the result from DB instance 0. GX2_COUNTER_DB_1_0 = 0x37, /// \brief DB counter 1, instance 1. When configuring counters, this is ignored. It is controlled by DB_1_0. When getting results, this holds the result from DB instance 1. GX2_COUNTER_DB_1_1 = 0x38, /// \brief DB counter 2, instance 0. When configuring counters, this controls what DB_2_0 and DB_2_1 count. When getting results, this holds the result from DB instance 0. GX2_COUNTER_DB_2_0 = 0x39, /// \brief DB counter 2, instance 1. When configuring counters, this is ignored. It is controlled by DB_2_0. When getting results, this holds the result from DB instance 1. GX2_COUNTER_DB_2_1 = 0x3a, /// \brief DB counter 3, instance 0. When configuring counters, this controls what DB_3_0 and DB_3_1 count. When getting results, this holds the result from DB instance 0. GX2_COUNTER_DB_3_0 = 0x3b, /// \brief DB counter 3, instance 1. When configuring counters, this is ignored. It is controlled by DB_3_0. When getting results, this holds the result from DB instance 1. GX2_COUNTER_DB_3_1 = 0x3c, GX2_COUNTER_PIPELINE = 0x45, GX2_COUNTER_FIRST = GX2_COUNTER_CP_0, GX2_COUNTER_LAST = GX2_COUNTER_PIPELINE } _GX2CounterId; /// \brief Indicates shader type for sq counter /// typedef enum __GX2SqType { GX2_SQ_PS = 0x00000100, GX2_SQ_VS = 0x00000200, GX2_SQ_GS = 0x00000400, GX2_SQ_ES = 0x00000800, GX2_SQ_FIRST = GX2_SQ_ES, GX2_SQ_LAST = GX2_SQ_PS } _GX2SqType; /// \brief Indicate a specific statistic in a GPU counter block /// typedef enum __GX2StatId { /// Always Count. GX2_STAT_CP_CP_COUNT = 0x00000000, /// RBIU Transaction FIFO FUll. GX2_STAT_CP_RBIU_FIFO_FULL = 0x00000001, /// CSF is Ready to Send data but the MIU is not Ready to Receive it. GX2_STAT_CP_CSF_RTS_BUT_MIU_NOT_RTR = 0x00000002, /// PFP to CSF I1 Request FIFO is FUll. GX2_STAT_CP_CSF_I1_BASE_SIZE_FIFO_FULL_6XX = 0x00000003, /// PFP to CSF I2 Request FIFO is FUll. GX2_STAT_CP_CSF_I2_BASE_SIZE_FIFO_FULL_6XX = 0x00000004, /// PFP to CSF State Request FIFO is FUll. GX2_STAT_CP_CSF_ST_BASE_SIZE_FIFO_FULL = 0x00000005, /// Ring Reorder Queue is Full. GX2_STAT_CP_RING_REORDER_QUEUE_FULL = 0x00000006, GX2_STAT_CP_I1_REORDER_QUEUE_FULL = 0x00000007, GX2_STAT_CP_I2_REORDER_QUEUE_FULL = 0x00000008, GX2_STAT_CP_ST_REORDER_QUEUE_FULL = 0x00000009, GX2_STAT_CP_CSF_RB_WPTR_NEQ_RPTR = 0x0000000A, GX2_STAT_CP_CSF_I1_SIZE_NEQ_ZERO = 0x0000000B, GX2_STAT_CP_CSF_I2_SIZE_NEQ_ZERO = 0x0000000C, GX2_STAT_CP_BRUSH_WR_CONFIRM_FIFO_FULL_6XX = 0x0000000D, GX2_STAT_CP_CP_GRBM_DWORDS_SENT = 0x0000000E, GX2_STAT_CP_ME_PARSER_BUSY = 0x0000000F, GX2_STAT_CP_COUNT_TYPE0_PACKETS = 0x00000010, GX2_STAT_CP_COUNT_TYPE3_PACKETS = 0x00000011, GX2_STAT_CP_CSF_RBI1I2_FETCHING = 0x00000012, GX2_STAT_CP_ME_STALLED_FOR_DATA_FROM_PFP = 0x00000013, GX2_STAT_CP_CP_GRBM_OUT_OF_CREDITS = 0x00000014, GX2_STAT_CP_CP_PFP_GRBM_OUT_OF_CREDITS = 0x00000015, GX2_STAT_CP_RCIU_STALLED_ON_ME_READ = 0x00000016, GX2_STAT_CP_RCIU_STALLED_ON_DMA_READ = 0x00000017, GX2_STAT_CP_MIU_STALLED_ON_RDREQ_CREDITS_6XX = 0x00000018, GX2_STAT_CP_MIU_STALLED_ON_WRREQ_CREDITS_6XX = 0x00000019, GX2_STAT_CP_MIU_STALLED_ON_WRCLEAN_PHASE_6XX = 0x0000001A, GX2_STAT_CP_SSU_STALLED_ON_ACTIVE_CNTX = 0x0000001B, GX2_STAT_CP_SSU_STALLED_ON_CLEAN_SIGNALS = 0x0000001C, GX2_STAT_CP_QU_STALLED_ON_RECT_DONE_PULSE_6XX = 0x0000001D, GX2_STAT_CP_QU_STALLED_ON_RECT_DONE_WR_CONFIRM_6XX = 0x0000001E, GX2_STAT_CP_QU_STALLED_ON_SC_EOP_DONE_PULSE = 0x0000001F, GX2_STAT_CP_QU_STALLED_ON_SX_EOP_DONE_PULSE = 0x00000020, GX2_STAT_CP_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x00000021, GX2_STAT_CP_QU_STALLED_ON_SIGNAL_SEMAPHORE = 0x00000022, GX2_STAT_CP_QU_STALLED_ON_STREAMOUT_ADDRESS = 0x00000023, GX2_STAT_CP_QU_STALLED_ON_STREAMOUT_DATA = 0x00000024, GX2_STAT_CP_QU_STALLED_ON_PIPELINE_STATISTICS = 0x00000025, GX2_STAT_CP_PFP_STALLED_ON_CSF_READY = 0x00000026, GX2_STAT_CP_PFP_STALLED_ON_MEQ_READY = 0x00000027, GX2_STAT_CP_PFP_STALLED_ON_VGT_READY = 0x00000028, GX2_STAT_CP_PFP_STALLED_ON_PENDING_MULTIPASS = 0x00000029, GX2_STAT_CP_ME_STALLED_ON_BRUSH_WR_CONFIRM_6XX = 0x0000002A, GX2_STAT_CP_ME_STALLED_ON_BUSY_BRUSH_LOGIC_6XX = 0x0000002B, GX2_STAT_CP_ME_STALLED_ON_NO_AVAIL_CR_CNTX_6XX = 0x0000002C, GX2_STAT_CP_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x0000002D, GX2_STAT_CP_ME_STALLED_WRITING_TO_RCIU = 0x0000002E, GX2_STAT_CP_ME_STALLED_WRITING_CONSTANTS = 0x0000002F, GX2_STAT_CP_RBIU_STALLED_WRITING_DMA_REGS = 0x00000030, GX2_STAT_CP_RBIU_STALLED_WRITING_SEM_REGS = 0x00000031, GX2_STAT_CP_RBIU_STALLED_WRITING_MC_WR_ADDR = 0x00000032, GX2_STAT_CP_RBIU_STALLED_WRITING_MC_RD_ADDR_6XX = 0x00000033, GX2_STAT_CP_RBIU_STALLED_WRITING_EOPDONE_FIFO_600 = 0x00000034, GX2_STAT_CP_RBIU_STALLED_WRITING_RECTDONE_FIFO_6XX = 0x00000035, GX2_STAT_CP_RBIU_STALLED_WRITING_STREAMOUT_FIFO_600 = 0x00000036, GX2_STAT_CP_RBIU_STALLED_WRITING_PIPESTATS_FIFO_600 = 0x00000037, GX2_STAT_CP_SEMAPHORE_BUSY_POLLING_FOR_PASS = 0x00000038, GX2_STAT_CP_LOAD_STALLED_ON_SET_COHERENCY = 0x00000039, GX2_STAT_CP_ME_STALLED_ON_PARTIAL_FLUSH = 0x0000003A, GX2_STAT_CP_CSF_IDLE_CONFIRM_TO_ACTIVE_6XX = 0x0000003B, GX2_STAT_CP_DYNAMIC_CLK_VALID = 0x0000003C, GX2_STAT_CP_REGISTER_CLK_VALID = 0x0000003D, GX2_STAT_CP_FIRST = GX2_STAT_CP_CP_COUNT, GX2_STAT_CP_LAST = GX2_STAT_CP_REGISTER_CLK_VALID, GX2_STAT_GRBM_COUNT = 0x00001000, GX2_STAT_GRBM_GUI_ACTIVE = 0x00001001, GX2_STAT_GRBM_VGT_NO_DMA_BUSY = 0x00001002, GX2_STAT_GRBM_VGT_DMA_BUSY = 0x00001003, GX2_STAT_GRBM_TA0_BUSY = 0x00001004, GX2_STAT_GRBM_TA1_BUSY = 0x00001005, GX2_STAT_GRBM_TA2_BUSY = 0x00001006, GX2_STAT_GRBM_TA3_BUSY = 0x00001007, GX2_STAT_GRBM_TC_BUSY_R6XX = 0x00001008, GX2_STAT_GRBM_SX_BUSY = 0x00001009, GX2_STAT_GRBM_SH_BUSY = 0x0000100A, GX2_STAT_GRBM_SPI_BUSY = 0x0000100B, GX2_STAT_GRBM_SMX_BUSY_R6XX = 0x0000100C, GX2_STAT_GRBM_SC_BUSY = 0x0000100D, GX2_STAT_GRBM_DRMDMA_BUSY_R6XX = 0x0000100E, GX2_STAT_GRBM_PA_BUSY = 0x0000100F, GX2_STAT_GRBM_DB0_BUSY = 0x00001010, GX2_STAT_GRBM_DB1_BUSY = 0x00001011, GX2_STAT_GRBM_DB2_BUSY = 0x00001012, GX2_STAT_GRBM_DB3_BUSY = 0x00001013, GX2_STAT_GRBM_CR_BUSY_R6XX = 0x00001014, GX2_STAT_GRBM_CP_COHER_BUSY = 0x00001015, GX2_STAT_GRBM_CP_BUSY = 0x00001016, GX2_STAT_GRBM_CP_DMA_BUSY = 0x00001017, GX2_STAT_GRBM_CB0_BUSY = 0x00001018, GX2_STAT_GRBM_CB1_BUSY = 0x00001019, GX2_STAT_GRBM_CB2_BUSY = 0x0000101A, GX2_STAT_GRBM_CB3_BUSY = 0x0000101B, GX2_STAT_GRBM_VC_BUSY_R6XX = 0x0000101C, GX2_STAT_GRBM_EXTERN_STALL = 0x0000101D, GX2_STAT_GRBM_CP_DMA_IDLE_STALL = 0x0000101E, GX2_STAT_GRBM_GFX_IDLE_STALL = 0x0000101F, GX2_STAT_GRBM_GFX_IDLE_CLEAN_STALL = 0x00001020, GX2_STAT_GRBM_GFX_IDLE_STALL_R600 = 0x00001021, GX2_STAT_GRBM_GFX_IDLE_CLEAN_STALL_R600 = 0x00001022, GX2_STAT_GRBM_TA4_BUSY = 0x00001023, GX2_STAT_GRBM_TA5_BUSY = 0x00001024, GX2_STAT_GRBM_TA6_BUSY = 0x00001025, GX2_STAT_GRBM_TA7_BUSY = 0x00001026, GX2_STAT_GRBM_TA8_BUSY = 0x00001027, GX2_STAT_GRBM_TA9_BUSY = 0x00001028, GX2_STAT_GRBM_TA10_BUSY = 0x00001029, GX2_STAT_GRBM_TA11_BUSY = 0x0000102A, GX2_STAT_GRBM_TA12_BUSY = 0x0000102B, GX2_STAT_GRBM_TA13_BUSY = 0x0000102C, GX2_STAT_GRBM_TA14_BUSY = 0x0000102D, GX2_STAT_GRBM_TA15_BUSY = 0x0000102E, GX2_STAT_GRBM_RESERVED0 = 0x0000102F, GX2_STAT_GRBM_RESERVED1 = 0x00001030, GX2_STAT_GRBM_RESERVED2 = 0x00001031, GX2_STAT_GRBM_RESERVED3 = 0x00001032, GX2_STAT_GRBM_RESERVED4 = 0x00001033, GX2_STAT_GRBM_RESERVED5 = 0x00001034, GX2_STAT_GRBM_RESERVED6 = 0x00001035, GX2_STAT_GRBM_RESERVED7 = 0x00001036, GX2_STAT_GRBM_RESERVED8 = 0x00001037, GX2_STAT_GRBM_RESERVED9 = 0x00001038, GX2_STAT_GRBM_RESERVED10 = 0x00001039, GX2_STAT_GRBM_RESERVED11 = 0x0000103A, GX2_STAT_GRBM_RESERVED12 = 0x0000103B, GX2_STAT_GRBM_RESERVED13 = 0x0000103C, GX2_STAT_GRBM_RESERVED14 = 0x0000103D, GX2_STAT_GRBM_RESERVED15 = 0x0000103E, GX2_STAT_GRBM_USER_DEFINED_BUSY = 0x0000103F, GX2_STAT_GRBM_FIRST = GX2_STAT_GRBM_COUNT, GX2_STAT_GRBM_LAST = GX2_STAT_GRBM_USER_DEFINED_BUSY, GX2_STAT_PA_SU_PASX_REQ = 0x00002000, GX2_STAT_PA_SU_PASX_DISABLE_PIPE = 0x00002001, GX2_STAT_PA_SU_PASX_FIRST_VECTOR = 0x00002002, GX2_STAT_PA_SU_PASX_SECOND_VECTOR = 0x00002003, GX2_STAT_PA_SU_PASX_FIRST_DEAD = 0x00002004, GX2_STAT_PA_SU_PASX_SECOND_DEAD = 0x00002005, GX2_STAT_PA_SU_PASX_VTX_KILL_DISCARD = 0x00002006, GX2_STAT_PA_SU_PASX_VTX_NAN_DISCARD = 0x00002007, GX2_STAT_PA_SU_PA_INPUT_PRIM = 0x00002008, GX2_STAT_PA_SU_PA_INPUT_NULL_PRIM = 0x00002009, GX2_STAT_PA_SU_PA_INPUT_EVENT_FLAG = 0x0000200A, GX2_STAT_PA_SU_PA_INPUT_FIRST_PRIM_SLOT = 0x0000200B, GX2_STAT_PA_SU_PA_INPUT_END_OF_PACKET = 0x0000200C, GX2_STAT_PA_SU_PA_INPUT_EXTENDED_EVENT = 0x0000200D, GX2_STAT_PA_SU_CLPR_CULL_PRIM = 0x0000200E, GX2_STAT_PA_SU_CLPR_VVUCP_CULL_PRIM = 0x0000200F, GX2_STAT_PA_SU_CLPR_VV_CULL_PRIM = 0x00002010, GX2_STAT_PA_SU_CLPR_UCP_CULL_PRIM = 0x00002011, GX2_STAT_PA_SU_CLPR_VTX_KILL_CULL_PRIM = 0x00002012, GX2_STAT_PA_SU_CLPR_VTX_NAN_CULL_PRIM = 0x00002013, GX2_STAT_PA_SU_CLPR_CULL_TO_NULL_PRIM = 0x00002014, GX2_STAT_PA_SU_CLPR_VVUCP_CLIP_PRIM = 0x00002015, GX2_STAT_PA_SU_CLPR_VV_CLIP_PRIM = 0x00002016, GX2_STAT_PA_SU_CLPR_UCP_CLIP_PRIM = 0x00002017, GX2_STAT_PA_SU_CLPR_POINT_CLIP_CANDIDATE = 0x00002018, GX2_STAT_PA_SU_CLPR_CLIP_PLANE_CNT_1 = 0x00002019, GX2_STAT_PA_SU_CLPR_CLIP_PLANE_CNT_2 = 0x0000201A, GX2_STAT_PA_SU_CLPR_CLIP_PLANE_CNT_3 = 0x0000201B, GX2_STAT_PA_SU_CLPR_CLIP_PLANE_CNT_4 = 0x0000201C, GX2_STAT_PA_SU_CLPR_CLIP_PLANE_CNT_5_8 = 0x0000201D, GX2_STAT_PA_SU_CLPR_CLIP_PLANE_CNT_9_12 = 0x0000201E, GX2_STAT_PA_SU_CLPR_CLIP_PLANE_NEAR = 0x0000201F, GX2_STAT_PA_SU_CLPR_CLIP_PLANE_FAR = 0x00002020, GX2_STAT_PA_SU_CLPR_CLIP_PLANE_LEFT = 0x00002021, GX2_STAT_PA_SU_CLPR_CLIP_PLANE_RIGHT = 0x00002022, GX2_STAT_PA_SU_CLPR_CLIP_PLANE_TOP = 0x00002023, GX2_STAT_PA_SU_CLPR_CLIP_PLANE_BOTTOM = 0x00002024, GX2_STAT_PA_SU_CLPR_GSC_KILL_CULL_PRIM = 0x00002025, GX2_STAT_PA_SU_CLPR_RASTER_KILL_CULL_PRIM = 0x00002026, GX2_STAT_PA_SU_CLSM_NULL_PRIM = 0x00002027, GX2_STAT_PA_SU_CLSM_TOTALLY_VISIBLE_PRIM = 0x00002028, GX2_STAT_PA_SU_CLSM_CULL_TO_NULL_PRIM = 0x00002029, GX2_STAT_PA_SU_CLSM_OUT_PRIM_CNT_1 = 0x0000202A, GX2_STAT_PA_SU_CLSM_OUT_PRIM_CNT_2 = 0x0000202B, GX2_STAT_PA_SU_CLSM_OUT_PRIM_CNT_3 = 0x0000202C, GX2_STAT_PA_SU_CLSM_OUT_PRIM_CNT_4 = 0x0000202D, GX2_STAT_PA_SU_CLSM_OUT_PRIM_CNT_5_8 = 0x0000202E, GX2_STAT_PA_SU_CLSM_OUT_PRIM_CNT_9_13 = 0x0000202F, GX2_STAT_PA_SU_CLIPGA_VTE_KILL_PRIM = 0x00002030, GX2_STAT_PA_SU_SU_INPUT_PRIM = 0x00002031, GX2_STAT_PA_SU_SU_INPUT_CLIP_PRIM = 0x00002032, GX2_STAT_PA_SU_SU_INPUT_NULL_PRIM = 0x00002033, GX2_STAT_PA_SU_SU_INPUT_PRIM_DUAL = 0x00002034, GX2_STAT_PA_SU_SU_INPUT_CLIP_PRIM_DUAL = 0x00002035, GX2_STAT_PA_SU_SU_ZERO_AREA_CULL_PRIM = 0x00002036, GX2_STAT_PA_SU_SU_BACK_FACE_CULL_PRIM = 0x00002037, GX2_STAT_PA_SU_SU_FRONT_FACE_CULL_PRIM = 0x00002038, GX2_STAT_PA_SU_SU_POLYMODE_FACE_CULL = 0x00002039, GX2_STAT_PA_SU_SU_POLYMODE_BACK_CULL = 0x0000203A, GX2_STAT_PA_SU_SU_POLYMODE_FRONT_CULL = 0x0000203B, GX2_STAT_PA_SU_SU_POLYMODE_INVALID_FILL = 0x0000203C, GX2_STAT_PA_SU_SU_OUTPUT_PRIM = 0x0000203D, GX2_STAT_PA_SU_SU_OUTPUT_CLIP_PRIM = 0x0000203E, GX2_STAT_PA_SU_SU_OUTPUT_NULL_PRIM = 0x0000203F, GX2_STAT_PA_SU_SU_OUTPUT_EVENT_FLAG = 0x00002040, GX2_STAT_PA_SU_SU_OUTPUT_FIRST_PRIM_SLOT = 0x00002041, GX2_STAT_PA_SU_SU_OUTPUT_END_OF_PACKET = 0x00002042, GX2_STAT_PA_SU_SU_OUTPUT_POLYMODE_FACE = 0x00002043, GX2_STAT_PA_SU_SU_OUTPUT_POLYMODE_BACK = 0x00002044, GX2_STAT_PA_SU_SU_OUTPUT_POLYMODE_FRONT = 0x00002045, GX2_STAT_PA_SU_SU_OUT_CLIP_POLYMODE_FACE = 0x00002046, GX2_STAT_PA_SU_SU_OUT_CLIP_POLYMODE_BACK = 0x00002047, GX2_STAT_PA_SU_SU_OUT_CLIP_POLYMODE_FRONT = 0x00002048, GX2_STAT_PA_SU_SU_OUTPUT_PRIM_DUAL = 0x00002049, GX2_STAT_PA_SU_SU_OUTPUT_CLIP_PRIM_DUAL = 0x0000204A, GX2_STAT_PA_SU_SU_OUTPUT_POLYMODE_DUAL = 0x0000204B, GX2_STAT_PA_SU_SU_OUTPUT_CLIP_POLYMODE_DUAL = 0x0000204C, GX2_STAT_PA_SU_PASX_REQ_IDLE = 0x0000204D, GX2_STAT_PA_SU_PASX_REQ_BUSY = 0x0000204E, GX2_STAT_PA_SU_PASX_REQ_STALLED = 0x0000204F, GX2_STAT_PA_SU_PASX_REC_IDLE = 0x00002050, GX2_STAT_PA_SU_PASX_REC_BUSY = 0x00002051, GX2_STAT_PA_SU_PASX_REC_STARVED_SX = 0x00002052, GX2_STAT_PA_SU_PASX_REC_STALLED = 0x00002053, GX2_STAT_PA_SU_PASX_REC_STALLED_POS_MEM = 0x00002054, GX2_STAT_PA_SU_PASX_REC_STALLED_CCGSM_IN = 0x00002055, GX2_STAT_PA_SU_CCGSM_IDLE = 0x00002056, GX2_STAT_PA_SU_CCGSM_BUSY = 0x00002057, GX2_STAT_PA_SU_CCGSM_STALLED = 0x00002058, GX2_STAT_PA_SU_CLPRIM_IDLE = 0x00002059, GX2_STAT_PA_SU_CLPRIM_BUSY = 0x0000205A, GX2_STAT_PA_SU_CLPRIM_STALLED = 0x0000205B, GX2_STAT_PA_SU_CLPRIM_STARVED_CCGSM = 0x0000205C, GX2_STAT_PA_SU_CLIPSM_IDLE = 0x0000205D, GX2_STAT_PA_SU_CLIPSM_BUSY = 0x0000205E, GX2_STAT_PA_SU_CLIPSM_WAIT_CLIP_VERT_ENGH = 0x0000205F, GX2_STAT_PA_SU_CLIPSM_WAIT_HIGH_PRI_SEQ = 0x00002060, GX2_STAT_PA_SU_CLIPSM_WAIT_CLIPGA = 0x00002061, GX2_STAT_PA_SU_CLIPSM_WAIT_AVAIL_VTE_CLIP = 0x00002062, GX2_STAT_PA_SU_CLIPSM_WAIT_CLIP_OUTSM = 0x00002063, GX2_STAT_PA_SU_CLIPGA_IDLE = 0x00002064, GX2_STAT_PA_SU_CLIPGA_BUSY = 0x00002065, GX2_STAT_PA_SU_CLIPGA_STARVED_VTE_CLIP = 0x00002066, GX2_STAT_PA_SU_CLIPGA_STALLED = 0x00002067, GX2_STAT_PA_SU_CLIP_IDLE = 0x00002068, GX2_STAT_PA_SU_CLIP_BUSY = 0x00002069, GX2_STAT_PA_SU_SU_IDLE = 0x0000206A, GX2_STAT_PA_SU_SU_BUSY = 0x0000206B, GX2_STAT_PA_SU_SU_STARVED_CLIP = 0x0000206C, GX2_STAT_PA_SU_SU_STALLED_SC = 0x0000206D, GX2_STAT_PA_SU_PA_DYN_SCLK_VLD = 0x0000206E, GX2_STAT_PA_SU_PA_REG_SCLK_VLD = 0x0000206F, GX2_STAT_PA_SU_FIRST = GX2_STAT_PA_SU_PASX_REQ, GX2_STAT_PA_SU_LAST = GX2_STAT_PA_SU_PA_REG_SCLK_VLD, /// Number of clocks event-window is valid at stage register/primitive setup GX2_STAT_PA_SC_SRPS_WINDOW_VALID = 0x00003000, /// Number of clocks event-window is valid at primitive setup/supertile walker GX2_STAT_PA_SC_PSSW_WINDOW_VALID = 0x00003001, /// Number of clocks event-window is valid at tile picker/quad-z GX2_STAT_PA_SC_TPQZ_WINDOW_VALID = 0x00003002, /// Number of clocks event-window is valid at quad-z/quad processor GX2_STAT_PA_SC_QZQP_WINDOW_VALID = 0x00003003, /// Number of clocks event-window is valid at tile reorder/packer GX2_STAT_PA_SC_TRPK_WINDOW_VALID = 0x00003004, /// Number of clocks event-window is valid at stage register/primitive setup with SC busy GX2_STAT_PA_SC_SRPS_WINDOW_VALID_BUSY = 0x00003005, /// Number of clocks event-window is valid at primitive setup/supertile walker with SC busy GX2_STAT_PA_SC_PSSW_WINDOW_VALID_BUSY = 0x00003006, /// Number of clocks event-window is valid at tile picker/quad-z with SC busy GX2_STAT_PA_SC_TPQZ_WINDOW_VALID_BUSY = 0x00003007, GX2_STAT_PA_SC_QZQP_WINDOW_VALID_BUSY = 0x00003008, GX2_STAT_PA_SC_TRPK_WINDOW_VALID_BUSY = 0x00003009, GX2_STAT_PA_SC_STARVED_BY_PA = 0x0000300A, GX2_STAT_PA_SC_STALLED_BY_PRIMFIFO = 0x0000300B, GX2_STAT_PA_SC_STARVED_BY_DB_TILE = 0x0000300C, GX2_STAT_PA_SC_STARVED_BY_DB_QUAD = 0x0000300D, GX2_STAT_PA_SC_STALLED_BY_TILEORDERFIFO = 0x0000300E, GX2_STAT_PA_SC_STALLED_BY_TILEFIFO = 0x0000300F, GX2_STAT_PA_SC_STALLED_BY_QUADFIFO = 0x00003010, GX2_STAT_PA_SC_STALLED_BY_DB_TILE = 0x00003011, GX2_STAT_PA_SC_STALLED_BY_DB_QUAD = 0x00003012, GX2_STAT_PA_SC_STALLED_BY_SX = 0x00003013, GX2_STAT_PA_SC_STALLED_BY_SPI = 0x00003014, GX2_STAT_PA_SC_SCISSOR_DISCARD = 0x00003015, GX2_STAT_PA_SC_BB_DISCARD = 0x00003016, GX2_STAT_PA_SC_MULTICHIP_PRIM_DISCARD = 0x00003017, GX2_STAT_PA_SC_SUPERTILE_COUNT = 0x00003018, GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H0 = 0x00003019, GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H1 = 0x0000301A, GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H2 = 0x0000301B, GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H3 = 0x0000301C, GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H4 = 0x0000301D, GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H5 = 0x0000301E, GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H6 = 0x0000301F, GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H7 = 0x00003020, GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H8 = 0x00003021, GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H9 = 0x00003022, GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H10 = 0x00003023, GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H11 = 0x00003024, GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H12 = 0x00003025, GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H13 = 0x00003026, GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H14 = 0x00003027, GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H15 = 0x00003028, GX2_STAT_PA_SC_SUPERTILE_PER_PRIM_H16 = 0x00003029, GX2_STAT_PA_SC_TILE_PER_PRIM_H0 = 0x0000302A, GX2_STAT_PA_SC_TILE_PER_PRIM_H1 = 0x0000302B, GX2_STAT_PA_SC_TILE_PER_PRIM_H2 = 0x0000302C, GX2_STAT_PA_SC_TILE_PER_PRIM_H3 = 0x0000302D, GX2_STAT_PA_SC_TILE_PER_PRIM_H4 = 0x0000302E, GX2_STAT_PA_SC_TILE_PER_PRIM_H5 = 0x0000302F, GX2_STAT_PA_SC_TILE_PER_PRIM_H6 = 0x00003030, GX2_STAT_PA_SC_TILE_PER_PRIM_H7 = 0x00003031, GX2_STAT_PA_SC_TILE_PER_PRIM_H8 = 0x00003032, GX2_STAT_PA_SC_TILE_PER_PRIM_H9 = 0x00003033, GX2_STAT_PA_SC_TILE_PER_PRIM_H10 = 0x00003034, GX2_STAT_PA_SC_TILE_PER_PRIM_H11 = 0x00003035, GX2_STAT_PA_SC_TILE_PER_PRIM_H12 = 0x00003036, GX2_STAT_PA_SC_TILE_PER_PRIM_H13 = 0x00003037, GX2_STAT_PA_SC_TILE_PER_PRIM_H14 = 0x00003038, GX2_STAT_PA_SC_TILE_PER_PRIM_H15 = 0x00003039, GX2_STAT_PA_SC_TILE_PER_PRIM_H16 = 0x0000303A, GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H0 = 0x0000303B, GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H1 = 0x0000303C, GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H2 = 0x0000303D, GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H3 = 0x0000303E, GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H4 = 0x0000303F, GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H5 = 0x00003040, GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H6 = 0x00003041, GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H7 = 0x00003042, GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H8 = 0x00003043, GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H9 = 0x00003044, GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H10 = 0x00003045, GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H11 = 0x00003046, GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H12 = 0x00003047, GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H13 = 0x00003048, GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H14 = 0x00003049, GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H15 = 0x0000304A, GX2_STAT_PA_SC_TILE_PER_SUPERTILE_H16 = 0x0000304B, GX2_STAT_PA_SC_TILE_PICKED_H1 = 0x0000304C, GX2_STAT_PA_SC_TILE_PICKED_H2 = 0x0000304D, GX2_STAT_PA_SC_TILE_PICKED_CONFLICT = 0x0000304E, GX2_STAT_PA_SC_QZ0_MULTICHIP_TILE_DISCARD = 0x0000304F, GX2_STAT_PA_SC_QZ1_MULTICHIP_TILE_DISCARD = 0x00003050, GX2_STAT_PA_SC_QZ0_TILE_COUNT = 0x00003051, GX2_STAT_PA_SC_QZ1_TILE_COUNT = 0x00003052, GX2_STAT_PA_SC_QZ0_TILE_COVERED_COUNT = 0x00003053, GX2_STAT_PA_SC_QZ1_TILE_COVERED_COUNT = 0x00003054, GX2_STAT_PA_SC_QZ0_TILE_NOT_COVERED_COUNT = 0x00003055, GX2_STAT_PA_SC_QZ1_TILE_NOT_COVERED_COUNT = 0x00003056, GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H0 = 0x00003057, GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H1 = 0x00003058, GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H2 = 0x00003059, GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H3 = 0x0000305A, GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H4 = 0x0000305B, GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H5 = 0x0000305C, GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H6 = 0x0000305D, GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H7 = 0x0000305E, GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H8 = 0x0000305F, GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H9 = 0x00003060, GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H10 = 0x00003061, GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H11 = 0x00003062, GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H12 = 0x00003063, GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H13 = 0x00003064, GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H14 = 0x00003065, GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H15 = 0x00003066, GX2_STAT_PA_SC_QZ0_QUAD_PER_TILE_H16 = 0x00003067, GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H0 = 0x00003068, GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H1 = 0x00003069, GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H2 = 0x0000306A, GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H3 = 0x0000306B, GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H4 = 0x0000306C, GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H5 = 0x0000306D, GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H6 = 0x0000306E, GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H7 = 0x0000306F, GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H8 = 0x00003070, GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H9 = 0x00003071, GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H10 = 0x00003072, GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H11 = 0x00003073, GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H12 = 0x00003074, GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H13 = 0x00003075, GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H14 = 0x00003076, GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H15 = 0x00003077, GX2_STAT_PA_SC_QZ1_QUAD_PER_TILE_H16 = 0x00003078, GX2_STAT_PA_SC_QZ0_QUAD_COUNT = 0x00003079, GX2_STAT_PA_SC_QZ1_QUAD_COUNT = 0x0000307A, GX2_STAT_PA_SC_QUAD0_NOT_PICKED_TB_R6XX = 0x0000307B, GX2_STAT_PA_SC_QUAD1_NOT_PICKED_TB_R6XX = 0x0000307C, GX2_STAT_PA_SC_QUAD2_NOT_PICKED_TB_R6XX = 0x0000307D, GX2_STAT_PA_SC_QUAD3_NOT_PICKED_TB_R6XX = 0x0000307E, GX2_STAT_PA_SC_P0_HIZ_TILE_COUNT = 0x0000307F, GX2_STAT_PA_SC_P1_HIZ_TILE_COUNT = 0x00003080, GX2_STAT_PA_SC_P2_HIZ_TILE_COUNT = 0x00003081, GX2_STAT_PA_SC_P3_HIZ_TILE_COUNT = 0x00003082, GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H0 = 0x00003083, GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H1 = 0x00003084, GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H2 = 0x00003085, GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H3 = 0x00003086, GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H4 = 0x00003087, GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H5 = 0x00003088, GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H6 = 0x00003089, GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H7 = 0x0000308A, GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H8 = 0x0000308B, GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H9 = 0x0000308C, GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H10 = 0x0000308D, GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H11 = 0x0000308E, GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H12 = 0x0000308F, GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H13 = 0x00003090, GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H14 = 0x00003091, GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H15 = 0x00003092, GX2_STAT_PA_SC_P0_HIZ_QUAD_PER_TILE_H16 = 0x00003093, GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H0 = 0x00003094, GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H1 = 0x00003095, GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H2 = 0x00003096, GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H3 = 0x00003097, GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H4 = 0x00003098, GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H5 = 0x00003099, GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H6 = 0x0000309A, GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H7 = 0x0000309B, GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H8 = 0x0000309C, GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H9 = 0x0000309D, GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H10 = 0x0000309E, GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H11 = 0x0000309F, GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H12 = 0x000030A0, GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H13 = 0x000030A1, GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H14 = 0x000030A2, GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H15 = 0x000030A3, GX2_STAT_PA_SC_P1_HIZ_QUAD_PER_TILE_H16 = 0x000030A4, GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H0 = 0x000030A5, GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H1 = 0x000030A6, GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H2 = 0x000030A7, GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H3 = 0x000030A8, GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H4 = 0x000030A9, GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H5 = 0x000030AA, GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H6 = 0x000030AB, GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H7 = 0x000030AC, GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H8 = 0x000030AD, GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H9 = 0x000030AE, GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H10 = 0x000030AF, GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H11 = 0x000030B0, GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H12 = 0x000030B1, GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H13 = 0x000030B2, GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H14 = 0x000030B3, GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H15 = 0x000030B4, GX2_STAT_PA_SC_P2_HIZ_QUAD_PER_TILE_H16 = 0x000030B5, GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H0 = 0x000030B6, GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H1 = 0x000030B7, GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H2 = 0x000030B8, GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H3 = 0x000030B9, GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H4 = 0x000030BA, GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H5 = 0x000030BB, GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H6 = 0x000030BC, GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H7 = 0x000030BD, GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H8 = 0x000030BE, GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H9 = 0x000030BF, GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H10 = 0x000030C0, GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H11 = 0x000030C1, GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H12 = 0x000030C2, GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H13 = 0x000030C3, GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H14 = 0x000030C4, GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H15 = 0x000030C5, GX2_STAT_PA_SC_P3_HIZ_QUAD_PER_TILE_H16 = 0x000030C6, GX2_STAT_PA_SC_P0_HIZ_QUAD_COUNT = 0x000030C7, GX2_STAT_PA_SC_P1_HIZ_QUAD_COUNT = 0x000030C8, GX2_STAT_PA_SC_P2_HIZ_QUAD_COUNT = 0x000030C9, GX2_STAT_PA_SC_P3_HIZ_QUAD_COUNT = 0x000030CA, GX2_STAT_PA_SC_P0_DETAIL_QUAD_COUNT = 0x000030CB, GX2_STAT_PA_SC_P1_DETAIL_QUAD_COUNT = 0x000030CC, GX2_STAT_PA_SC_P2_DETAIL_QUAD_COUNT = 0x000030CD, GX2_STAT_PA_SC_P3_DETAIL_QUAD_COUNT = 0x000030CE, GX2_STAT_PA_SC_P0_DETAIL_QUAD_WITH_1_PIX = 0x000030CF, GX2_STAT_PA_SC_P0_DETAIL_QUAD_WITH_2_PIX = 0x000030D0, GX2_STAT_PA_SC_P0_DETAIL_QUAD_WITH_3_PIX = 0x000030D1, GX2_STAT_PA_SC_P0_DETAIL_QUAD_WITH_4_PIX = 0x000030D2, GX2_STAT_PA_SC_P1_DETAIL_QUAD_WITH_1_PIX = 0x000030D3, GX2_STAT_PA_SC_P1_DETAIL_QUAD_WITH_2_PIX = 0x000030D4, GX2_STAT_PA_SC_P1_DETAIL_QUAD_WITH_3_PIX = 0x000030D5, GX2_STAT_PA_SC_P1_DETAIL_QUAD_WITH_4_PIX = 0x000030D6, GX2_STAT_PA_SC_P2_DETAIL_QUAD_WITH_1_PIX = 0x000030D7, GX2_STAT_PA_SC_P2_DETAIL_QUAD_WITH_2_PIX = 0x000030D8, GX2_STAT_PA_SC_P2_DETAIL_QUAD_WITH_3_PIX = 0x000030D9, GX2_STAT_PA_SC_P2_DETAIL_QUAD_WITH_4_PIX = 0x000030DA, GX2_STAT_PA_SC_P3_DETAIL_QUAD_WITH_1_PIX = 0x000030DB, GX2_STAT_PA_SC_P3_DETAIL_QUAD_WITH_2_PIX = 0x000030DC, GX2_STAT_PA_SC_P3_DETAIL_QUAD_WITH_3_PIX = 0x000030DD, GX2_STAT_PA_SC_P3_DETAIL_QUAD_WITH_4_PIX = 0x000030DE, GX2_STAT_PA_SC_EARLYZ_QUAD_COUNT = 0x000030DF, GX2_STAT_PA_SC_EARLYZ_QUAD_WITH_1_PIX = 0x000030E0, GX2_STAT_PA_SC_EARLYZ_QUAD_WITH_2_PIX = 0x000030E1, GX2_STAT_PA_SC_EARLYZ_QUAD_WITH_3_PIX = 0x000030E2, GX2_STAT_PA_SC_EARLYZ_QUAD_WITH_4_PIX = 0x000030E3, GX2_STAT_PA_SC_TILE_REORDER_DB_CONFLICT_R6XX = 0x000030E4, GX2_STAT_PA_SC_PKR_QUAD_PER_ROW_H1 = 0x000030E5, GX2_STAT_PA_SC_PKR_QUAD_PER_ROW_H2 = 0x000030E6, GX2_STAT_PA_SC_PKR_QUAD_PER_ROW_H3 = 0x000030E7, GX2_STAT_PA_SC_PKR_QUAD_PER_ROW_H4 = 0x000030E8, GX2_STAT_PA_SC_PKR_END_OF_VECTOR = 0x000030E9, GX2_STAT_PA_SC_PKR_CONTROL_XFER = 0x000030EA, GX2_STAT_PA_SC_PKR_DBHANG_FORCE_EOV = 0x000030EB, GX2_STAT_PA_SC_REG_SCLK_BUSY = 0x000030EC, GX2_STAT_PA_SC_GRP0_DYN_SCLK_BUSY = 0x000030ED, GX2_STAT_PA_SC_GRP1_DYN_SCLK_BUSY = 0x000030EE, GX2_STAT_PA_SC_GRP2_DYN_SCLK_BUSY = 0x000030EF, GX2_STAT_PA_SC_GRP3_DYN_SCLK_BUSY = 0x000030F0, GX2_STAT_PA_SC_GRP4_DYN_SCLK_BUSY = 0x000030F1, GX2_STAT_PA_SC_FIRST = GX2_STAT_PA_SC_SRPS_WINDOW_VALID, GX2_STAT_PA_SC_LAST = GX2_STAT_PA_SC_GRP4_DYN_SCLK_BUSY, GX2_STAT_VGT_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE = 0x00004000, GX2_STAT_VGT_VGT_SPI_ESVERT_VALID = 0x00004001, GX2_STAT_VGT_VGT_SPI_ESVERT_EOV = 0x00004002, GX2_STAT_VGT_VGT_SPI_ESVERT_STALLED = 0x00004003, GX2_STAT_VGT_VGT_SPI_ESVERT_STARVED_BUSY = 0x00004004, GX2_STAT_VGT_VGT_SPI_ESVERT_STARVED_IDLE = 0x00004005, GX2_STAT_VGT_VGT_SPI_ESVERT_STATIC = 0x00004006, GX2_STAT_VGT_VGT_SPI_ESTHREAD_IS_EVENT = 0x00004007, GX2_STAT_VGT_VGT_SPI_ESTHREAD_SEND = 0x00004008, GX2_STAT_VGT_VGT_SPI_GSPRIM_VALID = 0x00004009, GX2_STAT_VGT_VGT_SPI_GSPRIM_EOV = 0x0000400A, GX2_STAT_VGT_VGT_SPI_GSPRIM_CONT = 0x0000400B, GX2_STAT_VGT_VGT_SPI_GSPRIM_STALLED = 0x0000400C, GX2_STAT_VGT_VGT_SPI_GSPRIM_STARVED_BUSY = 0x0000400D, GX2_STAT_VGT_VGT_SPI_GSPRIM_STARVED_IDLE = 0x0000400E, GX2_STAT_VGT_VGT_SPI_GSPRIM_STATIC = 0x0000400F, GX2_STAT_VGT_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE = 0x00004010, GX2_STAT_VGT_VGT_SPI_GSTHREAD_IS_EVENT = 0x00004011, GX2_STAT_VGT_VGT_SPI_GSTHREAD_SEND = 0x00004012, GX2_STAT_VGT_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE = 0x00004013, GX2_STAT_VGT_VGT_SPI_VSVERT_SEND = 0x00004014, GX2_STAT_VGT_VGT_SPI_VSVERT_EOV = 0x00004015, GX2_STAT_VGT_VGT_SPI_VSVERT_STALLED = 0x00004016, GX2_STAT_VGT_VGT_SPI_VSVERT_STARVED_BUSY = 0x00004017, GX2_STAT_VGT_VGT_SPI_VSVERT_STARVED_IDLE = 0x00004018, GX2_STAT_VGT_VGT_SPI_VSVERT_STATIC = 0x00004019, GX2_STAT_VGT_VGT_SPI_VSTHREAD_IS_EVENT = 0x0000401A, GX2_STAT_VGT_VGT_SPI_VSTHREAD_SEND = 0x0000401B, GX2_STAT_VGT_VGT_PA_EVENT_WINDOW_ACTIVE = 0x0000401C, GX2_STAT_VGT_VGT_PA_CLIPV_SEND = 0x0000401D, GX2_STAT_VGT_VGT_PA_CLIPV_FIRSTVERT = 0x0000401E, GX2_STAT_VGT_VGT_PA_CLIPV_STALLED = 0x0000401F, GX2_STAT_VGT_VGT_PA_CLIPV_STARVED_BUSY = 0x00004020, GX2_STAT_VGT_VGT_PA_CLIPV_STARVED_IDLE = 0x00004021, GX2_STAT_VGT_VGT_PA_CLIPV_STATIC = 0x00004022, GX2_STAT_VGT_VGT_PA_CLIPP_SEND = 0x00004023, GX2_STAT_VGT_VGT_PA_CLIPP_EOP = 0x00004024, GX2_STAT_VGT_VGT_PA_CLIPP_IS_EVENT = 0x00004025, GX2_STAT_VGT_VGT_PA_CLIPP_NULL_PRIM = 0x00004026, GX2_STAT_VGT_VGT_PA_CLIPP_NEW_VTX_VECT = 0x00004027, GX2_STAT_VGT_VGT_PA_CLIPP_STALLED = 0x00004028, GX2_STAT_VGT_VGT_PA_CLIPP_STARVED_BUSY = 0x00004029, GX2_STAT_VGT_VGT_PA_CLIPP_STARVED_IDLE = 0x0000402A, GX2_STAT_VGT_VGT_PA_CLIPP_STATIC = 0x0000402B, GX2_STAT_VGT_VGT_PA_CLIPS_SEND = 0x0000402C, GX2_STAT_VGT_VGT_PA_CLIPS_STALLED = 0x0000402D, GX2_STAT_VGT_VGT_PA_CLIPS_STARVED_BUSY = 0x0000402E, GX2_STAT_VGT_VGT_PA_CLIPS_STARVED_IDLE = 0x0000402F, GX2_STAT_VGT_VGT_PA_CLIPS_STATIC = 0x00004030, GX2_STAT_VGT_RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 0x00004031, GX2_STAT_VGT_RBIU_IM_FIFO_STARVED = 0x00004032, GX2_STAT_VGT_RBIU_IM_FIFO_STALLED = 0x00004033, GX2_STAT_VGT_RBIU_DR_FIFO_STARVED = 0x00004034, GX2_STAT_VGT_RBIU_DR_FIFO_STALLED = 0x00004035, GX2_STAT_VGT_RBIU_DI_FIFO_STARVED = 0x00004036, GX2_STAT_VGT_RBIU_DI_FIFO_STALLED = 0x00004037, GX2_STAT_VGT_MC_LAT_BIN_0 = 0x00004038, GX2_STAT_VGT_MC_LAT_BIN_1 = 0x00004039, GX2_STAT_VGT_MC_LAT_BIN_2 = 0x0000403A, GX2_STAT_VGT_MC_LAT_BIN_3 = 0x0000403B, GX2_STAT_VGT_MC_LAT_BIN_4 = 0x0000403C, GX2_STAT_VGT_MC_LAT_BIN_5 = 0x0000403D, GX2_STAT_VGT_MC_LAT_BIN_6 = 0x0000403E, GX2_STAT_VGT_MC_LAT_BIN_7 = 0x0000403F, GX2_STAT_VGT_VGT_BUSY = 0x00004040, GX2_STAT_VGT_VGT_GS_BUSY = 0x00004041, GX2_STAT_VGT_ESVERT_STALLED_ES_TBL = 0x00004042, GX2_STAT_VGT_ESVERT_STALLED_GS_TBL = 0x00004043, GX2_STAT_VGT_ESVERT_STALLED_GS_EVENT = 0x00004044, GX2_STAT_VGT_ESVERT_STALLED_GSPRIM = 0x00004045, GX2_STAT_VGT_GSPRIM_STALLED_ES_TBL = 0x00004046, GX2_STAT_VGT_GSPRIM_STALLED_GS_TBL = 0x00004047, GX2_STAT_VGT_GSPRIM_STALLED_GS_EVENT = 0x00004048, GX2_STAT_VGT_GSPRIM_STALLED_ESVERT = 0x00004049, GX2_STAT_VGT_ESTHREAD_STALLED_ES_RB_FULL = 0x0000404A, GX2_STAT_VGT_ESTHREAD_STALLED_SPI_BP = 0x0000404B, GX2_STAT_VGT_COUNTERS_AVAIL_STALLED = 0x0000404C, GX2_STAT_VGT_GS_RB_SPACE_AVAIL_STALLED = 0x0000404D, GX2_STAT_VGT_GS_ISSUE_RTR_STALLED = 0x0000404E, GX2_STAT_VGT_GSTHREAD_STALLED = 0x0000404F, GX2_STAT_VGT_ES_CACHE_INVLD_STALLED = 0x00004050, GX2_STAT_VGT_WAIT_FOR_ES_DONE_STALLED = 0x00004051, GX2_STAT_VGT_CM_STALLED_BY_GOG = 0x00004052, GX2_STAT_VGT_CM_READING_STALLED = 0x00004053, GX2_STAT_VGT_CM_STALLED_BY_GSFETCH_DONE = 0x00004054, GX2_STAT_VGT_GOG_VS_TBL_STALLED = 0x00004055, GX2_STAT_VGT_GOG_OUT_INDX_STALLED = 0x00004056, GX2_STAT_VGT_GOG_OUT_PRIM_STALLED = 0x00004057, GX2_STAT_VGT_GS_RB_INVLD_STALLED = 0x00004058, GX2_STAT_VGT_GOG_BUSY = 0x00004059, GX2_STAT_VGT_REUSED_VS_INDICES = 0x0000405A, GX2_STAT_VGT_SCLK_REG_VLD_EVENT = 0x0000405B, GX2_STAT_VGT_SCLK_INPUT_VLD_EVENT = 0x0000405C, GX2_STAT_VGT_SCLK_CORE_VLD_EVENT = 0x0000405D, GX2_STAT_VGT_SCLK_INVAL_VLD_EVENT = 0x0000405E, GX2_STAT_VGT_SCLK_GS_VLD_EVENT = 0x0000405F, GX2_STAT_VGT_FIRST = GX2_STAT_VGT_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE, GX2_STAT_VGT_LAST = GX2_STAT_VGT_SCLK_GS_VLD_EVENT, GX2_STAT_SQ_NONE = 0x00005000, /// Clock cycles. Thread-type independent. GX2_STAT_SQ_CYCLES = 0x00005001, /// Clock cycles while SQ is reporting that it is busy. Thread-type independent. GX2_STAT_SQ_BUSY_CYCLES = 0x00005002, /// Number of cycles we have a thread or an event. Thread-type dependent. GX2_STAT_SQ_ANY_BUSY_PER_TYPE = 0x00005003, /// Number of events. Thread-type dependent. Caveat: Event counts are slightly unpredictable because they do not have an associated state and because we don`t count events when we don`t have active threads. GX2_STAT_SQ_EVENTS_PER_TYPE = 0x00005004, /// Number cycles we have an event. Thread-type dependent. GX2_STAT_SQ_EVENTS_BUSY_PER_TYPE = 0x00005005, /// Number of events in the pipeline per clock. GX2_STAT_SQ_EVENT_LEVEL_PER_TYPE = 0x00005006, /// Number of valid items per thread. Thread-type dependent. GX2_STAT_SQ_ITEMS_PER_TYPE = 0x00005007, /// Number of threads with a valid item in a position >= 48. Thread-type dependent. GX2_STAT_SQ_ITEMS_GT_48_PER_TYPE = 0x00005008, /// Number of threads with a valid item in a position >= 32. GX2_STAT_SQ_ITEMS_GT_32_PER_TYPE = 0x00005009, /// Number of threads with a valid item in a position >= 16. Thread-type dependent. GX2_STAT_SQ_ITEMS_GT_16_PER_TYPE = 0x0000500A, /// Number of valid pixel shader quads per thread. Deterministic. GX2_STAT_SQ_QUADS = 0x0000500B, /// Number cycles we have a thread. Thread-type dependent. GX2_STAT_SQ_THREADS_BUSY_PER_TYPE = 0x0000500C, /// Number of threads. Thread-type dependent. GX2_STAT_SQ_THREADS_PER_TYPE = 0x0000500D, /// Number of threads in the pipeline per clock. Thread-type dependent. GX2_STAT_SQ_THREAD_LEVEL_PER_TYPE = 0x0000500E, /// Number of threads waiting to be created. Thread-type dependent. GX2_STAT_SQ_THREAD_LEVEL_WAIT_CREATE_PER_TYPE = 0x0000500F, /// Number of threads with parameter cache unallocated. Thread-type dependent. GX2_STAT_SQ_THREAD_LEVEL_UNALLOC_PARAM_PER_TYPE = 0x00005010, /// Number of threads with pixel buffer unallocated. Thread-type dependent. GX2_STAT_SQ_THREAD_LEVEL_UNALLOC_PIX_PER_TYPE = 0x00005011, /// Number of threads with position buffer unallocated. GX2_STAT_SQ_THREAD_LEVEL_UNALLOC_POS_PER_TYPE = 0x00005012, /// Number of existing non-PS threads sharing the set of enabled thread-types with other selected NONPS counters. GX2_STAT_SQ_THREADS_NONPS = 0x00005013, /// Number of existing non-PS threads per cycle sharing the set of enabled thread-types with other selected NONPS counters. GX2_STAT_SQ_THREAD_LEVEL_NONPS = 0x00005014, /// Number of non-PS threads waiting for export space to be allocated. Must share the set of enabled thread-types with other selected NONPS counters. GX2_STAT_SQ_THREAD_LEVEL_WAIT_ALLOC_NONPS = 0x00005015, /// Number of non-PS threads waiting for instructions to be fetched or completed. Must share the set of enabled thread-types with other selected SHARED_TYPESET counters. GX2_STAT_SQ_THREAD_LEVEL_WAIT_OTHER_NONPS = 0x00005016, /// Number of PS threads waiting for pixel buffer to be allocated. GX2_STAT_SQ_THREAD_LEVEL_WAIT_ALLOC_PS = 0x00005017, /// Number of PS threads waiting for instructions to be fetched or completed. GX2_STAT_SQ_THREAD_LEVEL_WAIT_OTHER_PS = 0x00005018, /// Number of CF instruction issues. Thread-type dependent. Deterministic. GX2_STAT_SQ_CF_INST_ISSUES_PER_TYPE = 0x00005019, /// Number of times only a single instruction is issued on a cycle. GX2_STAT_SQ_CF_INST_ISSUE_ONE = 0x0000501A, /// Number of times two instructions are issued in a single cycle. Thread-type independent. GX2_STAT_SQ_CF_INST_ISSUE_TWO = 0x0000501B, /// Number of cycles when threads exist but no threads are ready to issue. Thread-type dependent. GX2_STAT_SQ_CF_INST_ISSUE_IDLE_PER_TYPE = 0x0000501C, /// Number of instructions executed in Fetch Shader Mode. Does not include initial CALL_FS instruction. Thread-type dependent. Deterministic. GX2_STAT_SQ_CF_INST_ISSUE_FS_PER_TYPE = 0x0000501D, /// Number of CF_ALU instructions issued.Thread-type dependent. GX2_STAT_SQ_CF_INST_ISSUE_ALU_PER_TYPE = 0x0000501E, /// Number of CF_TF instructions issued. Thread-type dependent. GX2_STAT_SQ_CF_INST_ISSUE_TF_PER_TYPE = 0x0000501F, /// Number of CF_VF instructions issued. Thread-type dependent. GX2_STAT_SQ_CF_INST_ISSUE_VF_PER_TYPE = 0x00005020, /// Number of Export instructions issued. Thread-type dependent. GX2_STAT_SQ_CF_INST_ISSUE_EX_PER_TYPE = 0x00005021, /// Number of SMX write instructions issued. Thread-type dependent. GX2_STAT_SQ_CF_INST_ISSUE_SMX_WR_PER_TYPE = 0x00005022, /// Number of SMX read instructions issued. Thread-type dependent. GX2_STAT_SQ_CF_INST_ISSUE_SMX_RD_PER_TYPE = 0x00005023, /// Number of geometry instructions issued. Thread-type dependent. GX2_STAT_SQ_CF_INST_ISSUE_GF_PER_TYPE = 0x00005024, /// Number of non-ALU/TF/VF/EX/SMX/GF instructions issued. Thread-type dependent. GX2_STAT_SQ_CF_INST_ISSUE_OTHER_PER_TYPE = 0x00005025, /// Number of ALU CF tags processed. Thread-type dependent. GX2_STAT_SQ_CF_INST_ISSUE_ALU_CF_PER_TYPE = 0x00005026, /// Number of OTHER and ALU CF tags processed. Thread-type dependent. GX2_STAT_SQ_CF_INST_ISSUE_BL_PER_TYPE = 0x00005027, /// Number of ALU instructions scheduled and trivially rejected. Thread-type dependent. GX2_STAT_SQ_CF_INST_REJECT_ALU_PER_TYPE = 0x00005028, /// Number of times a Texture Fetch instruction is scheduled and trivially rejected. Thread-type dependent. GX2_STAT_SQ_CF_INST_REJECT_TF_PER_TYPE = 0x00005029, /// Number of times a Vertex Fetch instruction is scheduled and trivially rejected. Thread-type dependent. GX2_STAT_SQ_CF_INST_REJECT_VF_PER_TYPE = 0x0000502A, /// Number of times an Export instruction is scheduled and trivially rejected. Thread-type dependent. GX2_STAT_SQ_CF_INST_REJECT_EX_PER_TYPE = 0x0000502B, /// Number of times a SMX write instruction is scheduled and trivially rejected. Thread-type dependent. GX2_STAT_SQ_CF_INST_REJECT_SMX_WR_PER_TYPE = 0x0000502C, /// Number of times a SMX read instruction is scheduled and trivially rejected. Thread-type dependent. GX2_STAT_SQ_CF_INST_REJECT_SMX_RD_PER_TYPE = 0x0000502D, /// Number of geometry instructions trivially rejected. Thread-type dependent. GX2_STAT_SQ_CF_INST_REJECT_GF_PER_TYPE = 0x0000502E, /// Number of non-ALU/TF/VF/EX/SMX/GF instructions rejected. Thread-type dependent. GX2_STAT_SQ_CF_INST_REJECT_OTHER_PER_TYPE = 0x0000502F, /// Number of instructions sent to ALU. Thread-type dependent. GX2_STAT_SQ_CF_INST_FIFO_SEND_ALU_PER_TYPE = 0x00005030, /// Number of instructions sent to Texture Fetch unit. Thread-type dependent. GX2_STAT_SQ_CF_INST_FIFO_SEND_TF_PER_TYPE = 0x00005031, /// Number of instructions sent to Vertex Fetch unit. Thread-type dependent. GX2_STAT_SQ_CF_INST_FIFO_SEND_VF_PER_TYPE = 0x00005032, /// Number of instructions sent to Export unit. Thread-type dependent. GX2_STAT_SQ_CF_INST_FIFO_SEND_EX_PER_TYPE = 0x00005033, /// Number of write instructions sent to SMX Export unit. Thread-type dependent. GX2_STAT_SQ_CF_INST_FIFO_SEND_SMX_WR_PER_TYPE = 0x00005034, /// Number of read instructions sent to SMX Export unit. Thread-type dependent. GX2_STAT_SQ_CF_INST_FIFO_SEND_SMX_RD_PER_TYPE = 0x00005035, /// Number of geometry instructions executed. Thread-type dependent. Deterministic. GX2_STAT_SQ_CF_INST_FIFO_SEND_GF_PER_TYPE = 0x00005036, /// Number of non-ALU/TF/VF/EX/SMX/GF instructions executed. Thread-type dependent. GX2_STAT_SQ_CF_INST_FIFO_SEND_OTHER_PER_TYPE = 0x00005037, /// Number of instructions sent to ALU with no kcache regions locked. Thread-type dependent. GX2_STAT_SQ_CF_INST_FIFO_SEND_ALU_KCACHE_NONE_PER_TYPE = 0x00005038, /// Number of instructions sent to ALU with one kcache regions locked. Thread-type dependent. GX2_STAT_SQ_CF_INST_FIFO_SEND_ALU_KCACHE_ONE_PER_TYPE = 0x00005039, /// Number of instructions sent to ALU with two kcache regions locked. Thread-type dependent. GX2_STAT_SQ_CF_INST_FIFO_SEND_ALU_KCACHE_TWO_PER_TYPE = 0x0000503A, /// Number of kcache region locks in instructions sent to ALU. Thread-type dependent. GX2_STAT_SQ_CF_INST_FIFO_SEND_ALU_KCACHE_PER_TYPE = 0x0000503B, /// Number of ALU units full on a cycle. Thread-type independent. GX2_STAT_SQ_CF_INST_FIFO_FULL_ALU = 0x0000503C, /// Number of cycles the Texture Fetch unit was full. Thread-type independent. GX2_STAT_SQ_CF_INST_FIFO_FULL_TF = 0x0000503D, /// Number of cycles the Vertex Fetch unit was full. Thread-type independent. GX2_STAT_SQ_CF_INST_FIFO_FULL_VF = 0x0000503E, /// Number of cycles the Export unit was full. Thread-type independent. GX2_STAT_SQ_CF_INST_FIFO_FULL_EX = 0x0000503F, /// Number of cycles the SMX Export unit was full. Thread-type independent. GX2_STAT_SQ_CF_INST_FIFO_FULL_SMX = 0x00005040, /// Number of cycles the Geometry Fifo was full. Thread-type independent. GX2_STAT_SQ_CF_INST_FIFO_FULL_GF = 0x00005041, GX2_STAT_SQ_CF_INST_FIFO_FULL_OTHER = 0x00005042, /// Number of credits available for all ALU units. Thread-type independent. GX2_STAT_SQ_CF_INST_FIFO_LEVEL_ALU = 0x00005043, /// Number of credits available for TF unit. Thread-type independent. GX2_STAT_SQ_CF_INST_FIFO_LEVEL_TF = 0x00005044, /// Number of credits available for VF unit. Thread-type independent. GX2_STAT_SQ_CF_INST_FIFO_LEVEL_VF = 0x00005045, /// Number of credits available for EX unit. Thread-type independent. GX2_STAT_SQ_CF_INST_FIFO_LEVEL_EX = 0x00005046, /// Number of credits available for SMX unit. Thread-type independent. GX2_STAT_SQ_CF_INST_FIFO_LEVEL_SMX = 0x00005047, /// Number of credits available for Geometry Fifo. Thread-type independent. GX2_STAT_SQ_CF_INST_FIFO_LEVEL_GF = 0x00005048, GX2_STAT_SQ_CF_INST_FIFO_LEVEL_OTHER = 0x00005049, /// Number of ALU units empty on a cycle. Thread-type independent. GX2_STAT_SQ_CF_INST_FIFO_EMPTY_ALU = 0x0000504A, /// Number of cycles the Texture Fetch unit was empty. Thread-type independent. GX2_STAT_SQ_CF_INST_FIFO_EMPTY_TF = 0x0000504B, /// Number of cycles the Vertex Fetch unit was empty. Thread-type independent. GX2_STAT_SQ_CF_INST_FIFO_EMPTY_VF = 0x0000504C, /// Number of cycles the Export unit was empty. Thread-type independent. GX2_STAT_SQ_CF_INST_FIFO_EMPTY_EX = 0x0000504D, /// Number of cycles the SMX unit was empty. Thread-type independent. GX2_STAT_SQ_CF_INST_FIFO_EMPTY_SMX = 0x0000504E, /// Number of cycles the Geometry fifo was empty. Thread-type independent. GX2_STAT_SQ_CF_INST_FIFO_EMPTY_GF = 0x0000504F, GX2_STAT_SQ_CF_INST_FIFO_EMPTY_OTHER = 0x00005050, /// Number of instructions outstanding for all ALU units. Thread-type dependent. GX2_STAT_SQ_CF_INST_ISSUE_LEVEL_ALU_PER_TYPE = 0x00005051, /// Number of instructions outstanding for TF unit. Thread-type dependent. GX2_STAT_SQ_CF_INST_ISSUE_LEVEL_TF_PER_TYPE = 0x00005052, /// Number of instructions outstanding for VF unit. Thread-type dependent. GX2_STAT_SQ_CF_INST_ISSUE_LEVEL_VF_PER_TYPE = 0x00005053, /// Number of instructions outstanding for EX unit. Thread-type dependent. GX2_STAT_SQ_CF_INST_ISSUE_LEVEL_EX_PER_TYPE = 0x00005054, /// Number of write instructions outstanding for SMX unit. Thread-type dependent. GX2_STAT_SQ_CF_INST_ISSUE_LEVEL_SMX_WR_PER_TYPE = 0x00005055, /// Number of read instructions outstanding for SMX unit. Thread-type dependent. GX2_STAT_SQ_CF_INST_ISSUE_LEVEL_SMX_RD_PER_TYPE = 0x00005056, /// Number of instructions outstanding for Geometry Fifo. Thread-type dependent. GX2_STAT_SQ_CF_INST_ISSUE_LEVEL_GF_PER_TYPE = 0x00005057, /// Number of instructions outstanding for non-ALU/TF/VF/EX/SMX/GF. Thread-type dependent. GX2_STAT_SQ_CF_INST_ISSUE_LEVEL_OTHER_PER_TYPE = 0x00005058, /// Number of times user specified CF address is executed. Deterministic. GX2_STAT_SQ_CF_INST_CHECKPOINT = 0x00005059, /// Number of CF instructions executed including and after the specified CF address. GX2_STAT_SQ_CF_INST_CHECKPOINT_BEFORE = 0x0000505A, /// Number of items valid for execution of instruction at CF address. Deterministic. GX2_STAT_SQ_CF_INST_CHECKPOINT_ITEMS_VALID = 0x0000505B, /// Number of times no items are valid for execution of instruction at CF address. GX2_STAT_SQ_CF_INST_CHECKPOINT_ITEMS_VALID_NONE = 0x0000505C, /// Number of items active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). GX2_STAT_SQ_CF_INST_CHECKPOINT_ITEMS_ACTIVE = 0x0000505D, /// Number of times no items are active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). GX2_STAT_SQ_CF_INST_CHECKPOINT_ITEMS_ACTIVE_NONE = 0x0000505E, /// Number of pixel quads active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). GX2_STAT_SQ_CF_INST_CHECKPOINT_QUADS_ACTIVE = 0x0000505F, /// Number of pixel quads valid for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). GX2_STAT_SQ_CF_INST_CHECKPOINT_QUADS_VALID = 0x00005060, /// Number of times a thread first reaches the CF address. GX2_STAT_SQ_CF_INST_CHECKPOINT_THREADS = 0x00005061, /// Number of threads that have reached the CF address per cycle. GX2_STAT_SQ_CF_INST_CHECKPOINT_THREAD_LEVEL = 0x00005062, /// Number of CF fetch requests from cache. Thread-type dependent. GX2_STAT_SQ_CF_INST_FETCH_PER_TYPE = 0x00005063, /// Number of CF fetch return cycles from cache. Thread-type dependent. GX2_STAT_SQ_CF_INST_FETCH_RETURNS_PER_TYPE = 0x00005064, /// Number of CF instructions requested from cache. Thread-type dependent. GX2_STAT_SQ_CF_INST_FETCH_INSTS_PER_TYPE = 0x00005065, /// Number of CF level requested from cache. Thread-type dependent. GX2_STAT_SQ_CF_INST_FETCH_LEVEL_PER_TYPE = 0x00005066, /// Number of times we did not issue the second instruction in a pair. Does not include instructions after PROGRAM_END. Thread-type dependent. GX2_STAT_SQ_CF_INST_FETCH_EXTRA_PER_TYPE = 0x00005067, /// Number of requests passing through the fetch fifo. Thread-type independent. GX2_STAT_SQ_CF_INST_FETCH_FIFO_SEND = 0x00005068, /// Control Flow Fetch fifo entry level. Thread-type independent. GX2_STAT_SQ_CF_INST_FETCH_FIFO_LEVEL = 0x00005069, /// Number of cycles when the CF fetch fifo is stalling issues. Thread-type independent. GX2_STAT_SQ_CF_INST_FETCH_FIFO_STALL = 0x0000506A, /// Number of requests passing through the cache fifo. Thread-type independent. GX2_STAT_SQ_CF_INST_CACHE_FIFO_SEND = 0x0000506B, /// Number of credits in cache. Thread-type independent. GX2_STAT_SQ_CF_INST_CACHE_FIFO_LEVEL = 0x0000506C, /// Number of cycles when we have no cache credits. Thread-type independent. GX2_STAT_SQ_CF_INST_CACHE_FIFO_FULL = 0x0000506D, /// Number of issues that need to be accounted for to avoid overflowing the done fifo. Thread-type independent. GX2_STAT_SQ_CF_INST_ISSUE_DONES = 0x0000506E, /// Number of issues pending at any given time that need to be accounted for to avoid overflowing the done fifo. Thread-type independent. GX2_STAT_SQ_CF_INST_ISSUE_DONE_LEVEL = 0x0000506F, /// Stalls triggered to avoid overflowing the done fifo. Thread-type independent. GX2_STAT_SQ_CF_INST_ISSUE_DONE_STALL = 0x00005070, /// Number of items passing through the done fifo. Thread-type independent. GX2_STAT_SQ_CF_INST_ISSUE_DONE_FIFO_SEND = 0x00005071, /// Control Flow Done fifo entry level. Thread-type independent. GX2_STAT_SQ_CF_INST_ISSUE_DONE_FIFO_LEVEL = 0x00005072, /// Macro sequencer alu update fifo send. Thread-type independent. GX2_STAT_SQ_CF_INST_ALU_UPDATE_FIFO_SEND = 0x00005073, /// Macro sequencer alu update fifo level. Thread-type independent. GX2_STAT_SQ_CF_INST_ALU_UPDATE_FIFO_LEVEL = 0x00005074, /// Number of cycles when the MS alu update fifo is stalling issues and alu returns. Thread-type independent. GX2_STAT_SQ_CF_INST_ALU_UPDATE_FIFO_STALL = 0x00005075, /// Number of threads and events in the ofifo. Thread-type dependent. GX2_STAT_SQ_OFIFO_LEVEL_PER_TYPE = 0x00005076, /// Number of cycles the SX event fifo is full. Thread-type dependent. GX2_STAT_SQ_SX_EVENT_FIFO_FULL_PER_TYPE = 0x00005077, /// Number of ALU instruction groups executed. Thread-type dependent. GX2_STAT_SQ_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE = 0x00005078, /// Number of ALU individual alu instructions executed. Thread-type dependent. GX2_STAT_SQ_ALU_CLAUSE_INSTRS_PER_TYPE = 0x00005079, /// Number of ALU instruction groups which use const-waterfall. Thread-type dependent. GX2_STAT_SQ_ALU_KWATERFALL_PER_TYPE = 0x0000507A, /// Number of ALU instruction groups which use gpr-waterfall. Thread-type dependent. GX2_STAT_SQ_ALU_GPRWATERFALL_PER_TYPE = 0x0000507B, /// Number of ALU instructions which use one or more constant (literal, kcache, or kfile). Thread-type dependent. GX2_STAT_SQ_ALU_K_INSTR_PER_TYPE = 0x0000507C, /// Number of times ALU Icache read was denied - cache busy. Thread-type dependent. GX2_STAT_SQ_ALU_ICACHE_BUSY_PER_TYPE = 0x0000507D, /// Number of times ALU Kcache/Kfile read was denied - cache busy. Thread-type dependent. GX2_STAT_SQ_ALU_KCACHE_BUSY_PER_TYPE = 0x0000507E, /// Number of instruction cycles idle waiting for MOVA to complete. Thread-type dependent. GX2_STAT_SQ_ALU_MOVA_IDLE_WAIT_PER_TYPE = 0x0000507F, /// Number of times (1 every 4 clocks) ALU has clauses in input fifo but no clauses locked -- ALU is idle. Thread-type independent. GX2_STAT_SQ_ALU_LOCK_WAIT = 0x00005080, /// Number of read requests to the ALU I-cache. Thread-type dependent. Deterministic. GX2_STAT_SQ_ALU_ICACHE_READS_PER_TYPE = 0x00005081, /// Number of read requests to the ALU K-cache/K-file. Thread-type dependent. Deterministic. GX2_STAT_SQ_ALU_KCACHE_READS_PER_TYPE = 0x00005082, /// Number of times the done-fifo is full and that caused a stall. Thread-type independent. GX2_STAT_SQ_ALU_DONE_FIFO_FULL = 0x00005083, /// Number of times more than one SIMD tried to execute MOVA, and one was denied access. Thread-type dependent. GX2_STAT_SQ_ALU_MOVA_WAIT_PER_TYPE = 0x00005084, /// Number of threads waiting in the alu sequencer`s input fifo each cycle, of the selected thread type. GX2_STAT_SQ_ALU_THREADS_IN_FIFO_PER_TYPE = 0x00005085, GX2_STAT_SQ_UNUSED_006 = 0x00005086, GX2_STAT_SQ_UNUSED_007 = 0x00005087, /// Number of cycles the Tex/Vtx Icache denied a read request (busy). Thread-type dependent. GX2_STAT_SQ_TV_ICACHE_WAIT_PER_TYPE = 0x00005088, GX2_STAT_SQ_UNUSED_010 = 0x00005089, GX2_STAT_SQ_UNUSED_001 = 0x0000508A, GX2_STAT_SQ_UNUSED_002 = 0x0000508B, /// Number of times the TF had data to send to TA, but the TA input fifo was full. Thread-type dependent. GX2_STAT_SQ_TF_TA_STALL_PER_TYPE = 0x0000508C, /// Number of times the VF had data to send to VC, but the VC instruction input fifo was full. Thread-type dependent. GX2_STAT_SQ_VF_VC_INSTR_STALL_PER_TYPE = 0x0000508D, /// SQ_PERF_SEL_VF_VC_INDEX_STALL_PER_TYPE: Number of times the VF had data to send to VC, but the VC index input fifo was full. Thread-type dependent. GX2_STAT_SQ_VF_VC_INDEX_STALL_PER_TYPE = 0x0000508E, GX2_STAT_SQ_UNUSED_003 = 0x0000508F, GX2_STAT_SQ_UNUSED_008 = 0x00005090, GX2_STAT_SQ_UNUSED_004 = 0x00005091, GX2_STAT_SQ_UNUSED_009 = 0x00005092, /// Number of exports (seen by export-seq). GX2_STAT_SQ_EXPORT_INSTR_PER_TYPE = 0x00005093, /// Number of clocks where export unit is idle. Thread-type independent. GX2_STAT_SQ_EXPORT_IDLE = 0x00005094, /// Number of clocks SMX export stalled waiting for alloc. Thread-type independent. GX2_STAT_SQ_EXPORT_SMX_AL_STALL = 0x00005095, /// Number of clocks Param.cache alloc was stalled. Thread-type independent. GX2_STAT_SQ_EXPORT_PC_AL_STALL = 0x00005096, /// Number of clocks Position export alloc was stalled. Thread-type independent. GX2_STAT_SQ_EXPORT_POS_AL_STALL = 0x00005097, /// Number of clocks Pixel export alloc was stalled. Thread-type independent. GX2_STAT_SQ_EXPORT_PIX_AL_STALL = 0x00005098, /// Number of position export cycles (4 clocks), * burst count). Thread-type independent. GX2_STAT_SQ_EXPORT_POS_CYCLE = 0x00005099, /// Number of pixel export cycles (4 clocks), * burst count). Thread-type independent. GX2_STAT_SQ_EXPORT_PIX_CYCLE = 0x0000509A, /// Number of param.cache export cycles (4 clocks), * burst count). Thread-type independent. GX2_STAT_SQ_EXPORT_PC_CYCLE = 0x0000509B, /// Number of SMX export cycles (4 clocks), * burst count). Thread-type dependent. GX2_STAT_SQ_EXPORT_SMX_CYCLE_PER_TYPE = 0x0000509C, /// Number of cache invalidation (surface synchronization) operations of any kind. GX2_STAT_SQ_CACHE_INVAL_ANY = 0x0000509D, /// Number of cache invalidation (surface synchronization) operations that invalidate the whole cache (due to a large invalidation region). Thread-type independent. GX2_STAT_SQ_CACHE_INVAL_ALL = 0x0000509E, /// Number of cache invalidation (surface synchronization) cycles, not including full invalidations; indicates the size of the invalidation regions in 4K byte increments. Thread-type independent. GX2_STAT_SQ_CACHE_INVAL_CYCLES = 0x0000509F, /// Number of CF instruction cache hits (it was found in the cache). Thread-type independent. GX2_STAT_SQ_CF_ICACHE_HITS = 0x000050A0, /// Number of TV instruction cache hits (it was found in the cache). Thread-type independent. GX2_STAT_SQ_TF_ICACHE_HITS = 0x000050A1, GX2_STAT_SQ_VF_ICACHE_HITS = 0x000050A2, /// Number of ALU instruction cache hits (it was found in the cache). Thread-type independent. GX2_STAT_SQ_ALU_ICACHE_HITS = 0x000050A3, /// Number of ALU constant cache hits (it was found in the cache). Thread-type independent. GX2_STAT_SQ_ALU_KCACHE_HITS = 0x000050A4, /// Number of CF instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. GX2_STAT_SQ_CF_ICACHE_MISSES = 0x000050A5, /// Number of TV instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. GX2_STAT_SQ_TF_ICACHE_MISSES = 0x000050A6, GX2_STAT_SQ_VF_ICACHE_MISSES = 0x000050A7, /// Number of ALU instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. GX2_STAT_SQ_ALU_ICACHE_MISSES = 0x000050A8, /// Number of ALU constant cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. GX2_STAT_SQ_ALU_KCACHE_MISSES = 0x000050A9, /// Number of CF instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. GX2_STAT_SQ_CF_ICACHE_DUP_MISSES = 0x000050AA, /// Number of TV instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. GX2_STAT_SQ_TF_ICACHE_DUP_MISSES = 0x000050AB, GX2_STAT_SQ_VF_ICACHE_DUP_MISSES = 0x000050AC, /// Number of ALU instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. GX2_STAT_SQ_ALU_ICACHE_DUP_MISSES = 0x000050AD, /// Number of ALU constant cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. GX2_STAT_SQ_ALU_KCACHE_DUP_MISSES = 0x000050AE, /// Number of CF instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. GX2_STAT_SQ_CF_ICACHE_ACCESSES = 0x000050AF, /// Number of TV instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. GX2_STAT_SQ_TF_ICACHE_ACCESSES = 0x000050B0, GX2_STAT_SQ_VF_ICACHE_ACCESSES = 0x000050B1, /// Number of ALU instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. GX2_STAT_SQ_ALU_ICACHE_ACCESSES = 0x000050B2, /// Number of ALU constant cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. GX2_STAT_SQ_ALU_KCACHE_ACCESSES = 0x000050B3, /// Count of CF instruction cache requests stored in the input FIFO. Thread-type independent. GX2_STAT_SQ_CF_ICACHE_INPUT_FIFO_ENTRIES = 0x000050B4, /// Count of TV instruction cache requests stored in the input FIFO. Thread-type independent. GX2_STAT_SQ_TF_ICACHE_INPUT_FIFO_ENTRIES = 0x000050B5, GX2_STAT_SQ_VF_ICACHE_INPUT_FIFO_ENTRIES = 0x000050B6, /// Count of ALU instruction cache requests stored in the input FIFO. Thread-type independent. GX2_STAT_SQ_ALU_ICACHE_INPUT_FIFO_ENTRIES = 0x000050B7, /// Count of ALU constant cache requests stored in the input FIFO. Thread-type independent. GX2_STAT_SQ_ALU_KCACHE_INPUT_FIFO_ENTRIES = 0x000050B8, /// Number of CF instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. GX2_STAT_SQ_CF_ICACHE_MISS_MEM_STALL = 0x000050B9, /// Number of TV instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. GX2_STAT_SQ_TF_ICACHE_MISS_MEM_STALL = 0x000050BA, GX2_STAT_SQ_VF_ICACHE_MISS_MEM_STALL = 0x000050BB, /// Number of ALU instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. GX2_STAT_SQ_ALU_ICACHE_MISS_MEM_STALL = 0x000050BC, /// Number of ALU constant cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. GX2_STAT_SQ_ALU_KCACHE_MISS_MEM_STALL = 0x000050BD, /// Number of CF instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. GX2_STAT_SQ_CF_ICACHE_MISS_FIFO_STALL = 0x000050BE, /// Number of TV instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. GX2_STAT_SQ_TF_ICACHE_MISS_FIFO_STALL = 0x000050BF, GX2_STAT_SQ_VF_ICACHE_MISS_FIFO_STALL = 0x000050C0, /// Number of ALU instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. GX2_STAT_SQ_ALU_ICACHE_MISS_FIFO_STALL = 0x000050C1, /// Number of ALU constant cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. GX2_STAT_SQ_ALU_KCACHE_MISS_FIFO_STALL = 0x000050C2, /// Number of CF instruction cache cycles that are a cache hit but are stalled due to processing previous misses. Thread-type independent. GX2_STAT_SQ_CF_ICACHE_HIT_STALL = 0x000050C3, /// Number of CF instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. GX2_STAT_SQ_CF_ICACHE_MISS_LOCKED_STALL = 0x000050C4, /// Number of TV instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. GX2_STAT_SQ_TF_ICACHE_MISS_LOCKED_STALL = 0x000050C5, GX2_STAT_SQ_VF_ICACHE_MISS_LOCKED_STALL = 0x000050C6, /// Number of ALU instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. GX2_STAT_SQ_ALU_ICACHE_MISS_LOCKED_STALL = 0x000050C7, /// Number of ALU constant cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. GX2_STAT_SQ_ALU_KCACHE_MISS_LOCKED_STALL = 0x000050C8, /// Count of CF instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. GX2_STAT_SQ_CF_ICACHE_LOCKED_TAGS = 0x000050C9, /// Count of TV instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. GX2_STAT_SQ_TF_ICACHE_LOCKED_TAGS = 0x000050CA, GX2_STAT_SQ_VF_ICACHE_LOCKED_TAGS = 0x000050CB, /// Count of ALU instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. GX2_STAT_SQ_ALU_ICACHE_LOCKED_TAGS = 0x000050CC, /// Count of ALU constant cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. GX2_STAT_SQ_ALU_KCACHE_LOCKED_TAGS = 0x000050CD, /// Count of CF instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. GX2_STAT_SQ_CF_ICACHE_MISS_LOCKED_TAGS = 0x000050CE, /// Count of TV instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. GX2_STAT_SQ_TF_ICACHE_MISS_LOCKED_TAGS = 0x000050CF, GX2_STAT_SQ_VF_ICACHE_MISS_LOCKED_TAGS = 0x000050D0, /// Count of ALU instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. GX2_STAT_SQ_ALU_ICACHE_MISS_LOCKED_TAGS = 0x000050D1, /// Count of ALU constant cache tags that are currently locked during a cache miss cycle. Thread-type independent. GX2_STAT_SQ_ALU_KCACHE_MISS_LOCKED_TAGS = 0x000050D2, /// Number of cache to memory controller requests of any type. Thread-type independent. GX2_STAT_SQ_CACHE_MEM_REQUESTS = 0x000050D3, /// Number of CF instruction cache to memory controller requests. Thread-type independent. GX2_STAT_SQ_CF_ICACHE_MEM_REQUESTS = 0x000050D4, /// Number of TV instruction cache to memory controller requests. Thread-type independent. GX2_STAT_SQ_TV_ICACHE_MEM_REQUESTS = 0x000050D5, /// Number of ALU instruction cache to memory controller requests. Thread-type independent. GX2_STAT_SQ_ALU_ICACHE_MEM_REQUESTS = 0x000050D6, /// Number of ALU constant cache to memory controller requests. Thread-type independent. GX2_STAT_SQ_ALU_KCACHE_MEM_REQUESTS = 0x000050D7, /// Number of times a read to the CF icache memory was blocked by a write from a memory return. Thread-type independent. GX2_STAT_SQ_CF_ICACHE_RD_WR_COLLISION = 0x000050D8, /// Number of times processing a hit is stalled by processing a now-resident miss. Thread-type independent. GX2_STAT_SQ_CF_ICACHE_MISS_HIT_RD_COLLISION = 0x000050D9, /// Count of the number of outstanding CF instruction cache to memory controller requests of any type. Thread-type independent. GX2_STAT_SQ_CF_ICACHE_MEM_REQUESTS_IN_FLIGHT = 0x000050DA, /// Count of the number of outstanding TV instruction cache to memory controller requests of any type. Thread-type independent. GX2_STAT_SQ_TV_ICACHE_MEM_REQUESTS_IN_FLIGHT = 0x000050DB, /// Count of the number of outstanding ALU instruction cache to memory controller requests of any type. Thread-type independent. GX2_STAT_SQ_ALU_ICACHE_MEM_REQUESTS_IN_FLIGHT = 0x000050DC, /// Count of the number of outstanding ALU constant cache to memory controller requests of any type. Thread-type independent. GX2_STAT_SQ_ALU_KCACHE_MEM_REQUESTS_IN_FLIGHT = 0x000050DD, /// Count of the number of CF instruction cache misses waiting in the miss FIFO. Thread-type independent. GX2_STAT_SQ_CF_ICACHE_MISS_FIFO_MISSES = 0x000050DE, /// Count of the number of TV instruction cache misses waiting in the miss FIFO. Thread-type independent. GX2_STAT_SQ_TF_ICACHE_MISS_FIFO_MISSES = 0x000050DF, GX2_STAT_SQ_VF_ICACHE_MISS_FIFO_MISSES = 0x000050E0, /// Count of the number of ALU instruction cache misses waiting in the miss FIFO. Divided by 2. Thread-type independent. GX2_STAT_SQ_ALU_ICACHE_MISS_FIFO_MISSES = 0x000050E1, /// Count of the number of ALU constant cache misses waiting in the miss FIFO. Divided by 2. Thread-type independent. GX2_STAT_SQ_ALU_KCACHE_MISS_FIFO_MISSES = 0x000050E2, /// Count of the number of outstanding cache to memory controller requests of any type. Divided by 2. Thread-type independent. GX2_STAT_SQ_CACHE_MEM_REQUESTS_IN_FLIGHT = 0x000050E3, /// Number of cache to memory controller cycles that are stalled. Thread-type independent. GX2_STAT_SQ_CACHE_MEM_STALL = 0x000050E4, /// Clock cycles GRBM stalled due to Timestamp-64 FIFO full. GX2_STAT_SQ_TM_TS64_STALL = 0x000050E5, /// Clock cycles GRBM stalled due to ALU constant overflow buffer full. GX2_STAT_SQ_TM_ALU_CONST_STALL = 0x000050E6, /// Clock cycles GRBM stalled due to Loop constant overflow buffer full. GX2_STAT_SQ_TM_LOOP_CONST_STALL = 0x000050E7, /// Clock cycles GRBM stalled due to VertexBase/InstantStart constant overflow buffer full. GX2_STAT_SQ_TM_TEX_BASE_CONST_STALL = 0x000050E8, /// Clock cycles GRBM stalled due to Texture Sampler constant overflow buffer full. GX2_STAT_SQ_TM_TEX_SAMPLER_STALL = 0x000050E9, /// Clock cycles GRBM stalled due to Texture Resource constant overflow buffer full. GX2_STAT_SQ_TM_TEX_RESOURCE_STALL = 0x000050EA, GX2_STAT_SQ_UNUSED_005 = 0x000050EB, /// Number of texture-fetch instructions executed by the Texture cache, including killed fetches. Thread-type dependent. GX2_STAT_SQ_TA_TEX_INSTRS_PER_TYPE = 0x000050EC, /// Number of vertex-fetch instructions executed by the Texture cache, including killed fetches. Thread-type dependent. GX2_STAT_SQ_TA_VTX_INSTRS_PER_TYPE = 0x000050ED, /// Number of instructions executed by the Vertex cache, including killed fetches. Thread-type dependent. GX2_STAT_SQ_VC_INSTRS_PER_TYPE = 0x000050EE, /// Number of cycles the TF input FIFO had clauses, none were locked. Thread-type independent GX2_STAT_SQ_TV_LOCK_WAIT = 0x000050EF, /// Number of times an TA fetch (16 pix or verts) was executed as a src-c export. GX2_STAT_SQ_TA_SRC_C = 0x000050F0, /// Number of times a VC fetch (16 pix or verts) was executed as a src-c export. GX2_STAT_SQ_VC_SRC_C = 0x000050F1, /// Number of fetch instructions killed (vertex semantic failed or gpr out of range). GX2_STAT_SQ_TV_KILLED_FETCH_PER_TYPE = 0x000050F2, /// Number of null fetches issued (null = issue empty fetch at end of clause due to killed fetches). GX2_STAT_SQ_TV_NULL_FETCH_PER_TYPE = 0x000050F3, /// Number of threads waiting in the fetch sequencer`s input fifo each cycle, of the selected thread type. GX2_STAT_SQ_TV_THREADS_IN_FIFO_PER_TYPE = 0x000050F4, /// Internal export per-quadpipe queue level average. GX2_STAT_SQ_EXPORT_SPQ_LEVEL = 0x000050F5, /// Internal export per-quadpipe stall cycles. GX2_STAT_SQ_EXPORT_SPQ_STALL = 0x000050F6, GX2_STAT_SQ_FIRST = GX2_STAT_SQ_NONE, GX2_STAT_SQ_LAST = GX2_STAT_SQ_EXPORT_SPQ_STALL, GX2_STAT_SPI_VS_WINDOW_VALID = 0x00006000, GX2_STAT_SPI_VS_BUSY = 0x00006001, GX2_STAT_SPI_VS_INPUT_STARVED = 0x00006002, GX2_STAT_SPI_VS_VSR_STALL = 0x00006003, GX2_STAT_SPI_VS_VSR_FULL = 0x00006004, GX2_STAT_SPI_VS_GPR_STALL = 0x00006005, GX2_STAT_SPI_VS_INPUT_STALL = 0x00006006, GX2_STAT_SPI_VS_MEM_STALL = 0x00006007, GX2_STAT_SPI_VS_TB_FULL = 0x00006008, GX2_STAT_SPI_VS_EV_FIFO_FULL = 0x00006009, GX2_STAT_SPI_VS_THREAD_STALL = 0x0000600A, GX2_STAT_SPI_VS_EVENT_VECTOR = 0x0000600B, GX2_STAT_SPI_VS_VECTOR = 0x0000600C, GX2_STAT_SPI_GS_WINDOW_VALID = 0x0000600D, GX2_STAT_SPI_GS_BUSY = 0x0000600E, GX2_STAT_SPI_GS_INPUT_STARVED = 0x0000600F, GX2_STAT_SPI_GS_GSR_STALL = 0x00006010, GX2_STAT_SPI_GS_GSR_FULL = 0x00006011, GX2_STAT_SPI_GS_GPR_STALL = 0x00006012, GX2_STAT_SPI_GS_INPUT_STALL = 0x00006013, GX2_STAT_SPI_GS_MEM_STALL = 0x00006014, GX2_STAT_SPI_GS_TB_FULL = 0x00006015, GX2_STAT_SPI_GS_EV_FIFO_FULL = 0x00006016, GX2_STAT_SPI_GS_THREAD_STALL = 0x00006017, GX2_STAT_SPI_GS_EVENT_VECTOR = 0x00006018, GX2_STAT_SPI_GS_VECTOR = 0x00006019, GX2_STAT_SPI_ES_WINDOW_VALID = 0x0000601A, GX2_STAT_SPI_ES_BUSY = 0x0000601B, GX2_STAT_SPI_ES_INPUT_STARVED = 0x0000601C, GX2_STAT_SPI_ES_ESR_STALL = 0x0000601D, GX2_STAT_SPI_ES_ESR_FULL = 0x0000601E, GX2_STAT_SPI_ES_GPR_STALL = 0x0000601F, GX2_STAT_SPI_ES_INPUT_STALL = 0x00006020, GX2_STAT_SPI_ES_MEM_STALL = 0x00006021, GX2_STAT_SPI_ES_TB_FULL = 0x00006022, GX2_STAT_SPI_ES_EV_FIFO_FULL = 0x00006023, GX2_STAT_SPI_ES_THREAD_STALL = 0x00006024, GX2_STAT_SPI_ES_EVENT_VECTOR = 0x00006025, GX2_STAT_SPI_ES_VECTOR = 0x00006026, GX2_STAT_SPI_ITER_CTRL_WINDOW_VALID = 0x00006027, GX2_STAT_SPI_ITER_CTRL_ACTIVE = 0x00006028, GX2_STAT_SPI_ITER_CTRL_FULL = 0x00006029, GX2_STAT_SPI_ITER_CTRL_STALL_PV = 0x0000602A, GX2_STAT_SPI_ITER_CTRL_STALL_EV = 0x0000602B, GX2_STAT_SPI_ITER_STARVED = 0x0000602C, GX2_STAT_SPI_ITER_ACTIVE = 0x0000602D, GX2_STAT_SPI_ITER_FULL = 0x0000602E, GX2_STAT_SPI_ITER_STALL = 0x0000602F, GX2_STAT_SPI_PTR_BUFF_WINDOW_VALID = 0x00006030, GX2_STAT_SPI_PTR_BUFF_BUSY = 0x00006031, GX2_STAT_SPI_PTR_BUFF_ACTIVE = 0x00006032, GX2_STAT_SPI_PTR_BUFF_STALL = 0x00006033, GX2_STAT_SPI_PTR_BUFF_GPR_STALL = 0x00006034, GX2_STAT_SPI_PTR_BUFF_MEM_STALL = 0x00006035, GX2_STAT_SPI_PTR_BUFF_IJ_STALL = 0x00006036, GX2_STAT_SPI_PTR_BUFF_CTL_STALL = 0x00006037, GX2_STAT_SPI_PTR_BUFF_EVENT_VECTOR = 0x00006038, GX2_STAT_SPI_PTR_BUFF_VECTOR = 0x00006039, GX2_STAT_SPI_PTR_BUFF_2_PASS_VEC = 0x0000603A, GX2_STAT_SPI_PTR_BUFF_3_PASS_VEC = 0x0000603B, GX2_STAT_SPI_PTR_BUFF_4_PASS_VEC = 0x0000603C, GX2_STAT_SPI_PCTL0_INPUT_STALL = 0x0000603D, GX2_STAT_SPI_PCTL0_PI_PPB_STALL = 0x0000603E, GX2_STAT_SPI_PCTL0_THREAD_STALL = 0x0000603F, GX2_STAT_SPI_PCTL0_PI_BUSY = 0x00006040, GX2_STAT_SPI_PCTL0_SX_VALID = 0x00006041, GX2_STAT_SPI_PCTL1_INPUT_STALL = 0x00006042, GX2_STAT_SPI_PCTL1_PI_PPB_STALL = 0x00006043, GX2_STAT_SPI_PCTL1_THREAD_STALL = 0x00006044, GX2_STAT_SPI_PCTL1_PI_BUSY = 0x00006045, GX2_STAT_SPI_PCTL1_SX_VALID = 0x00006046, GX2_STAT_SPI_PS_TB_FULL = 0x00006047, GX2_STAT_SPI_PS_EV_FIFO_FULL = 0x00006048, GX2_STAT_SPI_THREAD_CONFLICT = 0x00006049, GX2_STAT_SPI_VS_STK_STALL = 0x0000604A, GX2_STAT_SPI_VS_TMP_STALL = 0x0000604B, GX2_STAT_SPI_GS_STK_STALL = 0x0000604C, GX2_STAT_SPI_GS_TMP_STALL = 0x0000604D, GX2_STAT_SPI_ES_STK_STALL = 0x0000604E, GX2_STAT_SPI_ES_TMP_STALL = 0x0000604F, GX2_STAT_SPI_PS_STK_STALL = 0x00006050, GX2_STAT_SPI_PS_TMP_STALL = 0x00006051, GX2_STAT_SPI_PS_FBUF_STALL = 0x00006052, GX2_STAT_SPI_PTR_BUFF_FPOS = 0x00006053, GX2_STAT_SPI_PTR_BUFF_DEALLOC = 0x00006054, GX2_STAT_SPI_PTR_BUFF_0_CONFLICT_VEC = 0x00006055, GX2_STAT_SPI_PTR_BUFF_1_CONFLICT_VEC = 0x00006056, GX2_STAT_SPI_PTR_BUFF_2_CONFLICT_VEC = 0x00006057, GX2_STAT_SPI_PTR_BUFF_3_CONFLICT_VEC = 0x00006058, GX2_STAT_SPI_PTR_BUFF_4_CONFLICT_VEC = 0x00006059, GX2_STAT_SPI_PTR_BUFF_5_CONFLICT_VEC = 0x0000605A, GX2_STAT_SPI_DYN_GPR_PS_SKIP_SIMD = 0x0000605B, GX2_STAT_SPI_DYN_GPR_VS_SKIP_SIMD = 0x0000605C, GX2_STAT_SPI_DYN_GPR_GS_SKIP_SIMD = 0x0000605D, GX2_STAT_SPI_DYN_GPR_ES_SKIP_SIMD = 0x0000605E, GX2_STAT_SPI_DYN_GPR_PS_WRAP_SOONER = 0x0000605F, GX2_STAT_SPI_DYN_GPR_VS_WRAP_SOONER = 0x00006060, GX2_STAT_SPI_DYN_GPR_GS_WRAP_SOONER = 0x00006061, GX2_STAT_SPI_DYN_GPR_ES_WRAP_SOONER = 0x00006062, GX2_STAT_SPI_CLKGATE_BUSY_STALL = 0x00006063, GX2_STAT_SPI_CLKGATE_ACTIVE_STALL = 0x00006064, GX2_STAT_SPI_CLKGATE_ALL_CLOCKS_ON = 0x00006065, GX2_STAT_SPI_CLKGATE_SPI_CLOCKS_ON = 0x00006066, GX2_STAT_SPI_FIRST = GX2_STAT_SPI_VS_WINDOW_VALID, GX2_STAT_SPI_LAST = GX2_STAT_SPI_CLKGATE_SPI_CLOCKS_ON, GX2_STAT_SX_GS_FLUSH_EVENT_IN = 0x00007000, GX2_STAT_SX_ES_FLUSH_EVENT_IN = 0x00007001, GX2_STAT_SX_TS_EVENT_IN = 0x00007002, GX2_STAT_SX_CONTEXT_EVENT_IN = 0x00007003, GX2_STAT_SX_GS_FLUSH_EVENT_OUT = 0x00007004, GX2_STAT_SX_ES_FLUSH_EVENT_OUT = 0x00007005, GX2_STAT_SX_TS_EVENT_OUT = 0x00007006, GX2_STAT_SX_CONTEXT_EVENT_OUT = 0x00007007, GX2_STAT_SX_DB0_IDLE_CYCLES = 0x00007008, GX2_STAT_SX_DB0_STALL_CYCLES = 0x00007009, GX2_STAT_SX_DB0_HALF_QUADS = 0x0000700a, GX2_STAT_SX_DB0_PIXELS = 0x0000700b, GX2_STAT_SX_DB0_PRED_PIXELS = 0x0000700c, GX2_STAT_SX_DB1_IDLE_CYCLES = 0x0000700d, GX2_STAT_SX_DB1_STALL_CYCLES = 0x0000700e, GX2_STAT_SX_DB1_HALF_QUADS = 0x0000700f, GX2_STAT_SX_DB1_PIXELS = 0x00007010, GX2_STAT_SX_DB1_PRED_PIXELS = 0x00007011, GX2_STAT_SX_DB2_IDLE_CYCLES = 0x00007012, GX2_STAT_SX_DB2_STALL_CYCLES = 0x00007013, GX2_STAT_SX_DB2_HALF_QUADS = 0x00007014, GX2_STAT_SX_DB2_PIXELS = 0x00007015, GX2_STAT_SX_DB2_PRED_PIXELS = 0x00007016, GX2_STAT_SX_DB3_IDLE_CYCLES = 0x00007017, GX2_STAT_SX_DB3_STALL_CYCLES = 0x00007018, GX2_STAT_SX_DB3_HALF_QUADS = 0x00007019, GX2_STAT_SX_DB3_PIXELS = 0x0000701a, GX2_STAT_SX_DB3_PRED_PIXELS = 0x0000701b, GX2_STAT_SX_DB4_IDLE_CYCLES = 0x0000701c, GX2_STAT_SX_DB4_STALL_CYCLES = 0x0000701d, GX2_STAT_SX_DB4_HALF_QUADS = 0x0000701e, GX2_STAT_SX_DB4_PIXELS = 0x0000701f, GX2_STAT_SX_DB4_PRED_PIXELS = 0x00007020, GX2_STAT_SX_DB5_IDLE_CYCLES = 0x00007021, GX2_STAT_SX_DB5_STALL_CYCLES = 0x00007022, GX2_STAT_SX_DB5_HALF_QUADS = 0x00007023, GX2_STAT_SX_DB5_PIXELS = 0x00007024, GX2_STAT_SX_DB5_PRED_PIXELS = 0x00007025, GX2_STAT_SX_DB6_IDLE_CYCLES = 0x00007026, GX2_STAT_SX_DB6_STALL_CYCLES = 0x00007027, GX2_STAT_SX_DB6_HALF_QUADS = 0x00007028, GX2_STAT_SX_DB6_PIXELS = 0x00007029, GX2_STAT_SX_DB6_PRED_PIXELS = 0x0000702a, GX2_STAT_SX_DB7_IDLE_CYCLES = 0x0000702b, GX2_STAT_SX_DB7_STALL_CYCLES = 0x0000702c, GX2_STAT_SX_DB7_HALF_QUADS = 0x0000702d, GX2_STAT_SX_DB7_PIXELS = 0x0000702e, GX2_STAT_SX_DB7_PRED_PIXELS = 0x0000702f, GX2_STAT_SX_PA_IDLE_CYCLES = 0x00007030, GX2_STAT_SX_PA_REQ = 0x00007031, GX2_STAT_SX_PA_POS = 0x00007032, GX2_STAT_SX_SPI_REQ_0 = 0x00007033, GX2_STAT_SX_SPI_REQ_1 = 0x00007034, GX2_STAT_SX_CLOCK_PS = 0x00007035, GX2_STAT_SX_CLOCK_VS = 0x00007036, GX2_STAT_SX_CLOCK_GS = 0x00007037, GX2_STAT_SX_CLOCK_ES = 0x00007038, GX2_STAT_SX_CLOCK = 0x00007039, GX2_STAT_SX_DB0_ACK_REQUEST = 0x0000703a, GX2_STAT_SX_DB1_ACK_REQUEST = 0x0000703b, GX2_STAT_SX_DB2_ACK_REQUEST = 0x0000703c, GX2_STAT_SX_DB3_ACK_REQUEST = 0x0000703d, GX2_STAT_SX_DB4_ACK_REQUEST = 0x0000703e, GX2_STAT_SX_DB5_ACK_REQUEST = 0x0000703f, GX2_STAT_SX_DB6_ACK_REQUEST = 0x00007040, GX2_STAT_SX_DB7_ACK_REQUEST = 0x00007041, GX2_STAT_SX_SC_CLOCK = 0x00007042, GX2_STAT_SX_PS_ADJUSTED_CLOCK = 0x00007043, GX2_STAT_SX_DB0_ALPHA_KILLED_PIXELS = 0x00007044, GX2_STAT_SX_DB1_ALPHA_KILLED_PIXELS = 0x00007045, GX2_STAT_SX_DB2_ALPHA_KILLED_PIXELS = 0x00007046, GX2_STAT_SX_DB3_ALPHA_KILLED_PIXELS = 0x00007047, GX2_STAT_SX_GATE_EN1 = 0x00007048, GX2_STAT_SX_GATE_EN2 = 0x00007049, GX2_STAT_SX_GATE_EN3 = 0x0000704a, GX2_STAT_SX_GATE_EN4 = 0x0000704b, GX2_STAT_SX_GATE_EN5 = 0x0000704c, GX2_STAT_SX_PIX_CLK_VALID = 0x0000704d, GX2_STAT_SX_SC_CLK_VALID = 0x0000704e, GX2_STAT_SX_PA_CLK_VALID = 0x0000704f, GX2_STAT_SX_REG_CLK_VALID = 0x00007050, GX2_STAT_SX_SMX_CLK_VALID = 0x00007051, GX2_STAT_SX_ARB_QP0_COLLISION = 0x00007052, GX2_STAT_SX_ARB_QP1_COLLISION = 0x00007053, GX2_STAT_SX_ARB_QP2_COLLISION = 0x00007054, GX2_STAT_SX_ARB_QP3_COLLISION = 0x00007055, GX2_STAT_SX_FIRST = GX2_STAT_SX_GS_FLUSH_EVENT_IN, GX2_STAT_SX_LAST = GX2_STAT_SX_ARB_QP3_COLLISION, GX2_STAT_SMX_CACHE_IDLE_CYCLES = 0x00008000, GX2_STAT_SMX_CACHE_STALL_CYCLES = 0x00008001, GX2_STAT_SMX_WRITE_REQS = 0x00008002, GX2_STAT_SMX_WRITE_REQS_PS = 0x00008003, GX2_STAT_SMX_WRITE_REQS_VS = 0x00008004, GX2_STAT_SMX_WRITE_REQS_GS = 0x00008005, GX2_STAT_SMX_WRITE_REQS_ES = 0x00008006, GX2_STAT_SMX_WRITE_REQS_STREAM0 = 0x00008007, GX2_STAT_SMX_WRITE_REQS_STREAM1 = 0x00008008, GX2_STAT_SMX_WRITE_REQS_STREAM2 = 0x00008009, GX2_STAT_SMX_WRITE_REQS_STREAM3 = 0x0000800a, GX2_STAT_SMX_WRITE_REQS_SCRATCH = 0x0000800b, GX2_STAT_SMX_WRITE_REQS_REDUCTION = 0x0000800c, GX2_STAT_SMX_WRITE_REQS_RING = 0x0000800d, GX2_STAT_SMX_WRITE_REQS_FBUFFER = 0x0000800e, GX2_STAT_SMX_WRITE_REQS_SCATTER = 0x0000800f, GX2_STAT_SMX_VF_STALL = 0x00008010, GX2_STAT_SMX0_NUMBER_OF_PARTIAL_LINES = 0x00008011, GX2_STAT_SMX0_NUMBER_OF_ES_FLUSH = 0x00008012, GX2_STAT_SMX0_NUMBER_OF_GS_FLUSH = 0x00008013, GX2_STAT_SMX0_NUMBER_OF_SYNC_FLUSH = 0x00008014, GX2_STAT_SMX0_NUMBER_OF_ACK_FLUSH = 0x00008015, GX2_STAT_SMX0_NUMBER_OF_FLUSH = 0x00008016, GX2_STAT_SMX0_DW_WRITTEN = 0x00008017, GX2_STAT_SMX0_DW_MISS = 0x00008018, GX2_STAT_SMX0_DB_STALL = 0x00008019, GX2_STAT_SMX1_NUMBER_OF_PARTIAL_LINES = 0x0000801a, GX2_STAT_SMX1_NUMBER_OF_ES_FLUSH = 0x0000801b, GX2_STAT_SMX1_NUMBER_OF_GS_FLUSH = 0x0000801c, GX2_STAT_SMX1_NUMBER_OF_SYNC_FLUSH = 0x0000801d, GX2_STAT_SMX1_NUMBER_OF_ACK_FLUSH = 0x0000801e, GX2_STAT_SMX1_NUMBER_OF_FLUSH = 0x0000801f, GX2_STAT_SMX1_DW_WRITTEN = 0x00008020, GX2_STAT_SMX1_DW_MISS = 0x00008021, GX2_STAT_SMX1_DB_STALL = 0x00008022, GX2_STAT_SMX2_NUMBER_OF_PARTIAL_LINES = 0x00008023, GX2_STAT_SMX2_NUMBER_OF_ES_FLUSH = 0x00008024, GX2_STAT_SMX2_NUMBER_OF_GS_FLUSH = 0x00008025, GX2_STAT_SMX2_NUMBER_OF_SYNC_FLUSH = 0x00008026, GX2_STAT_SMX2_NUMBER_OF_ACK_FLUSH = 0x00008027, GX2_STAT_SMX2_NUMBER_OF_FLUSH = 0x00008028, GX2_STAT_SMX2_DW_WRITTEN = 0x00008029, GX2_STAT_SMX2_DW_MISS = 0x0000802a, GX2_STAT_SMX2_DB_STALL = 0x0000802b, GX2_STAT_SMX3_NUMBER_OF_PARTIAL_LINES = 0x0000802c, GX2_STAT_SMX3_NUMBER_OF_ES_FLUSH = 0x0000802d, GX2_STAT_SMX3_NUMBER_OF_GS_FLUSH = 0x0000802e, GX2_STAT_SMX3_NUMBER_OF_SYNC_FLUSH = 0x0000802f, GX2_STAT_SMX3_NUMBER_OF_ACK_FLUSH = 0x00008030, GX2_STAT_SMX3_NUMBER_OF_FLUSH = 0x00008031, GX2_STAT_SMX3_DW_WRITTEN = 0x00008032, GX2_STAT_SMX3_DW_MISS = 0x00008033, GX2_STAT_SMX3_DB_STALL = 0x00008034, GX2_STAT_SMX0_SET0_CNT = 0x00008035, GX2_STAT_SMX0_SET1_CNT = 0x00008036, GX2_STAT_SMX0_SET2_CNT = 0x00008037, GX2_STAT_SMX0_SET3_CNT = 0x00008038, GX2_STAT_SMX0_SET4_CNT = 0x00008039, GX2_STAT_SMX0_SET5_CNT = 0x0000803a, GX2_STAT_SMX0_SET6_CNT = 0x0000803b, GX2_STAT_SMX0_SET7_CNT = 0x0000803c, GX2_STAT_SMX1_SET0_CNT = 0x0000803d, GX2_STAT_SMX1_SET1_CNT = 0x0000803e, GX2_STAT_SMX1_SET2_CNT = 0x0000803f, GX2_STAT_SMX1_SET3_CNT = 0x00008040, GX2_STAT_SMX1_SET4_CNT = 0x00008041, GX2_STAT_SMX1_SET5_CNT = 0x00008042, GX2_STAT_SMX1_SET6_CNT = 0x00008043, GX2_STAT_SMX1_SET7_CNT = 0x00008044, GX2_STAT_SMX2_SET0_CNT = 0x00008045, GX2_STAT_SMX2_SET1_CNT = 0x00008046, GX2_STAT_SMX2_SET2_CNT = 0x00008047, GX2_STAT_SMX2_SET3_CNT = 0x00008048, GX2_STAT_SMX2_SET4_CNT = 0x00008049, GX2_STAT_SMX2_SET5_CNT = 0x0000804a, GX2_STAT_SMX2_SET6_CNT = 0x0000804b, GX2_STAT_SMX2_SET7_CNT = 0x0000804c, GX2_STAT_SMX3_SET0_CNT = 0x0000804d, GX2_STAT_SMX3_SET1_CNT = 0x0000804e, GX2_STAT_SMX3_SET2_CNT = 0x0000804f, GX2_STAT_SMX3_SET3_CNT = 0x00008050, GX2_STAT_SMX3_SET4_CNT = 0x00008051, GX2_STAT_SMX3_SET5_CNT = 0x00008052, GX2_STAT_SMX3_SET6_CNT = 0x00008053, GX2_STAT_SMX3_SET7_CNT = 0x00008054, GX2_STAT_SMX0_PROBE_COLLISION = 0x00008055, GX2_STAT_SMX1_PROBE_COLLISION = 0x00008056, GX2_STAT_SMX2_PROBE_COLLISION = 0x00008057, GX2_STAT_SMX3_PROBE_COLLISION = 0x00008058, GX2_STAT_SMX_FIRST = GX2_STAT_SMX_CACHE_IDLE_CYCLES, GX2_STAT_SMX_LAST = GX2_STAT_SMX3_PROBE_COLLISION, GX2_STAT_TD_TD_BUSY = 0x00009000, GX2_STAT_TD_INPUT_BUSY = 0x00009008, GX2_STAT_TD_OUTPUT_BUSY = 0x00009009, GX2_STAT_TD_SAMPLE_LATENCY_FIFO_BUSY = 0x0000900a, GX2_STAT_TD_CONSTANT_LATENCY_FIFO_BUSY = 0x0000900b, GX2_STAT_TD_FASTPATH_BUSY = 0x0000900c, GX2_STAT_TD_SH_FIFO_BUSY = 0x0000900d, GX2_STAT_TD_PHASE_SYNC_BUSY = 0x0000900e, GX2_STAT_TD_DATAOUT_FIFO_BUSY = 0x0000900f, GX2_STAT_TD_LATENCY_FIFO_BUSY_PIPE_IDLE = 0x00009010, GX2_STAT_TD_SYNC_PHASE_COUNT = 0x00009011, GX2_STAT_TD_VC_DATA_RETURN = 0x00009012, GX2_STAT_TD_STALL_DUE_TO_VC = 0x00009013, GX2_STAT_TD_STALL_DUE_TO_RSP = 0x00009014, GX2_STAT_TD_STALL_DUE_TO_VC_OR_RSP = 0x00009015, GX2_STAT_TD_TD_REG_SCLK_VLD = 0x00009016, GX2_STAT_TD_TD_LOCAL_CG_DYN_SCLK_GRP0_EN = 0x00009017, GX2_STAT_TD_TD_LOCAL_CG_DYN_SCLK_GRP1_EN = 0x00009018, GX2_STAT_TD_FIRST = GX2_STAT_TD_TD_BUSY, GX2_STAT_TD_LAST = GX2_STAT_TD_TD_LOCAL_CG_DYN_SCLK_GRP1_EN, GX2_STAT_TA_TA_BUSY = 0x0000a000, GX2_STAT_TA_GRADIENT_BUSY = 0x0000a001, GX2_STAT_TA_GRADIENT_FIFO_BUSY = 0x0000a002, GX2_STAT_TA_LOD_BUSY = 0x0000a003, GX2_STAT_TA_LOD_FIFO_BUSY = 0x0000a004, GX2_STAT_TA_ADDRESSER_BUSY = 0x0000a005, GX2_STAT_TA_ADDRESSER_FIFO_BUSY = 0x0000a006, GX2_STAT_TA_ALIGNER_BUSY = 0x0000a007, GX2_STAT_TA_PIX_0_QUAD = 0x0000a008, GX2_STAT_TA_PIX_1_QUAD = 0x0000a009, GX2_STAT_TA_PIX_2_QUAD = 0x0000a00a, GX2_STAT_TA_PIX_3_QUAD = 0x0000a00b, GX2_STAT_TA_PIX_4_QUAD = 0x0000a00c, GX2_STAT_TA_INPUT_CYCLES = 0x0000a010, GX2_STAT_TA_GRADIENT_BALANCING_CYCLES = 0x0000a011, GX2_STAT_TA_GRADIENT_CYCLES = 0x0000a012, GX2_STAT_TA_WALKER_BALANCING_CYCLES = 0x0000a013, GX2_STAT_TA_WALKER_CYCLES = 0x0000a014, GX2_STAT_TA_ALIGNER_BALANCING_CYCLES = 0x0000a015, GX2_STAT_TA_ALIGNER_CYCLES = 0x0000a016, GX2_STAT_TA_MIP_1_CYCLE_PIXELS = 0x0000a018, GX2_STAT_TA_MIP_2_CYCLE_PIXELS = 0x0000a019, GX2_STAT_TA_VOL_1_CYCLE_PIXELS = 0x0000a01a, GX2_STAT_TA_VOL_2_CYCLE_PIXELS = 0x0000a01b, GX2_STAT_TA_BILIN_POINT_1_CYCLE_PIXELS = 0x0000a01c, GX2_STAT_TA_BICUBIC_4_CYCLE_PIXELS = 0x0000a01d, GX2_STAT_TA_MIPMAP_LOD_0_SAMPLES = 0x0000a020, GX2_STAT_TA_MIPMAP_LOD_1_SAMPLES = 0x0000a021, GX2_STAT_TA_MIPMAP_LOD_2_SAMPLES = 0x0000a022, GX2_STAT_TA_MIPMAP_LOD_3_SAMPLES = 0x0000a023, GX2_STAT_TA_MIPMAP_LOD_4_SAMPLES = 0x0000a024, GX2_STAT_TA_MIPMAP_LOD_5_SAMPLES = 0x0000a025, GX2_STAT_TA_MIPMAP_LOD_6_SAMPLES = 0x0000a026, GX2_STAT_TA_MIPMAP_LOD_7_SAMPLES = 0x0000a027, GX2_STAT_TA_MIPMAP_LOD_8_SAMPLES = 0x0000a028, GX2_STAT_TA_MIPMAP_LOD_9_SAMPLES = 0x0000a029, GX2_STAT_TA_MIPMAP_LOD_10_SAMPLES = 0x0000a02a, GX2_STAT_TA_MIPMAP_LOD_11_SAMPLES = 0x0000a02b, GX2_STAT_TA_MIPMAP_LOD_12_SAMPLES = 0x0000a02c, GX2_STAT_TA_MIPMAP_LOD_13_SAMPLES = 0x0000a02d, GX2_STAT_TA_MIPMAP_LOD_14_SAMPLES = 0x0000a02e, GX2_STAT_TA_ANISO_1_1_QUADS = 0x0000a030, GX2_STAT_TA_ANISO_2_1_QUADS = 0x0000a031, GX2_STAT_TA_ANISO_3_1_QUADS = 0x0000a032, GX2_STAT_TA_ANISO_4_1_QUADS = 0x0000a033, GX2_STAT_TA_ANISO_5_1_QUADS = 0x0000a034, GX2_STAT_TA_ANISO_6_1_QUADS = 0x0000a035, GX2_STAT_TA_ANISO_7_1_QUADS = 0x0000a036, GX2_STAT_TA_ANISO_8_1_QUADS = 0x0000a037, GX2_STAT_TA_ANISO_9_1_QUADS = 0x0000a038, GX2_STAT_TA_ANISO_10_1_QUADS = 0x0000a039, GX2_STAT_TA_ANISO_11_1_QUADS = 0x0000a03a, GX2_STAT_TA_ANISO_12_1_QUADS = 0x0000a03b, GX2_STAT_TA_ANISO_13_1_QUADS = 0x0000a03c, GX2_STAT_TA_ANISO_14_1_QUADS = 0x0000a03d, GX2_STAT_TA_ANISO_15_1_QUADS = 0x0000a03e, GX2_STAT_TA_ANISO_16_1_QUADS = 0x0000a03f, GX2_STAT_TA_TA_REG_SCLK_VLD = 0x0000a040, GX2_STAT_TA_TA_LOCAL_CG_DYN_SCLK_GRP0_EN = 0x0000a041, GX2_STAT_TA_TA_LOCAL_CG_DYN_SCLK_GRP1_EN = 0x0000a042, GX2_STAT_TA_TA_LOCAL_CG_DYN_SCLK_GRP1_MEMS_EN = 0x0000a043, GX2_STAT_TA_FIRST = GX2_STAT_TA_TA_BUSY, GX2_STAT_TA_LAST = GX2_STAT_TA_TA_LOCAL_CG_DYN_SCLK_GRP1_MEMS_EN, GX2_STAT_TCP_TA_TCP_STARVE_CYCLES = 0x0000b000, GX2_STAT_TCP_TCP_TA_STALL_CYCLES = 0x0000b001, GX2_STAT_TCP_TD_TCP_STALL_CYCLES = 0x0000b002, GX2_STAT_TCP_TCC_TCP_STALL_CYCLES = 0x0000b003, GX2_STAT_TCP_TCC0_TCP_STALL_CYCLES = 0x0000b004, GX2_STAT_TCP_TCC1_TCP_STALL_CYCLES = 0x0000b005, GX2_STAT_TCP_TCC2_TCP_STALL_CYCLES = 0x0000b006, GX2_STAT_TCP_TCC3_TCP_STALL_CYCLES = 0x0000b007, GX2_STAT_TCP_TCC4_TCP_STALL_CYCLES = 0x0000b008, GX2_STAT_TCP_TCC5_TCP_STALL_CYCLES = 0x0000b009, GX2_STAT_TCP_TCC6_TCP_STALL_CYCLES = 0x0000b00a, GX2_STAT_TCP_TCC7_TCP_STALL_CYCLES = 0x0000b00b, GX2_STAT_TCP_TCP_LOD_STALL_CYCLES = 0x0000b00c, GX2_STAT_TCP_TCP_TAGCONFLICT_STALL_CYCLES = 0x0000b00d, GX2_STAT_TCP_TCP_ALLOC_STALL_CYCLES = 0x0000b00e, GX2_STAT_TCP_TCP_LFIFO_STALL_CYCLES = 0x0000b00f, GX2_STAT_TCP_TCP_RFIFO_STALL_CYCLES = 0x0000b010, GX2_STAT_TCP_TCP_FFIFO_STALL_CYCLES = 0x0000b011, GX2_STAT_TCP_TCP_CFIFO_STALL_CYCLES = 0x0000b012, GX2_STAT_TCP_TCP_READCONFLICT_STALL_CYCLES = 0x0000b013, GX2_STAT_TCP_TCP_PENDING_STALL_CYCLES = 0x0000b014, GX2_STAT_TCP_TCP_READFIFO_STALL_CYCLES = 0x0000b015, GX2_STAT_TCP_TCP_LATENCY = 0x0000b016, GX2_STAT_TCP_TCC_REQ_LATENCY = 0x0000b017, GX2_STAT_TCP_TCC0_REQ_LATENCY = 0x0000b018, GX2_STAT_TCP_TCC1_REQ_LATENCY = 0x0000b019, GX2_STAT_TCP_TCC2_REQ_LATENCY = 0x0000b01a, GX2_STAT_TCP_TCC3_REQ_LATENCY = 0x0000b01b, GX2_STAT_TCP_TCC4_REQ_LATENCY = 0x0000b01c, GX2_STAT_TCP_TCC5_REQ_LATENCY = 0x0000b01d, GX2_STAT_TCP_TCC6_REQ_LATENCY = 0x0000b01e, GX2_STAT_TCP_TCC7_REQ_LATENCY = 0x0000b01f, GX2_STAT_TCP_TCC_FREE_LATENCY = 0x0000b020, GX2_STAT_TCP_TCC0_FREE_LATENCY = 0x0000b021, GX2_STAT_TCP_TCC1_FREE_LATENCY = 0x0000b022, GX2_STAT_TCP_TCC2_FREE_LATENCY = 0x0000b023, GX2_STAT_TCP_TCC3_FREE_LATENCY = 0x0000b024, GX2_STAT_TCP_TCC4_FREE_LATENCY = 0x0000b025, GX2_STAT_TCP_TCC5_FREE_LATENCY = 0x0000b026, GX2_STAT_TCP_TCC6_FREE_LATENCY = 0x0000b027, GX2_STAT_TCP_TCC7_FREE_LATENCY = 0x0000b028, GX2_STAT_TCP_TCP_TCC_REQ = 0x0000b029, GX2_STAT_TCP_TCP_TCC0_REQ = 0x0000b02a, GX2_STAT_TCP_TCP_TCC1_REQ = 0x0000b02b, GX2_STAT_TCP_TCP_TCC2_REQ = 0x0000b02c, GX2_STAT_TCP_TCP_TCC3_REQ = 0x0000b02d, GX2_STAT_TCP_TCP_TCC4_REQ = 0x0000b02e, GX2_STAT_TCP_TCP_TCC5_REQ = 0x0000b02f, GX2_STAT_TCP_TCP_TCC6_REQ = 0x0000b030, GX2_STAT_TCP_TCP_TCC7_REQ = 0x0000b031, GX2_STAT_TCP_TCC_TCP_RDRET = 0x0000b032, GX2_STAT_TCP_TCC0_TCP_RDRET = 0x0000b033, GX2_STAT_TCP_TCC1_TCP_RDRET = 0x0000b034, GX2_STAT_TCP_TCC2_TCP_RDRET = 0x0000b035, GX2_STAT_TCP_TCC3_TCP_RDRET = 0x0000b036, GX2_STAT_TCP_TCC4_TCP_RDRET = 0x0000b037, GX2_STAT_TCP_TCC5_TCP_RDRET = 0x0000b038, GX2_STAT_TCP_TCC6_TCP_RDRET = 0x0000b039, GX2_STAT_TCP_TCC7_TCP_RDRET = 0x0000b03a, GX2_STAT_TCP_TOTAL_PIXELS = 0x0000b03b, GX2_STAT_TCP_UNCACHED_PIXELS = 0x0000b03c, GX2_STAT_TCP_FMT_1_PIXELS = 0x0000b03d, GX2_STAT_TCP_FMT_8_PIXELS = 0x0000b03e, GX2_STAT_TCP_FMT_16_PIXELS = 0x0000b03f, GX2_STAT_TCP_FMT_32_PIXELS = 0x0000b040, GX2_STAT_TCP_FMT_32_AS_8_PIXELS = 0x0000b041, GX2_STAT_TCP_FMT_32_AS_16_PIXELS = 0x0000b042, GX2_STAT_TCP_FMT_64_2_CYCLE_PIXELS = 0x0000b043, GX2_STAT_TCP_FMT_64_1_CYCLE_PIXELS = 0x0000b044, GX2_STAT_TCP_FMT_96_PIXELS = 0x0000b045, GX2_STAT_TCP_FMT_128_4_CYCLE_PIXELS = 0x0000b046, GX2_STAT_TCP_FMT_128_1_CYCLE_PIXELS = 0x0000b047, GX2_STAT_TCP_FMT_BC1_PIXELS = 0x0000b048, GX2_STAT_TCP_FMT_BC2_PIXELS = 0x0000b049, GX2_STAT_TCP_FMT_BC3_PIXELS = 0x0000b04a, GX2_STAT_TCP_FMT_BC4_PIXELS = 0x0000b04b, GX2_STAT_TCP_FMT_BC5_PIXELS = 0x0000b04c, GX2_STAT_TCP_FMT_I8_PIXELS = 0x0000b04d, GX2_STAT_TCP_FMT_I16_PIXELS = 0x0000b04e, GX2_STAT_TCP_FMT_I32_PIXELS = 0x0000b04f, GX2_STAT_TCP_FMT_I32_AS_8_PIXELS = 0x0000b050, GX2_STAT_TCP_FMT_I32_AS_16_PIXELS = 0x0000b051, GX2_STAT_TCP_FMT_D16_PIXELS = 0x0000b052, GX2_STAT_TCP_FMT_D32_PIXELS = 0x0000b053, GX2_STAT_TCP_FMT_V8_PIXELS = 0x0000b054, GX2_STAT_TCP_FMT_V16_PIXELS = 0x0000b055, GX2_STAT_TCP_FMT_V32_PIXELS = 0x0000b056, GX2_STAT_TCP_FMT_V64_2_CYCLE_PIXELS = 0x0000b057, GX2_STAT_TCP_FMT_V64_1_CYCLE_PIXELS = 0x0000b058, GX2_STAT_TCP_FMT_V128_4_CYCLE_PIXELS = 0x0000b059, GX2_STAT_TCP_FMT_V128_2_CYCLE_PIXELS = 0x0000b05a, GX2_STAT_TCP_FMT_V128_1_CYCLE_PIXELS = 0x0000b05b, GX2_STAT_TCP_ARR_LINEAR_GENERAL_PIXELS = 0x0000b05c, GX2_STAT_TCP_ARR_LINEAR_ALIGNED_PIXELS = 0x0000b05d, GX2_STAT_TCP_ARR_1D_THIN1_PIXELS = 0x0000b05e, GX2_STAT_TCP_ARR_1D_THICK_PIXELS = 0x0000b05f, GX2_STAT_TCP_ARR_2D_THIN1_PIXELS = 0x0000b060, GX2_STAT_TCP_ARR_2D_THIN2_PIXELS = 0x0000b061, GX2_STAT_TCP_ARR_2D_THIN4_PIXELS = 0x0000b062, GX2_STAT_TCP_ARR_2D_THICK_PIXELS = 0x0000b063, GX2_STAT_TCP_ARR_2B_THIN1_PIXELS = 0x0000b064, GX2_STAT_TCP_ARR_2B_THIN2_PIXELS = 0x0000b065, GX2_STAT_TCP_ARR_2B_THIN4_PIXELS = 0x0000b066, GX2_STAT_TCP_ARR_2B_THICK_PIXELS = 0x0000b067, GX2_STAT_TCP_ARR_3D_THIN1_PIXELS = 0x0000b068, GX2_STAT_TCP_ARR_3D_THICK_PIXELS = 0x0000b069, GX2_STAT_TCP_ARR_3B_THIN1_PIXELS = 0x0000b06a, GX2_STAT_TCP_ARR_3B_THICK_PIXELS = 0x0000b06b, GX2_STAT_TCP_DIM_1D_PIXELS = 0x0000b06c, GX2_STAT_TCP_DIM_2D_PIXELS = 0x0000b06d, GX2_STAT_TCP_DIM_3D_PIXELS = 0x0000b06e, GX2_STAT_TCP_DIM_CUBE_PIXELS = 0x0000b06f, GX2_STAT_TCP_DIM_1D_ARRAY_PIXELS = 0x0000b070, GX2_STAT_TCP_DIM_2D_ARRAY_PIXELS = 0x0000b071, GX2_STAT_TCP_DIM_2D_MSAA_PIXELS = 0x0000b072, GX2_STAT_TCP_DIM_2D_ARRAY_MSAA_PIXELS = 0x0000b073, GX2_STAT_TCP_DIM_CUBE_ARRAY_PIXELS = 0x0000b074, GX2_STAT_TCP_VGT_TCP_INVALIDATE = 0x0000b075, GX2_STAT_TCP_TA_TCP_STATE_READ = 0x0000b076, GX2_STAT_TCP_TCP_TAGRAM0_REQ = 0x0000b077, GX2_STAT_TCP_TCP_TAGRAM1_REQ = 0x0000b078, GX2_STAT_TCP_TCP_TAGRAM2_REQ = 0x0000b079, GX2_STAT_TCP_TCP_TAGRAM3_REQ = 0x0000b07a, GX2_STAT_TCP_TCP_GATE_EN1 = 0x0000b07b, GX2_STAT_TCP_TCP_GATE_EN2 = 0x0000b07c, GX2_STAT_TCP_TCP_CORE_REG_SCLK_VLD = 0x0000b07d, GX2_STAT_TCP_FMT_V96_PIXELS = 0x0000b07e, GX2_STAT_TCP_FIRST = GX2_STAT_TCP_TA_TCP_STARVE_CYCLES, GX2_STAT_TCP_LAST = GX2_STAT_TCP_FMT_V96_PIXELS, GX2_STAT_TCC_NONE = 0x0000C000, GX2_STAT_TCC_CYCLES = 0x0000C001, GX2_STAT_TCC_BUSY = 0x0000C002, GX2_STAT_TCC_BUSY_TC_TF = 0x0000C003, GX2_STAT_TCC_BUSY_TC_VF = 0x0000C004, GX2_STAT_TCC_BUSY_VC_VF = 0x0000C005, GX2_STAT_TCC_REQS = 0x0000C006, GX2_STAT_TCC_REQS_HIT = 0x0000C007, GX2_STAT_TCC_REQS_MISS = 0x0000C008, GX2_STAT_TCC_REQS_UNCACHED = 0x0000C009, GX2_STAT_TCC_REQS_CLIENT_0 = 0x0000C00A, GX2_STAT_TCC_REQS_CLIENT_1 = 0x0000C00B, GX2_STAT_TCC_REQS_CLIENT_2 = 0x0000C00C, GX2_STAT_TCC_REQS_CLIENT_3 = 0x0000C00D, GX2_STAT_TCC_REQS_CLIENT_4 = 0x0000C00E, GX2_STAT_TCC_REQS_CLIENT_5 = 0x0000C00F, GX2_STAT_TCC_REQS_CLIENT_6 = 0x0000C010, GX2_STAT_TCC_REQS_CLIENT_7 = 0x0000C011, GX2_STAT_TCC_REQS_CLIENT_8 = 0x0000C012, GX2_STAT_TCC_REQS_CLIENT_9 = 0x0000C013, GX2_STAT_TCC_REQS_CLIENT_10 = 0x0000C014, GX2_STAT_TCC_REQS_CLIENT_11 = 0x0000C015, GX2_STAT_TCC_REQS_CLIENT_12 = 0x0000C016, GX2_STAT_TCC_REQS_CLIENT_13 = 0x0000C017, GX2_STAT_TCC_REQS_CLIENT_14 = 0x0000C018, GX2_STAT_TCC_REQS_CLIENT_15 = 0x0000C019, GX2_STAT_TCC_REQS_CLIENT_16 = 0x0000C01A, GX2_STAT_TCC_REQS_CLIENT_17 = 0x0000C01B, GX2_STAT_TCC_REQS_CLIENT_18 = 0x0000C01C, GX2_STAT_TCC_REQS_CLIENT_19 = 0x0000C01D, GX2_STAT_TCC_REQS_CLIENT_20 = 0x0000C01E, GX2_STAT_TCC_REQS_CLIENT_21 = 0x0000C01F, GX2_STAT_TCC_REQS_CLIENT_22 = 0x0000C020, GX2_STAT_TCC_REQS_CLIENT_23 = 0x0000C021, GX2_STAT_TCC_REQS_TC_TF = 0x0000C022, GX2_STAT_TCC_REQS_TC_TF_HIT = 0x0000C023, GX2_STAT_TCC_REQS_TC_TF_MISS = 0x0000C024, GX2_STAT_TCC_REQS_TC_VF = 0x0000C025, GX2_STAT_TCC_REQS_TC_VF_HIT = 0x0000C026, GX2_STAT_TCC_REQS_TC_VF_MISS = 0x0000C027, GX2_STAT_TCC_REQS_VC_VF = 0x0000C028, GX2_STAT_TCC_REQS_VC_VF_HIT = 0x0000C029, GX2_STAT_TCC_REQS_VC_VF_MISS = 0x0000C02A, GX2_STAT_TCC_REQ_LEVEL_TC_TF = 0x0000C02B, GX2_STAT_TCC_REQ_LEVEL_TC_VF = 0x0000C02C, GX2_STAT_TCC_REQ_LEVEL_VC_VF = 0x0000C02D, GX2_STAT_TCC_REQ_LEVEL_CLIENT_0 = 0x0000C02E, GX2_STAT_TCC_REQ_LEVEL_CLIENT_1 = 0x0000C02F, GX2_STAT_TCC_REQ_LEVEL_CLIENT_2 = 0x0000C030, GX2_STAT_TCC_REQ_LEVEL_CLIENT_3 = 0x0000C031, GX2_STAT_TCC_REQ_LEVEL_CLIENT_4 = 0x0000C032, GX2_STAT_TCC_REQ_LEVEL_CLIENT_5 = 0x0000C033, GX2_STAT_TCC_REQ_LEVEL_CLIENT_6 = 0x0000C034, GX2_STAT_TCC_REQ_LEVEL_CLIENT_7 = 0x0000C035, GX2_STAT_TCC_REQ_LEVEL_CLIENT_8 = 0x0000C036, GX2_STAT_TCC_REQ_LEVEL_CLIENT_9 = 0x0000C037, GX2_STAT_TCC_REQ_LEVEL_CLIENT_10 = 0x0000C038, GX2_STAT_TCC_REQ_LEVEL_CLIENT_11 = 0x0000C039, GX2_STAT_TCC_REQ_LEVEL_CLIENT_12 = 0x0000C03A, GX2_STAT_TCC_REQ_LEVEL_CLIENT_13 = 0x0000C03B, GX2_STAT_TCC_REQ_LEVEL_CLIENT_14 = 0x0000C03C, GX2_STAT_TCC_REQ_LEVEL_CLIENT_15 = 0x0000C03D, GX2_STAT_TCC_REQ_LEVEL_CLIENT_16 = 0x0000C03E, GX2_STAT_TCC_REQ_LEVEL_CLIENT_17 = 0x0000C03F, GX2_STAT_TCC_REQ_LEVEL_CLIENT_18 = 0x0000C040, GX2_STAT_TCC_REQ_LEVEL_CLIENT_19 = 0x0000C041, GX2_STAT_TCC_REQ_LEVEL_CLIENT_20 = 0x0000C042, GX2_STAT_TCC_REQ_LEVEL_CLIENT_21 = 0x0000C043, GX2_STAT_TCC_REQ_LEVEL_CLIENT_22 = 0x0000C044, GX2_STAT_TCC_REQ_LEVEL_CLIENT_23 = 0x0000C045, GX2_STAT_TCC_MC_REQS = 0x0000C046, GX2_STAT_TCC_MC_REQS_TC_TF = 0x0000C047, GX2_STAT_TCC_MC_REQS_TC_VF = 0x0000C048, GX2_STAT_TCC_MC_REQS_VC_VF = 0x0000C049, GX2_STAT_TCC_MC_FULL = 0x0000C04A, GX2_STAT_TCC_MC_REQ_LEVEL = 0x0000C04B, GX2_STAT_TCC_MC_REQ_LEVEL_TC_TF = 0x0000C04C, GX2_STAT_TCC_MC_REQ_LEVEL_TC_VF = 0x0000C04D, GX2_STAT_TCC_MC_REQ_LEVEL_VC_VF = 0x0000C04E, GX2_STAT_TCC_MC_CREDIT_LEVEL = 0x0000C04F, GX2_STAT_TCC_CG_CORE_ENABLED = 0x0000C050, GX2_STAT_TCC_CG_BLOCK_ENABLED = 0x0000C051, GX2_STAT_TCC_LF_FULL = 0x0000C052, GX2_STAT_TCC_LF_FULL_VC = 0x0000C053, GX2_STAT_TCC_LF_FULL_TC = 0x0000C054, GX2_STAT_TCC_LF_FULL_CLIENT_VC = 0x0000C055, GX2_STAT_TCC_LF_FULL_CLIENT_TC = 0x0000C056, GX2_STAT_TCC_LF_LEVEL = 0x0000C057, GX2_STAT_TCC_LF_LEVEL_VC_VF = 0x0000C058, GX2_STAT_TCC_LF_LEVEL_TC_VF = 0x0000C059, GX2_STAT_TCC_LF_LEVEL_TC_TF = 0x0000C05A, GX2_STAT_TCC_LF_BLOCK_LEVEL = 0x0000C05B, GX2_STAT_TCC_LF_BLOCK_LEVEL_VC = 0x0000C05C, GX2_STAT_TCC_LF_BLOCK_LEVEL_TC = 0x0000C05D, GX2_STAT_TCC_OF_LEVEL = 0x0000C05E, GX2_STAT_TCC_OF_LEVEL_VC_VF = 0x0000C05F, GX2_STAT_TCC_OF_LEVEL_TC_VF = 0x0000C060, GX2_STAT_TCC_OF_LEVEL_TC_TF = 0x0000C061, GX2_STAT_TCC_TCA_LEVEL = 0x0000C062, GX2_STAT_TCC_TCA_LEVEL_VC_VF = 0x0000C063, GX2_STAT_TCC_TCA_LEVEL_TC_VF = 0x0000C064, GX2_STAT_TCC_TCA_LEVEL_TC_TF = 0x0000C065, GX2_STAT_TCC_TCA_LEVEL_CLIENT_0 = 0x0000C066, GX2_STAT_TCC_TCA_LEVEL_CLIENT_1 = 0x0000C067, GX2_STAT_TCC_TCA_LEVEL_CLIENT_2 = 0x0000C068, GX2_STAT_TCC_TCA_LEVEL_CLIENT_3 = 0x0000C069, GX2_STAT_TCC_TCA_LEVEL_CLIENT_4 = 0x0000C06A, GX2_STAT_TCC_TCA_LEVEL_CLIENT_5 = 0x0000C06B, GX2_STAT_TCC_TCA_LEVEL_CLIENT_6 = 0x0000C06C, GX2_STAT_TCC_TCA_LEVEL_CLIENT_7 = 0x0000C06D, GX2_STAT_TCC_TCA_LEVEL_CLIENT_8 = 0x0000C06E, GX2_STAT_TCC_TCA_LEVEL_CLIENT_9 = 0x0000C06F, GX2_STAT_TCC_TCA_LEVEL_CLIENT_10 = 0x0000C070, GX2_STAT_TCC_TCA_LEVEL_CLIENT_11 = 0x0000C071, GX2_STAT_TCC_TCA_LEVEL_CLIENT_12 = 0x0000C072, GX2_STAT_TCC_TCA_LEVEL_CLIENT_13 = 0x0000C073, GX2_STAT_TCC_TCA_LEVEL_CLIENT_14 = 0x0000C074, GX2_STAT_TCC_TCA_LEVEL_CLIENT_15 = 0x0000C075, GX2_STAT_TCC_TCA_LEVEL_CLIENT_16 = 0x0000C076, GX2_STAT_TCC_TCA_LEVEL_CLIENT_17 = 0x0000C077, GX2_STAT_TCC_TCA_LEVEL_CLIENT_18 = 0x0000C078, GX2_STAT_TCC_TCA_LEVEL_CLIENT_19 = 0x0000C079, GX2_STAT_TCC_TCA_LEVEL_CLIENT_20 = 0x0000C07A, GX2_STAT_TCC_TCA_LEVEL_CLIENT_21 = 0x0000C07B, GX2_STAT_TCC_TCA_LEVEL_CLIENT_22 = 0x0000C07C, GX2_STAT_TCC_TCA_LEVEL_CLIENT_23 = 0x0000C07D, GX2_STAT_TCC_CLIENTS_FULL = 0x0000C07E, GX2_STAT_TCC_CLIENTS_FULL_VC = 0x0000C07F, GX2_STAT_TCC_CLIENTS_FULL_TC = 0x0000C080, GX2_STAT_TCC_ARB_BURST = 0x0000C081, GX2_STAT_TCC_ARB_BURST_VC = 0x0000C082, GX2_STAT_TCC_ARB_BURST_TC = 0x0000C083, GX2_STAT_TCC_CACHE_TAG_STALL_TC_TF = 0x0000C084, GX2_STAT_TCC_CACHE_TAG_RENAME_TC_TF = 0x0000C085, GX2_STAT_TCC_CACHE_TAG_STALL_TC_VF = 0x0000C086, GX2_STAT_TCC_CACHE_TAG_RENAME_TC_VF = 0x0000C087, GX2_STAT_TCC_CACHE_TAG_STALL_VC_VF = 0x0000C088, GX2_STAT_TCC_CACHE_TAG_RENAME_VC_VF = 0x0000C089, GX2_STAT_TCC_CACHE_STALL = 0x0000C08A, GX2_STAT_TCC_DEALLOC = 0x0000C08B, GX2_STAT_TCC_DEALLOC_ALL = 0x0000C08C, GX2_STAT_TCC_DEALLOC_LINES = 0x0000C08D, GX2_STAT_TCC_DEALLOC_CYCLES = 0x0000C08E, GX2_STAT_TCC_REG_WRITES = 0x0000C08F, GX2_STAT_TCC_REG_READS = 0x0000C090, GX2_STAT_TCC_DEBUG_BUS = 0x0000C091, GX2_STAT_TCC_DUMMY_LAST = 0x0000C092, GX2_STAT_TCC_FIRST = GX2_STAT_TCC_NONE, GX2_STAT_TCC_LAST = GX2_STAT_TCC_DUMMY_LAST, /// Number of busy cycles GX2_STAT_CB_BUSY = 0x0000D000, /// Number of cycles the DB to CB tile interface is valid and ready. This is measured after the input fifo. GX2_STAT_CB_DB_CB_TILE_VALID_READY = 0x0000D001, /// Number of cycles the DB to CB tile interface is valid and not ready. This is measured after the input fifo. GX2_STAT_CB_DB_CB_TILE_VALID_READYB = 0x0000D002, /// Number of cycles the DB to CB tile interface is not valid and ready. This is measured after the input fifo. GX2_STAT_CB_DB_CB_TILE_VALIDB_READY = 0x0000D003, /// Number of cycles the DB to CB tile interface is not valid and not ready. This is measured after the input fifo. GX2_STAT_CB_DB_CB_TILE_VALIDB_READYB = 0x0000D004, /// Number of cycles the DB to CB lquad interface is valid and ready. This is measured after the input fifo GX2_STAT_CB_DB_CB_LQUAD_VALID_READY = 0x0000D005, /// Number of cycles the DB to CB lquad interface is valid and not ready. This is measured after the input fifo GX2_STAT_CB_DB_CB_LQUAD_VALID_READYB = 0x0000D006, /// Number of cycles the DB to CB lquad interface is not valid and ready. This is measured after the input fifo GX2_STAT_CB_DB_CB_LQUAD_VALIDB_READY = 0x0000D007, /// Number of cycles the DB to CB lquad interface is not valid and not ready. This is measured after the input fifo GX2_STAT_CB_DB_CB_LQUAD_VALIDB_READYB = 0x0000D008, /// Number of cycles the CB to TAP write request interface is valid and ready. This is measured at the interface converter rather than directly on the interface. GX2_STAT_CB_CB_TAP_WRREQ_VALID_READY = 0x0000D009, /// Number of cycles the CB to TAP write request interface is valid and not ready. This is measured at the interface converter rather than directly on the interface. GX2_STAT_CB_CB_TAP_WRREQ_VALID_READYB = 0x0000D00A, /// Number of cycles the CB to TAP write request interface is valid and ready. This is measured at the interface converter rather than directly on the interface. GX2_STAT_CB_CB_TAP_WRREQ_VALIDB_READY = 0x0000D00B, /// Number of cycles the CB to TAP write request interface is not valid and not ready. This is measured at the interface converter rather than directly on the interface. GX2_STAT_CB_CB_TAP_WRREQ_VALIDB_READYB = 0x0000D00C, /// Number of cycles the CB to TAP read request interface is valid and ready. This is measured at the interface converter rather than directly on the interface. GX2_STAT_CB_CB_TAP_RDREQ_VALID_READY = 0x0000D00D, /// Number of cycles the CB to TAP read request interface is valid and not ready. This is measured at the interface converter rather than directly on the interface. GX2_STAT_CB_CB_TAP_RDREQ_VALID_READYB = 0x0000D00E, /// Number of cycles the CB to TAP read request interface is not valid and ready. This is measured at the interface converter rather than directly on the interface. GX2_STAT_CB_CB_TAP_RDREQ_VALIDB_READY = 0x0000D00F, /// Number of cycles the CB to TAP read request interface is not valid and not ready. This is measured at the interface converter rather than directly on the interface. GX2_STAT_CB_CB_TAP_RDREQ_VALIDB_READYB = 0x0000D010, /// Number of cycles the cmask to fmask tile interface is valid and ready GX2_STAT_CB_CM_FC_TILE_VALID_READY = 0x0000D011, /// Number of cycles the cmask to fmask tile interface is valid and not ready GX2_STAT_CB_CM_FC_TILE_VALID_READYB = 0x0000D012, /// Number of cycles the cmask to fmask tile interface is not valid and ready GX2_STAT_CB_CM_FC_TILE_VALIDB_READY = 0x0000D013, /// Number of cycles the cmask to fmask tile interface is not valid and not ready GX2_STAT_CB_CM_FC_TILE_VALIDB_READYB = 0x0000D014, /// Number of cycles the fmask to color cache interface is valid and ready GX2_STAT_CB_FC_CC_QUADFRAG_VALID_READY = 0x0000D015, /// Number of cycles the fmask to color cache interface is valid and not ready GX2_STAT_CB_FC_CC_QUADFRAG_VALID_READYB = 0x0000D016, /// Number of cycles the fmask to color cache interface is not valid and ready GX2_STAT_CB_FC_CC_QUADFRAG_VALIDB_READY = 0x0000D017, /// Number of cycles the fmask to color cache interface is not valid and not ready GX2_STAT_CB_FC_CC_QUADFRAG_VALIDB_READYB = 0x0000D018, /// Number of cycles the fragop unit input interface is valid and ready GX2_STAT_CB_FOP_IN_VALID_READY = 0x0000D019, /// Number of cycles the fragop unit input interface is valid and not ready GX2_STAT_CB_FOP_IN_VALID_READYB = 0x0000D01A, /// Number of cycles the fragop unit input interface is not valid and ready GX2_STAT_CB_FOP_IN_VALIDB_READY = 0x0000D01B, /// Number of cycles the fragop unit input interface is not valid and not ready GX2_STAT_CB_FOP_IN_VALIDB_READYB = 0x0000D01C, /// Number of cycles the color cache input block to tag block interface is valid and ready GX2_STAT_CB_CC_IB_TB_FRAG_VALID_READY = 0x0000D01D, /// Number of cycles the color cache input block to tag block interface is valid and not ready GX2_STAT_CB_CC_IB_TB_FRAG_VALID_READYB = 0x0000D01E, /// Number of cycles the color cache input block to tag block interface is not valid and ready GX2_STAT_CB_CC_IB_TB_FRAG_VALIDB_READY = 0x0000D01F, /// Number of cycles the color cache input block to tag block interface is not valid and not ready GX2_STAT_CB_CC_IB_TB_FRAG_VALIDB_READYB = 0x0000D020, /// The color cache source fifo is full GX2_STAT_CB_CC_SF_FULL = 0x0000D021, /// The color cache reorder buffer is full GX2_STAT_CB_CC_RB_FULL = 0x0000D022, /// The fmask read latency fifo is full GX2_STAT_CB_FC_RDLAT_FIFO_FULL = 0x0000D023, /// The cmask tile queue is full GX2_STAT_CB_CM_TQ_FULL = 0x0000D024, /// A quad has arrived over the lquad interface but the corresponding tile has not arrive yet. GX2_STAT_CB_LQUAD_NO_TILE = 0x0000D025, /// Number of cmask cache hits GX2_STAT_CB_CM_CACHE_HIT = 0x0000D026, /// Number of cmask cache tag misses. A tag miss is when there is not a tag that matches the input. Because of sectoring, a tag hit does not imply that the required data is in the cache. GX2_STAT_CB_CM_CACHE_TAG_MISS = 0x0000D027, /// Number of cmask cache sector misses. A sector miss is when the required sector is not in the cache. Tag misses are included in this count because a sector cannot be in the cache if there is no tag for it. GX2_STAT_CB_CM_CACHE_SECTOR_MISS = 0x0000D028, /// The cmask cache is stalled because it is trying to evict a line that already has a pending evict GX2_STAT_CB_CM_CACHE_REEVICTION_STALL = 0x0000D029, /// The cmask cache is stalled because it is trying to evict a line that has a nonzero inflight count. This is usually a sign that the cache is unable to withstand the memory read latency. GX2_STAT_CB_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x0000D02A, /// The cmask cache is stalled because it is trying to evict a line that does not yet have resident data. GX2_STAT_CB_CM_CACHE_EVICT_NONRESIDENT_STALL = 0x0000D02B, /// The cmask cache is stalled because the line being replaced has a pending evict. This is usually a sign that the cache is unable to withstand the memory write latency. GX2_STAT_CB_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x0000D02C, /// The cmask cache is stalled because one of the inflight counters has reached the maximum value. GX2_STAT_CB_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x0000D02D, /// The cmask cache is stalled because the read request output path is stalled. GX2_STAT_CB_CM_CACHE_READ_OUTPUT_STALL = 0x0000D02E, /// The cmask cache is stalled because the write request output path is stalled. GX2_STAT_CB_CM_CACHE_WRITE_OUTPUT_STALL = 0x0000D02F, /// The cmask cache is stalled because the acknowledge output path is stalled. GX2_STAT_CB_CM_CACHE_ACK_OUTPUT_STALL = 0x0000D030, /// This is the number of cmask cache flushes. GX2_STAT_CB_CM_CACHE_FLUSH = 0x0000D031, /// Number of fmask cache hits GX2_STAT_CB_FC_CACHE_HIT = 0x0000D032, /// Number of fmask cache tag misses. A tag miss is when there is not a tag that matches the input. Because of sectoring, a tag hit does not imply that the required data is in the cache. GX2_STAT_CB_FC_CACHE_TAG_MISS = 0x0000D033, /// Number of fmask cache sector misses. A sector miss is when the required sector is not in the cache. Tag misses are included in this count because a sector cannot be in the cache if there is no tag for it. GX2_STAT_CB_FC_CACHE_SECTOR_MISS = 0x0000D034, /// The fmask cache is stalled because it is trying to evict a line that already has a pending evict GX2_STAT_CB_FC_CACHE_REEVICTION_STALL = 0x0000D035, /// The fmask cache is stalled because it is trying to evict a line that has a nonzero inflight count. This is usually a sign that the cache is unable to withstand the memory read latency. GX2_STAT_CB_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x0000D036, /// The fmask cache is stalled because it is trying to evict a line that does not yet have resident data. GX2_STAT_CB_FC_CACHE_EVICT_NONRESIDENT_STALL = 0x0000D037, /// The fmask cache is stalled because the line being replaced has a pending evict. This is usually a sign that the cache is unable to withstand the memory write latency. GX2_STAT_CB_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x0000D038, /// The fmask cache is stalled because one of the inflight counters has reached the maximum value. GX2_STAT_CB_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x0000D039, /// The fmask cache is stalled because the read request output path is stalled. GX2_STAT_CB_FC_CACHE_READ_OUTPUT_STALL = 0x0000D03A, /// The fmask cache is stalled because the write request output path is stalled. GX2_STAT_CB_FC_CACHE_WRITE_OUTPUT_STALL = 0x0000D03B, /// The fmask cache is stalled because the acknowledge output path is stalled. GX2_STAT_CB_FC_CACHE_ACK_OUTPUT_STALL = 0x0000D03C, /// This is the number of fmask cache flushes. GX2_STAT_CB_FC_CACHE_FLUSH = 0x0000D03D, /// Number of fmask cache hits GX2_STAT_CB_CC_CACHE_HIT = 0x0000D03E, /// Number of color cache tag misses. A tag miss is when there is not a tag that matches the input. Because of sectoring, a tag hit does not imply that the required data is in the cache. GX2_STAT_CB_CC_CACHE_TAG_MISS = 0x0000D03F, /// Number of color cache sector misses. A sector miss is when the required sector is not in the cache. Tag misses are included in this count because a sector cannot be in the cache if there is no tag for it. GX2_STAT_CB_CC_CACHE_SECTOR_MISS = 0x0000D040, /// The color cache is stalled because it is trying to evict a line that already has a pending evict GX2_STAT_CB_CC_CACHE_REEVICTION_STALL = 0x0000D041, /// The color cache is stalled because it is trying to evict a line that has a nonzero inflight count. This is usually a sign that the cache is unable to withstand the memory read latency. GX2_STAT_CB_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x0000D042, /// The color cache is stalled because it is trying to evict a line that does not yet have resident data. GX2_STAT_CB_CC_CACHE_EVICT_NONRESIDENT_STALL = 0x0000D043, /// The color cache is stalled because the line being replaced has a pending evict. This is usually a sign that the cache is unable to withstand the memory write latency. GX2_STAT_CB_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x0000D044, /// The color cache is stalled because one of the inflight counters has reached the maximum value. GX2_STAT_CB_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x0000D045, /// The color cache is stalled because the read request output path is stalled. GX2_STAT_CB_CC_CACHE_READ_OUTPUT_STALL = 0x0000D046, /// The color cache is stalled because the write request output path is stalled. GX2_STAT_CB_CC_CACHE_WRITE_OUTPUT_STALL = 0x0000D047, /// The color cache is stalled because the acknowledge output path is stalled. GX2_STAT_CB_CC_CACHE_ACK_OUTPUT_STALL = 0x0000D048, /// The number of times a write allocate cache line is converted to a read-modify-write cache line. GX2_STAT_CB_CC_CACHE_WA_TO_RMW_CONVERSION = 0x0000D049, /// This is the number of color cache flushes. This is includes surface sync flushes. GX2_STAT_CB_CC_CACHE_FLUSH = 0x0000D04A, /// Number of 32-byte cmask memory controller read requests. Cmask does not make 32-byte requests, so the counter will report the equivalent number of 32-byte requests. GX2_STAT_CB_CM_MC_READ_REQUEST = 0x0000D04B, /// Number of 32-byte fmask memory controller read requests. GX2_STAT_CB_FC_MC_READ_REQUEST = 0x0000D04C, /// Number of 32-byte color memory controller read requests. Color does not make 32-byte requests, so the counter will report the equivalent number of 32-byte requests. GX2_STAT_CB_CC_MC_READ_REQUEST = 0x0000D04D, /// Number of 32-byte cmask memory controller write requests. GX2_STAT_CB_CM_MC_WRITE_REQUEST = 0x0000D04E, /// Number of 32-byte fmask memory controller write requests. GX2_STAT_CB_FC_MC_WRITE_REQUEST = 0x0000D04F, /// Number of 32-byte color memory controller write requests. GX2_STAT_CB_CC_MC_WRITE_REQUEST = 0x0000D050, /// Number of 32-byte cmask memory controller read requests in flight. Cmask does not make 32-byte requests, so the counter will report the equivalent number of 32-byte requests. Dividing this number by the cmask read request count produces the average latency. GX2_STAT_CB_CM_MC_READ_REQUESTS_IN_FLIGHT = 0x0000D051, /// Number of 32-byte fmask memory controller read requests in flight. Dividing this number by the fmask read request count produces the average latency. GX2_STAT_CB_FC_MC_READ_REQUESTS_IN_FLIGHT = 0x0000D052, /// Number of 32-byte color memory controller read requests in flight. Color does not make 32-byte requests, so the counter will report the equivalent number of 32-byte requests. Dividing this number by the color read request count produces the average latency. GX2_STAT_CB_CC_MC_READ_REQUESTS_IN_FLIGHT = 0x0000D053, /// Number of 32-byte cmask memory controller write requests in flight. Dividing this number by the cmask write request count produces the average latency. GX2_STAT_CB_CM_MC_WRITE_REQUESTS_IN_FLIGHT = 0x0000D054, /// Number of 32-byte fmask memory controller write requests in flight. Dividing this number by the fmask write request count produces the average latency. GX2_STAT_CB_FC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x0000D055, /// Number of 32-byte color memory controller write requests in flight. Dividing this number by the color write request count produces the average latency. GX2_STAT_CB_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x0000D056, /// Number of surface syncs GX2_STAT_CB_CC_SURFACE_SYNC = 0x0000D057, /// Number of quad fragments that require two cache probes. AA blending can create these when the read fragment does not match the write fragment. GX2_STAT_CB_TWO_PROBE_QUAD_FRAGMENT = 0x0000D058, /// Number of slow mode quad fragments. GX2_STAT_CB_SLOW_MODE_QUAD_FRAGMENT = 0x0000D059, /// This is the number of dual source color quad fragments GX2_STAT_CB_DUAL_SOURCE_COLOR_QUAD_FRAGMENT = 0x0000D05A, /// This is the number of drawn quads. Filtering has an effect in this mode. GX2_STAT_CB_DRAWN_QUAD = 0x0000D05B, /// This is the number of drawn pixels. Filtering has an effect in this mode. GX2_STAT_CB_DRAWN_PIXEL = 0x0000D05C, /// This is the number of drawn quad fragments. Filtering has an effect in this mode. GX2_STAT_CB_DRAWN_QUAD_FRAGMENT = 0x0000D05D, /// This is the number of times the blend pipeline is stalled to handle read after write hazards. GX2_STAT_CB_BLENDER_RAW_HAZARD_STALL = 0x0000D05E, /// Total number of events reaching the CB. This includes events that the CB does not process. GX2_STAT_CB_EVENT = 0x0000D05F, /// Number of CACHE_FLUSH_TS events GX2_STAT_CB_EVENT_CACHE_FLUSH_TS = 0x0000D060, /// Number of CONTEXT_DONE events GX2_STAT_CB_EVENT_CONTEXT_DONE = 0x0000D061, /// Number of CACHE_FLUSH events GX2_STAT_CB_EVENT_CACHE_FLUSH = 0x0000D062, /// Number of CACHE_FLUSH_AND_INV_TS_EVENT events GX2_STAT_CB_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 0x0000D063, /// Number of_CACHE_FLUSH_AND_INV_EVENTevents GX2_STAT_CB_EVENT_CACHE_FLUSH_AND_INV_EVENT = 0x0000D064, /// Number of FLUSH_AND_INV_CB_DATA_TS events GX2_STAT_CB_EVENT_FLUSH_AND_INV_CB_DATA_TS = 0x0000D065, /// Number of FLUSH_AND_INV_CB_META events GX2_STAT_CB_EVENT_FLUSH_AND_INV_CB_META = 0x0000D066, /// Number of times a value of 0xC was read from cmask. Cmask reads only occur on fmask cache misses. A value of 0xC means that a fmask tile requires 0 bit planes. GX2_STAT_CB_CMASK_READ_DATA_0XC = 0x0000D067, /// Number of times a value of 0xD was read from cmask. Cmask reads only occur on fmask cache misses. A value of 0xD means that a fmask tile requires 1 bit planes. GX2_STAT_CB_CMASK_READ_DATA_0XD = 0x0000D068, /// Number of times a value of 0xE was read from cmask. Cmask reads only occur on fmask cache misses. A value of 0xE means that a fmask tile requires 2 bit planes. GX2_STAT_CB_CMASK_READ_DATA_0XE = 0x0000D069, /// Number of times a value of 0xF was read from cmask. Cmask reads only occur on fmask cache misses. A value of 0xF means that a fmask tile requires 3 bit planes. GX2_STAT_CB_CMASK_READ_DATA_0XF = 0x0000D06A, /// Number of times a value of 0xC was written to cmask. Cmask writes occur at the end of a tile. The hardware does not perform the write if fmask has not changed, but the counter will update as if regardless of whether the hardware wrote or not. A value of 0xC means that a fmask tile requires 0 bit planes. GX2_STAT_CB_CMASK_WRITE_DATA_0XC = 0x0000D06B, /// Number of times a value of 0xD was written to cmask. Cmask writes occur at the end of a tile. The hardware does not perform the write if fmask has not changed, but the counter will update as if regardless of whether the hardware wrote or not. A value of 0xD means that a fmask tile requires 1 bit planes. GX2_STAT_CB_CMASK_WRITE_DATA_0XD = 0x0000D06C, /// Number of times a value of 0xE was written to cmask. Cmask writes occur at the end of a tile. The hardware does not perform the write if fmask has not changed, but the counter will update as if regardless of whether the hardware wrote or not. A value of 0xE means that a fmask tile requires 2 bit planes. GX2_STAT_CB_CMASK_WRITE_DATA_0XE = 0x0000D06D, /// Number of times a value of 0xF was written to cmask. Cmask writes occur at the end of a tile. The hardware does not perform the write if fmask has not changed, but the counter will update as if regardless of whether the hardware wrote or not. A value of 0xF means that a fmask tile requires 3 bit planes. GX2_STAT_CB_CMASK_WRITE_DATA_0XF = 0x0000D06E, /// Number of cycles that the core clock is enabled. GX2_STAT_CB_CORE_SCLK_VLD = 0x0000D06F, /// Number of cycles that the register clock is enabled. GX2_STAT_CB_REG_SCLK_VLD = 0x0000D070, GX2_STAT_CB_FIRST = GX2_STAT_CB_BUSY, GX2_STAT_CB_LAST = GX2_STAT_CB_REG_SCLK_VLD, /// Cycles Interface is sending GX2_STAT_DB_SC_DB_TILE_SENDS = 0x0000E000, /// Cycles Interface is busy GX2_STAT_DB_SC_DB_TILE_BUSY = 0x0000E001, /// Cycles Interface is stalled GX2_STAT_DB_SC_DB_TILE_STALLS = 0x0000E002, /// Events sent over interface GX2_STAT_DB_SC_DB_TILE_EVENTS = 0x0000E003, /// Tiles sent over interface GX2_STAT_DB_SC_DB_TILE_TILES = 0x0000E004, /// Fully covered tiles GX2_STAT_DB_SC_DB_TILE_COVERED = 0x0000E005, /// HiZ starved waiting for htile data from cache GX2_STAT_DB_HIZ_TC_READ_STARVED = 0x0000E006, /// HiZ stalled writing to htile cache GX2_STAT_DB_HIZ_TC_WRITE_STALL = 0x0000E007, /// Quarter tiles culled by hiZ GX2_STAT_DB_HIZ_QTILES_CULLED = 0x0000E008, /// Quarter tiles culled by HiS GX2_STAT_DB_HIS_QTILES_CULLED = 0x0000E009, /// Cycles Interface is sending GX2_STAT_DB_DB_SC_TILE_SENDS = 0x0000E00A, /// Cycles Interface is busy GX2_STAT_DB_DB_SC_TILE_BUSY = 0x0000E00B, /// Cycles Interface is stalled by SC GX2_STAT_DB_DB_SC_TILE_STALLS = 0x0000E00C, /// Cycles Interface is stalled by detail walk tile fifo GX2_STAT_DB_DB_SC_TILE_DF_STALLS = 0x0000E00D, /// Tiles sent over interface GX2_STAT_DB_DB_SC_TILE_TILES = 0x0000E00E, /// Tiles culled in total GX2_STAT_DB_DB_SC_TILE_CULLED = 0x0000E00F, /// Tiles culled due to a hierarchical fail test GX2_STAT_DB_DB_SC_TILE_HIER_KILL = 0x0000E010, /// Tiles culled because they were accelerated fast tile ops. GX2_STAT_DB_DB_SC_TILE_FAST_OPS = 0x0000E011, /// Tiles culled because they would not do anything GX2_STAT_DB_DB_SC_TILE_NO_OPS = 0x0000E012, /// Tiles run at pixel rate as opposed to sample rate tile GX2_STAT_DB_DB_SC_TILE_PIXEL_RATE = 0x0000E013, /// Tiles culled because they were supersample tiles that are merged into a fast tile op GX2_STAT_DB_DB_SC_TILE_SSAA_KILL = 0x0000E014, /// Tiles that operate on Z in 1 clock. Can be inside a slow, pixel rate, or fast tile op GX2_STAT_DB_DB_SC_TILE_FAST_Z_OPS = 0x0000E015, /// Tiles that operate on stencil in 1 clock. Can be inside a slow, pixel rate, or fast tile op GX2_STAT_DB_DB_SC_TILE_FAST_STENCIL_OPS = 0x0000E016, /// Cycles Interface is sending GX2_STAT_DB_SC_DB_QUAD_SENDS = 0x0000E017, /// Cycles Interface is busy GX2_STAT_DB_SC_DB_QUAD_BUSY = 0x0000E018, /// Squads transferred over interface GX2_STAT_DB_SC_DB_QUAD_SQUADS = 0x0000E019, /// Tiles sent over interface GX2_STAT_DB_SC_DB_QUAD_TILES = 0x0000E01A, /// Pixels transferred over interface GX2_STAT_DB_SC_DB_QUAD_PIXELS = 0x0000E01B, /// Number of detail killed tiles GX2_STAT_DB_SC_DB_QUAD_KILLED_TILES = 0x0000E01C, /// Interface is sending GX2_STAT_DB_DB_SC_QUAD_SENDS = 0x0000E01D, /// Cycles Interface is busy GX2_STAT_DB_DB_SC_QUAD_BUSY = 0x0000E01E, /// Cycles Interface is stalled GX2_STAT_DB_DB_SC_QUAD_STALLS = 0x0000E01F, /// Squads sent over interface GX2_STAT_DB_DB_SC_QUAD_SQUADS = 0x0000E020, /// Tiles sent over interface GX2_STAT_DB_DB_SC_QUAD_TILES = 0x0000E021, /// Quads transferred over the DB_SC_quad interface GX2_STAT_DB_DB_SC_QUAD_QUADS = 0x0000E022, /// Cycles sending tiles/events to CB. Tiles not shaded or needed by the CB are not sent. GX2_STAT_DB_DB_CB_TILE_SENDS = 0x0000E023, GX2_STAT_DB_DB_CB_TILE_BUSY = 0x0000E024, GX2_STAT_DB_DB_CB_TILE_STALLS = 0x0000E025, /// Cycles Interface is sending GX2_STAT_DB_SX_DB_QUAD_SENDS = 0x0000E026, /// Cycles Interface is busy GX2_STAT_DB_SX_DB_QUAD_BUSY = 0x0000E027, /// Cycles Interface is stalled GX2_STAT_DB_SX_DB_QUAD_STALLS = 0x0000E028, /// Quads sent over interface GX2_STAT_DB_SX_DB_QUAD_QUADS = 0x0000E029, /// Pixels sent over interface GX2_STAT_DB_SX_DB_QUAD_PIXELS = 0x0000E02A, /// Each MRT of a quad sent over interface GX2_STAT_DB_SX_DB_QUAD_EXPORTS = 0x0000E02B, /// Divide by DB_SC_quad_quads to get PS latency. GX2_STAT_DB_SH_QUADS_OUTSTANDING_SUM = 0x0000E02C, /// Cycles Interface is sending GX2_STAT_DB_DB_CB_LQUAD_SENDS = 0x0000E02D, /// Cycles Interface is busy GX2_STAT_DB_DB_CB_LQUAD_BUSY = 0x0000E02E, /// Cycles Interface is stalled GX2_STAT_DB_DB_CB_LQUAD_STALLS = 0x0000E02F, /// Quads sent over interface GX2_STAT_DB_DB_CB_LQUAD_QUADS = 0x0000E030, /// HTile reads. Each is 256B GX2_STAT_DB_TILE_RD_SENDS = 0x0000E031, /// Divide by tile_rd_sends*8 to get htile memory latency GX2_STAT_DB_MI_TILE_RD_OUTSTANDING_SUM = 0x0000E032, /// Quad read reqs. Each is 32B to 256B GX2_STAT_DB_QUAD_RD_SENDS = 0x0000E033, /// Cycles quad read interface is trying to send requests GX2_STAT_DB_QUAD_RD_BUSY = 0x0000E034, /// Cycles quad read interface is stalled by the memory interface GX2_STAT_DB_QUAD_RD_MI_STALL = 0x0000E035, /// Cycles a quad read is stalled waiting for a write to finish GX2_STAT_DB_QUAD_RD_RW_COLLISION = 0x0000E036, /// Cycles a quad read is stalled because the read latency hiding fifo is full. GX2_STAT_DB_QUAD_RD_TAG_STALL = 0x0000E037, /// Number of 32 Byte quad read requests GX2_STAT_DB_QUAD_RD_32BYTE_REQS = 0x0000E038, /// Cycles DB is panicking for quad read data GX2_STAT_DB_QUAD_RD_PANIC = 0x0000E039, /// Divide by quad_rd_32byte_reqs to get depth buffer memory latency GX2_STAT_DB_MI_QUAD_RD_OUTSTANDING_SUM = 0x0000E03A, /// Number of 32 byte quad read returns GX2_STAT_DB_QUAD_RDRET_SENDS = 0x0000E03B, /// Cycles the quad read data is returning GX2_STAT_DB_QUAD_RDRET_BUSY = 0x0000E03C, /// 32 Byte HTile writes GX2_STAT_DB_TILE_WR_SENDS = 0x0000E03D, /// 32 Byte Htile write acks GX2_STAT_DB_TILE_WR_ACKS = 0x0000E03E, /// Divide by tile_wr_sends to get tile write memory latency GX2_STAT_DB_MI_TILE_WR_OUTSTANDING_SUM = 0x0000E03F, /// Cycles quad is sending write requests to the memory interface block of the DB GX2_STAT_DB_QUAD_WR_SENDS = 0x0000E040, /// Cycles quad is trying to write to the memory interface GX2_STAT_DB_QUAD_WR_BUSY = 0x0000E041, /// Cycles quad is stalled while writing to the memory interface GX2_STAT_DB_QUAD_WR_MI_STALL = 0x0000E042, /// Cycles quad write is stalled waiting for a previous write to finish on the same address GX2_STAT_DB_QUAD_WR_COHERENCY_STALL = 0x0000E043, /// Number of 32 Byte quad write acks GX2_STAT_DB_QUAD_WR_ACKS = 0x0000E044, /// Divide by the quad_wr_sends to get quad memory write latency GX2_STAT_DB_MI_QUAD_WR_OUTSTANDING_SUM = 0x0000E045, /// Htile Cache misses GX2_STAT_DB_TILE_CACHE_MISSES = 0x0000E046, /// Htile Cache hits GX2_STAT_DB_TILE_CACHE_HITS = 0x0000E047, /// Htile Cache flushes GX2_STAT_DB_TILE_CACHE_FLUSHES = 0x0000E048, /// Tile stalls waiting for an htile surface to flush and free GX2_STAT_DB_TILE_CACHE_SURFACE_STALL = 0x0000E049, /// Tile stalls waiting for an htile cacheline to free GX2_STAT_DB_TILE_CACHE_STARVES = 0x0000E04A, /// Tile stalls waiting for an htile memory read to return GX2_STAT_DB_TILE_CACHE_MEM_RETURN_STARVE = 0x0000E04B, /// Number of htile cachelines fetched by the normal tile stream GX2_STAT_DB_TCP_DISPATCHER_READS = 0x0000E04C, /// Number of htile cachelines fetched by the prefetcher GX2_STAT_DB_TCP_PREFETCHER_READS = 0x0000E04D, /// Number of htile cachelines fetched by the preloader GX2_STAT_DB_TCP_PRELOADER_READS = 0x0000E04E, /// Number of htile flushes caused by the normal tile stream GX2_STAT_DB_TCP_DISPATCHER_FLUSHES = 0x0000E04F, /// Number of htile flushes caused by the normal prefetcher GX2_STAT_DB_TCP_PREFETCHER_FLUSHES = 0x0000E050, /// Number of htile flushes caused by the normal preloader GX2_STAT_DB_TCP_PRELOADER_FLUSHES = 0x0000E051, /// Tiles/Events through the Depth Tile Cache GX2_STAT_DB_DEPTH_TILE_CACHE_SENDS = 0x0000E052, /// Cycles the Depth Tile Cache is busy testing hit/miss on tiles/events GX2_STAT_DB_DEPTH_TILE_CACHE_BUSY = 0x0000E053, /// Cycles starved waiting for a depth surface tile tag to free up GX2_STAT_DB_DEPTH_TILE_CACHE_STARVES = 0x0000E054, /// Cycles stalled waiting for a forced flush or invalidate to finish GX2_STAT_DB_DEPTH_TILE_CACHE_DTILE_LOCKED = 0x0000E055, /// Cycles depth tile stalled while allocating data GX2_STAT_DB_DEPTH_TILE_CACHE_ALLOC_STALL = 0x0000E056, /// Depth/Stencil Cache tile misses GX2_STAT_DB_DEPTH_TILE_CACHE_MISSES = 0x0000E057, /// Depth/Stencil Cache tile hits GX2_STAT_DB_DEPTH_TILE_CACHE_HITS = 0x0000E058, /// Depth/Stencil Cache tile flushes GX2_STAT_DB_DEPTH_TILE_CACHE_FLUSHES = 0x0000E059, /// No-op tiles through the depth tile cache GX2_STAT_DB_DEPTH_TILE_CACHE_NOOP_TILE = 0x0000E05A, /// Detail walked no-ops though the depth tile cache GX2_STAT_DB_DEPTH_TILE_CACHE_DETAILED_NOOP = 0x0000E05B, /// Events GX2_STAT_DB_DEPTH_TILE_CACHE_EVENT = 0x0000E05C, /// Depth tile frees GX2_STAT_DB_DEPTH_TILE_CACHE_TILE_FREES = 0x0000E05D, /// Depth tile data frees (may free data without freeing the depth tile) GX2_STAT_DB_DEPTH_TILE_CACHE_DATA_FREES = 0x0000E05E, /// Cycles depth/stencil cache is waiting for memory to return GX2_STAT_DB_DEPTH_TILE_CACHE_MEM_RETURN_STARVE = 0x0000E05F, /// 512 bit allocation GX2_STAT_DB_STENCIL_CACHE_MISSES = 0x0000E060, GX2_STAT_DB_STENCIL_CACHE_HITS = 0x0000E061, /// 256 bit flushes. Two per cacheline unless it is compressed, in which case it is 1. GX2_STAT_DB_STENCIL_CACHE_FLUSHES = 0x0000E062, /// Cache starves when the cache wants to miss but is out of cachelines to allocate GX2_STAT_DB_STENCIL_CACHE_STARVES = 0x0000E063, GX2_STAT_DB_STENCIL_CACHE_FREES = 0x0000E064, GX2_STAT_DB_Z_CACHE_SEPARATE_Z_MISSES = 0x0000E065, GX2_STAT_DB_Z_CACHE_SEPARATE_Z_HITS = 0x0000E066, GX2_STAT_DB_Z_CACHE_SEPARATE_Z_FLUSHES = 0x0000E067, /// Cache starves when the cache wants to miss but is out of cachelines to allocate GX2_STAT_DB_Z_CACHE_SEPARATE_Z_STARVES = 0x0000E068, GX2_STAT_DB_Z_CACHE_PMASK_MISSES = 0x0000E069, GX2_STAT_DB_Z_CACHE_PMASK_HITS = 0x0000E06A, GX2_STAT_DB_Z_CACHE_PMASK_FLUSHES = 0x0000E06B, /// Cache starves when the cache wants to miss but is out of cachelines to allocate GX2_STAT_DB_Z_CACHE_PMASK_STARVES = 0x0000E06C, GX2_STAT_DB_Z_CACHE_FREES = 0x0000E06D, GX2_STAT_DB_PLANE_CACHE_MISSES = 0x0000E06E, GX2_STAT_DB_PLANE_CACHE_HITS = 0x0000E06F, GX2_STAT_DB_PLANE_CACHE_FLUSHES = 0x0000E070, /// Cache starves when the cache wants to miss but is out of cachelines to allocate GX2_STAT_DB_PLANE_CACHE_STARVES = 0x0000E071, GX2_STAT_DB_PLANE_CACHE_FREES = 0x0000E072, /// Tiles flushed with expanded stencil GX2_STAT_DB_FLUSH_EXPANDED_STENCIL = 0x0000E073, /// Tiles flushed with compressed stencil GX2_STAT_DB_FLUSH_COMPRESSED_STENCIL = 0x0000E074, /// Tiles flushed with single stencil GX2_STAT_DB_FLUSH_SINGLE_STENCIL = 0x0000E075, /// Tiles flushed with 1 ZPlane GX2_STAT_DB_FLUSH_1PLANE = 0x0000E076, /// Tiles flushed with 2 ZPlane GX2_STAT_DB_FLUSH_2PLANE = 0x0000E077, /// Tiles flushed with 3 ZPlane GX2_STAT_DB_FLUSH_3PLANE = 0x0000E078, /// Tiles flushed with 4 ZPlane GX2_STAT_DB_FLUSH_4PLANE = 0x0000E079, /// Tiles flushed with 5 ZPlane GX2_STAT_DB_FLUSH_5PLANE = 0x0000E07A, /// Tiles flushed with 6 ZPlane GX2_STAT_DB_FLUSH_6PLANE = 0x0000E07B, /// Tiles flushed with 7 ZPlane GX2_STAT_DB_FLUSH_7PLANE = 0x0000E07C, /// Tiles flushed with 8 ZPlane GX2_STAT_DB_FLUSH_8PLANE = 0x0000E07D, /// Tiles flushed with 9 ZPlane GX2_STAT_DB_FLUSH_9PLANE = 0x0000E07E, /// Tiles flushed with 10 ZPlane GX2_STAT_DB_FLUSH_10PLANE = 0x0000E07F, /// Tiles flushed with 11 ZPlane GX2_STAT_DB_FLUSH_11PLANE = 0x0000E080, /// Tiles flushed with 12 ZPlane GX2_STAT_DB_FLUSH_12PLANE = 0x0000E081, /// Tiles flushed with 13 ZPlane GX2_STAT_DB_FLUSH_13PLANE = 0x0000E082, /// Tiles flushed with 14 ZPlane GX2_STAT_DB_FLUSH_14PLANE = 0x0000E083, /// Tiles flushed with 15 ZPlane GX2_STAT_DB_FLUSH_15PLANE = 0x0000E084, /// Tiles flushed with 16 ZPlane GX2_STAT_DB_FLUSH_16PLANE = 0x0000E085, /// Tiles flushed with expanded Z GX2_STAT_DB_FLUSH_EXPANDED_Z = 0x0000E086, /// Cycles stalled while transitioning from Late/ReZ to EarlyZ GX2_STAT_DB_EARLYZ_WAITING_FOR_POSTZ_DONE = 0x0000E087, /// Cycles stalled while transitioning to ReZ from an incompatible Z mode/func/etc. GX2_STAT_DB_REZ_WAITING_FOR_POSTZ_DONE = 0x0000E088, /// Detail kill block tiles/squads/events sent GX2_STAT_DB_DK_TILE_SENDS = 0x0000E089, /// Cycles Detail Kill block busy GX2_STAT_DB_DK_TILE_BUSY = 0x0000E08A, /// Cycles Detail Kill has tile, but no quads from the SC_DB_quad GX2_STAT_DB_DK_TILE_QUAD_STARVES = 0x0000E08B, /// Cycles Detail Kill is stalled from below GX2_STAT_DB_DK_TILE_STALLS = 0x0000E08C, /// Detail Kill squads GX2_STAT_DB_DK_SQUAD_SENDS = 0x0000E08D, /// Cycles the squad Detail Kill input is busy GX2_STAT_DB_DK_SQUAD_BUSY = 0x0000E08E, /// Cycles squads are stalled from below. GX2_STAT_DB_DK_SQUAD_STALLS = 0x0000E08F, /// Cycles the quad OP pipe of the DB is busy (including memory fetches, but not initial startup) GX2_STAT_DB_OP_PIPE_BUSY = 0x0000E090, /// Cycles the Op Pipe is waiting for memory to return (ignoring initial startup) GX2_STAT_DB_OP_PIPE_MC_READ_STALL = 0x0000E091, GX2_STAT_DB_QC_BUSY = 0x0000E092, GX2_STAT_DB_QC_XFC = 0x0000E093, GX2_STAT_DB_QC_CONFLICTS = 0x0000E094, GX2_STAT_DB_QC_FULL_STALL = 0x0000E095, GX2_STAT_DB_QC_IN_PREZ_TILE_STALLS_POSTZ = 0x0000E096, GX2_STAT_DB_QC_IN_POSTZ_TILE_STALLS_PREZ = 0x0000E097, GX2_STAT_DB_TSC_INSERT_SUMMARIZE_STALL = 0x0000E098, GX2_STAT_DB_TL_BUSY = 0x0000E099, GX2_STAT_DB_TL_DTC_READ_STARVED = 0x0000E09A, GX2_STAT_DB_TL_Z_FETCH_STALL = 0x0000E09B, GX2_STAT_DB_TL_STENCIL_STALL = 0x0000E09C, GX2_STAT_DB_TL_Z_DECOMPRESS_STALL = 0x0000E09D, GX2_STAT_DB_TL_STENCIL_LOCKED_STALL = 0x0000E09E, GX2_STAT_DB_TL_EVENTS = 0x0000E09F, GX2_STAT_DB_TL_SUMMARIZE_SQUADS = 0x0000E0A0, GX2_STAT_DB_TL_FLUSH_EXPAND_SQUADS = 0x0000E0A1, GX2_STAT_DB_TL_EXPAND_SQUADS = 0x0000E0A2, GX2_STAT_DB_TL_PREZ_SQUADS = 0x0000E0A3, GX2_STAT_DB_TL_POSTZ_SQUADS = 0x0000E0A4, GX2_STAT_DB_TL_PREZ_NOOP_SQUADS = 0x0000E0A5, GX2_STAT_DB_TL_POSTZ_NOOP_SQUADS = 0x0000E0A6, GX2_STAT_DB_TL_GETZ_SQUADS = 0x0000E0A7, GX2_STAT_DB_TL_TILE_OPS = 0x0000E0A8, GX2_STAT_DB_TL_IN_XFC = 0x0000E0A9, GX2_STAT_DB_TL_IN_SINGLE_STENCIL_EXPAND_STALL = 0x0000E0AA, GX2_STAT_DB_TL_IN_CONSTANT_STENCIL_WALK_STALL = 0x0000E0AB, GX2_STAT_DB_TL_IN_FAST_Z_STALL = 0x0000E0AC, GX2_STAT_DB_TL_OUT_XFC = 0x0000E0AD, GX2_STAT_DB_TL_OUT_SQUADS = 0x0000E0AE, GX2_STAT_DB_ZF_PLANE_MULTICYCLE = 0x0000E0AF, GX2_STAT_DB_POSTZ_SAMPLES_PASSING_Z = 0x0000E0B0, GX2_STAT_DB_POSTZ_SAMPLES_FAILING_Z = 0x0000E0B1, GX2_STAT_DB_POSTZ_SAMPLES_FAILING_S = 0x0000E0B2, GX2_STAT_DB_PREZ_SAMPLES_PASSING_Z = 0x0000E0B3, GX2_STAT_DB_PREZ_SAMPLES_FAILING_Z = 0x0000E0B4, GX2_STAT_DB_PREZ_SAMPLES_FAILING_S = 0x0000E0B5, GX2_STAT_DB_TS_TC_UPDATE_STALL = 0x0000E0B6, GX2_STAT_DB_SC_KICK_START = 0x0000E0B7, GX2_STAT_DB_SC_KICK_END = 0x0000E0B8, GX2_STAT_DB_SX_DB_MEM_EXPORTS = 0x0000E0B9, GX2_STAT_DB_SX_DB_MEM_EXPORTS_ACKED = 0x0000E0BA, GX2_STAT_DB_SX_DB_ACK_MEM_EXPORTS = 0x0000E0BB, GX2_STAT_DB_SX_DB_ACK_MEM_EXPORTS_ACKED = 0x0000E0BC, GX2_STAT_DB_MEM_EXPORT_BUSY = 0x0000E0BD, GX2_STAT_DB_MEM_EXPORT_MI_STALL = 0x0000E0BE, GX2_STAT_DB_MEM_EXPORT_TAG_STALL = 0x0000E0BF, GX2_STAT_DB_CLOCK_REG_ACTIVE = 0x0000E0C0, GX2_STAT_DB_CLOCK_MAIN_ACTIVE = 0x0000E0C1, GX2_STAT_DB_CLOCK_MEM_EXPORT_ACTIVE = 0x0000E0C2, GX2_STAT_DB_ESR_OUT_BUSY = 0x0000E0C3, GX2_STAT_DB_ESR_OUT_SC_STALL = 0x0000E0C4, GX2_STAT_DB_ESR_OUT_LQUAD_FIFO_FULL_STALL = 0x0000E0C5, GX2_STAT_DB_ETR_OUT_SEND = 0x0000E0C6, GX2_STAT_DB_ETR_OUT_BUSY = 0x0000E0C7, GX2_STAT_DB_ETR_OUT_LTILE_PROBE_FIFO_FULL_STALL = 0x0000E0C8, GX2_STAT_DB_ETR_OUT_CB_TILE_STALL = 0x0000E0C9, GX2_STAT_DB_ETR_OUT_ESR_STALL = 0x0000E0CA, GX2_STAT_DB_FIRST = GX2_STAT_DB_SC_DB_TILE_SENDS, GX2_STAT_DB_LAST = GX2_STAT_DB_ETR_OUT_ESR_STALL, GX2_STAT_PIPELINE = 0x0000F000, GX2_STAT_PIPELINE_FIRST = GX2_STAT_PIPELINE, GX2_STAT_PIPELINE_LAST = GX2_STAT_PIPELINE } _GX2StatId; /// \brief Indicates desired high-level performance metric to gather. typedef enum _GX2PerfMetric { /// Time this API call took to execute on the CPU+GPU in microseconds. /// Does not include time that draw calls are processed in parallel /// (GX2_STAT_GRBM_COUNT / 550.0f) GX2_PERF_U64_TIME, /// Time this API call took to execute on the GPU in microseconds. /// Does not include time that draw calls are processed in parallel /// (GX2_STAT_GRBM_GUI_ACTIVE / 550.0f) GX2_PERF_U64_GPU_TIME, /// Percentage of time GPU was busy /// (GX2_STAT_GRBM_GUI_ACTIVE / GX2_STAT_GRBM_COUNT) * 100.0f GX2_PERF_F32_GPU_BUSY, /// Percentage of GPU time that the shader unit is busy. /// (GX2_STAT_GRBM_SH_BUSY / GX2_STAT_GRBM_GUI_ACTIVE) * 100.0f GX2_PERF_F32_SHADER_BUSY, /// The number of reused indices, excluding geometry shader scenario /// (GX2_STAT_VGT_REUSED_VS_INDICES) GX2_PERF_U64_REUSED_INDICES_VS, /// The percentage of work done by the shader unit for the VS. /// ( GX2_STAT_SQ_THREAD_LEVEL_PER_TYPE[VS|ES] / /// GX2_STAT_SQ_THREAD_LEVEL_PER_TYPE[VS|ES|GS|PS] ) * 100.0f GX2_PERF_F32_SHADER_BUSY_VS, /// The percentage of work done by the shader unit for the GS. /// ( GX2_STAT_SQ_THREAD_LEVEL_PER_TYPE[GS] / /// GX2_STAT_SQ_THREAD_LEVEL_PER_TYPE[VS|ES|GS|PS] ) * 100.0f GX2_PERF_F32_SHADER_BUSY_GS, /// The percentage of work done by the shader unit for the PS. /// ( GX2_STAT_SQ_THREAD_LEVEL_PER_TYPE[PS] / /// GX2_STAT_SQ_THREAD_LEVEL_PER_TYPE[VS|ES|GS|PS] ) * 100.0f GX2_PERF_F32_SHADER_BUSY_PS, /// Average number of ALU instructions executed. /// ( GX2_STAT_SQ_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE[VS|ES|GS|PS] / /// GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f * 2.0f GX2_PERF_F32_ALU_BUSY, /// The percentage of GPUTime texture instructions are being processed. /// ( GX2_STAT_SQ_TA_TEX_INSTRS_PER_TYPE[VS|ES|GS|PS] / /// GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f * 8.0f GX2_PERF_F32_TEX_BUSY, /// The number of vertices processed by the VS. /// ( GX2_STAT_SQ_ITEMS_PER_TYPE[VS|ES] ) GX2_PERF_U64_VS_VERTICES_IN, /// Average number of texture instructions executed in VS. Affected by flow control. /// ( GX2_STAT_SQ_TA_TEX_INSTRS_PER_TYPE[VS|ES] / /// GX2_STAT_SQ_THREADS_PER_TYPE[VS|ES] ) GX2_PERF_F32_VS_TEX_INST_COUNT, /// The percentage of GPUTime texture instructions are being processed by the VS. /// ( GX2_STAT_SQ_TA_TEX_INSTRS_PER_TYPE[VS|ES] / /// GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f * 8.0f GX2_PERF_F32_VS_TEX_BUSY, /// Average number of ALU instructions executed in the VS. Affected by flow control. /// ( GX2_STAT_SQ_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE[VS|ES] / /// GX2_STAT_SQ_THREADS_PER_TYPE[VS|ES] ) GX2_PERF_F32_VS_ALU_INST_COUNT, /// The percentage of GPUTime ALU instructions are being processed by the VS. /// ( GX2_STAT_SQ_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE[VS|ES] / /// GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f * 2.0f GX2_PERF_F32_VS_ALU_BUSY, /// ALU vector packing efficiency. Values below 70 percent indicate that ALU dependency chains may be preventing full utilization of the processor. /// ( GX2_STAT_SQ_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE[VS|ES] / /// GX2_STAT_SQ_ALU_CLAUSE_INSTRS_PER_TYPE[VS|ES] ) * 100.0f GX2_PERF_F32_VS_ALU_EFFICIENCY, /// The ratio of ALU to texture instructions in the VS. This can be tuned appropriately to match the target hardware.When there are no texture instructions, it shows the number of ALU instructions. /// Apps built with SDK Versions prior to 2.10.01 multiply the numerator by an additional 100.0f. /// ( GX2_STAT_SQ_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE[VS|ES] / /// GX2_STAT_SQ_TA_TEX_INSTRS_PER_TYPE[VS|ES] ) GX2_PERF_F32_VS_ALU_TEX_RATIO, // Number of bytes read from memory due to vertex cache miss. // Note: only 32 byte or 128 byte vertices are accepted by runtime-version // GX2_PERF_VS_VERTEX_MEM_FETCHED, /// Average number of texture instructions executed in GS. /// Affected by flow control. /// ( GX2_STAT_SQ_TA_TEX_INSTRS_PER_TYPE[GS] / /// GX2_STAT_SQ_THREADS_PER_TYPE[GS] ) GX2_PERF_F32_GS_TEX_INST_COUNT, /// The percentage of GPUTime texture instructions are being processed /// by the GS. /// ( GX2_STAT_SQ_TA_TEX_INSTRS_PER_TYPE[GS] / /// GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f * 8.0f GX2_PERF_F32_GS_TEX_BUSY, /// Average number of ALU instructions executed in the GS. /// Affected by flow control. /// ( GX2_STAT_SQ_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE[GS] / /// GX2_STAT_SQ_THREADS_PER_TYPE[GS] ) GX2_PERF_F32_GS_ALU_INST_COUNT, /// The percentage of GPUTime ALU instructions are being processed /// by the GS. /// ( GX2_STAT_SQ_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE[GS] / /// GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f * 2.0f GX2_PERF_F32_GS_ALU_BUSY, /// ALU vector packing efficiency. Values below 70 percent indicate that /// ALU dependency chains may be preventing full utilization of /// the processor. /// ( GX2_STAT_SQ_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE[GS] / /// GX2_STAT_SQ_ALU_CLAUSE_INSTRS_PER_TYPE[GS]] ) * 100.0f GX2_PERF_F32_GS_ALU_EFFICIENCY, /// The ratio of ALU to texture instructions in the GS. /// This can be tuned appropriately to match the target hardware. /// When there are no texture instructions, /// it shows the number of ALU instructions. /// Apps built with SDK Versions prior to 2.10.01 multiply the numerator by an additional 100.0f. /// ( GX2_STAT_SQ_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE[GS] / /// GX2_STAT_SQ_TA_TEX_INSTRS_PER_TYPE[GS] ) GX2_PERF_F32_GS_ALU_TEX_RATIO, /// Percentage of GPUTime that clipping and culling is busy. /// TODO : not accurate calculation. Do not use this metric yet. /// ( GX2_STAT_PA_SU_CLIP_BUSY / GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f GX2_PERF_F32_PRIMITIVE_ASSEMBLY_BUSY, /// The number of primitives received by the hardware. /// ( GX2_STAT_VGT_VGT_PA_CLIPP_SEND - GX2_STAT_VGT_VGT_PA_CLIPP_IS_EVENT ) GX2_PERF_U64_PRIMITIVES_IN, // The number of culled primitives. Typical reasons include scissor, // the primitive having zero area, and back or front face culling. // GX2_PERF_CULLED_PRIMS, // The number of primitives that required one or more clipping operations // due to intersecting the view volume or user clip planes. // GX2_PERF_CLIPPED_PRIMS, /// Percentage of GPUTime that primitive assembly waits for rasterization /// to be ready to accept data. This roughly indicates for what percentage /// of time the pipeline is bottlenecked by pixel operations. /// ( GX2_STAT_PA_SU_SU_STALLED_SC / GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f GX2_PERF_F32_PA_STALLED_ON_RASTERIZER, /// Percentage of GPU time that the interpolator is busy. /// ( max (GX2_STAT_SPI_PCTL0_PI_BUSY, GX2_STAT_SPI_PCTL1_PI_BUSY) /// / GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f GX2_PERF_F32_INTERP_BUSY, /// The number of pixels processed by the PS. /// Does not count pixels culled by early Z or stencil tests. /// ( GX2_STAT_SQ_ITEMS_PER_TYPE[PS] ) GX2_PERF_U64_PS_PIXELS_IN, /// Average number of texture instructions executed in PS. Affected by flow control. /// ( GX2_STAT_SQ_TA_TEX_INSTRS_PER_TYPE[PS] / /// GX2_STAT_SQ_THREADS_PER_TYPE[PS] ) * 100.0f GX2_PERF_F32_PS_TEX_INST_COUNT, /// The percentage of GPUTime texture instructions are being processed by the PS. /// ( GX2_STAT_SQ_TA_TEX_INSTRS_PER_TYPE[PS] / /// GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f * 8.0f GX2_PERF_F32_PS_TEX_BUSY, /// Average number of ALU instructions executed in the PS. Affected by flow control. /// ( GX2_STAT_SQ_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE[PS] / /// GX2_STAT_SQ_THREADS_PER_TYPE[PS] ) GX2_PERF_F32_PS_ALU_INST_COUNT, /// The percentage of GPU time ALU instructions are processed by the PS. /// ( GX2_STAT_SQ_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE[PS] / /// GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f * 2.0f GX2_PERF_F32_PS_ALU_BUSY, /// ALU vector packing efficiency. Values below 70 percent indicate that ALU dependency chains may be preventing full utilization of the processor. /// ( GX2_STAT_SQ_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE[PS] / /// GX2_STAT_SQ_ALU_CLAUSE_INSTRS_PER_TYPE[PS]] ) * 100.0f GX2_PERF_F32_PS_ALU_EFFICIENCY, /// The ratio of ALU to texture instructions in the PS. This can be tuned appropriately to match the target hardware.When there are no texture instructions, it shows the number of ALU instructions. 4.0 is best balanced number. /// Apps built with SDK Versions prior to 2.10.01 multiply the numerator by an additional 100.0f. /// ( GX2_STAT_SQ_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE[PS] / /// GX2_STAT_SQ_TA_TEX_INSTRS_PER_TYPE[PS] ) GX2_PERF_F32_PS_ALU_TEX_RATIO, /// Pixels exported from shader to color buffers. Does not include killed /// or alpha tested pixels; if there are multiple rendertargets, /// each rendertarget receives one export, so this will be 2 for 1 pixel /// written to two RTs. /// ( GX2_STAT_SX_DB0_PIXELS + GX2_STAT_SX_DB1_PIXELS ) GX2_PERF_U64_PS_PIXELS_OUT, /// Percentage of GPUTime that PS output is stalled. /// Should be zero for PS or further upstream limited cases; /// if not zero, indicates a bottleneck in late z testing /// or in the color buffer. /// ( max( GX2_STAT_SX_DB0_STALL_CYCLES, GX2_STAT_SX_DB1_STALL_CYCLES ) / /// GX2_STAT_GRBM_GUI_ACTIVE ) GX2_PERF_F32_PS_EXPORT_STALLS, /// Percentage of GPU time the texture unit is active. /// This is measured with all extra fetches and any cache or /// memory effects taken into account. /// ( (GX2_STAT_TA_ALIGNER_CYCLES + GX2_STAT_TCP_TCP_TA_STALL_CYCLES ) / /// GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f GX2_PERF_F32_TEX_UNIT_BUSY, /// The total number of 32 bit words of texels and index/vertex data fetched. /// I.e., a single 128 bit texel will be reported as 4. /// This includes all shader types and any extra fetches caused by /// trilinear filtering, anisotropic filtering, color formats, /// and volume textures. /// ( GX2_STAT_TA_ALIGNER_CYCLES ) * 4.0f GX2_PERF_U64_TEXEL_FETCH_COUNT, /// Percentage of GPU time the texture cache is stalled. /// Try reducing the number of textures or reducing the number of bits /// per pixel (i.e., use compressed textures) if possible. /// ( GX2_STAT_TCP_TCP_TAGCONFLICT_STALL_CYCLES / /// GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f GX2_PERF_F32_TEX_CACHE_STALLED, /// Texture miss rate (bytes/texel). /// A normal value for mipmapped textures is approximately /// (texture_bpp / 4). For 1:1 mapping, it will be texture_bpp. /// ( GX2_STAT_TCC_REQS_TC_TF_MISS * 64.0 / /// GX2_STAT_TCP_TOTAL_PIXELS ) * 100.0f GX2_PERF_F32_TEX_MISS_RATE, /// Texture memory read in bytes. /// ( GX2_STAT_TCC_REQS_TC_TF_MISS * 64.0 ) GX2_PERF_U64_TEX_MEM_BYTES_READ, /// Percentage of GPU time spent performing depth and stencil tests. /// ( GX2_STAT_DB_OP_PIPE_BUSY / GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f GX2_PERF_F32_DEPTH_STENCIL_TEST_BUSY, /// Percentage of tiles that can be accepted by HiZ /// without doing per-pixel Z tests. /// ( (GX2_STAT_DB_DB_SC_TILE_NO_OPS + GX2_STAT_DB_DB_SC_TILE_PIXEL_RATE + GX2_STAT_DB_DB_SC_TILE_FAST_OPS) / GX2_STAT_DB_SC_DB_TILE_TILES) * 100.0f GX2_PERF_F32_HIZ_TRIVIAL_ACCEPT, /// Percentage of tiles that are rejected by HiZ. /// GX2_STAT_DB_DB_SC_TILE_HIER_KILL / GX2_STAT_DB_DB_SC_TILE_CULLED * 100.0f GX2_PERF_F32_HIZ_REJECT, /// Number of samples tested for Z before shading and passed. /// ( GX2_STAT_DB_PREZ_SAMPLES_PASSING_Z ) GX2_PERF_U64_PRE_Z_SAMPLES_PASSING, /// Number of samples tested for Z before shading and failed stencil test. /// ( GX2_STAT_DB_PREZ_SAMPLES_FAILING_S ) GX2_PERF_U64_PRE_Z_SAMPLES_FAILING_S, /// Number of samples tested for Z before shading and failed Z test. /// ( GX2_PERF_U64_PRE_Z_SAMPLES_FAILING_Z ) GX2_PERF_U64_PRE_Z_SAMPLES_FAILING_Z, /// Number of samples tested for Z after shading and passed. /// ( GX2_PERF_U64_POST_Z_SAMPLES_PASSING ) GX2_PERF_U64_POST_Z_SAMPLES_PASSING, /// Number of samples tested for Z after shading and failed stencil test. /// ( GX2_STAT_DB_POSTZ_SAMPLES_FAILING_S ) GX2_PERF_U64_POST_Z_SAMPLES_FAILING_S, /// Number of samples tested for Z after shading and failed Z test. /// ( GX2_PERF_U64_POST_Z_SAMPLES_FAILING_Z ) GX2_PERF_U64_POST_Z_SAMPLES_FAILING_Z, /// Percentage of GPUTime the depth buffer spends waiting for /// the color buffer to be ready to accept data. High figures here /// indicate a bottleneck in color buffer operations. /// ( GX2_STAT_DB_DB_CB_LQUAD_STALLS / GX2_STAT_GRBM_GUI_ACTIVE ) * 100.0f GX2_PERF_F32_Z_UNIT_STALLED, /// Number of pixels drawn into the color buffer. /// ( GX2_STAT_CB_DRAWN_PIXEL ) GX2_PERF_U64_PIXELS_AT_CB, /// Number of bytes written to the color buffer. /// ( GX2_STAT_CB_CC_MC_WRITE_REQUEST ) GX2_PERF_U64_PIXELS_CB_MEM_WRITTEN, /// The number of input assembler (IA, or fetch shader) vertices. GX2_PERF_U64_IA_VERTICES, /// The number of input assembler (IA, just after FS) primitives. GX2_PERF_U64_IA_PRIMITIVES, /// The number of vertex shader (VS) invocations. /// This may be less than GX2_PERF_U64_IA_VERTICES if the index buffer reuses vertices. GX2_PERF_U64_VS_INVOCATIONS, /// The number of geometry shader (GS) invocations. GX2_PERF_U64_GS_INVOCATIONS, /// The number of geometry shader (GS) primitives. GX2_PERF_U64_GS_PRIMITIVES, /// The number of clipper invocations. GX2_PERF_U64_C_INVOCATIONS, /// The number of clipped primitives rendered. This may be larger or smaller than clipper invocations(C_INVOCATIONS) or /// GX2_PERF_U64_IA_PRIMITIVES because after a primitive is clipped sometimes it is either broken up into more than one /// primitive or completely culled. GX2_PERF_U64_C_PRIMITIVES, /// The number of pixel shader (PS) invocations. GX2_PERF_U64_PS_INVOCATIONS, /// Number of Primitives input to PA GX2_PERF_U64_PA_INPUT_PRIM, GX2_PERF_LAST = GX2_PERF_U64_PA_INPUT_PRIM, GX2_PERF_FIRST = 0x0 } GX2PerfMetric; /// \brief Collection Method /// typedef enum _GX2PerfCollectionMethod { GX2_PERF_COLLECT_NONE, ///< turn off collection, minimize API run-time effect GX2_PERF_COLLECT_TAGS_ACCUMULATE, ///< collect accumulated results of all enabled tags in a pass GX2_PERF_COLLECT_TAGS_INDIVIDUAL ///< collect results at each tag start/end occurrence } GX2PerfCollectionMethod; /// \brief Type of perf metric/stat /// typedef enum _GX2PerfType { GX2_PERF_TYPE_GPU_METRIC, ///< high-level GPU metric GX2_PERF_TYPE_GPU_STAT, ///< low-level GPU stat GX2_PERF_TYPE_MEM_STAT ///< MEM stat } GX2PerfType; /// @} #ifdef __cplusplus } #endif // __cplusplus #endif // _CAFE_GX2_ENUM_H_