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Please contact the application's support team for more information. R6033 - Attempt to use MSIL code from this assembly during native code initialization This indicates a bug in your application. It is most likely the result of calling an MSIL-compiled (/clr) function from a native constructor or from DllMain. R6032 - not enough space for locale information R6031 - Attempt to initialize the CRT more than once. This indicates a bug in your application. R6030 - CRT not initialized R6028 - unable to initialize heap R6027 - not enough space for lowio initialization R6026 - not enough space for stdio initialization R6025 - pure virtual function call R6024 - not enough space for _onexit/atexit table R6019 - unable to open console device R6018 - unexpected heap error R6017 - unexpected multithread lock error R6016 - not enough space for thread data This application has requested the Runtime to terminate it in an unusual way. Please contact the application's support team for more information. R6009 - not enough space for environment R6008 - not enough space for arguments R6002 - floating point support not loaded Microsoft Visual C++ Runtime Library ...Runtime Error! Program:  EEE00P('8PW700PP (`h`hhhxppwpp/B)\-BYAbad exceptionHH:mm:ssdddd, MMMM dd, yyyyMM/dd/yyPMAMDecemberNovemberOctoberSeptemberAugustJulyJuneAprilMarchFebruaryJanuaryDecNovOctSepAugJulJunMayAprMarFebJanSaturdayFridayThursdayWednesdayTuesdayMondaySundaySatFriThuWedTueMonSununited-statesunited-kingdomtrinidad & tobagosouth-koreasouth-africasouth koreasouth africaslovakpuerto-ricopr-chinapr chinanznew-zealandhong-konghollandgreat britainenglandczechchinabritainamericausausukswissswedish-finlandspanish-venezuelaspanish-uruguayspanish-puerto ricospanish-peruspanish-paraguayspanish-panamaspanish-nicaraguaspanish-modernspanish-mexicanspanish-hondurasspanish-guatemalaspanish-el salvadorspanish-ecuadorspanish-dominican republicspanish-costa ricaspanish-colombiaspanish-chilespanish-boliviaspanish-argentinaportuguese-braziliannorwegian-nynorsknorwegian-bokmalnorwegianitalian-swissirish-englishgerman-swissgerman-luxembourggerman-lichtensteingerman-austrianfrench-swissfrench-luxembourgfrench-canadianfrench-belgianenglish-usaenglish-usenglish-ukenglish-trinidad y tobagoenglish-south africaenglish-nzenglish-jamaicaenglish-ireenglish-caribbeanenglish-canenglish-belizeenglish-ausenglish-americandutch-belgianchinese-traditionalchinese-singaporechinese-simplifiedchinese-hongkongchinesechichhcanadianbelgianaustralianamerican-englishamerican englishamerican>=%=/=-=+=*=||&&|^~(),>=><=<%/->*&+---++->operator[]!===!<<>> delete new__unaligned__restrict__ptr64__clrcall__fastcall__thiscall__stdcall__pascal__cdecl__based(lCdCXCLC@C4C(C CCCCPB4B BBBCCDBCCCCCCCCBCCCCCCCCCCCCCCCCCCCC|CxCtCpClChCdC`C\CPCDC<C0CC CCCCCxCXC4CCCCCCC|CtCdC@C8C,CCCBBBhB Opcode legend: [offset:cmd:type:reg/op:count]Color coding:PM4 opcodeopcodeOpcode parametersparamsGPU registerregisterRaw binaryraw binaryUser stringcommentGX2 APIgx2api %s(%s)GX2SetDefaultStateGX2ClearColorGX2ClearDepthStencilExGX2ClearBuffersExGX2CopySurfaceGX2CopySurfaceExGX2ResolveAAColorBufferGX2ExpandAAColorBufferGX2ExpandDepthBufferGX2ConvertDepthBufferToTextureSurfaceGX2CopyColorBufferToScanBufferGX2SwapScanBuffersGX2PerfPassStartGX2PerfPassEndGX2PerfTagStartGX2PerfTagEndIT_NOPIT_INDIRECT_BUFFER_ENDIT_OCCLUSION_QUERYIT_SET_PREDICATIONIT_REG_RMWIT_COND_EXECIT_PRED_EXECIT_INDEX_BASEIT_DRAW_INDEX_2IT_CONTEXT_CONTROLIT_DRAW_INDEX_OFFSETIT_INDEX_TYPEIT_DRAW_INDEXIT_DRAW_INDEX_AUTOIT_DRAW_INDEX_IMMDIT_NUM_INSTANCESIT_DRAW_INDEX_MULTI_AUTOIT_INDIRECT_BUFFER_PRIVIT_STRMOUT_BUFFER_UPDATEIT_DRAW_INDEX_OFFSET_2IT_DRAW_INDEX_MULTI_ELEMENTIT_INDIRECT_BUFFER_MPIT_MEM_SEMAPHOREIT_MPEG_INDEXIT_COPY_DWIT_WAIT_REG_MEMIT_MEM_WRITEIT_PER_FRAMEIT_INDIRECT_BUFFERIT_CP_DMAIT_PFP_SYNC_MEIT_SURFACE_SYNCIT_ME_INITIALIZEIT_COND_WRITEIT_EVENT_WRITEIT_EVENT_WRITE_EOPIT_LOAD_SURFACE_PROBEIT_SURFACE_PROBEIT_PREAMBLE_CNTLIT_RB_OFFSETIT_GFX_CNTX_UPDATEIT_BLK_CNTX_UPDATEIT_IB_OFFSETIT_INCR_UPDT_STATEIT_INCR_UPDT_CONSTIT_ONE_REG_WRITEIT_LOAD_CONFIG_REGIT_LOAD_CONTEXT_REGIT_LOAD_ALU_CONSTIT_LOAD_BOOL_CONSTIT_LOAD_LOOP_CONSTIT_LOAD_RESOURCEIT_LOAD_SAMPLERIT_LOAD_CTL_CONSTIT_SET_CONFIG_REGIT_SET_CONTEXT_REGIT_SET_ALU_CONSTIT_SET_BOOL_CONSTIT_SET_LOOP_CONSTIT_SET_RESOURCEIT_SET_SAMPLERIT_SET_CTL_CONSTIT_SET_RESOURCE_OFFSETIT_STRMOUT_BASE_UPDATEIT_SURFACE_BASE_UPDATEIT_SET_ALL_CONTEXTSIT_INDIRECT_BUFFER_BASEIT_EXECUTE_IB2IT_PFP_REG_WRIT_FORWARD_HEADERIT_SET_SCISSORSIT_START_3D_CMDBUFIT_START_2D_CMDBUFIT_LOAD_PALETTEIT_PAINTIT_BITBLTIT_HOSTDATA_BLTIT_POLYLINEIT_POLYSCANLINESIT_NEXTCHARIT_PAINT_MULTIIT_BITBLT_MULTIIT_TRANS_BITBLTIT_PLY_NEXTSCANIT_DRAW_2D_DIRTY_AREAA tool to convert .4mp capture files to human-readable format. Usage: pm4parse .4mp [-o .html] will default to .html OR: pm4parse -crashdump [-pm4] [-raw] Outputs .html which is the same as the input file except with the command buffer binary data disassembled. Additional options: [-pm4] [-raw] [-tracelevel n] -pm4 will output PM4 command disassembly in addition to GX2 API calls. -raw will output raw binary in addition to GX2/PM4. -tracelevel: -1=silent, 0=only errors, 1=top level info (default), 2=warnings, 3=functions, 4=detail, 5=high detail -o-crashdump-pm4-raw-tracelevelpm4capture-html%*x: %x %x %x %x %x %x %x %xrCrashdump couldn't open input "%s" (either doesn't exist or locked - try cafestop)Crashdump couldn't create output "%s"Crashdump %s -> %s

PFP header
PFP headers (last five PM4 headers read by PFP from most recent to least recent):
ME headerME headers (last five PM4 headers read by ME from most recent to least recent)
PFP header %x %x %x %x %xME header %x %x %x %x %x%x (%s)

%s
Command bufferCommand buffer at PA %*x, EA %*x size %x DWORDs

GX2Parse: parsing command buffer, size %d bytes (%d u32's)GX2Parse: End[%05d:%#010x] badopcode[%05d:%#010x:%d:%#06x:%04d] REG_WRITE %#06x[%05d:%#010x] TYPE2_NOP (padding)rawbinary+\@p@@й@p@@p@@*\@ l@0l@@l@`l@m@k@n@@@P@ n@0n@@n@m@L*\@$@`$@$@*\@@@@,@ -@-@-@PM4Stream: MS_LOAD compression not supported PM4Stream: CS compression not supported SOMETHING ELSE -\Pk@ l@0l@@l@`l@@k@k@k@@@P@pm@m@m@m@11:35:42May 23 2014GPUDB: Build date - %s %s PM4Parse: "%s" => "%s"ibPhysAddr=%#010x, byteSize=%dENABLEDDISABLEDState shadowing %s[%#06x] %-30s= %#010x (), offset=%d, count=%d, values=%f(0x%x), Attrib buffer=%d, size=%d, stride=%d, addr=%#010x%s texture slot=%d, imagePtr=%p, mipPtr=%p, width=%d, height=%d, depth=%d, format=%s, dim=%s, aa=%s, use=%s, tileMode=%s, viewFirstMip=%d, viewNumMips=%d, viewFirstSlice=%d, viewNumSlices=%d, swizzle=%#02x%s uniform block index=%d, size=%d, addr=%#010xGS RING IN size=%d, addr=%#010xGS RING OUT size=%d, addr=%#010x%s slot=%d, clampX=%s, clampY=%s, clampZ=%s, minFilter=%s, magFilter=%s, zFilter=%s, mipFilter=%s, maxAniso=%s, minLOD=%f, maxLOD=%f, LODBias=%f, border=%s, depthCompare=%s, highPrecision=%s, perfMip=%s, perfZ=%s, anisoBias=%f, lodUsesMinorAxis=%sLOAD REGS numRanges=%d, contextStateAddr=%pLOAD RESOURCE numRanges=%d, contextStateAddr=%pindexFmt=[%d] %snumInstances=%dindexCount=%d, indices=%#010xcount=%dindexCount=%dDISABLEtype=%s, hint=%s, enablePred=%s, physAddr=%#010x, size=%daddr=%p, size=%d, EVENT_TYPE=%saddr=%p, size=%dsrcAddr=%#010x, destAddr=%#010xinvType=%s, physAddr=%x, size=%usoTarget=%dSAVESETsoTarget=%d, ctxPtr=%p, op=%s> < COMMENT: BOOKMARK: TEXTURE_INFO pm4Slot=%d, imagePtr=%p, imageSize=%d, mipPtr=%p, mipSize=%d, numMips=%d, viewNumMips=%d%sw

%s

%s

%s

%s

%s

%s%s

rawbinary indent[%05d] %#010x[%05d:%#010x:%d:%#06x:%04d] %sUser Tag: INDENT: ]UNDENT: [leaving UNDENT: *** MISMATCHED UNDENT ***GX2 API bracket [id=%d, str="%s"]**Warning: unknown NOP tag type=%dcolor:redGX2SetContextState(%p)GX2DrawIndexedEx(primType=%s, indexCount=%d, indFmt=%s, indices=%#010x, baseVertex=%d, numInstances=%d)GX2DrawIndexedImmediateEx(primType=%s, indexCount=%d, indFmt=%s, baseVertex=%d, numInstances=%d)GX2DrawEx(primType=%s, indexCount=%d, firstVertex=%d, numInstances=%d)GX2DrawStreamOut(primType=%s)GX2SetAttribBuffer(buffer=%d, size=%d, stride=%d, ptr=%#010x)GX2Set%sTexture(slot=%d, imagePhysAddr=%p, mipPhysAddr=%p, width=%d, height=%d, depth=%d, format=%s, dim=%s, aa=%s, tileMode=%s, viewFirstMip=%d, viewNumMips=%d, viewFirstSlice=%d, viewNumSlices=%d, swizzle=%#02x)GX2Set%sUniformBlock(slot=%d, size=%d, addr=%#010x)GX2Set%sSampler(slot=%d, clampX=%s, clampY=%s, clampZ=%s, minFilter=%s, magFilter=%s, zFilter=%s, mipFilter=%s, maxAniso=%s, minLOD=%f, maxLOD=%f, LODBias=%f, border=%s, depthCompare=%s, highPrecision=%s, perfMip=%s, perfZ=%s, anisoBias=%f, lodUsesMinorAxis=%s)GX2SetColorBuffer(%d, 0x%p, pitch=%d, height=%d, format=%s, tilemode=%s, viewFirstSlice=%d, viewNumSlices=%d, aa=%s, auxPtr=%p)GX2SetDepthBuffer(0x%p, pitch=%d, format=%s, tilemode=%s, viewFirstSlice=%d, viewNumSlices=%d, htile=%p)GX2SetFetchShader(shaderPtr=0x%p, shaderSize=%d)GX2SetVertexShader(shaderPtr=0x%p, shaderSize=%d)GX2SetGeometryShader(shaderPtr=0x%p, shaderSize=%d, copyShaderPtr=%p, copyShaderSize=%d)GX2SetPixelShader(shaderPtr=0x%p, shaderSize=%d)deque too long@-\P@P@@й@p@@p@@,-\@p@@й@p@@p@@ /\/\..-\@@@@@@@P@ios_base::badbit setios_base::failbit setios_base::eofbit setCannot open <%s> PM4FilePC: Error opening %s file PM4FilePC: File %s is not a PM4 capture file PM4FilePC: File %s is not opened PM4FilePC: Cannot read block header from %s file PM4FilePC: Cannot allocate %u bytes of memory for block storage PM4FilePC: Cannot read block data from %s file pm4flip: unknown IS opcode %08X pm4flip: LOADZ opcode not supported, decompress the trace first pm4flip: unknown MS opcode %08X pm4flip: CSZ block not supported, decompress the trace first pm4flip: unsupported block type %08X bad cast2\p@t2\p@,2\PA0@0@@@P@`@@@@@@@@@@ @1\A81\ A@A@@ ApA@@@@A`APAAA0\AX0\@p@/\@P@0@@@@@@`@P@@?@ABCDEFGHIJKLMMNNNNNNNOOPPPPPQQSRTTUUUUUUUUUUUUUUUUUUUUUVVWWWWXXXYYZ[[\\\\\\]]]^^_``aaaaaabbccddeeffghhijjkklllmmmmmmmmmmmmmnooooppq 6DOY S 7EP TZpfhgjikoledmn_X[ 9GRQU`]^W:HVarABC8Fqb\/10243-.<;=>?@JIKMNLvtsc,5 !"#$&'()*+%uxwEjkrs"#$%>?~XYZz  ^$U`abNtuvw{sr|/D i+\ ,,      !"$%&'()*+,-./#3160XV2457J \4KJ&=w'lL81m LMN n.!MNOP:OP&deQ R|}QopRqSdTUVWeSTUVW|}flghim+' nf()*ghi -03<=C6op7@qABDHFIG[c^_`abtuvy{ /  %( !"#$)+ x9*,25;]   8A !  !)* 7)* "#$@9CAE=JK9>?8=BFHIJKFDHIJKJKFGHI9)*=>?D  :;<9 =>?   >? B !%&'( ,-./0123456   !%&'(,-./0123456  +      rX&j">MN7@CENOPQR8YZA^_Dbcdefg PRZ_ ce hiS   !)*9=FHIJKklmi 9=>?[\ >?B`a lnJKj !%&'(,-./0123456TU \ aFGHIo U:;<] j W"#$X+)*VVpq  qYXXp)XJ" pYXY""YCP_PERFMON_CNTLHYYPYPERFMON_STATEYY>CP_PERFMON_STATE_DISABLE_AND_RESET: Disable and Reset Count. Y`Y2CP_PERFMON_STATE_START_COUNTING: Start Counting. YY9CP_PERFMON_STATE_STOP_COUNTING: Freeze - Stop Counting. XYYCCP_PERFMON_STATE_RESERVED_3: Reserved for backwards compatibility PYYqCP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM: Disable and Reset Phantom Counters. Only useful during simulation. YoCP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM: Count and Dump out Phantom Counters. Only useful during simulation. @YYYPERFMON_ENABLE_MODEY8Y4CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT: Always Count. hYY<CP_PERFMON_ENABLE_MODE_RESERVED_1: Reserved for later use. PYYaCP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE: Count events whose contexts are marked for counting. YfCP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE: Count events whose contexts are not marked for counting. Y PERFMON_SAMPLE_ENABLE"YY""8YCP_PERFCOUNTER_HIY PERFCOUNT_HI"@YxY""YCP_PERFCOUNTER_LO Y PERFCOUNT_LO"ؓYY""YCP_PERFCOUNTER_SELECThYYPERFCOUNT_SEL>XYYCP_COUNT: Always Count. YY-RBIU_FIFO_FULL: RBIU Transaction FIFO FUll. YXY\CSF_RTS_BUT_MIU_NOT_RTR: CSF is Ready to Send data but the MIU is not Ready to Receive it. șY8YPCSF_I1_BASE_SIZE_FIFO_FULL_6xx: N/A GPU7 - PFP to CSF I1 Request FIFO is FUll. YYPCSF_I2_BASE_SIZE_FIFO_FULL_6xx: N/A GPU7 - PFP to CSF I2 Request FIFO is FUll. hYYDCSF_ST_BASE_SIZE_FIFO_FULL: PFP to CSF State Request FIFO is FUll. (YY6RING_REORDER_QUEUE_FULL: Ring Reorder Queue is Full. YpY2I1_REORDER_QUEUE_FULL: I1 Reorder Queue is Full. Y(Y2I2_REORDER_QUEUE_FULL: I2 Reorder Queue is Full. XYY 5ST_REORDER_QUEUE_FULL: State Reorder Queue is Full. (YY ECSF_RB_WPTR_NEQ_RPTR: Count of clocks that the RB is fetching data. YpY ECSF_I1_SIZE_NEQ_ZERO: Count of clocks that the I1 is fetching data. ȠY@Y ECSF_I2_SIZE_NEQ_ZERO: Count of clocks that the I2 is fetching data. YY NBRUSH_WR_CONFIRM_FIFO_FULL_6xx: N/A GPU7 - Brush Write Confirm FIFO is FULL. hYY>CP_GRBM_DWORDS_SENT: Count of DWs actually sent to the GRBM. YY3ME_PARSER_BUSY: Count of MicroEngine Busy Clokcs. YhY?COUNT_TYPE0_PACKETS: Count of Type0 Packets processed in NRT. Y0Y?COUNT_TYPE3_PACKETS: Count of Type3 Packets processed in NRT. YYNCSF_RBI1I2_FETCHING: Count of clocks that the RB, I1 & I2 are fetching data. hYХYUME_STALLED_FOR_DATA_FROM_PFP: MicroEngine is stalled waiting for data from the PFP. XYYeCP_GRBM_OUT_OF_CREDITS: CP to GRBM path has data to send but is waiting for credits (free signals). PYYmCP_PFP_GRBM_OUT_OF_CREDITS: CP.PFP to GRBM path has data to send but is waiting for credits (free signals). 8YYdRCIU_STALLED_ON_ME_READ: RCIU is stalled waiting for read data to be returned for the MicroEngine. YY]RCIU_STALLED_ON_DMA_READ: RCIU is stalled waiting for read data to be returned for the DMA. YhYvMIU_STALLED_ON_RDREQ_CREDITS_6xx: N/A GPU7 - CP has Read Requests to make but is waiting for credits (free signals). YhYvMIU_STALLED_ON_WRREQ_CREDITS_6xx: N/A GPU7 - CP has Write Request to make but is waiting for credits (free signals). (YhYMIU_STALLED_ON_WRCLEAN_PHASE_6xx: N/A GPU7 - CP block needs to do a write confirm, but there is not an available clean phase. YpYcSSU_STALLED_ON_ACTIVE_CNTX: Surface Sync Unit is waiting on a matching base in an Active Context. YXY\SSU_STALLED_ON_CLEAN_SIGNALS: Surface Sync Unit is waiting on all Clean signals to return. Y8YpQU_STALLED_ON_RECT_DONE_PULSE_6xx: N/A GPU7 - Query Unit is stalled waiting for a Rect Done pulse from the CR. Y0YyQU_STALLED_ON_RECT_DONE_WR_CONFIRM_6xx: N/A GPU7 - Query Unit is stalled waiting for a write confirm on Rect Done data. бY0YdQU_STALLED_ON_SC_EOP_DONE_PULSE: Query Unit is stalled waiting for an EOP Done signal from the SC. YY eQU_STALLED_ON_SX_EOP_DONE_PULSE: Query Unit is stalled waiting for an EOP Done signal from the SMX. YY!hQU_STALLED_ON_EOP_DONE_WR_CONFIRM: Query Unit is stalled waiting for a write confirm on EOP Done data. YY"ZQU_STALLED_ON_SIGNAL_SEMAPHORE: Query Unit is stalled trying to send a signal semaphore. pYشY#YQU_STALLED_ON_STREAMOUT_ADDRESS: Query Unit has Stream Out data to send but no address. PYY$VQU_STALLED_ON_STREAMOUT_DATA: Query Unit has Stream Out address to send bit no data. HYY%qQU_STALLED_ON_PIPELINE_STATISTICS: Query Unit is waiting for a Sample signal for at least 1 Pipeline Statistic. YY&FPFP_STALLED_ON_CSF_READY: PFP is stalled trying to write to the CSF. Y`Y'FPFP_STALLED_ON_MEQ_READY: PFP is stalled trying to write to the MEQ. Y0Y(FPFP_STALLED_ON_VGT_READY: PFP is stalled trying to write to the VGT. YY)bPFP_STALLED_ON_PENDING_MULTIPASS: PFP is stalled waiting for the multipass continue/loop signal. YY*aME_STALLED_ON_BRUSH_WR_CONFIRM_6xx: N/A GPU7 - ME is stalled waiting for a Brush Write Confirm. xYлY+gME_STALLED_ON_BUSY_BRUSH_LOGIC_6xx: N/A GPU7 - ME is stalled waiting for the Brush logic to complete. `YY,cME_STALLED_ON_NO_AVAIL_CR_CNTX_6xx: N/A GPU7 - ME is stalled waiting for an available CR context. @YY-VME_STALLED_ON_NO_AVAIL_GFX_CNTX: ME is stalled waiting for an available GFX context. YY.OME_STALLED_WRITING_TO_RCIU: ME is stalled trying to write to the RCIU (GRBM). Y`Y/bME_STALLED_WRITING_CONSTANTS: ME is stalled trying to write constants to the RCIU/MIU (GRBM/MC). YPY0RRBIU_STALLED_WRITING_DMA_REGS: RBIU is stalled trying to write to DMA registers. Y(Y1XRBIU_STALLED_WRITING_SEM_REGS: RBIU is stalled trying to write to Semaphore registers. YY2\RBIU_STALLED_WRITING_MC_WR_ADDR: RBIU is stalled trying to write to CP_MC write registers. YY3jRBIU_STALLED_WRITING_MC_RD_ADDR_6xx: N/A GPU7 - RBIU is stalled trying to write to CP_MC read registers. YY4tRBIU_STALLED_WRITING_EOPDONE_FIFO_600: N/A GPU7 - RBIU is stalled trying to write to Query Unit EOP Done registers YY5wRBIU_STALLED_WRITING_RECTDONE_FIFO_6xx: N/A GPU7 - RBIU is stalled trying to write to Query Unit Rect Done registers. YY6yRBIU_STALLED_WRITING_STREAMOUT_FIFO_600: N/A GPU7 - RBIU is stalled trying to write to Query Unit Stream Out registers. YY7}RBIU_STALLED_WRITING_PIPESTATS_FIFO_600: N/A GPU7 - RBIU is stalled trying to write to Query Unit Pipeline Stats registers. pYY8VSEMAPHORE_BUSY_POLLING_FOR_PASS: Semaphore Unit is busy polling for a Pass response. pYY9uLOAD_STALLED_ON_SET_COHERENCY: LOAD packet is stalled waiting on Coherency Counter=0 (SET packet writes completed). hYY:pME_STALLED_ON_PARTIAL_FLUSH: The ME sent out a Partial Flush event and is waiting for a response from the SPI. pYY;}CSF_IDLE_CONFIRM_TO_ACTIVE_6xx: N/A GPU7 - The Polling State went from IDLE_CONFIRM back to ACTIVE before DRMDMA went idle. 8YY<?DYNAMIC_CLK_VALID: Input from CGTT_LOCAL output: dyn_oclk_vld Y=@REGISTER_CLK_VALID: Input from CGTT_LOCAL output: reg_oclk_vld hYPY""YCP_DEBUG_DATAY DATA"YY""0YCP_DEBUG_CNTLYCP_DEBUG_INDX"YY܇܇""HYCP_INT_STAT_DEBUGYY!DISABLE_CNTX_SWITCH_INT_ASSERTED"YXY ENABLE_CNTX_SWITCH_INT_ASSERTED"pYY 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DB0_GRBM_stat_busy W0W$GRBM2_DB1_BUSY: DB1_GRBM_stat_busy 8WW$GRBM2_DB2_BUSY: DB2_GRBM_stat_busy WW$GRBM2_DB3_BUSY: DB3_GRBM_stat_busy W(W.GRBM2_CR_BUSY_R6xx: CR_GRBM_stat_busy (GPU6) PWW.GRBM2_CP_COHER_BUSY: CP_GRBM_stat_coher_busy WW"GRBM2_CP_BUSY: CP_GRBM_stat_busy W@W*GRBM2_CP_DMA_BUSY: CP_GRBM_stat_dma_busy PWW$GRBM2_CB0_BUSY: CB0_GRBM_stat_busy WW$GRBM2_CB1_BUSY: CB1_GRBM_stat_busy W@W$GRBM2_CB2_BUSY: CB2_GRBM_stat_busy HWW$GRBM2_CB3_BUSY: CB3_GRBM_stat_busy XW.GRBM2_VC_BUSY_R6xx: VC_GRBM_stat_busy (GPU6) XPX2GRBM2_EXTERN_STALL: Waiting for External Trigger XXAGRBM2_CP_DMA_IDLE_STALL: Waiting for CP's DMA engine to go idle HXX<GRBM2_GFX_IDLE_STALL: Waiting for Graphics Pipe to be idle XX LGRBM2_GFX_IDLE_CLEAN_STALL: Waiting for Graphics Pipe to be idle and clean X`X!HGRBM2_GFX_IDLE_STALL_R600: Waiting for Graphics Pipe to be idle (R600) X0X"XGRBM2_GFX_IDLE_CLEAN_STALL_R600: Waiting for Graphics Pipe to be idle and clean (R600) pXX#$GRBM2_TA4_BUSY: TA4_GRBM_stat_busy XX$$GRBM2_TA5_BUSY: TA5_GRBM_stat_busy X`X%$GRBM2_TA6_BUSY: TA6_GRBM_stat_busy hXX&$GRBM2_TA7_BUSY: TA7_GRBM_stat_busy XX'$GRBM2_TA8_BUSY: TA8_GRBM_stat_busy XXX($GRBM2_TA9_BUSY: TA9_GRBM_stat_busy h X X)&GRBM2_TA10_BUSY: TA10_GRBM_stat_busy  X X*&GRBM2_TA11_BUSY: TA11_GRBM_stat_busy X` X+&GRBM2_TA12_BUSY: TA12_GRBM_stat_busy x X X,&GRBM2_TA13_BUSY: TA13_GRBM_stat_busy ( X X-&GRBM2_TA14_BUSY: TA14_GRBM_stat_busy Xp X.&GRBM2_TA15_BUSY: TA15_GRBM_stat_busy X X//GRBM2_RESERVED0: Reserved for Future Projects HX X0/GRBM2_RESERVED1: Reserved for Future Projects XX1/GRBM2_RESERVED2: Reserved for Future Projects XHX2/GRBM2_RESERVED3: Reserved for Future Projects xXX3/GRBM2_RESERVED4: Reserved for Future Projects 0XX4/GRBM2_RESERVED5: Reserved for Future Projects XxX5/GRBM2_RESERVED6: Reserved for Future Projects X0X6/GRBM2_RESERVED7: Reserved for Future Projects XXX7/GRBM2_RESERVED8: Reserved for Future Projects XX8/GRBM2_RESERVED9: Reserved for Future Projects XXX90GRBM2_RESERVED10: Reserved for Future Projects XX:0GRBM2_RESERVED11: Reserved for Future Projects 8XX;0GRBM2_RESERVED12: Reserved for Future Projects XX<0GRBM2_RESERVED13: Reserved for Future Projects X8X=0GRBM2_RESERVED14: Reserved for Future Projects `XX>0GRBM2_RESERVED15: Reserved for Future Projects X?@GRBM2_USER_DEFINED_BUSY: User defined busy based on busy masks XX VGT_BUSY_USER_DEFINED_MASK"X0X TA_BUSY_USER_DEFINED_MASK"8XXSX_BUSY_USER_DEFINED_MASK"XXSH_BUSY_USER_DEFINED_MASK"X@XSPI_BUSY_USER_DEFINED_MASK"HXXSC_BUSY_USER_DEFINED_MASK"XXPA_BUSY_USER_DEFINED_MASK"XPXGRBM_BUSY_USER_DEFINED_MASK"XXXDB_BUSY_USER_DEFINED_MASK" XXCB_BUSY_USER_DEFINED_MASK"` XCP_BUSY_USER_DEFINED_MASK"WWpp""WGRBM_PERFCOUNTER1_SELECT XWPWWPERF_COUNT1_SEL@XWW0GRBM1_COUNT: Tie High - Count Number of Clocks WWGRBM1_GUI_ACTIVE: GUI Active WHW2GRBM1_VGT_NO_DMA_BUSY: VGT_GRBM_stat_no_dma_busy hWW,GRBM1_VGT_DMA_BUSY: VGT_GRBM_stat_dma_busy WW$GRBM1_TA0_BUSY: TA0_GRBM_stat_busy WXW$GRBM1_TA1_BUSY: TA1_GRBM_stat_busy `WW$GRBM1_TA2_BUSY: TA2_GRBM_stat_busy WW$GRBM1_TA3_BUSY: TA3_GRBM_stat_busy WPW.GRBM1_TC_BUSY_R6xx: TC_GRBM_stat_busy (GPU6) hWW "GRBM1_SX_BUSY: SX_GRBM_stat_busy WW "GRBM1_SH_BUSY: SH_GRBM_stat_busy WXW $GRBM1_SPI_BUSY: SPI_GRBM_stat_busy pWW 0GRBM1_SMX_BUSY_R6xx: SMX_GRBM_stat_busy (GPU6) WW "GRBM1_SC_BUSY: SC_GRBM_stat_busy W`W6GRBM1_DRMDMA_BUSY_R6xx: DRMDMA_GRBM_stat_busy (GPU6) W W"GRBM1_PA_BUSY: PA_GRBM_stat_busy (WW$GRBM1_DB0_BUSY: DB0_GRBM_stat_busy WpW$GRBM1_DB1_BUSY: DB1_GRBM_stat_busy xWW$GRBM1_DB2_BUSY: DB2_GRBM_stat_busy WW$GRBM1_DB3_BUSY: DB3_GRBM_stat_busy WhW.GRBM1_CR_BUSY_R6xx: CR_GRBM_stat_busy (GPU6) W W.GRBM1_CP_COHER_BUSY: CP_GRBM_stat_coher_busy 8WW"GRBM1_CP_BUSY: CP_GRBM_stat_busy WW*GRBM1_CP_DMA_BUSY: CP_GRBM_stat_dma_busy W0W$GRBM1_CB0_BUSY: CB0_GRBM_stat_busy 8WW$GRBM1_CB1_BUSY: CB1_GRBM_stat_busy WW$GRBM1_CB2_BUSY: CB2_GRBM_stat_busy W(W$GRBM1_CB3_BUSY: CB3_GRBM_stat_busy @WW.GRBM1_VC_BUSY_R6xx: VC_GRBM_stat_busy (GPU6) WW2GRBM1_EXTERN_STALL: Waiting for External Trigger W@WAGRBM1_CP_DMA_IDLE_STALL: Waiting for CP's DMA engine to go idle WW<GRBM1_GFX_IDLE_STALL: Waiting for Graphics Pipe to be idle PWW LGRBM1_GFX_IDLE_CLEAN_STALL: Waiting for Graphics Pipe to be idle and clean WW!HGRBM1_GFX_IDLE_STALL_R600: Waiting for Graphics Pipe to be idle (R600) WhW"XGRBM1_GFX_IDLE_CLEAN_STALL_R600: Waiting for Graphics Pipe to be idle and clean (R600) WHW#$GRBM1_TA4_BUSY: TA4_GRBM_stat_busy PWW$$GRBM1_TA5_BUSY: TA5_GRBM_stat_busy WW%$GRBM1_TA6_BUSY: TA6_GRBM_stat_busy W@W&$GRBM1_TA7_BUSY: TA7_GRBM_stat_busy HWW'$GRBM1_TA8_BUSY: TA8_GRBM_stat_busy WW($GRBM1_TA9_BUSY: TA9_GRBM_stat_busy W8W)&GRBM1_TA10_BUSY: TA10_GRBM_stat_busy PWW*&GRBM1_TA11_BUSY: TA11_GRBM_stat_busy WW+&GRBM1_TA12_BUSY: TA12_GRBM_stat_busy WHW,&GRBM1_TA13_BUSY: TA13_GRBM_stat_busy `WW-&GRBM1_TA14_BUSY: TA14_GRBM_stat_busy WW.&GRBM1_TA15_BUSY: TA15_GRBM_stat_busy WXW//GRBM1_RESERVED0: Reserved for Future Projects WW0/GRBM1_RESERVED1: Reserved for Future Projects 8WW1/GRBM1_RESERVED2: Reserved for Future Projects WW2/GRBM1_RESERVED3: Reserved for Future Projects W8W3/GRBM1_RESERVED4: Reserved for Future Projects `WW4/GRBM1_RESERVED5: Reserved for Future Projects WW5/GRBM1_RESERVED6: Reserved for Future Projects W`W6/GRBM1_RESERVED7: Reserved for Future Projects WW7/GRBM1_RESERVED8: Reserved for Future Projects @WW8/GRBM1_RESERVED9: Reserved for Future Projects WW90GRBM1_RESERVED10: Reserved for Future Projects W@W:0GRBM1_RESERVED11: Reserved for Future Projects hWW;0GRBM1_RESERVED12: Reserved for Future Projects WW<0GRBM1_RESERVED13: Reserved for Future Projects WhW=0GRBM1_RESERVED14: Reserved for Future Projects W W>0GRBM1_RESERVED15: Reserved for Future Projects W?@GRBM1_USER_DEFINED_BUSY: User defined busy based on busy masks WW VGT_BUSY_USER_DEFINED_MASK"W`W TA_BUSY_USER_DEFINED_MASK"hWWSX_BUSY_USER_DEFINED_MASK"WWSH_BUSY_USER_DEFINED_MASK"WpWSPI_BUSY_USER_DEFINED_MASK"xW WSC_BUSY_USER_DEFINED_MASK"(WWPA_BUSY_USER_DEFINED_MASK"WWGRBM_BUSY_USER_DEFINED_MASK"W0WDB_BUSY_USER_DEFINED_MASK"8WWCB_BUSY_USER_DEFINED_MASK"WCP_BUSY_USER_DEFINED_MASK"WW``""سWGRBM_INT_CNTLW0WRDERR_INT_ENABLE"شWGUI_IDLE_INT_ENABLE"WxWXX""ȯWGRBM_READ_ERRORpW W READ_ADDRESS"WȰWREAD_REQUESTER_SRBM"WpWREAD_REQUESTER_CP"pWWREAD_REQUESTER_WU_POLL"ȲW READ_ERROR"`W0WTT""WGRBM_DEBUG_SNAPSHOT WجWVGT_RDY"WxW SRBM_RDY"`WWSH_RDY"WCP_RDY"WئWPP"" W GRBM_DEBUGWxW OVERRIDE_WU"`WW IGNORE_RDY"WW IGNORE_FAO"WXWDISABLE_READ_TIMEOUT"XWWSNAPSHOT_FREE_CNTRS"WWHYSTERESIS_GUI_ACTIVE"`W GFX_CLOCK_DOMAIN_OVERRIDE"xW`WLL""WWAIT_UNTIL_POLL_REFDATAW POLL_REFDATA"WWHH""HWWAIT_UNTIL_POLL_MASKW POLL_MASK"W(WDD""WWAIT_UNTIL_POLL_CNTL WءW POLL_ADDR"ТWxWPOLL_COMPARE_FUNCTION"(W POLL_INTERVAL"WpW@@""W WAIT_UNTIL`WWWAIT_CP_DMA_IDLE"WW  WAIT_CMDFIFO"W`W WAIT_3D_IDLE"XWWWAIT_3D_IDLECLEAN"WWWAIT_EXTERN_SIG"`WCMDFIFO_ENTRIES" WW44""PWGRBM_WAIT_IDLE_CLOCKSWWAIT_IDLE_CLOCKS"WW""W DEBUG_DATA8W DEBUG_DATA"W8W""W DEBUG_INDEXؘW DEBUG_INDEX"@W W00""pWGRBM_GFX_CLKEN_CNTLWȖWPREFIX_DELAY_CNT"pWPOST_DELAY_CNT"ВWW((""WGRBM_DEBUG_DATA`W DATA"(WHW$$""WGRBM_DEBUG_CNTLWGRBM_DEBUG_INDEX"@wWW ""WGRBM_SOFT_RESET WHWSOFT_RESET_CP"@WWSOFT_RESET_CB"WWSOFT_RESET_DB"W@WSOFT_RESET_PA"8WWSOFT_RESET_SC"WWSOFT_RESET_SPI"W8W SOFT_RESET_SH"0WW SOFT_RESET_SX"ؐWW SOFT_RESET_TC"W0W SOFT_RESET_TA"(WؑW SOFT_RESET_VC"WSOFT_RESET_VGT"iWwW""xW GRBM_STATUS2xW`xW SX_CLEAN"HyWyW TA12_BUSY"yWyW TA13_BUSY"zW@zW TA14_BUSY"({WzW TA15_BUSY"{W{W SPI0_BUSY"h|W |W  SPI1_BUSY"}W|W  SPI2_BUSY"}W`}W  SPI3_BUSY"H~W~W  TA0_BUSY"~W~W  TA1_BUSY"W@W TA2_BUSY"(WW TA3_BUSY"ȀWW DB0_BUSY"hW W DB1_BUSY"WW DB2_BUSY"W`W DB3_BUSY"HWW CB0_BUSY"WW CB1_BUSY"W@W CB2_BUSY"(WW CB3_BUSY"ȅWW TA4_BUSY"hW W TA5_BUSY"WW TA6_BUSY"W`W TA7_BUSY"HWW TA8_BUSY"WW TA9_BUSY"W@W TA10_BUSY"W TA11_BUSY"gW8jW""jW GRBM_STATUS(kWjWCMDFIFO_AVAIL"kWkWSRBM_RQ_PENDING"xlW(lWCF_RQ_PENDING" mWlWPF_RQ_PENDING"mWxmW  GRBM_EE_BUSY"hnW nW  DB03_CLEAN"oWnW  CB03_CLEAN"oW`oWTA_BUSY"XpWpWVGT_BUSY_NO_DMA"pWpW VGT_BUSY"qWPqWSX_BUSY"8rWqWSH_BUSY"rWrW SPI03_BUSY"xsW0sWSC_BUSY"tWsWPA_BUSY"tWptW DB03_BUSY"`uWuWCP_COHERENCY_BUSY"vWuWCP_BUSY"vWXvW CB03_BUSY"vW GUI_ACTIVE"eW0hW ""hWGRBM_PWR_CNTL iWhW REQ_TYPE"xiW RSP_TYPE"@dW fW""pfWGRBM_SKEW_CNTLgWfWSKEW_TOP_THRESHOLD"pgW SKEW_COUNT"0bWdW""eW GRBM_CNTLXeW READ_TIMEOUT"`WbW""bWGRBM_CAM_DATAcWPcW CAM_ADDR"cWCAM_REMAPADDR"`ZW@aW""aWGRBM_CAM_INDEXaW CAM_INDEX"SWZW""([WCB_DEBUG_BUS_15[W[WCM_BUSY"h\W \WFC_BUSY"]W\WCC_BUSY"]W`]WBB_BUSY"H^W^WMA_BUSY"^W^W CB_FROZEN"_W@_WCORE_SCLK_VLD"_W REG_SCLK_VLD"0MWSW""SWCB_DEBUG_BUS_14 xTW(TWMC_RDREQ_CREDITS" UWTWLAST_RD_GRANT_VEC"UWxUW CC_RDREQ_EMPTY"pVW VW FC_RDREQ_EMPTY"WWVW CM_RDREQ_EMPTY"WWpWW MC_WRREQ_CREDITS"hXWXWLAST_WR_GRANT_VEC"YWXWCC_WRREQ_EMPTY"YWhYWFC_WRREQ_EMPTY"ZWCM_WRREQ_EMPTY"PGWMW""MWCB_DEBUG_BUS_13NWPNWSURF_SYNC_STATE"HOWNWSURF_SYNC_START"OWOWSF_BUSY"PW@PWCS_BUSY"(QWPWRB_BUSY"QWQWDS_BUSY"hRW RWTB_BUSY"RWIB_BUSY"=WGW""HWCB_DEBUG_BUS_12HWpHWTILE_RETIREMENT_BUSY"hIW IW FOP_BUSY"JWIW LAT_BUSY"JW`JWCACHE_CTL_BUSY"PKWKW ADDR_BUSY"KWKW MERGE_BUSY"LWHLW QUAD_BUSY"LW TILE_BUSY"W||""`>WCB_DEBUG_BUS_11?W>W MU_STATE"?WX?W TIF_FULL"@@W?W  TIF_EMPTY"@W@W TQ_FULL"AW8AW  TQ_EMPTY"(BWAW MC_WR_PENDING"BWBW FC_WR_PENDING"xCW(CWFC_RD_PENDING" DWCWEVICT_PENDING"DWxDWLAST_RD_ARB_WINNER"pEW EWCACHE_CTRL_BUSY"FWEW CRW_BUSY"FWhFWTQ_BUSY"GWMU_BUSY"6CB_PERF_SEL_CC_CACHE_HIT: Number of fmask cache hits VV?CB_PERF_SEL_CC_CACHE_TAG_MISS: Number of fmask cache tag misses. A tag miss is when there isn't a tag that matches the input. Because of sectoring, a tag hit does not imply that the required data is in the cache. 8VV@CB_PERF_SEL_CC_CACHE_SECTOR_MISS: Number of fmask cache sector misses. A sector miss is when the required sector is not in the cache. Tag misses are included in this count because a sector cannot be in the cache if there is no tag for it. HVVACB_PERF_SEL_CC_CACHE_REEVICTION_STALL: The color cache is stalled because it is trying to evict a line that already has a pending evict VVBCB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL: The color cache is stalled because it is trying to evict a line that has a nonzero inflight count. This is usually a sign that the cache is unable to withstand the memory read latency. VVC:CB_PERF_SEL_CC_CACHE_EVICT_NONRESIDENT_STALL: DEPRECATED VVDCB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL: The color cache is stalled because the line being replaced has a pending evict. This is usually a sign that the cache is unable to withstand the memory write latency. V(VECB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL: The color cache is stalled because one of the inflight counters has reached the maximum value. VHVFuCB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL: The color cache is stalled because the read request output path is stalled. VPVGwCB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL: The color cache is stalled because the write request output path is stalled. VPVHsCB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL: The color cache is stalled because the acknowledge output path is stalled. VHVICB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION: The number of times a write allocate cache line is converted to a read-modify-write cache line. VXVJpCB_PERF_SEL_CC_CACHE_FLUSH: This is the number of color cache flushes. This is includes surface sync flushes. HVPVKCB_PERF_SEL_CM_MC_READ_REQUEST: Number of 32-byte cmask mc read requests. Cmask does not make 32-byte requests, so the counter will report the equivalent number of 32-byte requests. VVLKCB_PERF_SEL_FC_MC_READ_REQUEST: Number of 32-byte fmask mc read requests. XV`VMCB_PERF_SEL_CC_MC_READ_REQUEST: Number of 32-byte color mc read requests. Color does not make 32-byte requests, so the counter will report the equivalent number of 32-byte requests. 0VVNMCB_PERF_SEL_CM_MC_WRITE_REQUEST: Number of 32-byte cmask mc write requests. VxVOMCB_PERF_SEL_FC_MC_WRITE_REQUEST: Number of 32-byte fmask mc write requests. VPVPMCB_PERF_SEL_CC_MC_WRITE_REQUEST: Number of 32-byte color mc write requests. V(VQ!CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT: Number of 32-byte cmask mc read requests in flight. Cmask does not make 32-byte requests, so the counter will report the equivalent number of 32-byte requests. Dividing this number by the cmask read request count produces the average latency. VVRCB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT: Number of 32-byte fmask mc read requests in flight. Dividing this number by the fmask read request count produces the average latency. hVVS!CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT: Number of 32-byte color mc read requests in flight. Color does not make 32-byte requests, so the counter will report the equivalent number of 32-byte requests. Dividing this number by the color read request count produces the average latency. VVTCB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT: Number of 32-byte cmask mc write requests in flight. Dividing this number by the cmask write request count produces the average latency. VVUCB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT: Number of 32-byte fmask mc write requests in flight. Dividing this number by the fmask write request count produces the average latency. (V0VVCB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT: Number of 32-byte color mc write requests in flight. Dividing this number by the color write request count produces the average latency. VpVW6CB_PERF_SEL_CC_SURFACE_SYNC: Number of surface syncs (V0VXCB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT: Number of quad fragments that require two cache probes. AA blending can create these when the read fragment does not match the write fragment. VpVYJCB_PERF_SEL_SLOW_MODE_QUAD_FRAGMENT: Number of slow mode quad fragments. V@VZeCB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT: This is the number of dual source color quad fragments V0V[cCB_PERF_SEL_DRAWN_QUAD: This is the number of drawn quads. Filtering has an effect in this mode. VV\eCB_PERF_SEL_DRAWN_PIXEL: This is the number of drawn pixels. Filtering has an effect in this mode. VV]uCB_PERF_SEL_DRAWN_QUAD_FRAGMENT: This is the number of drawn quad fragments. Filtering has an effect in this mode. VV^CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL: This is the number of times the blend pipeline is stalled to handle read after write hazards. VV_pCB_PERF_SEL_EVENT: Total number of events reaching the CB. This includes events that the CB does not process. VV`CCB_PERF_SEL_EVENT_CACHE_FLUSH_TS: Number of CACHE_FLUSH_TS events XVVa@CB_PERF_SEL_EVENT_CONTEXT_DONE: Number of CONTEXT_DONE events VVb=CB_PERF_SEL_EVENT_CACHE_FLUSH: Number of CACHE_FLUSH events VhVc_CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT: Number of CACHE_FLUSH_AND_INV_TS_EVENT events VPVdXCB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT: Number of_CACHE_FLUSH_AND_INV_EVENTevents V0VeWCB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS: Number of FLUSH_AND_INV_CB_DATA_TS events VVfQCB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META: Number of FLUSH_AND_INV_CB_META events VVgCB_PERF_SEL_CMASK_READ_DATA_0xC: Number of times a value of 0xC was read from cmask. Cmask reads only occur on fmask cache misses. A value of 0xC means that a fmask tile requires 0 bit planes. 0V0VhCB_PERF_SEL_CMASK_READ_DATA_0xD: Number of times a value of 0xD was read from cmask. Cmask reads only occur on fmask cache misses. A value of 0xD means that a fmask tile requires 1 bit planes. xVxViCB_PERF_SEL_CMASK_READ_DATA_0xE: Number of times a value of 0xE was read from cmask. Cmask reads only occur on fmask cache misses. A value of 0xE means that a fmask tile requires 2 bit planes. VVjCB_PERF_SEL_CMASK_READ_DATA_0xF: Number of times a value of 0xF was read from cmask. Cmask reads only occur on fmask cache misses. A value of 0xF means that a fmask tile requires 3 bit planes. VVkVCB_PERF_SEL_CMASK_WRITE_DATA_0xC: Number of times a value of 0xC was written to cmask. Cmask writes occur at the end of a tile. The hardware does not perform the write if fmask has not changed, but the counter will update as if regardless of whether the hardware wrote or not. A value of 0xC means that a fmask tile requires 0 bit planes. VVlVCB_PERF_SEL_CMASK_WRITE_DATA_0xD: Number of times a value of 0xD was written to cmask. Cmask writes occur at the end of a tile. The hardware does not perform the write if fmask has not changed, but the counter will update as if regardless of whether the hardware wrote or not. A value of 0xD means that a fmask tile requires 1 bit planes. `VVmVCB_PERF_SEL_CMASK_WRITE_DATA_0xE: Number of times a value of 0xE was written to cmask. Cmask writes occur at the end of a tile. The hardware does not perform the write if fmask has not changed, but the counter will update as if regardless of whether the hardware wrote or not. A value of 0xE means that a fmask tile requires 2 bit planes. @VVnVCB_PERF_SEL_CMASK_WRITE_DATA_0xF: Number of times a value of 0xF was written to cmask. Cmask writes occur at the end of a tile. The hardware does not perform the write if fmask has not changed, but the counter will update as if regardless of whether the hardware wrote or not. A value of 0xF means that a fmask tile requires 3 bit planes. VVoMCB_PERF_SEL_CORE_SCLK_VLD: Number of cycles that the core clock is enabled. `VpPCB_PERF_SEL_REG_SCLK_VLD: Number of cycles that the register clock is enabled. VHVOP_FILTER_ENABLE"WV @WOP_FILTER_SELWWDCB_PERF_OP_FILTER_SEL_WRITE_ONLY: Only count write only operations WPWuCB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION: Only count an operation if it needs the destination data like blend or rop WPW>CB_PERF_OP_FILTER_SEL_RESOLVE: Only count resolve operations WDCB_PERF_OP_FILTER_SEL_EXPAND: Only count expand samples operations HWW FORMAT_FILTER_ENABLE"WW WFORMAT_FILTER_SEL$W8W+COLOR_INVALID: this resource is disabled 8WWCOLOR_8: norm, int WWCOLOR_4_4: norm only xW WCOLOR_3_3_2: norm only WW RESERVED WPWCOLOR_16: norm, int, float H WWCOLOR_16_FLOAT: float only W WCOLOR_8_8: norm, int W0 WCOLOR_5_6_5: norm only ( W W COLOR_6_5_5: norm only Wp W ;COLOR_1_5_5_5: norm only, 1-bit component is always unorm W0 W COLOR_4_4_4_4: norm only H W W ;COLOR_5_5_5_1: norm only, 1-bit component is always unorm W W COLOR_32: int, float W0WCOLOR_32_FLOAT: float only 0WWCOLOR_16_16: norm, int, float WxWCOLOR_16_16_FLOAT: float only W W'COLOR_8_24: unorm depth, uint stencil PWW@COLOR_8_24_FLOAT: float depth, uint stencil; deprecated for CB WW'COLOR_24_8: unorm depth, uint stencil WHW@COLOR_24_8_FLOAT: float depth, uint stencil; deprecated for CB hWWCOLOR_10_11_11: float only WW"COLOR_10_11_11_FLOAT: float only WXWCOLOR_11_11_10: float only XWW"COLOR_11_11_10_FLOAT: float only WWCOLOR_2_10_10_10: norm, int WHW COLOR_8_8_8_8: norm, int, srgb PWWCOLOR_10_10_10_2: norm, int WW1COLOR_X24_8_32_FLOAT: float depth, uint stencil WPWCOLOR_32_32: int, float PWWCOLOR_32_32_FLOAT: float only WW%COLOR_16_16_16_16: norm, int, float WHW +COLOR_16_16_16_16_FLOAT: norm, int, float @WW! RESERVED WW"COLOR_32_32_32_32: int, float 0W#%COLOR_32_32_32_32_FLOAT: float only PWWMSAA_NUM_SAMPLES_FILTER_ENABLE"WWMSAA_NUM_SAMPLES_FILTER_SEL"WXWMRT_FILTER_ENABLE"PWWMRT_FILTER_SEL" WW#FMASK_QUAD_FRAGMENTS_FILTER_ENABLE""W` W W!FMASK_QUAD_FRAGMENTS_FILTER_TYPE!W!WZCB_PERF_FMASK_QUAD_FRAGMENTS_FILTER_TYPE_SEL_READ: Filter based on the fmask read values !W\CB_PERF_FMASK_QUAD_FRAGMENTS_FILTER_TYPE_SEL_WRITE: Filter based on the fmask write values "W"FMASK_QUAD_FRAGMENTS_FILTER_COUNT"?U8U((""UCB_PERF_CTR2_SEL ]VU USELqUhU)CB_PERF_SEL_BUSY: Number of busy cycles UUCB_PERF_SEL_DB_CB_TILE_VALID_READY: Number of cycles the DB to CB tile interface is valid and ready. This is measured after the input fifo. U0UCB_PERF_SEL_DB_CB_TILE_VALID_READYB: Number of cycles the DB to CB tile interface is valid and not ready. This is measured after the input fifo. UHUCB_PERF_SEL_DB_CB_TILE_VALIDB_READY: Number of cycles the DB to CB tile interface is not valid and ready. This is measured after the input fifo. 8U`UCB_PERF_SEL_DB_CB_TILE_VALIDB_READYB: Number of cycles the DB to CB tile interface is not valid and not ready. This is measured after the input fifo. PUUCB_PERF_SEL_DB_CB_LQUAD_VALID_READY: Number of cycles the DB to CB lquad interface is valid and ready. This is measured after the input fifo hUUCB_PERF_SEL_DB_CB_LQUAD_VALID_READYB: Number of cycles the DB to CB lquad interface is valid and not ready. This is measured after the input fifo UUCB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY: Number of cycles the DB to CB lquad interface is not valid and ready. This is measured after the input fifo UUCB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB: Number of cycles the DB to CB lquad interface is not valid and not ready. This is measured after the input fifo UU CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY: Number of cycles the CB to TAP write request interface is valid and ready. This is measured at the interface converter rather than directly on the interface. @U8U CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB: Number of cycles the CB to TAP write request interface is valid and not ready. This is measured at the interface converter rather than directly on the interface. UU CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY: Number of cycles the CB to TAP write request interface is valid and ready. This is measured at the interface converter rather than directly on the interface. UU CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB: Number of cycles the CB to TAP write request interface is not valid and not ready. This is measured at the interface converter rather than directly on the interface. 8U0U CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY: Number of cycles the CB to TAP read request interface is valid and ready. This is measured at the interface converter rather than directly on the interface. UUCB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB: Number of cycles the CB to TAP read request interface is valid and not ready. This is measured at the interface converter rather than directly on the interface. UUCB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY: Number of cycles the CB to TAP read request interface is not valid and ready. This is measured at the interface converter rather than directly on the interface. 0U UCB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB: Number of cycles the CB to TAP read request interface is not valid and not ready. This is measured at the interface converter rather than directly on the interface. UxUkCB_PERF_SEL_CM_FC_TILE_VALID_READY: Number of cycles the cmask to fmask tile interface is valid and ready UhUpCB_PERF_SEL_CM_FC_TILE_VALID_READYB: Number of cycles the cmask to fmask tile interface is valid and not ready U`UpCB_PERF_SEL_CM_FC_TILE_VALIDB_READY: Number of cycles the cmask to fmask tile interface is not valid and ready UXUuCB_PERF_SEL_CM_FC_TILE_VALIDB_READYB: Number of cycles the cmask to fmask tile interface is not valid and not ready UXUpCB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY: Number of cycles the fmask to color cache interface is valid and ready UPUuCB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB: Number of cycles the fmask to color cache interface is valid and not ready UPUuCB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY: Number of cycles the fmask to color cache interface is not valid and ready UPUzCB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB: Number of cycles the fmask to color cache interface is not valid and not ready UPUeCB_PERF_SEL_FOP_IN_VALID_READY: Number of cycles the fragop unit input interface is valid and ready U@UjCB_PERF_SEL_FOP_IN_VALID_READYB: Number of cycles the fragop unit input interface is valid and not ready V0VjCB_PERF_SEL_FOP_IN_VALIDB_READY: Number of cycles the fragop unit input interface is not valid and ready V VoCB_PERF_SEL_FOP_IN_VALIDB_READYB: Number of cycles the fragop unit input interface is not valid and not ready VVCB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY: Mumber of cycles the color cache input block to tag block interface is valid and ready V VCB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB: Mumber of cycles the color cache input block to tag block interface is valid and not ready V(VCB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY: Mumber of cycles the color cache input block to tag block interface is not valid and ready V0V CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB: Mumber of cycles the color cache input block to tag block interface is not valid and not ready V@V!=CB_PERF_SEL_CC_SF_FULL: The color cache source fifo is full VV"@CB_PERF_SEL_CC_RB_FULL: The color cache reorder buffer is full XVV#ECB_PERF_SEL_FC_RDLAT_FIFO_FULL: The fmask read latency fifo is full  VV$6CB_PERF_SEL_CM_TQ_FULL: The cmask tile queue is full  V` V%wCB_PERF_SEL_LQUAD_NO_TILE: A quad has arrived over the lquad interface but the corresponding tile has not arrive yet. V` V&6CB_PERF_SEL_CM_CACHE_HIT: Number of cmask cache hits 8 V V'CB_PERF_SEL_CM_CACHE_TAG_MISS: Number of cmask cache tag misses. A tag miss is when there isn't a tag that matches the input. Because of sectoring, a tag hit does not imply that the required data is in the cache. V V(CB_PERF_SEL_CM_CACHE_SECTOR_MISS: Number of cmask cache sector misses. A sector miss is when the required sector is not in the cache. Tag misses are included in this count because a sector cannot be in the cache if there is no tag for it. V V)CB_PERF_SEL_CM_CACHE_REEVICTION_STALL: The cmask cache is stalled because it is trying to evict a line that already has a pending evict 8VV*CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL: The cmask cache is stalled because it is trying to evict a line that has a nonzero inflight count. This is usually a sign that the cache is unable to withstand the memory read latency. VV+:CB_PERF_SEL_CM_CACHE_EVICT_NONRESIDENT_STALL: DEPRECATED XV@V,CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL: The cmask cache is stalled because the line being replaced has a pending evict. This is usually a sign that the cache is unable to withstand the memory write latency. xVV-CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL: The cmask cache is stalled because one of the inflight counters has reached the maximum value. xVV.uCB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL: The cmask cache is stalled because the read request output path is stalled. xVV/wCB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL: The cmask cache is stalled because the write request output path is stalled. pVV0sCB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL: The cmask cache is stalled because the acknowledge output path is stalled. @VV1HCB_PERF_SEL_CM_CACHE_FLUSH: This is the number of cmask cache flushes. VV26CB_PERF_SEL_FC_CACHE_HIT: Number of fmask cache hits `VHV3CB_PERF_SEL_FC_CACHE_TAG_MISS: Number of fmask cache tag misses. A tag miss is when there isn't a tag that matches the input. Because of sectoring, a tag hit does not imply that the required data is in the cache. VV4CB_PERF_SEL_FC_CACHE_SECTOR_MISS: Number of fmask cache sector misses. A sector miss is when the required sector is not in the cache. Tag misses are included in this count because a sector cannot be in the cache if there is no tag for it. V V5CB_PERF_SEL_FC_CACHE_REEVICTION_STALL: The fmask cache is stalled because it is trying to evict a line that already has a pending evict `V0V6CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL: The fmask cache is stalled because it is trying to evict a line that has a nonzero inflight count. This is usually a sign that the cache is unable to withstand the memory read latency. VV7:CB_PERF_SEL_FC_CACHE_EVICT_NONRESIDENT_STALL: DEPRECATED VhV8CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL: The fmask cache is stalled because the line being replaced has a pending evict. This is usually a sign that the cache is unable to withstand the memory write latency. VV9CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL: The fmask cache is stalled because one of the inflight counters has reached the maximum value. !V V:uCB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL: The fmask cache is stalled because the read request output path is stalled. "V!V;wCB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL: The fmask cache is stalled because the write request output path is stalled. #V"V<sCB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL: The fmask cache is stalled because the acknowledge output path is stalled. h$V#V=HCB_PERF_SEL_FC_CACHE_FLUSH: This is the number of fmask cache flushes. (%V$V>6CB_PERF_SEL_CC_CACHE_HIT: Number of fmask cache hits &Vp%V?CB_PERF_SEL_CC_CACHE_TAG_MISS: Number of fmask cache tag misses. A tag miss is when there isn't a tag that matches the input. Because of sectoring, a tag hit does not imply that the required data is in the cache. (V&V@CB_PERF_SEL_CC_CACHE_SECTOR_MISS: Number of fmask cache sector misses. A sector miss is when the required sector is not in the cache. Tag misses are included in this count because a sector cannot be in the cache if there is no tag for it. )VH(VACB_PERF_SEL_CC_CACHE_REEVICTION_STALL: The color cache is stalled because it is trying to evict a line that already has a pending evict *VX)VBCB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL: The color cache is stalled because it is trying to evict a line that has a nonzero inflight count. This is usually a sign that the cache is unable to withstand the memory read latency. H+V*VC:CB_PERF_SEL_CC_CACHE_EVICT_NONRESIDENT_STALL: DEPRECATED ,V+VDCB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL: The color cache is stalled because the line being replaced has a pending evict. This is usually a sign that the cache is unable to withstand the memory write latency. -V,VECB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL: The color cache is stalled because one of the inflight counters has reached the maximum value. .V.VFuCB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL: The color cache is stalled because the read request output path is stalled. /V/VGwCB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL: The color cache is stalled because the write request output path is stalled. 0V0VHsCB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL: The color cache is stalled because the acknowledge output path is stalled. 1V1VICB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION: The number of times a write allocate cache line is converted to a read-modify-write cache line. 2V2VJpCB_PERF_SEL_CC_CACHE_FLUSH: This is the number of color cache flushes. This is includes surface sync flushes. 4V3VKCB_PERF_SEL_CM_MC_READ_REQUEST: Number of 32-byte cmask mc read requests. Cmask does not make 32-byte requests, so the counter will report the equivalent number of 32-byte requests. 4VP4VLKCB_PERF_SEL_FC_MC_READ_REQUEST: Number of 32-byte fmask mc read requests. 6V 5VMCB_PERF_SEL_CC_MC_READ_REQUEST: Number of 32-byte color mc read requests. Color does not make 32-byte requests, so the counter will report the equivalent number of 32-byte requests. 6V`6VNMCB_PERF_SEL_CM_MC_WRITE_REQUEST: Number of 32-byte cmask mc write requests. 7V87VOMCB_PERF_SEL_FC_MC_WRITE_REQUEST: Number of 32-byte fmask mc write requests. 8V8VPMCB_PERF_SEL_CC_MC_WRITE_REQUEST: Number of 32-byte color mc write requests. H:V8VQ!CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT: Number of 32-byte cmask mc read requests in flight. Cmask does not make 32-byte requests, so the counter will report the equivalent number of 32-byte requests. Dividing this number by the cmask read request count produces the average latency. ;V:VRCB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT: Number of 32-byte fmask mc read requests in flight. Dividing this number by the fmask read request count produces the average latency. (=V;VS!CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT: Number of 32-byte color mc read requests in flight. Color does not make 32-byte requests, so the counter will report the equivalent number of 32-byte requests. Dividing this number by the color read request count produces the average latency. h>Vp=VTCB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT: Number of 32-byte cmask mc write requests in flight. Dividing this number by the cmask write request count produces the average latency. ?V>VUCB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT: Number of 32-byte fmask mc write requests in flight. Dividing this number by the fmask write request count produces the average latency. @V?VVCB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT: Number of 32-byte color mc write requests in flight. Dividing this number by the color write request count produces the average latency. AV0AVW6CB_PERF_SEL_CC_SURFACE_SYNC: Number of surface syncs BVAVXCB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT: Number of quad fragments that require two cache probes. AA blending can create these when the read fragment does not match the write fragment. CV0CVYJCB_PERF_SEL_SLOW_MODE_QUAD_FRAGMENT: Number of slow mode quad fragments. DVDVZeCB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT: This is the number of dual source color quad fragments EVDV[cCB_PERF_SEL_DRAWN_QUAD: This is the number of drawn quads. Filtering has an effect in this mode. FVEV\eCB_PERF_SEL_DRAWN_PIXEL: This is the number of drawn pixels. Filtering has an effect in this mode. GVFV]uCB_PERF_SEL_DRAWN_QUAD_FRAGMENT: This is the number of drawn quad fragments. Filtering has an effect in this mode. HVGV^CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL: This is the number of times the blend pipeline is stalled to handle read after write hazards. IVHV_pCB_PERF_SEL_EVENT: Total number of events reaching the CB. This includes events that the CB does not process. PJVIV`CCB_PERF_SEL_EVENT_CACHE_FLUSH_TS: Number of CACHE_FLUSH_TS events KVJVa@CB_PERF_SEL_EVENT_CONTEXT_DONE: Number of CONTEXT_DONE events KV`KVb=CB_PERF_SEL_EVENT_CACHE_FLUSH: Number of CACHE_FLUSH events LV(LVc_CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT: Number of CACHE_FLUSH_AND_INV_TS_EVENT events MVMVdXCB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT: Number of_CACHE_FLUSH_AND_INV_EVENTevents NVMVeWCB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS: Number of FLUSH_AND_INV_CB_DATA_TS events `OVNVfQCB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META: Number of FLUSH_AND_INV_CB_META events PVOVgCB_PERF_SEL_CMASK_READ_DATA_0xC: Number of times a value of 0xC was read from cmask. Cmask reads only occur on fmask cache misses. A value of 0xC means that a fmask tile requires 0 bit planes. QVPVhCB_PERF_SEL_CMASK_READ_DATA_0xD: Number of times a value of 0xD was read from cmask. Cmask reads only occur on fmask cache misses. A value of 0xD means that a fmask tile requires 1 bit planes. 8SV8RViCB_PERF_SEL_CMASK_READ_DATA_0xE: Number of times a value of 0xE was read from cmask. Cmask reads only occur on fmask cache misses. A value of 0xE means that a fmask tile requires 2 bit planes. TVSVjCB_PERF_SEL_CMASK_READ_DATA_0xF: Number of times a value of 0xF was read from cmask. Cmask reads only occur on fmask cache misses. A value of 0xF means that a fmask tile requires 3 bit planes. `VVTVkVCB_PERF_SEL_CMASK_WRITE_DATA_0xC: Number of times a value of 0xC was written to cmask. Cmask writes occur at the end of a tile. The hardware does not perform the write if fmask has not changed, but the counter will update as if regardless of whether the hardware wrote or not. A value of 0xC means that a fmask tile requires 0 bit planes. @XVVVlVCB_PERF_SEL_CMASK_WRITE_DATA_0xD: Number of times a value of 0xD was written to cmask. Cmask writes occur at the end of a tile. The hardware does not perform the write if fmask has not changed, but the counter will update as if regardless of whether the hardware wrote or not. A value of 0xD means that a fmask tile requires 1 bit planes. ZVXVmVCB_PERF_SEL_CMASK_WRITE_DATA_0xE: Number of times a value of 0xE was written to cmask. Cmask writes occur at the end of a tile. The hardware does not perform the write if fmask has not changed, but the counter will update as if regardless of whether the hardware wrote or not. A value of 0xE means that a fmask tile requires 2 bit planes. \VhZVnVCB_PERF_SEL_CMASK_WRITE_DATA_0xF: Number of times a value of 0xF was written to cmask. Cmask writes occur at the end of a tile. The hardware does not perform the write if fmask has not changed, but the counter will update as if regardless of whether the hardware wrote or not. A value of 0xF means that a fmask tile requires 3 bit planes. \VH\VoMCB_PERF_SEL_CORE_SCLK_VLD: Number of cycles that the core clock is enabled. ]VpPCB_PERF_SEL_REG_SCLK_VLD: Number of cycles that the register clock is enabled. X^V^VOP_FILTER_ENABLE"XbV^V _VOP_FILTER_SEL_VH_VDCB_PERF_OP_FILTER_SEL_WRITE_ONLY: Only count write only operations `V`VuCB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION: Only count an operation if it needs the destination data like blend or rop aVaV>CB_PERF_OP_FILTER_SEL_RESOLVE: Only count resolve operations aVDCB_PERF_OP_FILTER_SEL_EXPAND: Only count expand samples operations cVbV FORMAT_FILTER_ENABLE"X{V`cV cVFORMAT_FILTER_SEL$`dVcV+COLOR_INVALID: this resource is disabled dVdVCOLOR_8: norm, int eV@eVCOLOR_4_4: norm only 8fVeVCOLOR_3_3_2: norm only fVfV RESERVED hgVgVCOLOR_16: norm, int, float hVgVCOLOR_16_FLOAT: float only hVPhVCOLOR_8_8: norm, int HiVhVCOLOR_5_6_5: norm only iViV COLOR_6_5_5: norm only jV0jV ;COLOR_1_5_5_5: norm only, 1-bit component is always unorm HkVjV COLOR_4_4_4_4: norm only lVkV ;COLOR_5_5_5_1: norm only, 1-bit component is always unorm lVPlV COLOR_32: int, float HmVlVCOLOR_32_FLOAT: float only mVmVCOLOR_16_16: norm, int, float nV8nVCOLOR_16_16_FLOAT: float only HoVnV'COLOR_8_24: unorm depth, uint stencil pVoV@COLOR_8_24_FLOAT: float depth, uint stencil; deprecated for CB pVXpV'COLOR_24_8: unorm depth, uint stencil qVqV@COLOR_24_8_FLOAT: float depth, uint stencil; deprecated for CB (rVqVCOLOR_10_11_11: float only rVprV"COLOR_10_11_11_FLOAT: float only psVsVCOLOR_11_11_10: float only tVsV"COLOR_11_11_10_FLOAT: float only tV`tVCOLOR_2_10_10_10: norm, int huVuV COLOR_8_8_8_8: norm, int, srgb vVuVCOLOR_10_10_10_2: norm, int vVXvV1COLOR_X24_8_32_FLOAT: float depth, uint stencil hwVwVCOLOR_32_32: int, float xVwVCOLOR_32_32_FLOAT: float only xVXxV%COLOR_16_16_16_16: norm, int, float pyVyV +COLOR_16_16_16_16_FLOAT: norm, int, float zVyV! RESERVED zVHzV"COLOR_32_32_32_32: int, float zV#%COLOR_32_32_32_32_FLOAT: float only |V{VMSAA_NUM_SAMPLES_FILTER_ENABLE"|Vh|VMSAA_NUM_SAMPLES_FILTER_SEL"h}V}VMRT_FILTER_ENABLE"~V}VMRT_FILTER_SEL"~Vh~V#FMASK_QUAD_FRAGMENTS_FILTER_ENABLE"@V VV!FMASK_QUAD_FRAGMENTS_FILTER_TYPE`VVZCB_PERF_FMASK_QUAD_FRAGMENTS_FILTER_TYPE_SEL_READ: Filter based on the fmask read values V\CB_PERF_FMASK_QUAD_FRAGMENTS_FILTER_TYPE_SEL_WRITE: Filter based on the fmask write values V"FMASK_QUAD_FRAGMENTS_FILTER_COUNT"@T?U$$""H@UCB_PERF_CTR1_SEL xU@U@USELqAU(AU)CB_PERF_SEL_BUSY: Number of busy cycles BUAUCB_PERF_SEL_DB_CB_TILE_VALID_READY: Number of cycles the DB to CB tile interface is valid and ready. This is measured after the input fifo. CUBUCB_PERF_SEL_DB_CB_TILE_VALID_READYB: Number of cycles the DB to CB tile interface is valid and not ready. This is measured after the input fifo. DUDUCB_PERF_SEL_DB_CB_TILE_VALIDB_READY: Number of cycles the DB to CB tile interface is not valid and ready. This is measured after the input fifo. EU EUCB_PERF_SEL_DB_CB_TILE_VALIDB_READYB: Number of cycles the DB to CB tile interface is not valid and not ready. This is measured after the input fifo. GU@FUCB_PERF_SEL_DB_CB_LQUAD_VALID_READY: Number of cycles the DB to CB lquad interface is valid and ready. This is measured after the input fifo (HUXGUCB_PERF_SEL_DB_CB_LQUAD_VALID_READYB: Number of cycles the DB to CB lquad interface is valid and not ready. This is measured after the input fifo @IUpHUCB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY: Number of cycles the DB to CB lquad interface is not valid and ready. This is measured after the input fifo `JUIUCB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB: Number of cycles the DB to CB lquad interface is not valid and not ready. This is measured after the input fifo KUJU CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY: Number of cycles the CB to TAP write request interface is valid and ready. This is measured at the interface converter rather than directly on the interface. MUKU CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB: Number of cycles the CB to TAP write request interface is valid and not ready. This is measured at the interface converter rather than directly on the interface. PNUHMU CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY: Number of cycles the CB to TAP write request interface is valid and ready. This is measured at the interface converter rather than directly on the interface. OUNU CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB: Number of cycles the CB to TAP write request interface is not valid and not ready. This is measured at the interface converter rather than directly on the interface. PUOU CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY: Number of cycles the CB to TAP read request interface is valid and ready. This is measured at the interface converter rather than directly on the interface. HRU@QUCB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB: Number of cycles the CB to TAP read request interface is valid and not ready. This is measured at the interface converter rather than directly on the interface. SURUCB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY: Number of cycles the CB to TAP read request interface is not valid and ready. This is measured at the interface converter rather than directly on the interface. TUSUCB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB: Number of cycles the CB to TAP read request interface is not valid and not ready. This is measured at the interface converter rather than directly on the interface. UU8UUkCB_PERF_SEL_CM_FC_TILE_VALID_READY: Number of cycles the cmask to fmask tile interface is valid and ready VU(VUpCB_PERF_SEL_CM_FC_TILE_VALID_READYB: Number of cycles the cmask to fmask tile interface is valid and not ready WU WUpCB_PERF_SEL_CM_FC_TILE_VALIDB_READY: Number of cycles the cmask to fmask tile interface is not valid and ready XUXUuCB_PERF_SEL_CM_FC_TILE_VALIDB_READYB: Number of cycles the cmask to fmask tile interface is not valid and not ready YUYUpCB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY: Number of cycles the fmask to color cache interface is valid and ready ZUZUuCB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB: Number of cycles the fmask to color cache interface is valid and not ready [U[UuCB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY: Number of cycles the fmask to color cache interface is not valid and ready \U\UzCB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB: Number of cycles the fmask to color cache interface is not valid and not ready ]U]UeCB_PERF_SEL_FOP_IN_VALID_READY: Number of cycles the fragop unit input interface is valid and ready ^U^UjCB_PERF_SEL_FOP_IN_VALID_READYB: Number of cycles the fragop unit input interface is valid and not ready _U^UjCB_PERF_SEL_FOP_IN_VALIDB_READY: Number of cycles the fragop unit input interface is not valid and ready `U_UoCB_PERF_SEL_FOP_IN_VALIDB_READYB: Number of cycles the fragop unit input interface is not valid and not ready aU`UCB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY: Mumber of cycles the color cache input block to tag block interface is valid and ready bUaUCB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB: Mumber of cycles the color cache input block to tag block interface is valid and not ready cUbUCB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY: Mumber of cycles the color cache input block to tag block interface is not valid and ready dUcU CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB: Mumber of cycles the color cache input block to tag block interface is not valid and not ready eUeU!=CB_PERF_SEL_CC_SF_FULL: The color cache source fifo is full HfUeU"@CB_PERF_SEL_CC_RB_FULL: The color cache reorder buffer is full gUfU#ECB_PERF_SEL_FC_RDLAT_FIFO_FULL: The fmask read latency fifo is full gU`gU$6CB_PERF_SEL_CM_TQ_FULL: The cmask tile queue is full hU hU%wCB_PERF_SEL_LQUAD_NO_TILE: A quad has arrived over the lquad interface but the corresponding tile has not arrive yet. iU iU&6CB_PERF_SEL_CM_CACHE_HIT: Number of cmask cache hits jUiU'CB_PERF_SEL_CM_CACHE_TAG_MISS: Number of cmask cache tag misses. A tag miss is when there isn't a tag that matches the input. Because of sectoring, a tag hit does not imply that the required data is in the cache. plU@kU(CB_PERF_SEL_CM_CACHE_SECTOR_MISS: Number of cmask cache sector misses. A sector miss is when the required sector is not in the cache. Tag misses are included in this count because a sector cannot be in the cache if there is no tag for it. mUlU)CB_PERF_SEL_CM_CACHE_REEVICTION_STALL: The cmask cache is stalled because it is trying to evict a line that already has a pending evict nUmU*CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL: The cmask cache is stalled because it is trying to evict a line that has a nonzero inflight count. This is usually a sign that the cache is unable to withstand the memory read latency. oU@oU+:CB_PERF_SEL_CM_CACHE_EVICT_NONRESIDENT_STALL: DEPRECATED qUpU,CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL: The cmask cache is stalled because the line being replaced has a pending evict. This is usually a sign that the cache is unable to withstand the memory write latency. @rUhqU-CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL: The cmask cache is stalled because one of the inflight counters has reached the maximum value. @sUrU.uCB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL: The cmask cache is stalled because the read request output path is stalled. @tUsU/wCB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL: The cmask cache is stalled because the write request output path is stalled. 8uUtU0sCB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL: The cmask cache is stalled because the acknowledge output path is stalled. vUuU1HCB_PERF_SEL_CM_CACHE_FLUSH: This is the number of cmask cache flushes. vUPvU26CB_PERF_SEL_FC_CACHE_HIT: Number of fmask cache hits (xUwU3CB_PERF_SEL_FC_CACHE_TAG_MISS: Number of fmask cache tag misses. A tag miss is when there isn't a tag that matches the input. Because of sectoring, a tag hit does not imply that the required data is in the cache. yUpxU4CB_PERF_SEL_FC_CACHE_SECTOR_MISS: Number of fmask cache sector misses. A sector miss is when the required sector is not in the cache. Tag misses are included in this count because a sector cannot be in the cache if there is no tag for it. zUyU5CB_PERF_SEL_FC_CACHE_REEVICTION_STALL: The fmask cache is stalled because it is trying to evict a line that already has a pending evict (|UzU6CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL: The fmask cache is stalled because it is trying to evict a line that has a nonzero inflight count. This is usually a sign that the cache is unable to withstand the memory read latency. |Up|U7:CB_PERF_SEL_FC_CACHE_EVICT_NONRESIDENT_STALL: DEPRECATED H~U0}U8CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL: The fmask cache is stalled because the line being replaced has a pending evict. This is usually a sign that the cache is unable to withstand the memory write latency. hU~U9CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL: The fmask cache is stalled because one of the inflight counters has reached the maximum value. hUU:uCB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL: The fmask cache is stalled because the read request output path is stalled. hUU;wCB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL: The fmask cache is stalled because the write request output path is stalled. `UU<sCB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL: The fmask cache is stalled because the acknowledge output path is stalled. 0UU=HCB_PERF_SEL_FC_CACHE_FLUSH: This is the number of fmask cache flushes. UxU>6CB_PERF_SEL_CC_CACHE_HIT: Number of fmask cache hits PU8U?CB_PERF_SEL_CC_CACHE_TAG_MISS: Number of fmask cache tag misses. A tag miss is when there isn't a tag that matches the input. Because of sectoring, a tag hit does not imply that the required data is in the cache. ȆUU@CB_PERF_SEL_CC_CACHE_SECTOR_MISS: Number of fmask cache sector misses. A sector miss is when the required sector is not in the cache. Tag misses are included in this count because a sector cannot be in the cache if there is no tag for it. ؇UUACB_PERF_SEL_CC_CACHE_REEVICTION_STALL: The color cache is stalled because it is trying to evict a line that already has a pending evict PU UBCB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL: The color cache is stalled because it is trying to evict a line that has a nonzero inflight count. This is usually a sign that the cache is unable to withstand the memory read latency. UUC:CB_PERF_SEL_CC_CACHE_EVICT_NONRESIDENT_STALL: DEPRECATED pUXUDCB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL: The color cache is stalled because the line being replaced has a pending evict. This is usually a sign that the cache is unable to withstand the memory write latency. UUECB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL: The color cache is stalled because one of the inflight counters has reached the maximum value. U،UFuCB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL: The color cache is stalled because the read request output path is stalled. U؍UGwCB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL: The color cache is stalled because the write request output path is stalled. U؎UHsCB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL: The color cache is stalled because the acknowledge output path is stalled. UЏUICB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION: The number of times a write allocate cache line is converted to a read-modify-write cache line. UUJpCB_PERF_SEL_CC_CACHE_FLUSH: This is the number of color cache flushes. This is includes surface sync flushes. ВUؑUKCB_PERF_SEL_CM_MC_READ_REQUEST: Number of 32-byte cmask mc read requests. Cmask does not make 32-byte requests, so the counter will report the equivalent number of 32-byte requests. UULKCB_PERF_SEL_FC_MC_READ_REQUEST: Number of 32-byte fmask mc read requests. UUMCB_PERF_SEL_CC_MC_READ_REQUEST: Number of 32-byte color mc read requests. Color does not make 32-byte requests, so the counter will report the equivalent number of 32-byte requests. U(UNMCB_PERF_SEL_CM_MC_WRITE_REQUEST: Number of 32-byte cmask mc write requests. UUOMCB_PERF_SEL_FC_MC_WRITE_REQUEST: Number of 32-byte fmask mc write requests. hUؖUPMCB_PERF_SEL_CC_MC_WRITE_REQUEST: Number of 32-byte color mc write requests. UUQ!CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT: Number of 32-byte cmask mc read requests in flight. Cmask does not make 32-byte requests, so the counter will report the equivalent number of 32-byte requests. Dividing this number by the cmask read request count produces the average latency. HUXURCB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT: Number of 32-byte fmask mc read requests in flight. Dividing this number by the fmask read request count produces the average latency. UUS!CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT: Number of 32-byte color mc read requests in flight. Color does not make 32-byte requests, so the counter will report the equivalent number of 32-byte requests. Dividing this number by the color read request count produces the average latency. 0U8UTCB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT: Number of 32-byte cmask mc write requests in flight. Dividing this number by the cmask write request count produces the average latency. pUxUUCB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT: Number of 32-byte fmask mc write requests in flight. Dividing this number by the fmask write request count produces the average latency. UUVCB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT: Number of 32-byte color mc write requests in flight. Dividing this number by the color write request count produces the average latency. pUUW6CB_PERF_SEL_CC_SURFACE_SYNC: Number of surface syncs UUXCB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT: Number of quad fragments that require two cache probes. AA blending can create these when the read fragment does not match the write fragment. UUYJCB_PERF_SEL_SLOW_MODE_QUAD_FRAGMENT: Number of slow mode quad fragments. pUȢUZeCB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT: This is the number of dual source color quad fragments XUU[cCB_PERF_SEL_DRAWN_QUAD: This is the number of drawn quads. Filtering has an effect in this mode. HUU\eCB_PERF_SEL_DRAWN_PIXEL: This is the number of drawn pixels. Filtering has an effect in this mode. HUU]uCB_PERF_SEL_DRAWN_QUAD_FRAGMENT: This is the number of drawn quad fragments. Filtering has an effect in this mode. XUU^CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL: This is the number of times the blend pipeline is stalled to handle read after write hazards. PUU_pCB_PERF_SEL_EVENT: Total number of events reaching the CB. This includes events that the CB does not process. UU`CCB_PERF_SEL_EVENT_CACHE_FLUSH_TS: Number of CACHE_FLUSH_TS events U`Ua@CB_PERF_SEL_EVENT_CONTEXT_DONE: Number of CONTEXT_DONE events U(Ub=CB_PERF_SEL_EVENT_CACHE_FLUSH: Number of CACHE_FLUSH events UUc_CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT: Number of CACHE_FLUSH_AND_INV_TS_EVENT events pUثUdXCB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT: Number of_CACHE_FLUSH_AND_INV_EVENTevents PUUeWCB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS: Number of FLUSH_AND_INV_CB_DATA_TS events (UUfQCB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META: Number of FLUSH_AND_INV_CB_META events pUpUgCB_PERF_SEL_CMASK_READ_DATA_0xC: Number of times a value of 0xC was read from cmask. Cmask reads only occur on fmask cache misses. A value of 0xC means that a fmask tile requires 0 bit planes. UUhCB_PERF_SEL_CMASK_READ_DATA_0xD: Number of times a value of 0xD was read from cmask. Cmask reads only occur on fmask cache misses. A value of 0xD means that a fmask tile requires 1 bit planes. UUiCB_PERF_SEL_CMASK_READ_DATA_0xE: Number of times a value of 0xE was read from cmask. Cmask reads only occur on fmask cache misses. A value of 0xE means that a fmask tile requires 2 bit planes. HUHUjCB_PERF_SEL_CMASK_READ_DATA_0xF: Number of times a value of 0xF was read from cmask. Cmask reads only occur on fmask cache misses. A value of 0xF means that a fmask tile requires 3 bit planes. (UUkVCB_PERF_SEL_CMASK_WRITE_DATA_0xC: Number of times a value of 0xC was written to cmask. Cmask writes occur at the end of a tile. The hardware does not perform the write if fmask has not changed, but the counter will update as if regardless of whether the hardware wrote or not. A value of 0xC means that a fmask tile requires 0 bit planes. UpUlVCB_PERF_SEL_CMASK_WRITE_DATA_0xD: Number of times a value of 0xD was written to cmask. Cmask writes occur at the end of a tile. The hardware does not perform the write if fmask has not changed, but the counter will update as if regardless of whether the hardware wrote or not. A value of 0xD means that a fmask tile requires 1 bit planes. UPUmVCB_PERF_SEL_CMASK_WRITE_DATA_0xE: Number of times a value of 0xE was written to cmask. Cmask writes occur at the end of a tile. The hardware does not perform the write if fmask has not changed, but the counter will update as if regardless of whether the hardware wrote or not. A value of 0xE means that a fmask tile requires 2 bit planes. ȺU0UnVCB_PERF_SEL_CMASK_WRITE_DATA_0xF: Number of times a value of 0xF was written to cmask. Cmask writes occur at the end of a tile. The hardware does not perform the write if fmask has not changed, but the counter will update as if regardless of whether the hardware wrote or not. A value of 0xF means that a fmask tile requires 3 bit planes. UUoMCB_PERF_SEL_CORE_SCLK_VLD: Number of cycles that the core clock is enabled. UpPCB_PERF_SEL_REG_SCLK_VLD: Number of cycles that the register clock is enabled. UмUOP_FILTER_ENABLE" UxU ȽUOP_FILTER_SELUUDCB_PERF_OP_FILTER_SEL_WRITE_ONLY: Only count write only operations UؾUuCB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION: Only count an operation if it needs the destination data like blend or rop XUؿU>CB_PERF_OP_FILTER_SEL_RESOLVE: Only count resolve operations UDCB_PERF_OP_FILTER_SEL_EXPAND: Only count expand samples operations UxU FORMAT_FILTER_ENABLE" U(U xUFORMAT_FILTER_SEL$(UU+COLOR_INVALID: this resource is disabled UpUCOLOR_8: norm, int `UUCOLOR_4_4: norm only UUCOLOR_3_3_2: norm only UHU RESERVED 0UUCOLOR_16: norm, int, float UxUCOLOR_16_FLOAT: float only pUUCOLOR_8_8: norm, int UUCOLOR_5_6_5: norm only UXU COLOR_6_5_5: norm only pUU ;COLOR_1_5_5_5: norm only, 1-bit component is always unorm UU COLOR_4_4_4_4: norm only UXU ;COLOR_5_5_5_1: norm only, 1-bit component is always unorm pUU COLOR_32: int, float UUCOLOR_32_FLOAT: float only UXUCOLOR_16_16: norm, int, float `UUCOLOR_16_16_FLOAT: float only UU'COLOR_8_24: unorm depth, uint stencil UXU@COLOR_8_24_FLOAT: float depth, uint stencil; deprecated for CB U U'COLOR_24_8: unorm depth, uint stencil PUU@COLOR_24_8_FLOAT: float depth, uint stencil; deprecated for CB UUCOLOR_10_11_11: float only U8U"COLOR_10_11_11_FLOAT: float only 8UUCOLOR_11_11_10: float only UU"COLOR_11_11_10_FLOAT: float only U(UCOLOR_2_10_10_10: norm, int 0UU COLOR_8_8_8_8: norm, int, srgb UxUCOLOR_10_10_10_2: norm, int U U1COLOR_X24_8_32_FLOAT: float depth, uint stencil 0UUCOLOR_32_32: int, float UxUCOLOR_32_32_FLOAT: float only U U%COLOR_16_16_16_16: norm, int, float 8UU +COLOR_16_16_16_16_FLOAT: norm, int, float UU! RESERVED pUU"COLOR_32_32_32_32: int, float U#%COLOR_32_32_32_32_FLOAT: float only UxUMSAA_NUM_SAMPLES_FILTER_ENABLE"U0UMSAA_NUM_SAMPLES_FILTER_SEL"0UUMRT_FILTER_ENABLE"UUMRT_FILTER_SEL"U0U#FMASK_QUAD_FRAGMENTS_FILTER_ENABLE"UUHU!FMASK_QUAD_FRAGMENTS_FILTER_TYPE(UUZCB_PERF_FMASK_QUAD_FRAGMENTS_FILTER_TYPE_SEL_READ: Filter based on the fmask read values pU\CB_PERF_FMASK_QUAD_FRAGMENTS_FILTER_TYPE_SEL_WRITE: Filter based on the fmask write values `U"FMASK_QUAD_FRAGMENTS_FILTER_COUNT"TT ""TCB_PERF_CTR0_SEL 8U`TTSELqPTT)CB_PERF_SEL_BUSY: Number of busy cycles hTTCB_PERF_SEL_DB_CB_TILE_VALID_READY: Number of cycles the DB to CB tile interface is valid and ready. This is measured after the input fifo. TTCB_PERF_SEL_DB_CB_TILE_VALID_READYB: Number of cycles the DB to CB tile interface is valid and not ready. This is measured after the input fifo. TȢTCB_PERF_SEL_DB_CB_TILE_VALIDB_READY: Number of cycles the DB to CB tile interface is not valid and ready. This is measured after the input fifo. TTCB_PERF_SEL_DB_CB_TILE_VALIDB_READYB: Number of cycles the DB to CB tile interface is not valid and not ready. This is measured after the input fifo. ХTTCB_PERF_SEL_DB_CB_LQUAD_VALID_READY: Number of cycles the DB to CB lquad interface is valid and ready. This is measured after the input fifo TTCB_PERF_SEL_DB_CB_LQUAD_VALID_READYB: Number of cycles the DB to CB lquad interface is valid and not ready. This is measured after the input fifo T0TCB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY: Number of cycles the DB to CB lquad interface is not valid and ready. This is measured after the input fifo THTCB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB: Number of cycles the DB to CB lquad interface is not valid and not ready. This is measured after the input fifo pThT CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY: Number of cycles the CB to TAP write request interface is valid and ready. This is measured at the interface converter rather than directly on the interface. TT CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB: Number of cycles the CB to TAP write request interface is valid and not ready. This is measured at the interface converter rather than directly on the interface. TT CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY: Number of cycles the CB to TAP write request interface is valid and ready. This is measured at the interface converter rather than directly on the interface. hTXT CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB: Number of cycles the CB to TAP write request interface is not valid and not ready. This is measured at the interface converter rather than directly on the interface. TT CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY: Number of cycles the CB to TAP read request interface is valid and ready. This is measured at the interface converter rather than directly on the interface. TTCB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB: Number of cycles the CB to TAP read request interface is valid and not ready. This is measured at the interface converter rather than directly on the interface. `TXTCB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY: Number of cycles the CB to TAP read request interface is not valid and ready. This is measured at the interface converter rather than directly on the interface. TTCB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB: Number of cycles the CB to TAP read request interface is not valid and not ready. This is measured at the interface converter rather than directly on the interface. TTkCB_PERF_SEL_CM_FC_TILE_VALID_READY: Number of cycles the cmask to fmask tile interface is valid and ready TTpCB_PERF_SEL_CM_FC_TILE_VALID_READYB: Number of cycles the cmask to fmask tile interface is valid and not ready TTpCB_PERF_SEL_CM_FC_TILE_VALIDB_READY: Number of cycles the cmask to fmask tile interface is not valid and ready TTuCB_PERF_SEL_CM_FC_TILE_VALIDB_READYB: Number of cycles the cmask to fmask tile interface is not valid and not ready TTpCB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY: Number of cycles the fmask to color cache interface is valid and ready TظTuCB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB: Number of cycles the fmask to color cache interface is valid and not ready TعTuCB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY: Number of cycles the fmask to color cache interface is not valid and ready TغTzCB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB: Number of cycles the fmask to color cache interface is not valid and not ready TػTeCB_PERF_SEL_FOP_IN_VALID_READY: Number of cycles the fragop unit input interface is valid and ready pTȼTjCB_PERF_SEL_FOP_IN_VALID_READYB: Number of cycles the fragop unit input interface is valid and not ready `TTjCB_PERF_SEL_FOP_IN_VALIDB_READY: Number of cycles the fragop unit input interface is not valid and ready XTToCB_PERF_SEL_FOP_IN_VALIDB_READYB: Number of cycles the fragop unit input interface is not valid and not ready `TTCB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY: Mumber of cycles the color cache input block to tag block interface is valid and ready hTTCB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB: Mumber of cycles the color cache input block to tag block interface is valid and not ready pTTCB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY: Mumber of cycles the color cache input block to tag block interface is not valid and ready TT CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB: Mumber of cycles the color cache input block to tag block interface is not valid and not ready HTT!=CB_PERF_SEL_CC_SF_FULL: The color cache source fifo is full TT"@CB_PERF_SEL_CC_RB_FULL: The color cache reorder buffer is full TXT#ECB_PERF_SEL_FC_RDLAT_FIFO_FULL: The fmask read latency fifo is full T(T$6CB_PERF_SEL_CM_TQ_FULL: The cmask tile queue is full TT%wCB_PERF_SEL_LQUAD_NO_TILE: A quad has arrived over the lquad interface but the corresponding tile has not arrive yet. `TT&6CB_PERF_SEL_CM_CACHE_HIT: Number of cmask cache hits TT'CB_PERF_SEL_CM_CACHE_TAG_MISS: Number of cmask cache tag misses. A tag miss is when there isn't a tag that matches the input. Because of sectoring, a tag hit does not imply that the required data is in the cache. 8TT(CB_PERF_SEL_CM_CACHE_SECTOR_MISS: Number of cmask cache sector misses. A sector miss is when the required sector is not in the cache. Tag misses are included in this count because a sector cannot be in the cache if there is no tag for it. HTT)CB_PERF_SEL_CM_CACHE_REEVICTION_STALL: The cmask cache is stalled because it is trying to evict a line that already has a pending evict TT*CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL: The cmask cache is stalled because it is trying to evict a line that has a nonzero inflight count. This is usually a sign that the cache is unable to withstand the memory read latency. TT+:CB_PERF_SEL_CM_CACHE_EVICT_NONRESIDENT_STALL: DEPRECATED TT,CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL: The cmask cache is stalled because the line being replaced has a pending evict. This is usually a sign that the cache is unable to withstand the memory write latency. T(T-CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL: The cmask cache is stalled because one of the inflight counters has reached the maximum value. THT.uCB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL: The cmask cache is stalled because the read request output path is stalled. THT/wCB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL: The cmask cache is stalled because the write request output path is stalled. THT0sCB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL: The cmask cache is stalled because the acknowledge output path is stalled. T@T1HCB_PERF_SEL_CM_CACHE_FLUSH: This is the number of cmask cache flushes. TT26CB_PERF_SEL_FC_CACHE_HIT: Number of fmask cache hits TT3CB_PERF_SEL_FC_CACHE_TAG_MISS: Number of fmask cache tag misses. A tag miss is when there isn't a tag that matches the input. Because of sectoring, a tag hit does not imply that the required data is in the cache. `T0T4CB_PERF_SEL_FC_CACHE_SECTOR_MISS: Number of fmask cache sector misses. A sector miss is when the required sector is not in the cache. Tag misses are included in this count because a sector cannot be in the cache if there is no tag for it. pTT5CB_PERF_SEL_FC_CACHE_REEVICTION_STALL: The fmask cache is stalled because it is trying to evict a line that already has a pending evict TT6CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL: The fmask cache is stalled because it is trying to evict a line that has a nonzero inflight count. This is usually a sign that the cache is unable to withstand the memory read latency. T0T7:CB_PERF_SEL_FC_CACHE_EVICT_NONRESIDENT_STALL: DEPRECATED TT8CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL: The fmask cache is stalled because the line being replaced has a pending evict. This is usually a sign that the cache is unable to withstand the memory write latency. (TPT9CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL: The fmask cache is stalled because one of the inflight counters has reached the maximum value. (TpT:uCB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL: The fmask cache is stalled because the read request output path is stalled. (TpT;wCB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL: The fmask cache is stalled because the write request output path is stalled. TpT<sCB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL: The fmask cache is stalled because the acknowledge output path is stalled. ThT=HCB_PERF_SEL_FC_CACHE_FLUSH: This is the number of fmask cache flushes. T8T>6CB_PERF_SEL_CC_CACHE_HIT: Number of fmask cache hits TT?CB_PERF_SEL_CC_CACHE_TAG_MISS: Number of fmask cache tag misses. A tag miss is when there isn't a tag that matches the input. Because of sectoring, a tag hit does not imply that the required data is in the cache. TXT@CB_PERF_SEL_CC_CACHE_SECTOR_MISS: Number of fmask cache sector misses. A sector miss is when the required sector is not in the cache. Tag misses are included in this count because a sector cannot be in the cache if there is no tag for it. TTACB_PERF_SEL_CC_CACHE_REEVICTION_STALL: The color cache is stalled because it is trying to evict a line that already has a pending evict TTBCB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL: The color cache is stalled because it is trying to evict a line that has a nonzero inflight count. This is usually a sign that the cache is unable to withstand the memory read latency. TXTC:CB_PERF_SEL_CC_CACHE_EVICT_NONRESIDENT_STALL: DEPRECATED 0TTDCB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL: The color cache is stalled because the line being replaced has a pending evict. This is usually a sign that the cache is unable to withstand the memory write latency. PTxTECB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL: The color cache is stalled because one of the inflight counters has reached the maximum value. PTTFuCB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL: The color cache is stalled because the read request output path is stalled. PTTGwCB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL: The color cache is stalled because the write request output path is stalled. HTTHsCB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL: The color cache is stalled because the acknowledge output path is stalled. XTTICB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION: The number of times a write allocate cache line is converted to a read-modify-write cache line. PTTJpCB_PERF_SEL_CC_CACHE_FLUSH: This is the number of color cache flushes. This is includes surface sync flushes. TTKCB_PERF_SEL_CM_MC_READ_REQUEST: Number of 32-byte cmask mc read requests. Cmask does not make 32-byte requests, so the counter will report the equivalent number of 32-byte requests. `TTLKCB_PERF_SEL_FC_MC_READ_REQUEST: Number of 32-byte fmask mc read requests. TTMCB_PERF_SEL_CC_MC_READ_REQUEST: Number of 32-byte color mc read requests. Color does not make 32-byte requests, so the counter will report the equivalent number of 32-byte requests. xTTNMCB_PERF_SEL_CM_MC_WRITE_REQUEST: Number of 32-byte cmask mc write requests. PTTOMCB_PERF_SEL_FC_MC_WRITE_REQUEST: Number of 32-byte fmask mc write requests. (TTPMCB_PERF_SEL_CC_MC_WRITE_REQUEST: Number of 32-byte color mc write requests. TpTQ!CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT: Number of 32-byte cmask mc read requests in flight. Cmask does not make 32-byte requests, so the counter will report the equivalent number of 32-byte requests. Dividing this number by the cmask read request count produces the average latency. TTRCB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT: Number of 32-byte fmask mc read requests in flight. Dividing this number by the fmask read request count produces the average latency. TPTS!CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT: Number of 32-byte color mc read requests in flight. Color does not make 32-byte requests, so the counter will report the equivalent number of 32-byte requests. Dividing this number by the color read request count produces the average latency. TTTCB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT: Number of 32-byte cmask mc write requests in flight. Dividing this number by the cmask write request count produces the average latency. 0T8TUCB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT: Number of 32-byte fmask mc write requests in flight. Dividing this number by the fmask write request count produces the average latency. pTxTVCB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT: Number of 32-byte color mc write requests in flight. Dividing this number by the color write request count produces the average latency. 0TTW6CB_PERF_SEL_CC_SURFACE_SYNC: Number of surface syncs pUxTXCB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT: Number of quad fragments that require two cache probes. AA blending can create these when the read fragment does not match the write fragment. @UUYJCB_PERF_SEL_SLOW_MODE_QUAD_FRAGMENT: Number of slow mode quad fragments. 0UUZeCB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT: This is the number of dual source color quad fragments UxU[cCB_PERF_SEL_DRAWN_QUAD: This is the number of drawn quads. Filtering has an effect in this mode. U`U\eCB_PERF_SEL_DRAWN_PIXEL: This is the number of drawn pixels. Filtering has an effect in this mode. UPU]uCB_PERF_SEL_DRAWN_QUAD_FRAGMENT: This is the number of drawn quad fragments. Filtering has an effect in this mode. UPU^CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL: This is the number of times the blend pipeline is stalled to handle read after write hazards. U`U_pCB_PERF_SEL_EVENT: Total number of events reaching the CB. This includes events that the CB does not process. UXU`CCB_PERF_SEL_EVENT_CACHE_FLUSH_TS: Number of CACHE_FLUSH_TS events U Ua@CB_PERF_SEL_EVENT_CONTEXT_DONE: Number of CONTEXT_DONE events h UUb=CB_PERF_SEL_EVENT_CACHE_FLUSH: Number of CACHE_FLUSH events P U Uc_CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT: Number of CACHE_FLUSH_AND_INV_TS_EVENT events 0 U UdXCB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT: Number of_CACHE_FLUSH_AND_INV_EVENTevents  Ux UeWCB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS: Number of FLUSH_AND_INV_CB_DATA_TS events UX UfQCB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META: Number of FLUSH_AND_INV_CB_META events 0U0 UgCB_PERF_SEL_CMASK_READ_DATA_0xC: Number of times a value of 0xC was read from cmask. Cmask reads only occur on fmask cache misses. A value of 0xC means that a fmask tile requires 0 bit planes. xUxUhCB_PERF_SEL_CMASK_READ_DATA_0xD: Number of times a value of 0xD was read from cmask. Cmask reads only occur on fmask cache misses. A value of 0xD means that a fmask tile requires 1 bit planes. UUiCB_PERF_SEL_CMASK_READ_DATA_0xE: Number of times a value of 0xE was read from cmask. Cmask reads only occur on fmask cache misses. A value of 0xE means that a fmask tile requires 2 bit planes. UUjCB_PERF_SEL_CMASK_READ_DATA_0xF: Number of times a value of 0xF was read from cmask. Cmask reads only occur on fmask cache misses. A value of 0xF means that a fmask tile requires 3 bit planes. UPUkVCB_PERF_SEL_CMASK_WRITE_DATA_0xC: Number of times a value of 0xC was written to cmask. Cmask writes occur at the end of a tile. The hardware does not perform the write if fmask has not changed, but the counter will update as if regardless of whether the hardware wrote or not. A value of 0xC means that a fmask tile requires 0 bit planes. U0UlVCB_PERF_SEL_CMASK_WRITE_DATA_0xD: Number of times a value of 0xD was written to cmask. Cmask writes occur at the end of a tile. The hardware does not perform the write if fmask has not changed, but the counter will update as if regardless of whether the hardware wrote or not. A value of 0xD means that a fmask tile requires 1 bit planes. UUmVCB_PERF_SEL_CMASK_WRITE_DATA_0xE: Number of times a value of 0xE was written to cmask. Cmask writes occur at the end of a tile. The hardware does not perform the write if fmask has not changed, but the counter will update as if regardless of whether the hardware wrote or not. A value of 0xE means that a fmask tile requires 2 bit planes. UUnVCB_PERF_SEL_CMASK_WRITE_DATA_0xF: Number of times a value of 0xF was written to cmask. Cmask writes occur at the end of a tile. The hardware does not perform the write if fmask has not changed, but the counter will update as if regardless of whether the hardware wrote or not. A value of 0xF means that a fmask tile requires 3 bit planes. `UUoMCB_PERF_SEL_CORE_SCLK_VLD: Number of cycles that the core clock is enabled. UpPCB_PERF_SEL_REG_SCLK_VLD: Number of cycles that the register clock is enabled. UUOP_FILTER_ENABLE"U8U UOP_FILTER_SELPUUDCB_PERF_OP_FILTER_SEL_WRITE_ONLY: Only count write only operations PUUuCB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION: Only count an operation if it needs the destination data like blend or rop UU>CB_PERF_OP_FILTER_SEL_RESOLVE: Only count resolve operations `UDCB_PERF_OP_FILTER_SEL_EXPAND: Only count expand samples operations U8 U FORMAT_FILTER_ENABLE"8U U 8!UFORMAT_FILTER_SEL$!U!U+COLOR_INVALID: this resource is disabled "U0"UCOLOR_8: norm, int #U"UCOLOR_4_4: norm only #Uh#UCOLOR_3_3_2: norm only P$U$U RESERVED $U$UCOLOR_16: norm, int, float %U8%UCOLOR_16_FLOAT: float only 0&U%UCOLOR_8_8: norm, int &Ux&UCOLOR_5_6_5: norm only p'U'U COLOR_6_5_5: norm only 0(U'U ;COLOR_1_5_5_5: norm only, 1-bit component is always unorm (Ux(U COLOR_4_4_4_4: norm only )U)U ;COLOR_5_5_5_1: norm only, 1-bit component is always unorm 0*U)U COLOR_32: int, float *Ux*UCOLOR_32_FLOAT: float only x+U+UCOLOR_16_16: norm, int, float ,U+UCOLOR_16_16_FLOAT: float only ,Uh,U'COLOR_8_24: unorm depth, uint stencil -U-U@COLOR_8_24_FLOAT: float depth, uint stencil; deprecated for CB H.U-U'COLOR_24_8: unorm depth, uint stencil /U.U@COLOR_24_8_FLOAT: float depth, uint stencil; deprecated for CB /UX/UCOLOR_10_11_11: float only X0U/U"COLOR_10_11_11_FLOAT: float only 0U0UCOLOR_11_11_10: float only 1U@1U"COLOR_11_11_10_FLOAT: float only H2U1UCOLOR_2_10_10_10: norm, int 2U2U COLOR_8_8_8_8: norm, int, srgb 3U83UCOLOR_10_10_10_2: norm, int P4U3U1COLOR_X24_8_32_FLOAT: float depth, uint stencil 4U4UCOLOR_32_32: int, float 5U85UCOLOR_32_32_FLOAT: float only H6U5U%COLOR_16_16_16_16: norm, int, float 6U6U +COLOR_16_16_16_16_FLOAT: norm, int, float 7U@7U! RESERVED 08U7U"COLOR_32_32_32_32: int, float x8U#%COLOR_32_32_32_32_FLOAT: float only 9U89UMSAA_NUM_SAMPLES_FILTER_ENABLE"H:U9UMSAA_NUM_SAMPLES_FILTER_SEL":U:UMRT_FILTER_ENABLE";UH;UMRT_FILTER_SEL"PUU\CB_PERF_FMASK_QUAD_FRAGMENTS_FILTER_TYPE_SEL_WRITE: Filter based on the fmask write values ?U"FMASK_QUAD_FRAGMENTS_FILTER_COUNT"ȓT8T""TCB_INSTANCE_CONTROL(TT TARGET_ID"TМTWRITE_TARGET_ONLYpTTWrite all CB blocks TGJust write the registers in the CB block indicated by TARGET_ID field T@T""TCB_HW_CONTROL @TTCM_CACHE_EVICT_POINT"TTFC_CACHE_EVICT_POINT"THT CC_CACHE_EVICT_POINT"`TT&DISABLE_BLEND_NEEDS_DST_OPTIMIZATIONS"TTFORCE_NEEDS_DST"T`TFORCE_ALWAYS_TOGGLE"XTTUSE_PHYSICAL_CB_ID"TTDISABLE_FULL_WRITE_MASK"`TDISABLE_IB_TB_FRAG_IS_LINEAR"@TT""БTCB_CREDIT_LIMITxT(TDB_CB_TILE_CREDITS" TВTDB_CB_EQUAD_CREDITS"xTDB_CB_LQUAD_CREDITS"8TT""TCB_SHADER_CONTROLT`T RT0_ENABLE"HTT RT1_ENABLE"TT RT2_ENABLE"T@T RT3_ENABLE"(TT RT4_ENABLE"ȏTT RT5_ENABLE"hT T RT6_ENABLE"T RT7_ENABLE"0TT<<""TCB_SHADER_MASKTXTOUTPUT0_ENABLE"PTTOUTPUT1_ENABLE"TTOUTPUT2_ENABLE"TPT OUTPUT3_ENABLE"HTTOUTPUT4_ENABLE"TTOUTPUT5_ENABLE"THTOUTPUT6_ENABLE"TOUTPUT7_ENABLE"}TT88""TCB_TARGET_MASKTPTTARGET0_ENABLE"HTTTARGET1_ENABLE"TTTARGET2_ENABLE"THT TARGET3_ENABLE"@TTTARGET4_ENABLE"TTTARGET5_ENABLE"T@TTARGET6_ENABLE"TTARGET7_ENABLE"`|T@~T,,""~TCB_CLEAR_ALPHA_R6XX~T CLEAR_ALPHA"zT|T((""(}TCB_CLEAR_BLUE_R6XX}T CLEAR_BLUE"yTp{T$$""{TCB_CLEAR_GREEN_R6XX|T CLEAR_GREEN"xwTzT  ""XzTCB_CLEAR_RED_R6XXzT CLEAR_RED"`uTwT""@xTCB_COLOR7_MASKxTxT CMASK_BLOCK_MAX"@yT FMASK_TILE_MAX"HsTuT""(vTCB_COLOR6_MASKvTvT CMASK_BLOCK_MAX"(wT FMASK_TILE_MAX"0qTsT""tTCB_COLOR5_MASKtThtT CMASK_BLOCK_MAX"uT FMASK_TILE_MAX"oTqT""qTCB_COLOR4_MASKrTPrT CMASK_BLOCK_MAX"rT FMASK_TILE_MAX"mToT  ""oTCB_COLOR3_MASKpT8pT CMASK_BLOCK_MAX"pT FMASK_TILE_MAX"jTxmT""mTCB_COLOR2_MASKpnT nT CMASK_BLOCK_MAX"nT FMASK_TILE_MAX"hT`kT""kTCB_COLOR1_MASKXlTlT CMASK_BLOCK_MAX"lT FMASK_TILE_MAX"hgTHiT""iTCB_COLOR0_MASK@jTiT CMASK_BLOCK_MAX"jT FMASK_TILE_MAX"fTgT""0hTCB_COLOR7_FRAGhT BASE_256B"dTxfT""fTCB_COLOR6_FRAG gT BASE_256B"0cTeT""`eTCB_COLOR5_FRAGeT BASE_256B"aTcT""cTCB_COLOR4_FRAGPdT BASE_256B"``T@bT""bTCB_COLOR3_FRAGbT BASE_256B"^T`T""(aTCB_COLOR2_FRAGaT BASE_256B"]Tp_T""_TCB_COLOR1_FRAG`T BASE_256B"(\T^T""X^TCB_COLOR0_FRAG^T BASE_256B"ZT\T܀܀""\TCB_COLOR7_TILEH]T BASE_256B"XYT8[T؀؀""[TCB_COLOR6_TILE[T BASE_256B"WTYTԀԀ"" ZTCB_COLOR5_TILExZT BASE_256B"VThXTЀЀ""XTCB_COLOR4_TILEYT BASE_256B" UTWT̀̀""PWTCB_COLOR3_TILEWT BASE_256B"STUTȀȀ""UTCB_COLOR2_TILE@VT BASE_256B"PRT0TTĀĀ""TTCB_COLOR1_TILETT BASE_256B"hTRT""STCB_COLOR0_TILEpST BASE_256B"xST""0TCB_COLOR7_INFOTTTENDIANTT,ENDIAN_NONE: No endian swapping (XOR by 0) XTTTENDIAN_8IN16: 8 bit swap within 16 bit word (XOR by 1): 0xAABBCCDD -> 0xBBAADDCC 0TTTENDIAN_8IN32: 8 bit swap within 32 bit word (XOR by 3): 0xAABBCCDD -> 0xDDCCBBAA xT\ENDIAN_8IN64: 8 bit swap in 64 bits (XOR by 7): 0xaabbccddeeffgghh -> 0xhhggffeeddccbbaa X.ThTTFORMAT$`TT+COLOR_INVALID: this resource is disabled TTCOLOR_8: norm, int T@TCOLOR_4_4: norm only 8TTCOLOR_3_3_2: norm only TT RESERVED hTTCOLOR_16: norm, int, float TTCOLOR_16_FLOAT: float only TPTCOLOR_8_8: norm, int HTTCOLOR_5_6_5: norm only TT COLOR_6_5_5: norm only T0T ;COLOR_1_5_5_5: norm only, 1-bit component is always unorm HTT COLOR_4_4_4_4: norm only TT ;COLOR_5_5_5_1: norm only, 1-bit component is always unorm TPT COLOR_32: int, float H TTCOLOR_32_FLOAT: float only T TCOLOR_16_16: norm, int, float !T8!TCOLOR_16_16_FLOAT: float only H"T!T'COLOR_8_24: unorm depth, uint stencil #T"T@COLOR_8_24_FLOAT: float depth, uint stencil; deprecated for CB #TX#T'COLOR_24_8: unorm depth, uint stencil $T$T@COLOR_24_8_FLOAT: float depth, uint stencil; deprecated for CB (%T$TCOLOR_10_11_11: float only %Tp%T"COLOR_10_11_11_FLOAT: float only p&T&TCOLOR_11_11_10: float only 'T&T"COLOR_11_11_10_FLOAT: float only 'T`'TCOLOR_2_10_10_10: norm, int h(T(T COLOR_8_8_8_8: norm, int, srgb )T(TCOLOR_10_10_10_2: norm, int )TX)T1COLOR_X24_8_32_FLOAT: float depth, uint stencil h*T*TCOLOR_32_32: int, float +T*TCOLOR_32_32_FLOAT: float only +TX+T%COLOR_16_16_16_16: norm, int, float p,T,T +COLOR_16_16_16_16_FLOAT: norm, int, float -T,T! RESERVED -TH-T"COLOR_32_32_32_32: int, float -T#%COLOR_32_32_32_32_FLOAT: float only `:T.T.T ARRAY_MODE/T@/T.ARRAY_LINEAR_GENERAL: Unaligned linear array `0T/T,ARRAY_LINEAR_ALIGNED: Aligned linear array 1T0T+ARRAY_1D_TILED_THIN1: Uses 1D 8x8x1 tiles 1TX1T+ARRAY_1D_TILED_THICK: Uses 1D 8x8x4 tiles x2T2T.ARRAY_2D_TILED_THIN1: Uses 8x8x1 macro-tiles 03T2T/ARRAY_2D_TILED_THIN2: Macro-tiles are 2x high 3Tx3T/ARRAY_2D_TILED_THIN4: Macro-tiles are 4x high 4T04T.ARRAY_2D_TILED_THICK: Uses 8x8x4 macro-tiles X5T4T.ARRAY_2B_TILED_THIN1: uses row bank swapping 6T5T .ARRAY_2B_TILED_THIN2: uses row bank swapping 6TX6T .ARRAY_2B_TILED_THIN4: uses row bank swapping 7T7T .ARRAY_2B_TILED_THICK: uses row bank swapping 88T7T /ARRAY_3D_TILED_THIN1: Slices are pipe rotated 8T8T /ARRAY_3D_TILED_THICK: Slices are pipe rotated 9T89T/ARRAY_3B_TILED_THIN1: Slices are pipe rotated 9T/ARRAY_3B_TILED_THICK: Slices are pipe rotated HBT:T ;T NUMBER_TYPE;TH;TUNUMBER_UNORM: unsigned repeating fraction (urf): range [0..1], scale factor (2^n)-1 T=T*NUMBER_SSCALED: DEPRECATED. Do not use. >T`>TRNUMBER_UINT: zero-extended bit field, int in shader: not blendable or filterable ?T8?TRNUMBER_SINT: sign-extended bit field, int in shader: not blendable or filterable @T@TtNUMBER_SRGB: gamma corrected, range [0..1] (only supported for COLOR_8_8_8_8 format; always rounds color channels) ATNUMBER_FLOAT: floating point: 32-bit: IEEE float, SE8M23, bias 127, range (-2^129..2^129); 16-bit: Short float SE5M10, bias 15, range (-2^17..2^17); 11-bit: Packed float, E5M6 bias 15, range [0..2^17); 10-bit: Packed float, E5M5 bias 15, range [0..2^17) BTBT READ_SIZE"PFT@CTCT COMP_SWAP@DTCT-SWAP_STD: standard little-endian comp order DTDT)SWAP_ALT: alternate components or order ET8ET'SWAP_STD_REV: reverses SWAP_STD order ET'SWAP_ALT_REV: reverses SWAP_ALT order ITFTFT TILE_MODEHT8GTTILE_DISABLE: Disable compression for this MRT; the colour surface will always be in a fully-expanded state. Neither CMASK nor FMASK are allocated for this MRT. HT`HT-TILE_CLEAR_ENABLE: DEPRECATED. Do not use. ITkTILE_FRAG_ENABLE: Enable compression for this (multisampled) MRT. Both CMASK and FMASK must be allocated. `JTJT BLEND_CLAMP"KTJT CLEAR_COLOR"KTXKT BLEND_BYPASS"PLTLTBLEND_FLOAT32"LTLT SIMPLE_FLOAT" OTPMTMT ROUND_MODEPNTMT.ROUND_BY_HALF: add 1/2 lsb and then truncate NTFROUND_TRUNCATE: truncate toward zero for float, else toward negative OTxOT TILE_COMPACT" PTpPTSOURCE_FORMAT8QTPTAEXPORT_FULL: PS exports must use the full 32-bits per component QTEXPORT_NORM: PS exports may use a 18-bit per component format that supports 11-bit or smaller UNORM/SNORM/SRGB and 16-bit or smaller FLOAT. SS""@SCB_COLOR6_INFO SSSENDIANS(S,ENDIAN_NONE: No endian swapping (XOR by 0) hSSTENDIAN_8IN16: 8 bit swap within 16 bit word (XOR by 1): 0xAABBCCDD -> 0xBBAADDCC @SSTENDIAN_8IN32: 8 bit swap within 32 bit word (XOR by 3): 0xAABBCCDD -> 0xDDCCBBAA S\ENDIAN_8IN64: 8 bit swap in 64 bits (XOR by 7): 0xaabbccddeeffgghh -> 0xhhggffeeddccbbaa pSxSSFORMAT$pSS+COLOR_INVALID: this resource is disabled SSCOLOR_8: norm, int SPSCOLOR_4_4: norm only HSSCOLOR_3_3_2: norm only SS RESERVED xS SCOLOR_16: norm, int, float SSCOLOR_16_FLOAT: float only S`SCOLOR_8_8: norm, int XSSCOLOR_5_6_5: norm only SS COLOR_6_5_5: norm only S@S ;COLOR_1_5_5_5: norm only, 1-bit component is always unorm XSS COLOR_4_4_4_4: norm only SS ;COLOR_5_5_5_1: norm only, 1-bit component is always unorm S`S COLOR_32: int, float XSSCOLOR_32_FLOAT: float only SSCOLOR_16_16: norm, int, float SPSCOLOR_16_16_FLOAT: float only `SS'COLOR_8_24: unorm depth, uint stencil (SS@COLOR_8_24_FLOAT: float depth, uint stencil; deprecated for CB SpS'COLOR_24_8: unorm depth, uint stencil S S@COLOR_24_8_FLOAT: float depth, uint stencil; deprecated for CB @SSCOLOR_10_11_11: float only SS"COLOR_10_11_11_FLOAT: float only S0SCOLOR_11_11_10: float only 0SS"COLOR_11_11_10_FLOAT: float only SxSCOLOR_2_10_10_10: norm, int S S COLOR_8_8_8_8: norm, int, srgb (SSCOLOR_10_10_10_2: norm, int SpS1COLOR_X24_8_32_FLOAT: float depth, uint stencil S(SCOLOR_32_32: int, float (SSCOLOR_32_32_FLOAT: float only SpS%COLOR_16_16_16_16: norm, int, float S S +COLOR_16_16_16_16_FLOAT: norm, int, float SS! RESERVED S`S"COLOR_32_32_32_32: int, float S#%COLOR_32_32_32_32_FLOAT: float only xSSS ARRAY_MODESXS.ARRAY_LINEAR_GENERAL: Unaligned linear array xSS,ARRAY_LINEAR_ALIGNED: Aligned linear array (SS+ARRAY_1D_TILED_THIN1: Uses 1D 8x8x1 tiles SpS+ARRAY_1D_TILED_THICK: Uses 1D 8x8x4 tiles S S.ARRAY_2D_TILED_THIN1: Uses 8x8x1 macro-tiles HSS/ARRAY_2D_TILED_THIN2: Macro-tiles are 2x high SS/ARRAY_2D_TILED_THIN4: Macro-tiles are 4x high SHS.ARRAY_2D_TILED_THICK: Uses 8x8x4 macro-tiles pSS.ARRAY_2B_TILED_THIN1: uses row bank swapping (SS .ARRAY_2B_TILED_THIN2: uses row bank swapping SpS .ARRAY_2B_TILED_THIN4: uses row bank swapping S(S .ARRAY_2B_TILED_THICK: uses row bank swapping PSS /ARRAY_3D_TILED_THIN1: Slices are pipe rotated SS /ARRAY_3D_TILED_THICK: Slices are pipe rotated SPS/ARRAY_3B_TILED_THIN1: Slices are pipe rotated S/ARRAY_3B_TILED_THICK: Slices are pipe rotated `TS S NUMBER_TYPES`SUNUMBER_UNORM: unsigned repeating fraction (urf): range [0..1], scale factor (2^n)-1 S@SRNUMBER_SNORM: Microsoft-style signed rf: range [-1..1], scale factor (2^(n-1))-1 SS*NUMBER_USCALED: DEPRECATED. Do not use. 0SS*NUMBER_SSCALED: DEPRECATED. Do not use. SxSRNUMBER_UINT: zero-extended bit field, int in shader: not blendable or filterable SPSRNUMBER_SINT: sign-extended bit field, int in shader: not blendable or filterable S(StNUMBER_SRGB: gamma corrected, range [0..1] (only supported for COLOR_8_8_8_8 format; always rounds color channels) TNUMBER_FLOAT: floating point: 32-bit: IEEE float, SE8M23, bias 127, range (-2^129..2^129); 16-bit: Short float SE5M10, bias 15, range (-2^17..2^17); 11-bit: Packed float, E5M6 bias 15, range [0..2^17); 10-bit: Packed float, E5M5 bias 15, range [0..2^17) TT READ_SIZE"hTXTT COMP_SWAPXTT-SWAP_STD: standard little-endian comp order TT)SWAP_ALT: alternate components or order TPT'SWAP_STD_REV: reverses SWAP_STD order T'SWAP_ALT_REV: reverses SWAP_ALT order TTT TILE_MODE0TPTTILE_DISABLE: Disable compression for this MRT; the colour surface will always be in a fully-expanded state. Neither CMASK nor FMASK are allocated for this MRT. TxT-TILE_CLEAR_ENABLE: DEPRECATED. Do not use. 0TkTILE_FRAG_ENABLE: Enable compression for this (multisampled) MRT. Both CMASK and FMASK must be allocated. x T0 T BLEND_CLAMP" T T CLEAR_COLOR" Tp T BLEND_BYPASS"h T TBLEND_FLOAT32" T T SIMPLE_FLOAT"8Th T T ROUND_MODEh T T.ROUND_BY_HALF: add 1/2 lsb and then truncate TFROUND_TRUNCATE: truncate toward zero for float, else toward negative TT TILE_COMPACT"8TTSOURCE_FORMATPTTAEXPORT_FULL: PS exports must use the full 32-bits per component TEXPORT_NORM: PS exports may use a 18-bit per component format that supports 11-bit or smaller UNORM/SNORM/SRGB and 16-bit or smaller FLOAT. NSS""XSCB_COLOR5_INFO8SSSENDIANS@S,ENDIAN_NONE: No endian swapping (XOR by 0) SSTENDIAN_8IN16: 8 bit swap within 16 bit word (XOR by 1): 0xAABBCCDD -> 0xBBAADDCC XSȒSTENDIAN_8IN32: 8 bit swap within 32 bit word (XOR by 3): 0xAABBCCDD -> 0xDDCCBBAA S\ENDIAN_8IN64: 8 bit swap in 64 bits (XOR by 7): 0xaabbccddeeffgghh -> 0xhhggffeeddccbbaa SSؔSFORMAT$S S+COLOR_INVALID: this resource is disabled SЕSCOLOR_8: norm, int ShSCOLOR_4_4: norm only `SSCOLOR_3_3_2: norm only SS RESERVED S8SCOLOR_16: norm, int, float 0SؘSCOLOR_16_FLOAT: float only ЙSxSCOLOR_8_8: norm, int pSSCOLOR_5_6_5: norm only SS COLOR_6_5_5: norm only ЛSXS ;COLOR_1_5_5_5: norm only, 1-bit component is always unorm pSS COLOR_4_4_4_4: norm only 0SS ;COLOR_5_5_5_1: norm only, 1-bit component is always unorm НSxS COLOR_32: int, float pSSCOLOR_32_FLOAT: float only SSCOLOR_16_16: norm, int, float S`SCOLOR_16_16_FLOAT: float only pSS'COLOR_8_24: unorm depth, uint stencil 8SS@COLOR_8_24_FLOAT: float depth, uint stencil; deprecated for CB SS'COLOR_24_8: unorm depth, uint stencil S0S@COLOR_24_8_FLOAT: float depth, uint stencil; deprecated for CB PSSCOLOR_10_11_11: float only SS"COLOR_10_11_11_FLOAT: float only S@SCOLOR_11_11_10: float only @SS"COLOR_11_11_10_FLOAT: float only SSCOLOR_2_10_10_10: norm, int S0S COLOR_8_8_8_8: norm, int, srgb 8SئSCOLOR_10_10_10_2: norm, int SS1COLOR_X24_8_32_FLOAT: float depth, uint stencil S8SCOLOR_32_32: int, float 8SبSCOLOR_32_32_FLOAT: float only SS%COLOR_16_16_16_16: norm, int, float S0S +COLOR_16_16_16_16_FLOAT: norm, int, float (SS! RESERVED ЫSpS"COLOR_32_32_32_32: int, float S#%COLOR_32_32_32_32_FLOAT: float only SجS S ARRAY_MODEحShS.ARRAY_LINEAR_GENERAL: Unaligned linear array S S,ARRAY_LINEAR_ALIGNED: Aligned linear array 8SЮS+ARRAY_1D_TILED_THIN1: Uses 1D 8x8x1 tiles SS+ARRAY_1D_TILED_THICK: Uses 1D 8x8x4 tiles S0S.ARRAY_2D_TILED_THIN1: Uses 8x8x1 macro-tiles XSS/ARRAY_2D_TILED_THIN2: Macro-tiles are 2x high SS/ARRAY_2D_TILED_THIN4: Macro-tiles are 4x high ȲSXS.ARRAY_2D_TILED_THICK: Uses 8x8x4 macro-tiles SS.ARRAY_2B_TILED_THIN1: uses row bank swapping 8SȳS .ARRAY_2B_TILED_THIN2: uses row bank swapping SS .ARRAY_2B_TILED_THIN4: uses row bank swapping S8S .ARRAY_2B_TILED_THICK: uses row bank swapping `SS /ARRAY_3D_TILED_THIN1: Slices are pipe rotated SS /ARRAY_3D_TILED_THICK: Slices are pipe rotated зS`S/ARRAY_3B_TILED_THIN1: Slices are pipe rotated S/ARRAY_3B_TILED_THICK: Slices are pipe rotated pSS (S NUMBER_TYPESpSUNUMBER_UNORM: unsigned repeating fraction (urf): range [0..1], scale factor (2^n)-1 SPSRNUMBER_SNORM: Microsoft-style signed rf: range [-1..1], scale factor (2^(n-1))-1 S(S*NUMBER_USCALED: DEPRECATED. Do not use. @SػS*NUMBER_SSCALED: DEPRECATED. Do not use. SSRNUMBER_UINT: zero-extended bit field, int in shader: not blendable or filterable S`SRNUMBER_SINT: sign-extended bit field, int in shader: not blendable or filterable S8StNUMBER_SRGB: gamma corrected, range [0..1] (only supported for COLOR_8_8_8_8 format; always rounds color channels) 0SNUMBER_FLOAT: floating point: 32-bit: IEEE float, SE8M23, bias 127, range (-2^129..2^129); 16-bit: Short float SE5M10, bias 15, range (-2^17..2^17); 11-bit: Packed float, E5M6 bias 15, range [0..2^17); 10-bit: Packed float, E5M5 bias 15, range [0..2^17) SS READ_SIZE"xShSS COMP_SWAPhSS-SWAP_STD: standard little-endian comp order SS)SWAP_ALT: alternate components or order S`S'SWAP_STD_REV: reverses SWAP_STD order S'SWAP_ALT_REV: reverses SWAP_ALT order SSS TILE_MODE@S`STILE_DISABLE: Disable compression for this MRT; the colour surface will always be in a fully-expanded state. Neither CMASK nor FMASK are allocated for this MRT. SS-TILE_CLEAR_ENABLE: DEPRECATED. Do not use. @SkTILE_FRAG_ENABLE: Enable compression for this (multisampled) MRT. Both CMASK and FMASK must be allocated. S@S BLEND_CLAMP"(SS CLEAR_COLOR"SS BLEND_BYPASS"xS(SBLEND_FLOAT32" SS SIMPLE_FLOAT"HSxSS ROUND_MODExSS.ROUND_BY_HALF: add 1/2 lsb and then truncate SFROUND_TRUNCATE: truncate toward zero for float, else toward negative SS TILE_COMPACT"HSSSOURCE_FORMAT`SSAEXPORT_FULL: PS exports must use the full 32-bits per component SEXPORT_NORM: PS exports may use a 18-bit per component format that supports 11-bit or smaller UNORM/SNORM/SRGB and 16-bit or smaller FLOAT. SOS""`OSCB_COLOR4_INFOHSSOSPSENDIANPSPPS,ENDIAN_NONE: No endian swapping (XOR by 0) QSQSTENDIAN_8IN16: 8 bit swap within 16 bit word (XOR by 1): 0xAABBCCDD -> 0xBBAADDCC hRSQSTENDIAN_8IN32: 8 bit swap within 32 bit word (XOR by 3): 0xAABBCCDD -> 0xDDCCBBAA RS\ENDIAN_8IN64: 8 bit swap in 64 bits (XOR by 7): 0xaabbccddeeffgghh -> 0xhhggffeeddccbbaa kSSSSSFORMAT$TS0TS+COLOR_INVALID: this resource is disabled 0USTSCOLOR_8: norm, int USxUSCOLOR_4_4: norm only pVSVSCOLOR_3_3_2: norm only WSVS RESERVED WSHWSCOLOR_16: norm, int, float @XSWSCOLOR_16_FLOAT: float only XSXSCOLOR_8_8: norm, int YS(YSCOLOR_5_6_5: norm only ZSYS COLOR_6_5_5: norm only ZShZS ;COLOR_1_5_5_5: norm only, 1-bit component is always unorm [S([S COLOR_4_4_4_4: norm only @\S[S ;COLOR_5_5_5_1: norm only, 1-bit component is always unorm \S\S COLOR_32: int, float ]S(]SCOLOR_32_FLOAT: float only (^S]SCOLOR_16_16: norm, int, float ^Sp^SCOLOR_16_16_FLOAT: float only _S_S'COLOR_8_24: unorm depth, uint stencil H`S_S@COLOR_8_24_FLOAT: float depth, uint stencil; deprecated for CB `S`S'COLOR_24_8: unorm depth, uint stencil aS@aS@COLOR_24_8_FLOAT: float depth, uint stencil; deprecated for CB `bSbSCOLOR_10_11_11: float only cSbS"COLOR_10_11_11_FLOAT: float only cSPcSCOLOR_11_11_10: float only PdScS"COLOR_11_11_10_FLOAT: float only dSdSCOLOR_2_10_10_10: norm, int eS@eS COLOR_8_8_8_8: norm, int, srgb HfSeSCOLOR_10_10_10_2: norm, int gSfS1COLOR_X24_8_32_FLOAT: float depth, uint stencil gSHgSCOLOR_32_32: int, float HhSgSCOLOR_32_32_FLOAT: float only hShS%COLOR_16_16_16_16: norm, int, float iS@iS +COLOR_16_16_16_16_FLOAT: norm, int, float 8jSiS! RESERVED jSjS"COLOR_32_32_32_32: int, float (kS#%COLOR_32_32_32_32_FLOAT: float only wSkS0lS ARRAY_MODElSxlS.ARRAY_LINEAR_GENERAL: Unaligned linear array mS0mS,ARRAY_LINEAR_ALIGNED: Aligned linear array HnSmS+ARRAY_1D_TILED_THIN1: Uses 1D 8x8x1 tiles nSnS+ARRAY_1D_TILED_THICK: Uses 1D 8x8x4 tiles oS@oS.ARRAY_2D_TILED_THIN1: Uses 8x8x1 macro-tiles hpSoS/ARRAY_2D_TILED_THIN2: Macro-tiles are 2x high qSpS/ARRAY_2D_TILED_THIN4: Macro-tiles are 4x high qShqS.ARRAY_2D_TILED_THICK: Uses 8x8x4 macro-tiles rS rS.ARRAY_2B_TILED_THIN1: uses row bank swapping HsSrS .ARRAY_2B_TILED_THIN2: uses row bank swapping tSsS .ARRAY_2B_TILED_THIN4: uses row bank swapping tSHtS .ARRAY_2B_TILED_THICK: uses row bank swapping puSuS /ARRAY_3D_TILED_THIN1: Slices are pipe rotated (vSuS /ARRAY_3D_TILED_THICK: Slices are pipe rotated vSpvS/ARRAY_3B_TILED_THIN1: Slices are pipe rotated (wS/ARRAY_3B_TILED_THICK: Slices are pipe rotated SwS 8xS NUMBER_TYPEySxSUNUMBER_UNORM: unsigned repeating fraction (urf): range [0..1], scale factor (2^n)-1 yS`ySRNUMBER_SNORM: Microsoft-style signed rf: range [-1..1], scale factor (2^(n-1))-1 zS8zS*NUMBER_USCALED: DEPRECATED. Do not use. P{SzS*NUMBER_SSCALED: DEPRECATED. Do not use. (|S{SRNUMBER_UINT: zero-extended bit field, int in shader: not blendable or filterable }Sp|SRNUMBER_SINT: sign-extended bit field, int in shader: not blendable or filterable }SH}StNUMBER_SRGB: gamma corrected, range [0..1] (only supported for COLOR_8_8_8_8 format; always rounds color channels) @~SNUMBER_FLOAT: floating point: 32-bit: IEEE float, SE8M23, bias 127, range (-2^129..2^129); 16-bit: Short float SE5M10, bias 15, range (-2^17..2^17); 11-bit: Packed float, E5M6 bias 15, range [0..2^17); 10-bit: Packed float, E5M5 bias 15, range [0..2^17) SS READ_SIZE"SxSS COMP_SWAPxSS-SWAP_STD: standard little-endian comp order (SS)SWAP_ALT: alternate components or order ؂SpS'SWAP_STD_REV: reverses SWAP_STD order S'SWAP_ALT_REV: reverses SWAP_ALT order SS(S TILE_MODEPSpSTILE_DISABLE: Disable compression for this MRT; the colour surface will always be in a fully-expanded state. Neither CMASK nor FMASK are allocated for this MRT. SS-TILE_CLEAR_ENABLE: DEPRECATED. Do not use. PSkTILE_FRAG_ENABLE: Enable compression for this (multisampled) MRT. Both CMASK and FMASK must be allocated. SPS BLEND_CLAMP"8SS CLEAR_COLOR"SS BLEND_BYPASS"S8SBLEND_FLOAT32"0SS SIMPLE_FLOAT"XSSЊS ROUND_MODESS.ROUND_BY_HALF: add 1/2 lsb and then truncate ЋSFROUND_TRUNCATE: truncate toward zero for float, else toward negative SS TILE_COMPACT"XSSSOURCE_FORMATpSSAEXPORT_FULL: PS exports must use the full 32-bits per component SEXPORT_NORM: PS exports may use a 18-bit per component format that supports 11-bit or smaller UNORM/SNORM/SRGB and 16-bit or smaller FLOAT. RS""hSCB_COLOR3_INFOPSSSENDIANSPS,ENDIAN_NONE: No endian swapping (XOR by 0) SSTENDIAN_8IN16: 8 bit swap within 16 bit word (XOR by 1): 0xAABBCCDD -> 0xBBAADDCC pSSTENDIAN_8IN32: 8 bit swap within 32 bit word (XOR by 3): 0xAABBCCDD -> 0xDDCCBBAA S\ENDIAN_8IN64: 8 bit swap in 64 bits (XOR by 7): 0xaabbccddeeffgghh -> 0xhhggffeeddccbbaa *SSSFORMAT$S8S+COLOR_INVALID: this resource is disabled 8SSCOLOR_8: norm, int SSCOLOR_4_4: norm only xS SCOLOR_3_3_2: norm only SS RESERVED SPSCOLOR_16: norm, int, float HSSCOLOR_16_FLOAT: float only SSCOLOR_8_8: norm, int S0SCOLOR_5_6_5: norm only (SS COLOR_6_5_5: norm only SpS ;COLOR_1_5_5_5: norm only, 1-bit component is always unorm S0S COLOR_4_4_4_4: norm only HSS ;COLOR_5_5_5_1: norm only, 1-bit component is always unorm SS COLOR_32: int, float S0SCOLOR_32_FLOAT: float only 0SSCOLOR_16_16: norm, int, float SxSCOLOR_16_16_FLOAT: float only S S'COLOR_8_24: unorm depth, uint stencil PSS@COLOR_8_24_FLOAT: float depth, uint stencil; deprecated for CB  SS'COLOR_24_8: unorm depth, uint stencil SP S@COLOR_24_8_FLOAT: float depth, uint stencil; deprecated for CB p!S!SCOLOR_10_11_11: float only "S!S"COLOR_10_11_11_FLOAT: float only "S`"SCOLOR_11_11_10: float only `#S#S"COLOR_11_11_10_FLOAT: float only $S#SCOLOR_2_10_10_10: norm, int $SP$S COLOR_8_8_8_8: norm, int, srgb X%S$SCOLOR_10_10_10_2: norm, int &S%S1COLOR_X24_8_32_FLOAT: float depth, uint stencil &SX&SCOLOR_32_32: int, float X'S&SCOLOR_32_32_FLOAT: float only (S'S%COLOR_16_16_16_16: norm, int, float (SP(S +COLOR_16_16_16_16_FLOAT: norm, int, float H)S)S! RESERVED )S)S"COLOR_32_32_32_32: int, float 8*S#%COLOR_32_32_32_32_FLOAT: float only 6S*S@+S ARRAY_MODE+S+S.ARRAY_LINEAR_GENERAL: Unaligned linear array ,S@,S,ARRAY_LINEAR_ALIGNED: Aligned linear array X-S,S+ARRAY_1D_TILED_THIN1: Uses 1D 8x8x1 tiles .S-S+ARRAY_1D_TILED_THICK: Uses 1D 8x8x4 tiles .SP.S.ARRAY_2D_TILED_THIN1: Uses 8x8x1 macro-tiles x/S/S/ARRAY_2D_TILED_THIN2: Macro-tiles are 2x high 00S/S/ARRAY_2D_TILED_THIN4: Macro-tiles are 4x high 0Sx0S.ARRAY_2D_TILED_THICK: Uses 8x8x4 macro-tiles 1S01S.ARRAY_2B_TILED_THIN1: uses row bank swapping X2S1S .ARRAY_2B_TILED_THIN2: uses row bank swapping 3S2S .ARRAY_2B_TILED_THIN4: uses row bank swapping 3SX3S .ARRAY_2B_TILED_THICK: uses row bank swapping 4S4S /ARRAY_3D_TILED_THIN1: Slices are pipe rotated 85S4S /ARRAY_3D_TILED_THICK: Slices are pipe rotated 5S5S/ARRAY_3B_TILED_THIN1: Slices are pipe rotated 86S/ARRAY_3B_TILED_THICK: Slices are pipe rotated >S7S H7S NUMBER_TYPE(8S7SUNUMBER_UNORM: unsigned repeating fraction (urf): range [0..1], scale factor (2^n)-1 9Sp8SRNUMBER_SNORM: Microsoft-style signed rf: range [-1..1], scale factor (2^(n-1))-1 9SH9S*NUMBER_USCALED: DEPRECATED. Do not use. `:S9S*NUMBER_SSCALED: DEPRECATED. Do not use. 8;S:SRNUMBER_UINT: zero-extended bit field, int in shader: not blendable or filterable S READ_SIZE"BS?S?S COMP_SWAP@S@S-SWAP_STD: standard little-endian comp order 8AS@S)SWAP_ALT: alternate components or order ASAS'SWAP_STD_REV: reverses SWAP_STD order 0BS'SWAP_ALT_REV: reverses SWAP_ALT order FSBS8CS TILE_MODE`DSCSTILE_DISABLE: Disable compression for this MRT; the colour surface will always be in a fully-expanded state. Neither CMASK nor FMASK are allocated for this MRT. ESDS-TILE_CLEAR_ENABLE: DEPRECATED. Do not use. `ESkTILE_FRAG_ENABLE: Enable compression for this (multisampled) MRT. Both CMASK and FMASK must be allocated. FS`FS BLEND_CLAMP"HGSGS CLEAR_COLOR"GSGS BLEND_BYPASS"HSHHSBLEND_FLOAT32"@ISHS SIMPLE_FLOAT"hKSISIS ROUND_MODEJS(JS.ROUND_BY_HALF: add 1/2 lsb and then truncate JSFROUND_TRUNCATE: truncate toward zero for float, else toward negative LSKS TILE_COMPACT"hLSLSSOURCE_FORMATMSMSAEXPORT_FULL: PS exports must use the full 32-bits per component MSEXPORT_NORM: PS exports may use a 18-bit per component format that supports 11-bit or smaller UNORM/SNORM/SRGB and 16-bit or smaller FLOAT. ȋR0R""RCB_COLOR2_INFO`RR RENDIANRhR,ENDIAN_NONE: No endian swapping (XOR by 0) RRTENDIAN_8IN16: 8 bit swap within 16 bit word (XOR by 1): 0xAABBCCDD -> 0xBBAADDCC RRTENDIAN_8IN32: 8 bit swap within 32 bit word (XOR by 3): 0xAABBCCDD -> 0xDDCCBBAA R\ENDIAN_8IN64: 8 bit swap in 64 bits (XOR by 7): 0xaabbccddeeffgghh -> 0xhhggffeeddccbbaa RRRFORMAT$RHR+COLOR_INVALID: this resource is disabled HRRCOLOR_8: norm, int RRCOLOR_4_4: norm only R0RCOLOR_3_3_2: norm only RR RESERVED R`RCOLOR_16: norm, int, float XRRCOLOR_16_FLOAT: float only RRCOLOR_8_8: norm, int R@RCOLOR_5_6_5: norm only 8RR COLOR_6_5_5: norm only RR ;COLOR_1_5_5_5: norm only, 1-bit component is always unorm R@R COLOR_4_4_4_4: norm only XRR ;COLOR_5_5_5_1: norm only, 1-bit component is always unorm RR COLOR_32: int, float R@RCOLOR_32_FLOAT: float only @RRCOLOR_16_16: norm, int, float RRCOLOR_16_16_FLOAT: float only R0R'COLOR_8_24: unorm depth, uint stencil `RR@COLOR_8_24_FLOAT: float depth, uint stencil; deprecated for CB RR'COLOR_24_8: unorm depth, uint stencil RXR@COLOR_24_8_FLOAT: float depth, uint stencil; deprecated for CB xR RCOLOR_10_11_11: float only RR"COLOR_10_11_11_FLOAT: float only RhRCOLOR_11_11_10: float only hRR"COLOR_11_11_10_FLOAT: float only RRCOLOR_2_10_10_10: norm, int RXR COLOR_8_8_8_8: norm, int, srgb `RRCOLOR_10_10_10_2: norm, int RR1COLOR_X24_8_32_FLOAT: float depth, uint stencil R`RCOLOR_32_32: int, float `RRCOLOR_32_32_FLOAT: float only RR%COLOR_16_16_16_16: norm, int, float RXR +COLOR_16_16_16_16_FLOAT: norm, int, float PRR! RESERVED RR"COLOR_32_32_32_32: int, float @R#%COLOR_32_32_32_32_FLOAT: float only RRHR ARRAY_MODERR.ARRAY_LINEAR_GENERAL: Unaligned linear array RHR,ARRAY_LINEAR_ALIGNED: Aligned linear array `RR+ARRAY_1D_TILED_THIN1: Uses 1D 8x8x1 tiles RR+ARRAY_1D_TILED_THICK: Uses 1D 8x8x4 tiles RXR.ARRAY_2D_TILED_THIN1: Uses 8x8x1 macro-tiles RR/ARRAY_2D_TILED_THIN2: Macro-tiles are 2x high 8RR/ARRAY_2D_TILED_THIN4: Macro-tiles are 4x high RR.ARRAY_2D_TILED_THICK: Uses 8x8x4 macro-tiles R8R.ARRAY_2B_TILED_THIN1: uses row bank swapping `RR .ARRAY_2B_TILED_THIN2: uses row bank swapping RR .ARRAY_2B_TILED_THIN4: uses row bank swapping R`R .ARRAY_2B_TILED_THICK: uses row bank swapping RR /ARRAY_3D_TILED_THIN1: Slices are pipe rotated @RR /ARRAY_3D_TILED_THICK: Slices are pipe rotated RR/ARRAY_3B_TILED_THIN1: Slices are pipe rotated @R/ARRAY_3B_TILED_THICK: Slices are pipe rotated RR PR NUMBER_TYPE0RRUNUMBER_UNORM: unsigned repeating fraction (urf): range [0..1], scale factor (2^n)-1 RxRRNUMBER_SNORM: Microsoft-style signed rf: range [-1..1], scale factor (2^(n-1))-1 RPR*NUMBER_USCALED: DEPRECATED. Do not use. hRR*NUMBER_SSCALED: DEPRECATED. Do not use. @RRRNUMBER_UINT: zero-extended bit field, int in shader: not blendable or filterable RRRNUMBER_SINT: sign-extended bit field, int in shader: not blendable or filterable R`RtNUMBER_SRGB: gamma corrected, range [0..1] (only supported for COLOR_8_8_8_8 format; always rounds color channels) XRNUMBER_FLOAT: floating point: 32-bit: IEEE float, SE8M23, bias 127, range (-2^129..2^129); 16-bit: Short float SE5M10, bias 15, range (-2^17..2^17); 11-bit: Packed float, E5M6 bias 15, range [0..2^17); 10-bit: Packed float, E5M5 bias 15, range [0..2^17) 8RR READ_SIZE"SRR COMP_SWAPR R-SWAP_STD: standard little-endian comp order @SR)SWAP_ALT: alternate components or order SS'SWAP_STD_REV: reverses SWAP_STD order 8S'SWAP_ALT_REV: reverses SWAP_ALT order SS@S TILE_MODEhSSTILE_DISABLE: Disable compression for this MRT; the colour surface will always be in a fully-expanded state. Neither CMASK nor FMASK are allocated for this MRT. SS-TILE_CLEAR_ENABLE: DEPRECATED. Do not use. hSkTILE_FRAG_ENABLE: Enable compression for this (multisampled) MRT. Both CMASK and FMASK must be allocated. ShS BLEND_CLAMP"PSS CLEAR_COLOR"SS BLEND_BYPASS"SPSBLEND_FLOAT32"HSS SIMPLE_FLOAT"p SSS ROUND_MODE S0 S.ROUND_BY_HALF: add 1/2 lsb and then truncate SFROUND_TRUNCATE: truncate toward zero for float, else toward negative  S S TILE_COMPACT"p S SSOURCE_FORMAT S SAEXPORT_FULL: PS exports must use the full 32-bits per component SEXPORT_NORM: PS exports may use a 18-bit per component format that supports 11-bit or smaller UNORM/SNORM/SRGB and 16-bit or smaller FLOAT. JR@R""RCB_COLOR1_INFOpRR0RENDIANRxR,ENDIAN_NONE: No endian swapping (XOR by 0) R(RTENDIAN_8IN16: 8 bit swap within 16 bit word (XOR by 1): 0xAABBCCDD -> 0xBBAADDCC RRTENDIAN_8IN32: 8 bit swap within 32 bit word (XOR by 3): 0xAABBCCDD -> 0xDDCCBBAA ؏R\ENDIAN_8IN64: 8 bit swap in 64 bits (XOR by 7): 0xaabbccddeeffgghh -> 0xhhggffeeddccbbaa RȐRRFORMAT$RXR+COLOR_INVALID: this resource is disabled XRRCOLOR_8: norm, int RRCOLOR_4_4: norm only R@RCOLOR_3_3_2: norm only (RR RESERVED ȔRpRCOLOR_16: norm, int, float hRRCOLOR_16_FLOAT: float only RRCOLOR_8_8: norm, int RPRCOLOR_5_6_5: norm only HRR COLOR_6_5_5: norm only RR ;COLOR_1_5_5_5: norm only, 1-bit component is always unorm RPR COLOR_4_4_4_4: norm only hRR ;COLOR_5_5_5_1: norm only, 1-bit component is always unorm RR COLOR_32: int, float RPRCOLOR_32_FLOAT: float only PRRCOLOR_16_16: norm, int, float RRCOLOR_16_16_FLOAT: float only R@R'COLOR_8_24: unorm depth, uint stencil pRR@COLOR_8_24_FLOAT: float depth, uint stencil; deprecated for CB RR'COLOR_24_8: unorm depth, uint stencil RhR@COLOR_24_8_FLOAT: float depth, uint stencil; deprecated for CB R0RCOLOR_10_11_11: float only 0RПR"COLOR_10_11_11_FLOAT: float only РRxRCOLOR_11_11_10: float only xRR"COLOR_11_11_10_FLOAT: float only RRCOLOR_2_10_10_10: norm, int ȢRhR COLOR_8_8_8_8: norm, int, srgb pRRCOLOR_10_10_10_2: norm, int (RR1COLOR_X24_8_32_FLOAT: float depth, uint stencil ȤRpRCOLOR_32_32: int, float pRRCOLOR_32_32_FLOAT: float only RR%COLOR_16_16_16_16: norm, int, float ЦRhR +COLOR_16_16_16_16_FLOAT: norm, int, float `RR! RESERVED RR"COLOR_32_32_32_32: int, float PR#%COLOR_32_32_32_32_FLOAT: float only ȴRRXR ARRAY_MODERR.ARRAY_LINEAR_GENERAL: Unaligned linear array RXR,ARRAY_LINEAR_ALIGNED: Aligned linear array pRR+ARRAY_1D_TILED_THIN1: Uses 1D 8x8x1 tiles RR+ARRAY_1D_TILED_THICK: Uses 1D 8x8x4 tiles جRhR.ARRAY_2D_TILED_THIN1: Uses 8x8x1 macro-tiles R R/ARRAY_2D_TILED_THIN2: Macro-tiles are 2x high HRحR/ARRAY_2D_TILED_THIN4: Macro-tiles are 4x high RR.ARRAY_2D_TILED_THICK: Uses 8x8x4 macro-tiles RHR.ARRAY_2B_TILED_THIN1: uses row bank swapping xRR .ARRAY_2B_TILED_THIN2: uses row bank swapping 0RR .ARRAY_2B_TILED_THIN4: uses row bank swapping RxR .ARRAY_2B_TILED_THICK: uses row bank swapping R0R /ARRAY_3D_TILED_THIN1: Slices are pipe rotated XRR /ARRAY_3D_TILED_THICK: Slices are pipe rotated RR/ARRAY_3B_TILED_THIN1: Slices are pipe rotated XR/ARRAY_3B_TILED_THICK: Slices are pipe rotated R R hR NUMBER_TYPEHRRUNUMBER_UNORM: unsigned repeating fraction (urf): range [0..1], scale factor (2^n)-1 RRRNUMBER_SNORM: Microsoft-style signed rf: range [-1..1], scale factor (2^(n-1))-1 зRhR*NUMBER_USCALED: DEPRECATED. Do not use. RR*NUMBER_SSCALED: DEPRECATED. Do not use. XRȸRRNUMBER_UINT: zero-extended bit field, int in shader: not blendable or filterable 0RRRNUMBER_SINT: sign-extended bit field, int in shader: not blendable or filterable (RxRtNUMBER_SRGB: gamma corrected, range [0..1] (only supported for COLOR_8_8_8_8 format; always rounds color channels) pRNUMBER_FLOAT: floating point: 32-bit: IEEE float, SE8M23, bias 127, range (-2^129..2^129); 16-bit: Short float SE5M10, bias 15, range (-2^17..2^17); 11-bit: Packed float, E5M6 bias 15, range [0..2^17); 10-bit: Packed float, E5M5 bias 15, range [0..2^17) PRR READ_SIZE"RRR COMP_SWAPR8R-SWAP_STD: standard little-endian comp order XRR)SWAP_ALT: alternate components or order RR'SWAP_STD_REV: reverses SWAP_STD order PR'SWAP_ALT_REV: reverses SWAP_ALT order (RRXR TILE_MODERRTILE_DISABLE: Disable compression for this MRT; the colour surface will always be in a fully-expanded state. Neither CMASK nor FMASK are allocated for this MRT. 8RR-TILE_CLEAR_ENABLE: DEPRECATED. Do not use. RkTILE_FRAG_ENABLE: Enable compression for this (multisampled) MRT. Both CMASK and FMASK must be allocated. RR BLEND_CLAMP"hR R CLEAR_COLOR"RR BLEND_BYPASS"RhRBLEND_FLOAT32"`RR SIMPLE_FLOAT"RRR ROUND_MODERHR.ROUND_BY_HALF: add 1/2 lsb and then truncate RFROUND_TRUNCATE: truncate toward zero for float, else toward negative 0RR TILE_COMPACT"RRSOURCE_FORMATR RAEXPORT_FULL: PS exports must use the full 32-bits per component REXPORT_NORM: PS exports may use a 18-bit per component format that supports 11-bit or smaller UNORM/SNORM/SRGB and 16-bit or smaller FLOAT. HRXKR""KRCB_COLOR0_INFOORLRHLRENDIANLRLR,ENDIAN_NONE: No endian swapping (XOR by 0) MR@MRTENDIAN_8IN16: 8 bit swap within 16 bit word (XOR by 1): 0xAABBCCDD -> 0xBBAADDCC NRNRTENDIAN_8IN32: 8 bit swap within 32 bit word (XOR by 3): 0xAABBCCDD -> 0xDDCCBBAA NR\ENDIAN_8IN64: 8 bit swap in 64 bits (XOR by 7): 0xaabbccddeeffgghh -> 0xhhggffeeddccbbaa gROR(PRFORMAT$PRpPR+COLOR_INVALID: this resource is disabled pQR QRCOLOR_8: norm, int RRQRCOLOR_4_4: norm only RRXRRCOLOR_3_3_2: norm only @SRRR RESERVED SRSRCOLOR_16: norm, int, float TR(TRCOLOR_16_FLOAT: float only URTRCOLOR_8_8: norm, int URhURCOLOR_5_6_5: norm only `VRVR COLOR_6_5_5: norm only WRVR ;COLOR_1_5_5_5: norm only, 1-bit component is always unorm WRhWR COLOR_4_4_4_4: norm only XRXR ;COLOR_5_5_5_1: norm only, 1-bit component is always unorm YRXR COLOR_32: int, float YRhYRCOLOR_32_FLOAT: float only hZRZRCOLOR_16_16: norm, int, float [RZRCOLOR_16_16_FLOAT: float only [RX[R'COLOR_8_24: unorm depth, uint stencil \R\R@COLOR_8_24_FLOAT: float depth, uint stencil; deprecated for CB 8]R\R'COLOR_24_8: unorm depth, uint stencil ^R]R@COLOR_24_8_FLOAT: float depth, uint stencil; deprecated for CB ^RH^RCOLOR_10_11_11: float only H_R^R"COLOR_10_11_11_FLOAT: float only _R_RCOLOR_11_11_10: float only `R0`R"COLOR_11_11_10_FLOAT: float only 8aR`RCOLOR_2_10_10_10: norm, int aRaR COLOR_8_8_8_8: norm, int, srgb bR(bRCOLOR_10_10_10_2: norm, int @cRbR1COLOR_X24_8_32_FLOAT: float depth, uint stencil cRcRCOLOR_32_32: int, float dR(dRCOLOR_32_32_FLOAT: float only 8eRdR%COLOR_16_16_16_16: norm, int, float eReR +COLOR_16_16_16_16_FLOAT: norm, int, float xfR0fR! RESERVED gRfR"COLOR_32_32_32_32: int, float hgR#%COLOR_32_32_32_32_FLOAT: float only sR(hRphR ARRAY_MODE(iRhR.ARRAY_LINEAR_GENERAL: Unaligned linear array iRpiR,ARRAY_LINEAR_ALIGNED: Aligned linear array jR jR+ARRAY_1D_TILED_THIN1: Uses 1D 8x8x1 tiles 8kRjR+ARRAY_1D_TILED_THICK: Uses 1D 8x8x4 tiles kRkR.ARRAY_2D_TILED_THIN1: Uses 8x8x1 macro-tiles lR8lR/ARRAY_2D_TILED_THIN2: Macro-tiles are 2x high `mRlR/ARRAY_2D_TILED_THIN4: Macro-tiles are 4x high nRmR.ARRAY_2D_TILED_THICK: Uses 8x8x4 macro-tiles nR`nR.ARRAY_2B_TILED_THIN1: uses row bank swapping oRoR .ARRAY_2B_TILED_THIN2: uses row bank swapping @pRoR .ARRAY_2B_TILED_THIN4: uses row bank swapping pRpR .ARRAY_2B_TILED_THICK: uses row bank swapping qR@qR /ARRAY_3D_TILED_THIN1: Slices are pipe rotated hrRqR /ARRAY_3D_TILED_THICK: Slices are pipe rotated sRrR/ARRAY_3B_TILED_THIN1: Slices are pipe rotated hsR/ARRAY_3B_TILED_THICK: Slices are pipe rotated {R0tR xtR NUMBER_TYPEXuRtRUNUMBER_UNORM: unsigned repeating fraction (urf): range [0..1], scale factor (2^n)-1 0vRuRRNUMBER_SNORM: Microsoft-style signed rf: range [-1..1], scale factor (2^(n-1))-1 vRxvR*NUMBER_USCALED: DEPRECATED. Do not use. wR(wR*NUMBER_SSCALED: DEPRECATED. Do not use. hxRwRRNUMBER_UINT: zero-extended bit field, int in shader: not blendable or filterable @yRxRRNUMBER_SINT: sign-extended bit field, int in shader: not blendable or filterable 8zRyRtNUMBER_SRGB: gamma corrected, range [0..1] (only supported for COLOR_8_8_8_8 format; always rounds color channels) zRNUMBER_FLOAT: floating point: 32-bit: IEEE float, SE8M23, bias 127, range (-2^129..2^129); 16-bit: Short float SE5M10, bias 15, range (-2^17..2^17); 11-bit: Packed float, E5M6 bias 15, range [0..2^17); 10-bit: Packed float, E5M5 bias 15, range [0..2^17) `|R|R READ_SIZE"R|R}R COMP_SWAP}RH}R-SWAP_STD: standard little-endian comp order h~R~R)SWAP_ALT: alternate components or order R~R'SWAP_STD_REV: reverses SWAP_STD order `R'SWAP_ALT_REV: reverses SWAP_ALT order 8R RhR TILE_MODERRTILE_DISABLE: Disable compression for this MRT; the colour surface will always be in a fully-expanded state. Neither CMASK nor FMASK are allocated for this MRT. HR؁R-TILE_CLEAR_ENABLE: DEPRECATED. Do not use. RkTILE_FRAG_ENABLE: Enable compression for this (multisampled) MRT. Both CMASK and FMASK must be allocated. ؃RR BLEND_CLAMP"xR0R CLEAR_COLOR" RЄR BLEND_BYPASS"ȅRxRBLEND_FLOAT32"pR R SIMPLE_FLOAT"RȆRR ROUND_MODEȇRXR.ROUND_BY_HALF: add 1/2 lsb and then truncate RFROUND_TRUNCATE: truncate toward zero for float, else toward negative @RR TILE_COMPACT"RRSOURCE_FORMATR0RAEXPORT_FULL: PS exports must use the full 32-bits per component REXPORT_NORM: PS exports may use a 18-bit per component format that supports 11-bit or smaller UNORM/SNORM/SRGB and 16-bit or smaller FLOAT. FRPIR""IRCB_COLOR7_VIEW@JRIR SLICE_START"JR SLICE_MAX"DRHGR""GRCB_COLOR6_VIEW8HRGR SLICE_START"HR SLICE_MAX"BR@ER""ERCB_COLOR5_VIEW0FRER SLICE_START"FR SLICE_MAX"@R8CR""CRCB_COLOR4_VIEW(DRCR SLICE_START"DR SLICE_MAX">R0AR""ARCB_COLOR3_VIEW BRAR SLICE_START"xBR SLICE_MAX"R=R SLICE_START"h>R SLICE_MAX"8R;R""h;RCB_COLOR0_VIEWQ=Q 0BLEND_BOTH_SRC_ALPHA: DEPRECATED. Do not use. >Q>Q 4BLEND_BOTH_INV_SRC_ALPHA: DEPRECATED. Do not use. ?Q@?Q PBLEND_CONSTANT_COLOR: (d3d_blendfactor, uses corresponding RB_BLEND component) @Q@Q6BLEND_ONE_MINUS_CONSTANT_COLOR: (d3d_invblendfactor) @AQ@Q)BLEND_SRC1_COLOR: DX10 dual-source mode AQAQ-BLEND_INV_SRC1_COLOR: DX10 dual-source mode BQ@BQ)BLEND_SRC1_ALPHA: DX10 dual-source mode `CQBQ-BLEND_INV_SRC1_ALPHA: DX10 dual-source mode DQCQ-BLEND_CONSTANT_ALPHA: (uses RB_BLEND_ALPHA) `DQ#BLEND_ONE_MINUS_CONSTANT_ALPHA: IQEQhEQCOLOR_COMB_FCN(FQEQ;COMB_DST_PLUS_SRC: (ADD): Source*SRCBLEND + Dest*DSTBLEND FQpFQACOMB_SRC_MINUS_DST: (SUBTRACT): Source*SRCBLEND - Dest*DSTBLEND GQ8GQ,COMB_MIN_DST_SRC: (MIN): min(Source, Dest) PHQGQ,COMB_MAX_DST_SRC: (MAX): max(Source, Dest) HQDCOMB_DST_MINUS_SRC: (REVSUBTRACT): Dest*DSTBLEND - Source*SRCBLEND pXQpIQIQCOLOR_DESTBLEND`JQJQBLEND_ZERO: (d3d_zero) KQJQBLEND_ONE: (d3d_one) KQHKQ!BLEND_SRC_COLOR: (d3d_srccolor) `LQKQ.BLEND_ONE_MINUS_SRC_COLOR: (d3d_invsrccolor) MQLQ!BLEND_SRC_ALPHA: (d3d_srcalpha) MQPMQ.BLEND_ONE_MINUS_SRC_ALPHA: (d3d_invsrcalpha) hNQNQ"BLEND_DST_ALPHA: (d3d_destalpha) OQNQ/BLEND_ONE_MINUS_DST_ALPHA: (d3d_invdestalpha) OQhOQ"BLEND_DST_COLOR: (d3d_destcolor) PQPQ /BLEND_ONE_MINUS_DST_COLOR: (d3d_invdestcolor) 8QQPQ -BLEND_SRC_ALPHA_SATURATE: (d3d_srcalphasat) QQQQ 0BLEND_BOTH_SRC_ALPHA: DEPRECATED. Do not use. RQ8RQ 4BLEND_BOTH_INV_SRC_ALPHA: DEPRECATED. Do not use. SQRQ PBLEND_CONSTANT_COLOR: (d3d_blendfactor, uses corresponding RB_BLEND component) @TQSQ6BLEND_ONE_MINUS_CONSTANT_COLOR: (d3d_invblendfactor) TQTQ)BLEND_SRC1_COLOR: DX10 dual-source mode UQ8UQ-BLEND_INV_SRC1_COLOR: DX10 dual-source mode XVQUQ)BLEND_SRC1_ALPHA: DX10 dual-source mode WQVQ-BLEND_INV_SRC1_ALPHA: DX10 dual-source mode WQXWQ-BLEND_CONSTANT_ALPHA: (uses RB_BLEND_ALPHA) XQ#BLEND_ONE_MINUS_CONSTANT_ALPHA: YQXQ OPACITY_WEIGHT"phQpYQYQALPHA_SRCBLEND`ZQZQBLEND_ZERO: (d3d_zero) [QZQBLEND_ONE: (d3d_one) [QH[Q!BLEND_SRC_COLOR: (d3d_srccolor) `\Q[Q.BLEND_ONE_MINUS_SRC_COLOR: (d3d_invsrccolor) ]Q\Q!BLEND_SRC_ALPHA: (d3d_srcalpha) ]QP]Q.BLEND_ONE_MINUS_SRC_ALPHA: (d3d_invsrcalpha) h^Q^Q"BLEND_DST_ALPHA: (d3d_destalpha) _Q^Q/BLEND_ONE_MINUS_DST_ALPHA: (d3d_invdestalpha) _Qh_Q"BLEND_DST_COLOR: (d3d_destcolor) `Q`Q /BLEND_ONE_MINUS_DST_COLOR: (d3d_invdestcolor) 8aQ`Q -BLEND_SRC_ALPHA_SATURATE: (d3d_srcalphasat) aQaQ 0BLEND_BOTH_SRC_ALPHA: DEPRECATED. Do not use. bQ8bQ 4BLEND_BOTH_INV_SRC_ALPHA: DEPRECATED. Do not use. cQbQ PBLEND_CONSTANT_COLOR: (d3d_blendfactor, uses corresponding RB_BLEND component) @dQcQ6BLEND_ONE_MINUS_CONSTANT_COLOR: (d3d_invblendfactor) dQdQ)BLEND_SRC1_COLOR: DX10 dual-source mode eQ8eQ-BLEND_INV_SRC1_COLOR: DX10 dual-source mode XfQeQ)BLEND_SRC1_ALPHA: DX10 dual-source mode gQfQ-BLEND_INV_SRC1_ALPHA: DX10 dual-source mode gQXgQ-BLEND_CONSTANT_ALPHA: (uses RB_BLEND_ALPHA) hQ#BLEND_ONE_MINUS_CONSTANT_ALPHA: lQhQiQALPHA_COMB_FCNiQ`iQ;COMB_DST_PLUS_SRC: (ADD): Source*SRCBLEND + Dest*DSTBLEND jQ jQACOMB_SRC_MINUS_DST: (SUBTRACT): Source*SRCBLEND - Dest*DSTBLEND PkQjQ,COMB_MIN_DST_SRC: (MIN): min(Source, Dest) lQkQ,COMB_MAX_DST_SRC: (MAX): max(Source, Dest) HlQDCOMB_DST_MINUS_SRC: (REVSUBTRACT): Dest*DSTBLEND - Source*SRCBLEND |Q mQpmQALPHA_DESTBLENDnQmQBLEND_ZERO: (d3d_zero) nQXnQBLEND_ONE: (d3d_one) XoQnQ!BLEND_SRC_COLOR: (d3d_srccolor) pQoQ.BLEND_ONE_MINUS_SRC_COLOR: (d3d_invsrccolor) pQXpQ!BLEND_SRC_ALPHA: (d3d_srcalpha) pqQqQ.BLEND_ONE_MINUS_SRC_ALPHA: (d3d_invsrcalpha) rQqQ"BLEND_DST_ALPHA: (d3d_destalpha) rQ`rQ/BLEND_ONE_MINUS_DST_ALPHA: (d3d_invdestalpha) xsQsQ"BLEND_DST_COLOR: (d3d_destcolor) 0tQsQ /BLEND_ONE_MINUS_DST_COLOR: (d3d_invdestcolor) tQxtQ -BLEND_SRC_ALPHA_SATURATE: (d3d_srcalphasat) uQ0uQ 0BLEND_BOTH_SRC_ALPHA: DEPRECATED. Do not use. XvQuQ 4BLEND_BOTH_INV_SRC_ALPHA: DEPRECATED. Do not use. 0wQvQ PBLEND_CONSTANT_COLOR: (d3d_blendfactor, uses corresponding RB_BLEND component) wQxwQ6BLEND_ONE_MINUS_CONSTANT_COLOR: (d3d_invblendfactor) xQ8xQ)BLEND_SRC1_COLOR: DX10 dual-source mode XyQxQ-BLEND_INV_SRC1_COLOR: DX10 dual-source mode zQyQ)BLEND_SRC1_ALPHA: DX10 dual-source mode zQPzQ-BLEND_INV_SRC1_ALPHA: DX10 dual-source mode x{Q{Q-BLEND_CONSTANT_ALPHA: (uses RB_BLEND_ALPHA) {Q#BLEND_ONE_MINUS_CONSTANT_ALPHA: x|QSEPARATE_ALPHA_BLEND"@PP""8PCB_BLEND4_CONTROLPPPCOLOR_SRCBLENDP(PBLEND_ZERO: (d3d_zero) PPBLEND_ONE: (d3d_one) PhP!BLEND_SRC_COLOR: (d3d_srccolor) PP.BLEND_ONE_MINUS_SRC_COLOR: (d3d_invsrccolor) (PP!BLEND_SRC_ALPHA: (d3d_srcalpha) PpP.BLEND_ONE_MINUS_SRC_ALPHA: (d3d_invsrcalpha) P(P"BLEND_DST_ALPHA: (d3d_destalpha) @PP/BLEND_ONE_MINUS_DST_ALPHA: (d3d_invdestalpha) PP"BLEND_DST_COLOR: (d3d_destcolor) P0P /BLEND_ONE_MINUS_DST_COLOR: (d3d_invdestcolor) XPP -BLEND_SRC_ALPHA_SATURATE: (d3d_srcalphasat) PP 0BLEND_BOTH_SRC_ALPHA: DEPRECATED. Do not use. PXP 4BLEND_BOTH_INV_SRC_ALPHA: DEPRECATED. Do not use. PP PBLEND_CONSTANT_COLOR: (d3d_blendfactor, uses corresponding RB_BLEND component) `PP6BLEND_ONE_MINUS_CONSTANT_COLOR: (d3d_invblendfactor) PP)BLEND_SRC1_COLOR: DX10 dual-source mode PXP-BLEND_INV_SRC1_COLOR: DX10 dual-source mode xPP)BLEND_SRC1_ALPHA: DX10 dual-source mode 0PP-BLEND_INV_SRC1_ALPHA: DX10 dual-source mode PxP-BLEND_CONSTANT_ALPHA: (uses RB_BLEND_ALPHA) 0P#BLEND_ONE_MINUS_CONSTANT_ALPHA: QP8PCOLOR_COMB_FCNPP;COMB_DST_PLUS_SRC: (ADD): Source*SRCBLEND + Dest*DSTBLEND P@PACOMB_SRC_MINUS_DST: (SUBTRACT): Source*SRCBLEND - Dest*DSTBLEND pPP,COMB_MIN_DST_SRC: (MIN): min(Source, Dest) QP,COMB_MAX_DST_SRC: (MAX): max(Source, Dest) hQDCOMB_DST_MINUS_SRC: (REVSUBTRACT): Dest*DSTBLEND - Source*SRCBLEND @Q@QQCOLOR_DESTBLEND0QQBLEND_ZERO: (d3d_zero) QxQBLEND_ONE: (d3d_one) xQQ!BLEND_SRC_COLOR: (d3d_srccolor) 0QQ.BLEND_ONE_MINUS_SRC_COLOR: (d3d_invsrccolor) QxQ!BLEND_SRC_ALPHA: (d3d_srcalpha) Q Q.BLEND_ONE_MINUS_SRC_ALPHA: (d3d_invsrcalpha) 8QQ"BLEND_DST_ALPHA: (d3d_destalpha) QQ/BLEND_ONE_MINUS_DST_ALPHA: (d3d_invdestalpha) Q8Q"BLEND_DST_COLOR: (d3d_destcolor) PQQ /BLEND_ONE_MINUS_DST_COLOR: (d3d_invdestcolor)  QQ -BLEND_SRC_ALPHA_SATURATE: (d3d_srcalphasat) QP Q 0BLEND_BOTH_SRC_ALPHA: DEPRECATED. Do not use. x Q Q 4BLEND_BOTH_INV_SRC_ALPHA: DEPRECATED. Do not use. P Q Q PBLEND_CONSTANT_COLOR: (d3d_blendfactor, uses corresponding RB_BLEND component)  Q Q6BLEND_ONE_MINUS_CONSTANT_COLOR: (d3d_invblendfactor) QX Q)BLEND_SRC1_COLOR: DX10 dual-source mode x Q Q-BLEND_INV_SRC1_COLOR: DX10 dual-source mode (Q Q)BLEND_SRC1_ALPHA: DX10 dual-source mode QpQ-BLEND_INV_SRC1_ALPHA: DX10 dual-source mode Q(Q-BLEND_CONSTANT_ALPHA: (uses RB_BLEND_ALPHA) Q#BLEND_ONE_MINUS_CONSTANT_ALPHA: QQ OPACITY_WEIGHT"@ Q@QQALPHA_SRCBLEND0QQBLEND_ZERO: (d3d_zero) QxQBLEND_ONE: (d3d_one) xQQ!BLEND_SRC_COLOR: (d3d_srccolor) 0QQ.BLEND_ONE_MINUS_SRC_COLOR: (d3d_invsrccolor) QxQ!BLEND_SRC_ALPHA: (d3d_srcalpha) Q Q.BLEND_ONE_MINUS_SRC_ALPHA: (d3d_invsrcalpha) 8QQ"BLEND_DST_ALPHA: (d3d_destalpha) QQ/BLEND_ONE_MINUS_DST_ALPHA: (d3d_invdestalpha) Q8Q"BLEND_DST_COLOR: (d3d_destcolor) PQQ /BLEND_ONE_MINUS_DST_COLOR: (d3d_invdestcolor) QQ -BLEND_SRC_ALPHA_SATURATE: (d3d_srcalphasat) QPQ 0BLEND_BOTH_SRC_ALPHA: DEPRECATED. Do not use. xQQ 4BLEND_BOTH_INV_SRC_ALPHA: DEPRECATED. Do not use. PQQ PBLEND_CONSTANT_COLOR: (d3d_blendfactor, uses corresponding RB_BLEND component) QQ6BLEND_ONE_MINUS_CONSTANT_COLOR: (d3d_invblendfactor) QXQ)BLEND_SRC1_COLOR: DX10 dual-source mode xQQ-BLEND_INV_SRC1_COLOR: DX10 dual-source mode (QQ)BLEND_SRC1_ALPHA: DX10 dual-source mode QpQ-BLEND_INV_SRC1_ALPHA: DX10 dual-source mode Q(Q-BLEND_CONSTANT_ALPHA: (uses RB_BLEND_ALPHA) Q#BLEND_ONE_MINUS_CONSTANT_ALPHA: $Q Q QALPHA_COMB_FCN!Q0!Q;COMB_DST_PLUS_SRC: (ADD): Source*SRCBLEND + Dest*DSTBLEND p"Q!QACOMB_SRC_MINUS_DST: (SUBTRACT): Source*SRCBLEND - Dest*DSTBLEND #Q"Q,COMB_MIN_DST_SRC: (MIN): min(Source, Dest) #Qh#Q,COMB_MAX_DST_SRC: (MAX): max(Source, Dest) $QDCOMB_DST_MINUS_SRC: (REVSUBTRACT): Dest*DSTBLEND - Source*SRCBLEND 3Q$Q@%QALPHA_DESTBLEND%Q%QBLEND_ZERO: (d3d_zero) &Q(&QBLEND_ONE: (d3d_one) ('Q&Q!BLEND_SRC_COLOR: (d3d_srccolor) 'Qp'Q.BLEND_ONE_MINUS_SRC_COLOR: (d3d_invsrccolor) (Q((Q!BLEND_SRC_ALPHA: (d3d_srcalpha) @)Q(Q.BLEND_ONE_MINUS_SRC_ALPHA: (d3d_invsrcalpha) )Q)Q"BLEND_DST_ALPHA: (d3d_destalpha) *Q0*Q/BLEND_ONE_MINUS_DST_ALPHA: (d3d_invdestalpha) H+Q*Q"BLEND_DST_COLOR: (d3d_destcolor) ,Q+Q /BLEND_ONE_MINUS_DST_COLOR: (d3d_invdestcolor) ,QH,Q -BLEND_SRC_ALPHA_SATURATE: (d3d_srcalphasat) p-Q-Q 0BLEND_BOTH_SRC_ALPHA: DEPRECATED. Do not use. (.Q-Q 4BLEND_BOTH_INV_SRC_ALPHA: DEPRECATED. Do not use. /Qp.Q PBLEND_CONSTANT_COLOR: (d3d_blendfactor, uses corresponding RB_BLEND component) /QH/Q6BLEND_ONE_MINUS_CONSTANT_COLOR: (d3d_invblendfactor) p0Q0Q)BLEND_SRC1_COLOR: DX10 dual-source mode (1Q0Q-BLEND_INV_SRC1_COLOR: DX10 dual-source mode 1Qp1Q)BLEND_SRC1_ALPHA: DX10 dual-source mode 2Q 2Q-BLEND_INV_SRC1_ALPHA: DX10 dual-source mode H3Q2Q-BLEND_CONSTANT_ALPHA: (uses RB_BLEND_ALPHA) 3Q#BLEND_ONE_MINUS_CONSTANT_ALPHA: H4QSEPARATE_ALPHA_BLEND"\PP""PCB_BLEND3_CONTROL`P`PPCOLOR_SRCBLENDPPPBLEND_ZERO: (d3d_zero) PPBLEND_ONE: (d3d_one) P8P!BLEND_SRC_COLOR: (d3d_srccolor) PPP.BLEND_ONE_MINUS_SRC_COLOR: (d3d_invsrccolor) PP!BLEND_SRC_ALPHA: (d3d_srcalpha) P@P.BLEND_ONE_MINUS_SRC_ALPHA: (d3d_invsrcalpha) XPP"BLEND_DST_ALPHA: (d3d_destalpha) PP/BLEND_ONE_MINUS_DST_ALPHA: (d3d_invdestalpha) PXP"BLEND_DST_COLOR: (d3d_destcolor) pPP /BLEND_ONE_MINUS_DST_COLOR: (d3d_invdestcolor) (PP -BLEND_SRC_ALPHA_SATURATE: (d3d_srcalphasat) PpP 0BLEND_BOTH_SRC_ALPHA: DEPRECATED. Do not use. P(P 4BLEND_BOTH_INV_SRC_ALPHA: DEPRECATED. Do not use. pPP PBLEND_CONSTANT_COLOR: (d3d_blendfactor, uses corresponding RB_BLEND component) 0PP6BLEND_ONE_MINUS_CONSTANT_COLOR: (d3d_invblendfactor) PxP)BLEND_SRC1_COLOR: DX10 dual-source mode P(P-BLEND_INV_SRC1_COLOR: DX10 dual-source mode HPP)BLEND_SRC1_ALPHA: DX10 dual-source mode PP-BLEND_INV_SRC1_ALPHA: DX10 dual-source mode PHP-BLEND_CONSTANT_ALPHA: (uses RB_BLEND_ALPHA) P#BLEND_ONE_MINUS_CONSTANT_ALPHA: PPPCOLOR_COMB_FCNȵPPP;COMB_DST_PLUS_SRC: (ADD): Source*SRCBLEND + Dest*DSTBLEND PPACOMB_SRC_MINUS_DST: (SUBTRACT): Source*SRCBLEND - Dest*DSTBLEND @PضP,COMB_MIN_DST_SRC: (MIN): min(Source, Dest) PP,COMB_MAX_DST_SRC: (MAX): max(Source, Dest) 8PDCOMB_DST_MINUS_SRC: (REVSUBTRACT): Dest*DSTBLEND - Source*SRCBLEND PP`PCOLOR_DESTBLENDPPBLEND_ZERO: (d3d_zero) PHPBLEND_ONE: (d3d_one) HPP!BLEND_SRC_COLOR: (d3d_srccolor) PP.BLEND_ONE_MINUS_SRC_COLOR: (d3d_invsrccolor) PHP!BLEND_SRC_ALPHA: (d3d_srcalpha) `PP.BLEND_ONE_MINUS_SRC_ALPHA: (d3d_invsrcalpha) PP"BLEND_DST_ALPHA: (d3d_destalpha) PPP/BLEND_ONE_MINUS_DST_ALPHA: (d3d_invdestalpha) hPP"BLEND_DST_COLOR: (d3d_destcolor) PP /BLEND_ONE_MINUS_DST_COLOR: (d3d_invdestcolor) PhP -BLEND_SRC_ALPHA_SATURATE: (d3d_srcalphasat) P P 0BLEND_BOTH_SRC_ALPHA: DEPRECATED. Do not use. HPP 4BLEND_BOTH_INV_SRC_ALPHA: DEPRECATED. Do not use. PP PBLEND_CONSTANT_COLOR: (d3d_blendfactor, uses corresponding RB_BLEND component) PhP6BLEND_ONE_MINUS_CONSTANT_COLOR: (d3d_invblendfactor) P(P)BLEND_SRC1_COLOR: DX10 dual-source mode HPP-BLEND_INV_SRC1_COLOR: DX10 dual-source mode PP)BLEND_SRC1_ALPHA: DX10 dual-source mode P@P-BLEND_INV_SRC1_ALPHA: DX10 dual-source mode hPP-BLEND_CONSTANT_ALPHA: (uses RB_BLEND_ALPHA) P#BLEND_ONE_MINUS_CONSTANT_ALPHA: PhP OPACITY_WEIGHT"PP`PALPHA_SRCBLENDPPBLEND_ZERO: (d3d_zero) PHPBLEND_ONE: (d3d_one) HPP!BLEND_SRC_COLOR: (d3d_srccolor) PP.BLEND_ONE_MINUS_SRC_COLOR: (d3d_invsrccolor) PHP!BLEND_SRC_ALPHA: (d3d_srcalpha) `PP.BLEND_ONE_MINUS_SRC_ALPHA: (d3d_invsrcalpha) PP"BLEND_DST_ALPHA: (d3d_destalpha) PPP/BLEND_ONE_MINUS_DST_ALPHA: (d3d_invdestalpha) hPP"BLEND_DST_COLOR: (d3d_destcolor) PP /BLEND_ONE_MINUS_DST_COLOR: (d3d_invdestcolor) PhP -BLEND_SRC_ALPHA_SATURATE: (d3d_srcalphasat) P P 0BLEND_BOTH_SRC_ALPHA: DEPRECATED. Do not use. HPP 4BLEND_BOTH_INV_SRC_ALPHA: DEPRECATED. Do not use. PP PBLEND_CONSTANT_COLOR: (d3d_blendfactor, uses corresponding RB_BLEND component) PhP6BLEND_ONE_MINUS_CONSTANT_COLOR: (d3d_invblendfactor) P(P)BLEND_SRC1_COLOR: DX10 dual-source mode HPP-BLEND_INV_SRC1_COLOR: DX10 dual-source mode PP)BLEND_SRC1_ALPHA: DX10 dual-source mode P@P-BLEND_INV_SRC1_ALPHA: DX10 dual-source mode hPP-BLEND_CONSTANT_ALPHA: (uses RB_BLEND_ALPHA) P#BLEND_ONE_MINUS_CONSTANT_ALPHA: hPhPPALPHA_COMB_FCNxPP;COMB_DST_PLUS_SRC: (ADD): Source*SRCBLEND + Dest*DSTBLEND @PPACOMB_SRC_MINUS_DST: (SUBTRACT): Source*SRCBLEND - Dest*DSTBLEND PP,COMB_MIN_DST_SRC: (MIN): min(Source, Dest) P8P,COMB_MAX_DST_SRC: (MAX): max(Source, Dest) PDCOMB_DST_MINUS_SRC: (REVSUBTRACT): Dest*DSTBLEND - Source*SRCBLEND PPPALPHA_DESTBLENDPXPBLEND_ZERO: (d3d_zero) PPPBLEND_ONE: (d3d_one) PP!BLEND_SRC_COLOR: (d3d_srccolor) P@P.BLEND_ONE_MINUS_SRC_COLOR: (d3d_invsrccolor) XPP!BLEND_SRC_ALPHA: (d3d_srcalpha) PP.BLEND_ONE_MINUS_SRC_ALPHA: (d3d_invsrcalpha) PXP"BLEND_DST_ALPHA: (d3d_destalpha) pPP/BLEND_ONE_MINUS_DST_ALPHA: (d3d_invdestalpha) PP"BLEND_DST_COLOR: (d3d_destcolor) P`P /BLEND_ONE_MINUS_DST_COLOR: (d3d_invdestcolor) PP -BLEND_SRC_ALPHA_SATURATE: (d3d_srcalphasat) @PP 0BLEND_BOTH_SRC_ALPHA: DEPRECATED. Do not use. PP 4BLEND_BOTH_INV_SRC_ALPHA: DEPRECATED. Do not use. P@P PBLEND_CONSTANT_COLOR: (d3d_blendfactor, uses corresponding RB_BLEND component) PP6BLEND_ONE_MINUS_CONSTANT_COLOR: (d3d_invblendfactor) @PP)BLEND_SRC1_COLOR: DX10 dual-source mode PP-BLEND_INV_SRC1_COLOR: DX10 dual-source mode P@P)BLEND_SRC1_ALPHA: DX10 dual-source mode `PP-BLEND_INV_SRC1_ALPHA: DX10 dual-source mode PP-BLEND_CONSTANT_ALPHA: (uses RB_BLEND_ALPHA) `P#BLEND_ONE_MINUS_CONSTANT_ALPHA: PSEPARATE_ALPHA_BLEND"P\P""\PCB_BLEND2_CONTROL0lP0]P]PCOLOR_SRCBLEND ^P]PBLEND_ZERO: (d3d_zero) ^Ph^PBLEND_ONE: (d3d_one) h_P_P!BLEND_SRC_COLOR: (d3d_srccolor) `P_P.BLEND_ONE_MINUS_SRC_COLOR: (d3d_invsrccolor) `Ph`P!BLEND_SRC_ALPHA: (d3d_srcalpha) aPaP.BLEND_ONE_MINUS_SRC_ALPHA: (d3d_invsrcalpha) (bPaP"BLEND_DST_ALPHA: (d3d_destalpha) bPpbP/BLEND_ONE_MINUS_DST_ALPHA: (d3d_invdestalpha) cP(cP"BLEND_DST_COLOR: (d3d_destcolor) @dPcP /BLEND_ONE_MINUS_DST_COLOR: (d3d_invdestcolor) dPdP -BLEND_SRC_ALPHA_SATURATE: (d3d_srcalphasat) eP@eP 0BLEND_BOTH_SRC_ALPHA: DEPRECATED. Do not use. hfPeP 4BLEND_BOTH_INV_SRC_ALPHA: DEPRECATED. Do not use. @gPfP PBLEND_CONSTANT_COLOR: (d3d_blendfactor, uses corresponding RB_BLEND component) hPgP6BLEND_ONE_MINUS_CONSTANT_COLOR: (d3d_invblendfactor) hPHhP)BLEND_SRC1_COLOR: DX10 dual-source mode hiPhP-BLEND_INV_SRC1_COLOR: DX10 dual-source mode jPiP)BLEND_SRC1_ALPHA: DX10 dual-source mode jP`jP-BLEND_INV_SRC1_ALPHA: DX10 dual-source mode kPkP-BLEND_CONSTANT_ALPHA: (uses RB_BLEND_ALPHA) kP#BLEND_ONE_MINUS_CONSTANT_ALPHA: pPlPlPCOLOR_COMB_FCNmP mP;COMB_DST_PLUS_SRC: (ADD): Source*SRCBLEND + Dest*DSTBLEND `nPmPACOMB_SRC_MINUS_DST: (SUBTRACT): Source*SRCBLEND - Dest*DSTBLEND oPnP,COMB_MIN_DST_SRC: (MIN): min(Source, Dest) oPXoP,COMB_MAX_DST_SRC: (MAX): max(Source, Dest) pPDCOMB_DST_MINUS_SRC: (REVSUBTRACT): Dest*DSTBLEND - Source*SRCBLEND PpP0qPCOLOR_DESTBLENDqPxqPBLEND_ZERO: (d3d_zero) prPrPBLEND_ONE: (d3d_one) sPrP!BLEND_SRC_COLOR: (d3d_srccolor) sP`sP.BLEND_ONE_MINUS_SRC_COLOR: (d3d_invsrccolor) xtPtP!BLEND_SRC_ALPHA: (d3d_srcalpha) 0uPtP.BLEND_ONE_MINUS_SRC_ALPHA: (d3d_invsrcalpha) uPxuP"BLEND_DST_ALPHA: (d3d_destalpha) vP vP/BLEND_ONE_MINUS_DST_ALPHA: (d3d_invdestalpha) 8wPvP"BLEND_DST_COLOR: (d3d_destcolor) wPwP /BLEND_ONE_MINUS_DST_COLOR: (d3d_invdestcolor) xP8xP -BLEND_SRC_ALPHA_SATURATE: (d3d_srcalphasat) `yPxP 0BLEND_BOTH_SRC_ALPHA: DEPRECATED. Do not use. zPyP 4BLEND_BOTH_INV_SRC_ALPHA: DEPRECATED. Do not use. zP`zP PBLEND_CONSTANT_COLOR: (d3d_blendfactor, uses corresponding RB_BLEND component) {P8{P6BLEND_ONE_MINUS_CONSTANT_COLOR: (d3d_invblendfactor) `|P{P)BLEND_SRC1_COLOR: DX10 dual-source mode }P|P-BLEND_INV_SRC1_COLOR: DX10 dual-source mode }P`}P)BLEND_SRC1_ALPHA: DX10 dual-source mode ~P~P-BLEND_INV_SRC1_ALPHA: DX10 dual-source mode 8P~P-BLEND_CONSTANT_ALPHA: (uses RB_BLEND_ALPHA) P#BLEND_ONE_MINUS_CONSTANT_ALPHA: P8P OPACITY_WEIGHT"PP0PALPHA_SRCBLENDЁPxPBLEND_ZERO: (d3d_zero) pPPBLEND_ONE: (d3d_one) PP!BLEND_SRC_COLOR: (d3d_srccolor) ЃP`P.BLEND_ONE_MINUS_SRC_COLOR: (d3d_invsrccolor) xPP!BLEND_SRC_ALPHA: (d3d_srcalpha) 0PP.BLEND_ONE_MINUS_SRC_ALPHA: (d3d_invsrcalpha) ؅PxP"BLEND_DST_ALPHA: (d3d_destalpha) P P/BLEND_ONE_MINUS_DST_ALPHA: (d3d_invdestalpha) 8P؆P"BLEND_DST_COLOR: (d3d_destcolor) PP /BLEND_ONE_MINUS_DST_COLOR: (d3d_invdestcolor) P8P -BLEND_SRC_ALPHA_SATURATE: (d3d_srcalphasat) `PP 0BLEND_BOTH_SRC_ALPHA: DEPRECATED. Do not use. PP 4BLEND_BOTH_INV_SRC_ALPHA: DEPRECATED. Do not use. P`P PBLEND_CONSTANT_COLOR: (d3d_blendfactor, uses corresponding RB_BLEND component) P8P6BLEND_ONE_MINUS_CONSTANT_COLOR: (d3d_invblendfactor) `PP)BLEND_SRC1_COLOR: DX10 dual-source mode PP-BLEND_INV_SRC1_COLOR: DX10 dual-source mode ȍP`P)BLEND_SRC1_ALPHA: DX10 dual-source mode PP-BLEND_INV_SRC1_ALPHA: DX10 dual-source mode 8PȎP-BLEND_CONSTANT_ALPHA: (uses RB_BLEND_ALPHA) P#BLEND_ONE_MINUS_CONSTANT_ALPHA: 8P8PPALPHA_COMB_FCNHPАP;COMB_DST_PLUS_SRC: (ADD): Source*SRCBLEND + Dest*DSTBLEND PPACOMB_SRC_MINUS_DST: (SUBTRACT): Source*SRCBLEND - Dest*DSTBLEND PXP,COMB_MIN_DST_SRC: (MIN): min(Source, Dest) pPP,COMB_MAX_DST_SRC: (MAX): max(Source, Dest) PDCOMB_DST_MINUS_SRC: (REVSUBTRACT): Dest*DSTBLEND - Source*SRCBLEND PPPALPHA_DESTBLENDP(PBLEND_ZERO: (d3d_zero) PȕPBLEND_ONE: (d3d_one) ȖPhP!BLEND_SRC_COLOR: (d3d_srccolor) PP.BLEND_ONE_MINUS_SRC_COLOR: (d3d_invsrccolor) (PȗP!BLEND_SRC_ALPHA: (d3d_srcalpha) PpP.BLEND_ONE_MINUS_SRC_ALPHA: (d3d_invsrcalpha) P(P"BLEND_DST_ALPHA: (d3d_destalpha) @PЙP/BLEND_ONE_MINUS_DST_ALPHA: (d3d_invdestalpha) PP"BLEND_DST_COLOR: (d3d_destcolor) P0P /BLEND_ONE_MINUS_DST_COLOR: (d3d_invdestcolor) XPP -BLEND_SRC_ALPHA_SATURATE: (d3d_srcalphasat) PP 0BLEND_BOTH_SRC_ALPHA: DEPRECATED. Do not use. ȝPXP 4BLEND_BOTH_INV_SRC_ALPHA: DEPRECATED. Do not use. PP PBLEND_CONSTANT_COLOR: (d3d_blendfactor, uses corresponding RB_BLEND component) `PP6BLEND_ONE_MINUS_CONSTANT_COLOR: (d3d_invblendfactor) PP)BLEND_SRC1_COLOR: DX10 dual-source mode ȠPXP-BLEND_INV_SRC1_COLOR: DX10 dual-source mode xPP)BLEND_SRC1_ALPHA: DX10 dual-source mode 0PP-BLEND_INV_SRC1_ALPHA: DX10 dual-source mode PxP-BLEND_CONSTANT_ALPHA: (uses RB_BLEND_ALPHA) 0P#BLEND_ONE_MINUS_CONSTANT_ALPHA: PSEPARATE_ALPHA_BLEND"8PP""PCB_BLEND1_CONTROL#PPHPCOLOR_SRCBLENDPPBLEND_ZERO: (d3d_zero) P0PBLEND_ONE: (d3d_one) 0PP!BLEND_SRC_COLOR: (d3d_srccolor) PxP.BLEND_ONE_MINUS_SRC_COLOR: (d3d_invsrccolor) P0P!BLEND_SRC_ALPHA: (d3d_srcalpha) HPP.BLEND_ONE_MINUS_SRC_ALPHA: (d3d_invsrcalpha) PP"BLEND_DST_ALPHA: (d3d_destalpha) P8P/BLEND_ONE_MINUS_DST_ALPHA: (d3d_invdestalpha) PPP"BLEND_DST_COLOR: (d3d_destcolor) PP /BLEND_ONE_MINUS_DST_COLOR: (d3d_invdestcolor) PPP -BLEND_SRC_ALPHA_SATURATE: (d3d_srcalphasat) xPP 0BLEND_BOTH_SRC_ALPHA: DEPRECATED. Do not use. 0PP 4BLEND_BOTH_INV_SRC_ALPHA: DEPRECATED. Do not use. PxP PBLEND_CONSTANT_COLOR: (d3d_blendfactor, uses corresponding RB_BLEND component) PPP6BLEND_ONE_MINUS_CONSTANT_COLOR: (d3d_invblendfactor) x P P)BLEND_SRC1_COLOR: DX10 dual-source mode 0!P P-BLEND_INV_SRC1_COLOR: DX10 dual-source mode !Px!P)BLEND_SRC1_ALPHA: DX10 dual-source mode "P("P-BLEND_INV_SRC1_ALPHA: DX10 dual-source mode P#P"P-BLEND_CONSTANT_ALPHA: (uses RB_BLEND_ALPHA) #P#BLEND_ONE_MINUS_CONSTANT_ALPHA: P(PP$P$PCOLOR_COMB_FCN`%P$P;COMB_DST_PLUS_SRC: (ADD): Source*SRCBLEND + Dest*DSTBLEND (&P%PACOMB_SRC_MINUS_DST: (SUBTRACT): Source*SRCBLEND - Dest*DSTBLEND &Pp&P,COMB_MIN_DST_SRC: (MIN): min(Source, Dest) 'P 'P,COMB_MAX_DST_SRC: (MAX): max(Source, Dest) 'PDCOMB_DST_MINUS_SRC: (REVSUBTRACT): Dest*DSTBLEND - Source*SRCBLEND 7P(P(PCOLOR_DESTBLEND)P@)PBLEND_ZERO: (d3d_zero) 8*P)PBLEND_ONE: (d3d_one) *P*P!BLEND_SRC_COLOR: (d3d_srccolor) +P(+P.BLEND_ONE_MINUS_SRC_COLOR: (d3d_invsrccolor) @,P+P!BLEND_SRC_ALPHA: (d3d_srcalpha) ,P,P.BLEND_ONE_MINUS_SRC_ALPHA: (d3d_invsrcalpha) -P@-P"BLEND_DST_ALPHA: (d3d_destalpha) X.P-P/BLEND_ONE_MINUS_DST_ALPHA: (d3d_invdestalpha) /P.P"BLEND_DST_COLOR: (d3d_destcolor) /PH/P /BLEND_ONE_MINUS_DST_COLOR: (d3d_invdestcolor) x0P0P -BLEND_SRC_ALPHA_SATURATE: (d3d_srcalphasat) 01P0P 0BLEND_BOTH_SRC_ALPHA: DEPRECATED. Do not use. 1Px1P 4BLEND_BOTH_INV_SRC_ALPHA: DEPRECATED. Do not use. 2P02P PBLEND_CONSTANT_COLOR: (d3d_blendfactor, uses corresponding RB_BLEND component) 3P3P6BLEND_ONE_MINUS_CONSTANT_COLOR: (d3d_invblendfactor) 04P3P)BLEND_SRC1_COLOR: DX10 dual-source mode 4Px4P-BLEND_INV_SRC1_COLOR: DX10 dual-source mode 5P05P)BLEND_SRC1_ALPHA: DX10 dual-source mode P6P5P-BLEND_INV_SRC1_ALPHA: DX10 dual-source mode 7P6P-BLEND_CONSTANT_ALPHA: (uses RB_BLEND_ALPHA) P7P#BLEND_ONE_MINUS_CONSTANT_ALPHA: X8P8P OPACITY_WEIGHT"GP8P9PALPHA_SRCBLEND9PH9PBLEND_ZERO: (d3d_zero) @:P9PBLEND_ONE: (d3d_one) :P:P!BLEND_SRC_COLOR: (d3d_srccolor) ;P0;P.BLEND_ONE_MINUS_SRC_COLOR: (d3d_invsrccolor) HP=P/BLEND_ONE_MINUS_DST_ALPHA: (d3d_invdestalpha) ?P>P"BLEND_DST_COLOR: (d3d_destcolor) ?PP?P /BLEND_ONE_MINUS_DST_COLOR: (d3d_invdestcolor) x@P@P -BLEND_SRC_ALPHA_SATURATE: (d3d_srcalphasat) 0AP@P 0BLEND_BOTH_SRC_ALPHA: DEPRECATED. Do not use. APxAP 4BLEND_BOTH_INV_SRC_ALPHA: DEPRECATED. Do not use. BP0BP PBLEND_CONSTANT_COLOR: (d3d_blendfactor, uses corresponding RB_BLEND component) CPCP6BLEND_ONE_MINUS_CONSTANT_COLOR: (d3d_invblendfactor) 0DPCP)BLEND_SRC1_COLOR: DX10 dual-source mode DPxDP-BLEND_INV_SRC1_COLOR: DX10 dual-source mode EP0EP)BLEND_SRC1_ALPHA: DX10 dual-source mode PFPEP-BLEND_INV_SRC1_ALPHA: DX10 dual-source mode GPFP-BLEND_CONSTANT_ALPHA: (uses RB_BLEND_ALPHA) PGP#BLEND_ONE_MINUS_CONSTANT_ALPHA: LPHPXHPALPHA_COMB_FCNIPHP;COMB_DST_PLUS_SRC: (ADD): Source*SRCBLEND + Dest*DSTBLEND IP`IPACOMB_SRC_MINUS_DST: (SUBTRACT): Source*SRCBLEND - Dest*DSTBLEND JP(JP,COMB_MIN_DST_SRC: (MIN): min(Source, Dest) @KPJP,COMB_MAX_DST_SRC: (MAX): max(Source, Dest) KPDCOMB_DST_MINUS_SRC: (REVSUBTRACT): Dest*DSTBLEND - Source*SRCBLEND `[P`LPLPALPHA_DESTBLENDPMPLPBLEND_ZERO: (d3d_zero) MPMPBLEND_ONE: (d3d_one) NP8NP!BLEND_SRC_COLOR: (d3d_srccolor) POPNP.BLEND_ONE_MINUS_SRC_COLOR: (d3d_invsrccolor) OPOP!BLEND_SRC_ALPHA: (d3d_srcalpha) PP@PP.BLEND_ONE_MINUS_SRC_ALPHA: (d3d_invsrcalpha) XQPPP"BLEND_DST_ALPHA: (d3d_destalpha) RPQP/BLEND_ONE_MINUS_DST_ALPHA: (d3d_invdestalpha) RPXRP"BLEND_DST_COLOR: (d3d_destcolor) pSPSP /BLEND_ONE_MINUS_DST_COLOR: (d3d_invdestcolor) (TPSP -BLEND_SRC_ALPHA_SATURATE: (d3d_srcalphasat) TPpTP 0BLEND_BOTH_SRC_ALPHA: DEPRECATED. Do not use. UP(UP 4BLEND_BOTH_INV_SRC_ALPHA: DEPRECATED. Do not use. pVPUP PBLEND_CONSTANT_COLOR: (d3d_blendfactor, uses corresponding RB_BLEND component) 0WPVP6BLEND_ONE_MINUS_CONSTANT_COLOR: (d3d_invblendfactor) WPxWP)BLEND_SRC1_COLOR: DX10 dual-source mode XP(XP-BLEND_INV_SRC1_COLOR: DX10 dual-source mode HYPXP)BLEND_SRC1_ALPHA: DX10 dual-source mode ZPYP-BLEND_INV_SRC1_ALPHA: DX10 dual-source mode ZPHZP-BLEND_CONSTANT_ALPHA: (uses RB_BLEND_ALPHA) [P#BLEND_ONE_MINUS_CONSTANT_ALPHA: [PSEPARATE_ALPHA_BLEND"x""CB_BLEND0_CONTROLXXCOLOR_SRCBLENDHBLEND_ZERO: (d3d_zero) BLEND_ONE: (d3d_one) 0!BLEND_SRC_COLOR: (d3d_srccolor) H.BLEND_ONE_MINUS_SRC_COLOR: (d3d_invsrccolor) !BLEND_SRC_ALPHA: (d3d_srcalpha) 8.BLEND_ONE_MINUS_SRC_ALPHA: (d3d_invsrcalpha) P"BLEND_DST_ALPHA: (d3d_destalpha) /BLEND_ONE_MINUS_DST_ALPHA: (d3d_invdestalpha) P"BLEND_DST_COLOR: (d3d_destcolor) h /BLEND_ONE_MINUS_DST_COLOR: (d3d_invdestcolor) -BLEND_SRC_ALPHA_SATURATE: (d3d_srcalphasat) h 0BLEND_BOTH_SRC_ALPHA: DEPRECATED. Do not use. 4BLEND_BOTH_INV_SRC_ALPHA: DEPRECATED. Do not use. h PBLEND_CONSTANT_COLOR: (d3d_blendfactor, uses corresponding RB_BLEND component) (6BLEND_ONE_MINUS_CONSTANT_COLOR: (d3d_invblendfactor) p)BLEND_SRC1_COLOR: DX10 dual-source mode -BLEND_INV_SRC1_COLOR: DX10 dual-source mode @)BLEND_SRC1_ALPHA: DX10 dual-source mode -BLEND_INV_SRC1_ALPHA: DX10 dual-source mode @-BLEND_CONSTANT_ALPHA: (uses RB_BLEND_ALPHA) #BLEND_ONE_MINUS_CONSTANT_ALPHA: COLOR_COMB_FCNH;COMB_DST_PLUS_SRC: (ADD): Source*SRCBLEND + Dest*DSTBLEND ACOMB_SRC_MINUS_DST: (SUBTRACT): Source*SRCBLEND - Dest*DSTBLEND 8,COMB_MIN_DST_SRC: (MIN): min(Source, Dest) ,COMB_MAX_DST_SRC: (MAX): max(Source, Dest) 0DCOMB_DST_MINUS_SRC: (REVSUBTRACT): Dest*DSTBLEND - Source*SRCBLEND XCOLOR_DESTBLENDBLEND_ZERO: (d3d_zero) @BLEND_ONE: (d3d_one) @!BLEND_SRC_COLOR: (d3d_srccolor) .BLEND_ONE_MINUS_SRC_COLOR: (d3d_invsrccolor) @!BLEND_SRC_ALPHA: (d3d_srcalpha) X.BLEND_ONE_MINUS_SRC_ALPHA: (d3d_invsrcalpha) "BLEND_DST_ALPHA: (d3d_destalpha) H/BLEND_ONE_MINUS_DST_ALPHA: (d3d_invdestalpha) `"BLEND_DST_COLOR: (d3d_destcolor)  /BLEND_ONE_MINUS_DST_COLOR: (d3d_invdestcolor) ` -BLEND_SRC_ALPHA_SATURATE: (d3d_srcalphasat)  0BLEND_BOTH_SRC_ALPHA: DEPRECATED. Do not use. @ 4BLEND_BOTH_INV_SRC_ALPHA: DEPRECATED. Do not use.  PBLEND_CONSTANT_COLOR: (d3d_blendfactor, uses corresponding RB_BLEND component) `6BLEND_ONE_MINUS_CONSTANT_COLOR: (d3d_invblendfactor) )BLEND_SRC1_COLOR: DX10 dual-source mode @-BLEND_INV_SRC1_COLOR: DX10 dual-source mode )BLEND_SRC1_ALPHA: DX10 dual-source mode 8-BLEND_INV_SRC1_ALPHA: DX10 dual-source mode `-BLEND_CONSTANT_ALPHA: (uses RB_BLEND_ALPHA) #BLEND_ONE_MINUS_CONSTANT_ALPHA: ` OPACITY_WEIGHT"XALPHA_SRCBLENDBLEND_ZERO: (d3d_zero) @BLEND_ONE: (d3d_one) @!BLEND_SRC_COLOR: (d3d_srccolor) .BLEND_ONE_MINUS_SRC_COLOR: (d3d_invsrccolor) @!BLEND_SRC_ALPHA: (d3d_srcalpha) X.BLEND_ONE_MINUS_SRC_ALPHA: (d3d_invsrcalpha) "BLEND_DST_ALPHA: (d3d_destalpha) H/BLEND_ONE_MINUS_DST_ALPHA: (d3d_invdestalpha) `"BLEND_DST_COLOR: (d3d_destcolor)  /BLEND_ONE_MINUS_DST_COLOR: (d3d_invdestcolor) ` -BLEND_SRC_ALPHA_SATURATE: (d3d_srcalphasat)  0BLEND_BOTH_SRC_ALPHA: DEPRECATED. Do not use. @ 4BLEND_BOTH_INV_SRC_ALPHA: DEPRECATED. Do not use.  PBLEND_CONSTANT_COLOR: (d3d_blendfactor, uses corresponding RB_BLEND component) `6BLEND_ONE_MINUS_CONSTANT_COLOR: (d3d_invblendfactor) )BLEND_SRC1_COLOR: DX10 dual-source mode @-BLEND_INV_SRC1_COLOR: DX10 dual-source mode )BLEND_SRC1_ALPHA: DX10 dual-source mode 8-BLEND_INV_SRC1_ALPHA: DX10 dual-source mode `-BLEND_CONSTANT_ALPHA: (uses RB_BLEND_ALPHA) #BLEND_ONE_MINUS_CONSTANT_ALPHA: P`ALPHA_COMB_FCNPhP;COMB_DST_PLUS_SRC: (ADD): Source*SRCBLEND + Dest*DSTBLEND P(PACOMB_SRC_MINUS_DST: (SUBTRACT): Source*SRCBLEND - Dest*DSTBLEND XPP,COMB_MIN_DST_SRC: (MIN): min(Source, Dest) PP,COMB_MAX_DST_SRC: (MAX): max(Source, Dest) PPDCOMB_DST_MINUS_SRC: (REVSUBTRACT): Dest*DSTBLEND - Source*SRCBLEND (P(PxPALPHA_DESTBLENDPPBLEND_ZERO: (d3d_zero) P`PBLEND_ONE: (d3d_one) `PP!BLEND_SRC_COLOR: (d3d_srccolor) PP.BLEND_ONE_MINUS_SRC_COLOR: (d3d_invsrccolor) P`P!BLEND_SRC_ALPHA: (d3d_srcalpha) xPP.BLEND_ONE_MINUS_SRC_ALPHA: (d3d_invsrcalpha) PP"BLEND_DST_ALPHA: (d3d_destalpha) Ph P/BLEND_ONE_MINUS_DST_ALPHA: (d3d_invdestalpha) P P"BLEND_DST_COLOR: (d3d_destcolor) 8 P P /BLEND_ONE_MINUS_DST_COLOR: (d3d_invdestcolor) P P -BLEND_SRC_ALPHA_SATURATE: (d3d_srcalphasat) P8 P 0BLEND_BOTH_SRC_ALPHA: DEPRECATED. Do not use. ` P P 4BLEND_BOTH_INV_SRC_ALPHA: DEPRECATED. Do not use. 8P P PBLEND_CONSTANT_COLOR: (d3d_blendfactor, uses corresponding RB_BLEND component) PP6BLEND_ONE_MINUS_CONSTANT_COLOR: (d3d_invblendfactor) P@P)BLEND_SRC1_COLOR: DX10 dual-source mode `PP-BLEND_INV_SRC1_COLOR: DX10 dual-source mode PP)BLEND_SRC1_ALPHA: DX10 dual-source mode PXP-BLEND_INV_SRC1_ALPHA: DX10 dual-source mode PP-BLEND_CONSTANT_ALPHA: (uses RB_BLEND_ALPHA) P#BLEND_ONE_MINUS_CONSTANT_ALPHA: PSEPARATE_ALPHA_BLEND"h""@CB_COLOR_CONTROL FOG_ENABLE"8MULTIWRITE_ENABLE"0DITHER_ENABLE"رDEGAMMA_ENABLE" 0x SPECIAL_OP(%SPECIAL_NORMAL: use state to render 0p}SPECIAL_DISABLE: Disables drawing to color buffer. Causes db to not send tiles/quads to cb. cb itself ignores this field. x.SPECIAL_FAST_CLEAR: DEPRECATED. Do not use. 0/SPECIAL_FORCE_CLEAR: DEPRECATED. Do not use. X0SPECIAL_EXPAND_COLOR: DEPRECATED. Do not use. 2SPECIAL_EXPAND_TEXTURE: DEPRECATED. Do not use. 8XSPECIAL_EXPAND_SAMPLES: expand MRT0 to a decompressed colour format. This is required before a multisampled surface is accessed by the CPU, or used as a texture. cSPECIAL_RESOLVE_BOX: read from MRT0, average all samples, and write to MRT1, which is one-sample. ȹxPER_MRT_BLEND"p TARGET_BLEND_ENABLE"ȺROP3X0x00: BLACKNESS 80x05 ȼ 0x0A X0x0F 0x11: NOTSRCERASE 8"0x22 Ⱦ30x33: NOTSRCCOPY `D0x44: SRCERASE @P0x50 U0x55: DSTINVERT p Z0x5A: PATINVERT _0x5F Hf0x66: SRCINVERT (w0x77 p0x88: SRCAND P0x99 0xA0 p(0xA5 0xAA H0xAF (0xBB: MERGEPAINT p0xCC: SRCCOPY P0xDD 0xEE: SRCPAINT 00xF0: PATCOPY 0xF5 X0xFA 0xFF: WHITENESS ""0CB_BLEND_CONTROLةCOLOR_SRCBLEND"0COLOR_COMB_FCN"(تCOLOR_DESTBLEND"Ы OPACITY_WEIGHT"x(ALPHA_SRCBLEND" ЬALPHA_COMB_FCN"ȭxALPHA_DESTBLEND" SEPARATE_ALPHA_BLEND"x,,""ȧCB_FOG_BLUE_R6XX FOG_BLUE"0((""`CB_FOG_GREEN_R6XX FOG_GREEN"Ȣ$$""CB_FOG_RED_R6XXP FOG_RED"`@  ""CB_BLEND_ALPHA BLEND_ALPHA"ء""(CB_BLEND_BLUE BLEND_BLUE"p""CB_BLEND_GREEN BLEND_GREEN"""X CB_BLEND_RED BLEND_RED"pp""DB_CGTT_CLK_CTRL_0 8 ON_DELAY"(ؗOFF_HYSTERESIS"Ș RESERVED"p SOFT_OVERRIDE7"șSOFT_OVERRIDE6"pSOFT_OVERRIDE5"hSOFT_OVERRIDE4"SOFT_OVERRIDE3"hSOFT_OVERRIDE2"`SOFT_OVERRIDE1"SOFT_OVERRIDE0"H(""xDB3_READ_DEBUG_FЕ DEBUG_DATA"""DB2_READ_DEBUG_Fh DEBUG_DATA"xX||""DB1_READ_DEBUG_F DEBUG_DATA"<<""@DB0_READ_DEBUG_F DEBUG_DATA"""؏DB3_READ_DEBUG_E0 DEBUG_DATA"@ ""pDB2_READ_DEBUG_EȎ DEBUG_DATA"؊xx""DB1_READ_DEBUG_E` DEBUG_DATA"pP88""DB0_READ_DEBUG_E DEBUG_DATA"""8DB3_READ_DEBUG_D DEBUG_DATA"""ЈDB2_READ_DEBUG_D( DEBUG_DATA"8tt""hDB1_READ_DEBUG_D DEBUG_DATA"Ѓ44""DB0_READ_DEBUG_DX DEBUG_DATA"hH""DB3_READ_DEBUG_C DEBUG_DATA"""0DB2_READ_DEBUG_C DEBUG_DATA"xpp""ȁDB1_READ_DEBUG_C DEBUG_DATA"0~00""`DB0_READ_DEBUG_C DEBUG_DATA"|~""~DB3_READ_DEBUG_BP DEBUG_DATA"`{@}""}DB2_READ_DEBUG_B} DEBUG_DATA"y{ll""(|DB1_READ_DEBUG_B| DEBUG_DATA"xpz,,""zDB0_READ_DEBUG_B{ DEBUG_DATA"(wy""XyDB3_READ_DEBUG_Ay DEBUG_DATA"uw""wDB2_READ_DEBUG_AHx DEBUG_DATA"Xt8vhh""vDB1_READ_DEBUG_Av DEBUG_DATA"rt(("" uDB0_READ_DEBUG_Axu DEBUG_DATA"qhs""sDB3_READ_DEBUG_9t DEBUG_DATA" pr""PrDB2_READ_DEBUG_9r DEBUG_DATA"npdd""pDB1_READ_DEBUG_9@q DEBUG_DATA"Pm0o$$""oDB0_READ_DEBUG_9o DEBUG_DATA"km""nDB3_READ_DEBUG_8pn DEBUG_DATA"j`l""lDB2_READ_DEBUG_8m DEBUG_DATA"ij``""HkDB1_READ_DEBUG_8k DEBUG_DATA"gi ""iDB0_READ_DEBUG_88j DEBUG_DATA"Hf(hܙܙ""xhDB3_READ_DEBUG_7h DEBUG_DATA"df""gDB2_READ_DEBUG_7hg DEBUG_DATA"xcXe\\""eDB1_READ_DEBUG_7f DEBUG_DATA"bc""@dDB0_READ_DEBUG_7d DEBUG_DATA"`bؙؙ""bDB3_READ_DEBUG_60c DEBUG_DATA"@_ a""paDB2_READ_DEBUG_6a DEBUG_DATA"]_XX""`DB1_READ_DEBUG_6`` DEBUG_DATA"p\P^""^DB0_READ_DEBUG_6^ DEBUG_DATA"[\ԙԙ""8]DB3_READ_DEBUG_5] DEBUG_DATA"Y[""[DB2_READ_DEBUG_5(\ DEBUG_DATA"8XZTT""hZDB1_READ_DEBUG_5Z DEBUG_DATA"VX""YDB0_READ_DEBUG_5XY DEBUG_DATA"hUHWЙЙ""WDB3_READ_DEBUG_4W DEBUG_DATA"TU""0VDB2_READ_DEBUG_4V DEBUG_DATA"RxTPP""TDB1_READ_DEBUG_4 U DEBUG_DATA"0QS""`SDB0_READ_DEBUG_4S DEBUG_DATA"OQ̙̙""QDB3_READ_DEBUG_3PR DEBUG_DATA"`N@P""PDB2_READ_DEBUG_3P DEBUG_DATA"LNLL""(ODB1_READ_DEBUG_3O DEBUG_DATA"KpM ""MDB0_READ_DEBUG_3N DEBUG_DATA"(JLșș""XLDB3_READ_DEBUG_2L BUSY_DATA2"HJ""JDB2_READ_DEBUG_2HK BUSY_DATA2"XG8IHH""IDB1_READ_DEBUG_2I BUSY_DATA2"EG"" HDB0_READ_DEBUG_2xH BUSY_DATA2"DhFęę""FDB3_READ_DEBUG_1G BUSY_DATA1" CE""PEDB2_READ_DEBUG_1E BUSY_DATA1"ACDD""CDB1_READ_DEBUG_1@D BUSY_DATA1"P@0B""BDB0_READ_DEBUG_1B BUSY_DATA1">@""ADB3_READ_DEBUG_0pA BUSY_DATA0"x=X?""?DB2_READ_DEBUG_0@ BUSY_DATA0"<=@@""@>DB1_READ_DEBUG_0> BUSY_DATA0":<""<DB0_READ_DEBUG_00= BUSY_DATA0"@9 ;""p;DB3_ZPASS_COUNT_HI; COUNT_HI"79"":DB3_ZPASS_COUNT_LOW`: COUNT_LOW"p6P8""8DB2_ZPASS_COUNT_HI8 COUNT_HI"56""87DB2_ZPASS_COUNT_LOW7 COUNT_LOW"35""5DB1_ZPASS_COUNT_HI(6 COUNT_HI"824||""h4DB1_ZPASS_COUNT_LOW4 COUNT_LOW"02xx""3DB0_ZPASS_COUNT_HIX3 COUNT_HI"&H1tt""1DB0_ZPASS_COUNT_LOW1 COUNT_LOW"hH'""' DB_DEBUG4 @('QC_DISABLE_WRITE_SLOT_CLEAR"((OPTIMIZE_FRONT_FACE_CULLING")H)"DONT_STALL_TS_EVENT_WHILE_TC_BUSY"`** DISABLE_OP_PIPE_Z_OVERWRITE_OPT"+*ALLOC_ALL_PLANES_ON_DECOMPRESS"+p+DISABLE_BUG8315_PSITER_FIX", ,!DISABLE_TILE_COVERED_FOR_PS_ITER"@-,&FORCE_FIRST_SUPERSAMPLE_WHEN_TF_EMPTY".-*ENABLE_HIZ_STALL_BETWEEN_SUPERSAMPLE_SETS".X.  ENABLE_6XX_TS_SUPPRESS_NEW_TILE"p// FORCE_FULL_WRITE_ON_FAST_Z_OP"(0/ DISABLE_PREZ_ZI_STALL_8945_FIX"0 DB_EXTRA_DEBUG4" ""( DB_DEBUG3DTR_ROUND_ROBIN_ARB"(DTR_PREZ_STALLS_FOR_ETF_ROOM"8REVERT_RR_PLANE_CL_SIZE"DISABLE_PREZL_LPF_STALL" @ ENABLE_PREZL_CB_STALL"H! DISABLE_PREZL_LPF_STALL_REZ"!!DISABLE_PREZL_CB_STALL_REZ""P" DISABLE_STENCIL_DST_VALID_CHECK"`##ALLOC_DTILE_FOR_NOOPS"$# FORCE_RR_PMASK_WMASK_HIGH"$h$ "FORCE_RR_PMASK_WMASK_HIGH_FOR_PMZ"p% % CLK_OFF_DELAY"(&%DISABLE_SUPERSAMPLE_FAST_Z_FIX"&DB_EXTRA_DEBUG3" <<""` DB_DEBUG2 'DISABLE_ESR_POSTZ_SQL_WAIT_FOR_SX_QUAD" x &ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS" 8 "DISABLE_VPORT_ZPLANE_OPTIMIZATION"H ENABLE_SURFACE_ON_NEVER" ALLOW_RF2P_RW_COLLISION"P#DISABLE_2_TO_1_STENCIL_COMPRESSION"`DECOMPRESS_AFTER_N_ZPLANES" USE_ORIGINAL_PZW_SKIP_CODE"h "DISABLE_PZW_UP_WAITS_FOR_SKIP_CMD" FORCE_SUPERSAMPLE_POINTER_READ"8REZ_MUST_WAIT_FOR_POSTZ_DONE"USE_ORIGINAL_QC_FULL"@QC_SKEW_LIMIT"@DISABLE_DROP_FREES_ON_FLUSH"ONE_FREE_IN_FLIGHT"@FORCE_RR_PC_MASK"@FORCE_MISS_IF_NOT_INFLIGHT"DISABLE_DEPTH_SURFACE_SYNC"HDISABLE_HTILE_SURFACE_SYNC"PALLOW_COMPZ_BYTE_MASKING"TILE_OPS_DONT_USE_LIT_QTILE_XY"` RETRO_FG_GA"XDISABLE_DEFERED_SLOT_DONE"DISABLE_FAST_OP_CLEAN_UP"`DISABLE_TC_ZRANGE_L0_CACHE"DISABLE_TC_MASK_L0_CACHE"`88""DB_WATERMARKS P DEPTH_FREE" DEPTH_FLUSH"H FORCE_SUMMARIZE"@DEPTH_PENDING_FREE"DEPTH_CACHELINE_FREE"HEARLY_Z_PANIC_DISABLE"PLATE_Z_PANIC_DISABLE"RE_Z_PANIC_DISABLE"P DB_EXTRA_DEBUG"pP""DB_FREE_CACHELINESHFREE_DTILE_DEPTH"FREE_PLANE_DEPTH"H  FREE_Z_DEPTH"@FREE_HTILE_DEPTH"QUAD_READ_REQS"h""8DB_FIFO_DEPTH2EQUAD_FIFO_DEPTH"8ETILE_OP_FIFO_DEPTH"0 LQUAD_FIFO_DEPTH"LTILE_OP_FIFO_DEPTH"X""0DB_FIFO_DEPTH1MI_RDREQ_FIFO_DEPTH"0MI_WRREQ_FIFO_DEPTH"  MCC_DEPTH"x QC_DEPTH"LTILE_PROBE_FIFO_DEPTH"`44"" DB_CREDIT_LIMITxDB_SC_TILE_CREDITS"p DB_SC_QUAD_CREDITS" DB_CB_EQUAD_CREDITS"pDB_CB_LQUAD_CREDITS"DB_CB_TILE_CREDITS"00"" DB_DEBUGxDEBUG_STENCIL_COMPRESS_DISABLE"0DEBUG_DEPTH_COMPRESS_DISABLE"8FETCH_FULL_Z_TILE"FETCH_FULL_STENCIL_TILE"@DEPTH_QUAD_DISABLE"@READ_RETURN_STALL_DISABLE"8 FORCE_Z_MODEx0 NO_FORCEFORCE_EARLY_ZX FORCE_LATE_Z FORCE_RE_ZDEBUG_FORCE_DEPTH_READ"@ DEBUG_FORCE_DEPTH_WRITE"H DEBUG_FORCE_STENCIL_READ" DEBUG_FORCE_STENCIL_WRITE"P DEBUG_FORCE_HIZ_ENABLE8 FORCE_OFF FORCE_ENABLEhFORCE_DISABLEFORCE_RESERVEDXDEBUG_FORCE_HIS_ENABLE0@ FORCE_OFF FORCE_ENABLEp FORCE_DISABLEFORCE_RESERVED`DEBUG_FORCE_HIS_ENABLE1H FORCE_OFF FORCE_ENABLEx(FORCE_DISABLEFORCE_RESERVEDhDEBUG_FAST_Z_DISABLE"pDEBUG_FAST_STENCIL_DISABLE" DEBUG_NOOP_CULL_DISABLE"xDISABLE_SUMM_SQUADS"x DEPTH_CACHE_FORCE_MISS"(DEBUG_FORCE_FULL_Z_RANGEp FORCE_OFFP FORCE_ENABLEFORCE_DISABLE0FORCE_RESERVED(NEVER_FREE_Z_ONLY"FORCE_FG_SERIALIZE"(ENABLE_MIXED_PREZ_POSTZ_OPS"8!DISABLE_FL_WRITE_COHERENCY_CHECK"DISABLE_ESR_SKIP_COLLAPSE"@DISABLE_MIXED_PREZ_POSTZ_OPS"PREZ_MUST_WAIT_FOR_POSTZ_DONE"p""DB3_PERFCOUNTER3_HI PERF_COUNT"(""XDB3_PERFCOUNTER2_HI PERF_COUNT"ԘԘ""DB3_PERFCOUNTER1_HIH PERF_COUNT"P8ȘȘ""DB3_PERFCOUNTER0_HI PERF_COUNT""" DB3_PERFCOUNTER3_LOWx PERF_COUNT"pXܘܘ""DB3_PERFCOUNTER2_LOW PERF_COUNT"ИИ""@DB3_PERFCOUNTER1_LOW PERF_COUNT"0%xĘĘ""DB3_PERFCOUNTER0_LOW( PERF_COUNT"X%""&DB3_PERFCOUNTER3_SELECTX&& PERF_SELX'&4PERF_SC_DB_tile_sends: Cycles Interface is sending ('0PERF_SC_DB_tile_busy: Cycles Interface is busy (X(5PERF_SC_DB_tile_stalls: Cycles Interface is stalled ))4PERF_SC_DB_tile_events: Events sent over interface @*)2PERF_SC_DB_tile_tiles: Tiles sent over interface **.PERF_SC_DB_tile_covered: Fully covered tiles +@+IPERF_hiz_tc_read_starved: HiZ starved waiting for htile data from cache ,,=PERF_hiz_tc_write_stall: HiZ stalled writing to htile cache P-,5PERF_hiz_qtiles_culled: Quarter tiles culled by hiZ .- 5PERF_his_qtiles_culled: Quarter tiles culled by HiS .X. 4PERF_DB_SC_tile_sends: Cycles Interface is sending // 0PERF_DB_SC_tile_busy: Cycles Interface is busy @0/ ;PERF_DB_SC_tile_stalls: Cycles Interface is stalled by SC 10 QPERF_DB_SC_tile_df_stalls: Cycles Interface is stalled by detail walk tile fifo 1`12PERF_DB_SC_tile_tiles: Tiles sent over interface 22/PERF_DB_SC_tile_culled: Tiles culled in total X32IPERF_DB_SC_tile_hier_kill: Tiles culled due to a hierarchical fail test 043SPERF_DB_SC_tile_fast_ops: Tiles culled because they were accerated fast tile ops. 5x4IPERF_DB_SC_tile_no_ops: Tiles culled because they would not do anything 5H5TPERF_DB_SC_tile_pixel_rate: Tiles run at pixel rate as opposed to sample rate tile 6 6qPERF_DB_SC_tile_ssaa_kill: Tiles culled because they were supersample tiles that are merged into a fast tile op 77tPERF_DB_SC_tile_fast_z_ops: Tiles that operate on Z in 1 clock. Can be inside a slow, pixel rate, or fast tile op 88PERF_DB_SC_tile_fast_stencil_ops: Tiles that operate on stencil in 1 clock. Can be inside a slow, pixel rate, or fast tile op 994PERF_SC_DB_quad_sends: Cycles Interface is sending @:90PERF_SC_DB_quad_busy: Cycles Interface is busy ;:;PERF_SC_DB_quad_squads: Squads transferred over interface ;H;2PERF_SC_DB_quad_tiles: Tiles sent over interface x<<:PERF_SC_DB_quad_pixels: Pixels transfered over interface @=<=PERF_SC_DB_quad_killed_tiles: Number of detail killed tiles ==4PERF_DB_SC_quad_sends: Cycles Interface is sending >@>0PERF_DB_SC_quad_busy: Cycles Interface is busy p?>5PERF_DB_SC_quad_stalls: Cycles Interface is stalled (@? 4PERF_DB_SC_quad_squads: Squads sent over interface @p@!2PERF_DB_SC_quad_tiles: Tiles sent over interface A(A"HPERF_DB_SC_quad_quads: Quads transferred over the DB_SC_quad interface BA#nPERF_DB_CB_tile_sends: Cycles sending tiles/events to CB. Tiles not shaded or needed by the CB are not sent. HCB$PERF_DB_CB_tile_busy: CC%PERF_DB_CB_tile_stalls: D0D&4PERF_SX_DB_quad_sends: Cycles Interface is sending XED'0PERF_SX_DB_quad_busy: Cycles Interface is busy FE(5PERF_SX_DB_quad_stalls: Cycles Interface is stalled F`F)2PERF_SX_DB_quad_quads: Quads sent over interface GG*4PERF_SX_DB_quad_pixels: Pixels sent over interface PHG+APERF_SX_DB_quad_exports: Each MRT of a quad sent over interface 8IH,bPERF_SH_quads_outstanding_sum: Multiple by 128 and divide by DB_SC_quad_quads to get PS latency. II-5PERF_DB_CB_lquad_sends: Cycles Interface is sending J@J.1PERF_DB_CB_lquad_busy: Cycles Interface is busy pKJ/6PERF_DB_CB_lquad_stalls: Cycles Interface is stalled (LK03PERF_DB_CB_lquad_quads: Quads sent over interface LpL1/PERF_tile_rd_sends: HTile reads. Each is 256B M(M2hPERF_mi_tile_rd_outstanding_sum: Multiply by 2 and divide by tile_rd_sends to get htile memory latency NN3:PERF_quad_rd_sends: Quad read reqs. Each is 32B to 256B `ON4JPERF_quad_rd_busy: Cycles quad read interface is trying to send requests @PO5VPERF_quad_rd_mi_stall: Cycles quad read interface is stalled by the memory interface QP6XPERF_quad_rd_rw_collision: Cycles a quad read is stalled waiting for a write to finish RhQ7ePERF_quad_rd_tag_stall: Cycles a quad read is stalled because the read latency hiding fifo is full. RXR8@PERF_quad_rd_32byte_reqs: Number of 32 Byte quad read requests S S9>PERF_quad_rd_panic: Cycles DB is panicing for quad read data TS:vPERF_mi_quad_rd_outstanding_sum: Multiply by 16 and divide by quad_rd_32byte_reqs to get depth buffer memory latency `UT;<PERF_quad_rdret_sends: Number of 32 byte quad read returns (VU<>PERF_quad_rdret_busy: Cycles the quad read data is returning VpV=*PERF_tile_wr_sends: 32 Byte HTile writes W W>-PERF_tile_wr_acks: 32 Byte Htile write acks XW?nPERF_mi_tile_wr_outstanding_sum: Multiply by 16 and divide by tile_wr_sends to get tile write memory latency pYX@cPERF_quad_wr_sends: Cycles quad is sending write requests to the memory interface block of the DB @ZYAKPERF_quad_wr_busy: Cycles quad is trying to write to the memory interface [ZBUPERF_quad_wr_mi_stall: Cycles quad is stalled while writing to the memory interface \h[CwPERF_quad_wr_coherency_stall: Cycles quad write is stalled waiting for a previous write to finish on the same address \h\D6PERF_quad_wr_acks: Number of 32 Byte quad write acks ](]ErPERF_mi_quad_wr_outstanding_sum: Multiply by 16 and divide by the quad_wr_sends to get quad memory write latency ^ ^F,PERF_Tile_Cache_misses: Htile Cache misses 8_^G(PERF_Tile_Cache_hits: Htile Cache hits __H.PERF_Tile_Cache_flushes: Htile Cache flushes `8`I[PERF_Tile_Cache_surface_stall: Tile stalls waiting for an htile surface to flush and free aaJMPERF_Tile_Cache_starves: Tile stalls waiting for an htile cacheline to free baK[PERF_Tile_Cache_mem_return_starve: Tile stalls waiting for an htile memory read to return hcbLYPERF_tcp_dispatcher_reads: Number of htile cachelines fetched by the normal tile stream @dcMQPERF_tcp_prefetcher_reads: Number of htile cachelines fetched by the prefetcher edNOPERF_tcp_preloader_reads: Number of htile cachelines fetched by the preloader e`eOXPERF_tcp_dispatcher_flushes: Number of htile flushes caused byt the normal tile stream f@fPWPERF_tcp_prefetcher_flushes: Number of htile flushes caused byt the normal prefetcher g gQUPERF_tcp_preloader_flushes: Number of htile flushes caused byt the normal preloader hhRHPERF_Depth_Tile_Cache_sends: Tiles/Events through the Depth Tile Cache pihSbPERF_Depth_Tile_Cache_busy: Cycles the Depth Tile Cache is busy testing hit/miss on tiles/events XjiT_PERF_Depth_Tile_Cache_starves: Cycles starved waiting for a depth surface tile tag to free up HkjUgPERF_Depth_Tile_Cache_dtile_locked: Cycles stalled waiting for a forced flush or invalidate to finish lkVTPERF_Depth_Tile_Cache_alloc_stall: Cycles depth tile stalled while allocating data lhlW?PERF_Depth_Tile_Cache_misses: Depth/Stencil Cache tile misses m0mX;PERF_Depth_Tile_Cache_hits: Depth/Stencil Cache tile hits pnmYAPERF_Depth_Tile_Cache_flushes: Depth/Stencil Cache tile flushes @onZJPERF_Depth_Tile_Cache_noop_tile: Noop tiles through the depth tile cache po[VPERF_Depth_Tile_Cache_detailed_noop: Detail walked noops though the depth tile cache php\%PERF_Depth_Tile_Cache_event: Events qq]4PERF_Depth_Tile_Cache_tile_frees: Depth tile frees prq^cPERF_Depth_Tile_Cache_data_frees: Depth tile data frees (may free data without freeing the dtile) `sr_ePERF_Depth_Tile_Cache_mem_return_starve: Cycles depth/stencil cache is waiting for memory to return ts`/PERF_Stencil_Cache_misses: 512 bit allocation t`taPERF_Stencil_Cache_hits: uubpPERF_Stencil_Cache_flushes: 256 bit flushes. Two per cacheline unless it is compressed, in which case it is 1. vucmPERF_Stencil_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate HwvdPERF_Stencil_Cache_frees: wwe"PERF_Z_Cache_separate_Z_misses: x8xf PERF_Z_Cache_separate_Z_hits: @yxg#PERF_Z_Cache_separate_Z_flushes: 8zyhrPERF_Z_Cache_separate_Z_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate zziPERF_Z_Cache_pmask_misses: {({jPERF_Z_Cache_pmask_hits: (|{kPERF_Z_Cache_pmask_flushes: }p|lmPERF_Z_Cache_pmask_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate }h}mPERF_Z_Cache_frees: `~~nPERF_Plane_Cache_misses: ~oPERF_Plane_Cache_hits: HpPERF_Plane_Cache_flushes: qkPERF_Plane_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate 0؀rPERF_Plane_Cache_frees: xsGPERF_flush_expanded_stencil: Tiles flushed with with expanded stencil ЂHtKPERF_flush_compressed_stencil: Tiles flushed with with compressed stencil uCPERF_flush_single_stencil: Tiles flushed with with single stencil Pv0PERF_flush_1plane: Tiles flushed with 1 ZPlane w1PERF_flush_2plane: Tiles flushed with 2 ZPlanes Px1PERF_flush_3plane: Tiles flushed with 3 ZPlanes xy1PERF_flush_4plane: Tiles flushed with 4 ZPlanes 0z1PERF_flush_5plane: Tiles flushed with 5 ZPlanes x{1PERF_flush_6plane: Tiles flushed with 6 ZPlanes 0|1PERF_flush_7plane: Tiles flushed with 7 ZPlanes X}1PERF_flush_8plane: Tiles flushed with 8 ZPlanes ~1PERF_flush_9plane: Tiles flushed with 9 ZPlanes ȊX3PERF_flush_10plane: Tiles flushed with 10 ZPlanes 3PERF_flush_11plane: Tiles flushed with 11 ZPlanes 8ȋ3PERF_flush_12plane: Tiles flushed with 12 ZPlanes 3PERF_flush_13plane: Tiles flushed with 13 ZPlanes 83PERF_flush_14plane: Tiles flushed with 14 ZPlanes `3PERF_flush_15plane: Tiles flushed with 15 ZPlanes 3PERF_flush_16plane: Tiles flushed with 16 ZPlanes ؏`6PERF_flush_expanded_z: Tiles flushed with expanded Z `PERF_earlyZ_waiting_for_postZ_done: Cycles stalled while transitioning from Late/ReZ to EarlyZ rPERF_reZ_waiting_for_postZ_done: Cycles stalled while transitioning to ReZ from an incompatible Z mode/func/etc. @PERF_dk_tile_sends: Detail kill block tiles/squads/events sent 8Ȓ2PERF_dk_tile_busy: Cycles Detail Kill block busy ZPERF_dk_tile_quad_starves: Cycles Detail Kill has tile, but no quads from the SC_DB_quad `?PERF_dk_tile_stalls: Cycles Detail Kill is stalled from below ()PERF_dk_squad_sends: Detail Kill squads Xؕ@PERF_dk_squad_busy: Cycles the squad Detail Kill input is busy =PERF_dk_squad_stalls: Cycles squads are stalled from below. hrPERF_Op_Pipe_Busy: Cycles the quad OP pipe of the DB is busy (including memory fetches, but not initial startup) `kPERF_Op_Pipe_MC_Read_stall: Cycles the Op Pipe is waiting for memory to return (ignoring initial startup) P1PERF_qc_busy: Cycles the Quad Coherency is busy CPERF_qc_xfc: Number of transfers through the Quad Coherency block КPERF_qc_conflicts: Stalls on a squad input because of a coherency check conflict (the same sample ahead of it could affect the dest data) hKPERF_qc_full_stall: Quad Coherency is stalled because it is out of slots. PERF_qc_in_preZ_tile_stalls_postZ: Cycles postZ squad inputs are stalled because the OP pipe is operating on a preZ tile, and there is no PreZ squad input available ȞPERF_qc_in_postZ_tile_stalls_preZ: Cycles preZ squad inputs are stalled because the OP pipe is operating on a postZ tile, and there is no PostZ squad input available rPERF_tsc_insert_summarize_stall: Cycles the op pipe is stalled by the tile summarizer inserting summarize squads x-PERF_tl_busy: Cycles Tile Lookup block busy 04PERF_tl_dtc_read_starved: Cycles Tile Lookup block xIPERF_tl_z_fetch_stall: Cycles Tile Lookup block stalled by zfetch block آHOPERF_tl_stencil_stall: Cycles Tile Lookup block stalled by stencil test block TPERF_tl_z_decompress_stall: Cycles Tile Lookup block stalled by z decompress block XPERF_tl_stencil_locked_stall: Cycles Tile Lookup block stalled by stencil being locked Pؤ;PERF_tl_events: Cycles Tile Lookup block sends out events (OPERF_tl_summarize_squads: Cycles Tile Lookup block sends out summarize squads pUPERF_tl_flush_expand_squads: Cycles Tile Lookup block sends out flush expand squads اPIPERF_tl_expand_squads: Cycles Tile Lookup block sends out expand squads EPERF_tl_preZ_squads: Cycles Tile Lookup block sends out preZ squads xGPERF_tl_postZ_squads: Cycles Tile Lookup block sends out postZ squads XUPERF_tl_preZ_noop_squads: Cycles Tile Lookup block sends out noops on the preZ path 8WPERF_tl_postZ_noop_squads: Cycles Tile Lookup block sends out noops on the postZ path NPERF_tl_getZ_squads: Cycles Tile Lookup block sends out z import pass squads XEPERF_tl_tile_ops: Cycles Tile Lookup block sends out tile op squads (=PERF_tl_in_xfc: Cycles Tile Lookup block receives any input nPERF_tl_in_single_stencil_expand_stall: Cycles Tile Lookup block is stalling due to expanding single stencil ePERF_tl_in_constant_stencil_walk_stall: Cycles Tile Lookup block is stalling due to walking stencil `دLPERF_tl_in_fast_z_stall: Cycles Tile Lookup block is stalling due to fastZ (CPERF_tl_out_xfc: Cycles Tile Lookup block is sending anything out pDPERF_tl_out_squads: Cycles Tile Lookup block is sending squads out 8PERF_zf_plane_multicycle: Cycles the z fetch is multicycling a squad because it needs to fetch more than 2 planes from the cache for compressed Z سPJPERF_PostZ_Samples_passing_Z: Samples passing Z test during a PostZ pass JPERF_PostZ_Samples_failing_Z: Samples failing Z test during a PostZ pass PPERF_PostZ_Samples_failing_S: Samples failing Stencil test during a PostZ pass PȵHPERF_PreZ_Samples_passing_Z: Samples passing Z test during a PreZ pass HPERF_PreZ_Samples_failing_Z: Samples failing Z test during a PreZ pass hNPERF_PreZ_Samples_failing_S: Samples failing Stencil test during a PreZ pass ظ@ZPERF_ts_tc_update_stall: Cycles Tile Summarizer to Tile Cache write interface is stalled >PERF_sc_kick_start: Times the DB sent a hang panic to the SC `7PERF_sc_kick_end: Times the DB completed a hang panic (>PERF_SX_DB_mem_exports: Number of memory exports from the SX pPPERF_SX_DB_mem_exports_acked: Number of memory export writes acked from the MC ؼHPPERF_SX_DB_ack_mem_exports: Number of ack requested memory exports from the SX SPERF_SX_DB_ack_mem_exports_acked: Number of memory export acks returned to the SX p5PERF_mem_export_busy: Cycles writing memory exports hsPERF_mem_export_mi_stall: Cycles mem exports are stalled waiting for other DB writes or MC write bus arbitration. PdPERF_mem_export_tag_stall: Cycles mem exports are stalled waiting for a free mem export write tag. <PERF_clock_reg_active: Cycles register part of DB is awake X9PERF_clock_main_active: Cycles core part of DB is awake EPERF_clock_mem_export_active: Cycles mem export part of DB is awake `7PERF_esr_out_busy: Early Squad Router Out cycles busy ;PERF_esr_out_sc_stall: Early Squad Router Out to SC stall hZPERF_esr_out_lquad_fifo_full_stall: Early Squad Router Out to Late Quad Fifo full stalls H0PERF_etr_out_send: Early Tile Router Out sends x6PERF_etr_out_busy: Early Tile Router Out cycles busy hePERF_etr_out_ltile_probe_fifo_full_stall: Early Tile Router Out to Late Tile Probe Fifo full stalls 0APERF_etr_out_cb_tile_stall: Early Tile Router to CB tile stalls xIPERF_etr_out_esr_stall: Early Tile Router to Early Squad Router stalls. xݿЁؘؘ""(DB3_PERFCOUNTER2_SELECTȂ PERF_SEL4PERF_SC_DB_tile_sends: Cycles Interface is sending 8ȃ0PERF_SC_DB_tile_busy: Cycles Interface is busy 5PERF_SC_DB_tile_stalls: Cycles Interface is stalled @4PERF_SC_DB_tile_events: Events sent over interface h2PERF_SC_DB_tile_tiles: Tiles sent over interface .PERF_SC_DB_tile_covered: Fully covered tiles hIPERF_hiz_tc_read_starved: HiZ starved waiting for htile data from cache 8=PERF_hiz_tc_write_stall: HiZ stalled writing to htile cache x5PERF_hiz_qtiles_culled: Quarter tiles culled by hiZ 8 5PERF_his_qtiles_culled: Quarter tiles culled by HiS 4PERF_DB_SC_tile_sends: Cycles Interface is sending 8 0PERF_DB_SC_tile_busy: Cycles Interface is busy h ;PERF_DB_SC_tile_stalls: Cycles Interface is stalled by SC @ QPERF_DB_SC_tile_df_stalls: Cycles Interface is stalled by detail walk tile fifo 2PERF_DB_SC_tile_tiles: Tiles sent over interface @/PERF_DB_SC_tile_culled: Tiles culled in total IPERF_DB_SC_tile_hier_kill: Tiles culled due to a hierarchical fail test XȏSPERF_DB_SC_tile_fast_ops: Tiles culled because they were accerated fast tile ops. (IPERF_DB_SC_tile_no_ops: Tiles culled because they would not do anything pTPERF_DB_SC_tile_pixel_rate: Tiles run at pixel rate as opposed to sample rate tile HqPERF_DB_SC_tile_ssaa_kill: Tiles culled because they were supersample tiles that are merged into a fast tile op @tPERF_DB_SC_tile_fast_z_ops: Tiles that operate on Z in 1 clock. Can be inside a slow, pixel rate, or fast tile op 8PERF_DB_SC_tile_fast_stencil_ops: Tiles that operate on stencil in 1 clock. Can be inside a slow, pixel rate, or fast tile op @4PERF_SC_DB_quad_sends: Cycles Interface is sending h0PERF_SC_DB_quad_busy: Cycles Interface is busy (;PERF_SC_DB_quad_squads: Squads transferred over interface p2PERF_SC_DB_quad_tiles: Tiles sent over interface (:PERF_SC_DB_quad_pixels: Pixels transfered over interface h=PERF_SC_DB_quad_killed_tiles: Number of detail killed tiles 4PERF_DB_SC_quad_sends: Cycles Interface is sending ؚh0PERF_DB_SC_quad_busy: Cycles Interface is busy 5PERF_DB_SC_quad_stalls: Cycles Interface is stalled P 4PERF_DB_SC_quad_squads: Squads sent over interface !2PERF_DB_SC_quad_tiles: Tiles sent over interface ؝P"HPERF_DB_SC_quad_quads: Quads transferred over the DB_SC_quad interface О #nPERF_DB_CB_tile_sends: Cycles sending tiles/events to CB. Tiles not shaded or needed by the CB are not sent. p$PERF_DB_CB_tile_busy: %PERF_DB_CB_tile_stalls: ȠX&4PERF_SX_DB_quad_sends: Cycles Interface is sending '0PERF_SX_DB_quad_busy: Cycles Interface is busy @ȡ(5PERF_SX_DB_quad_stalls: Cycles Interface is stalled )2PERF_SX_DB_quad_quads: Quads sent over interface @*4PERF_SX_DB_quad_pixels: Pixels sent over interface x+APERF_SX_DB_quad_exports: Each MRT of a quad sent over interface `,bPERF_SH_quads_outstanding_sum: Multiple by 128 and divide by DB_SC_quad_quads to get PS latency. -5PERF_DB_CB_lquad_sends: Cycles Interface is sending ئh.1PERF_DB_CB_lquad_busy: Cycles Interface is busy /6PERF_DB_CB_lquad_stalls: Cycles Interface is stalled P03PERF_DB_CB_lquad_quads: Quads sent over interface 1/PERF_tile_rd_sends: HTile reads. Each is 256B P2hPERF_mi_tile_rd_outstanding_sum: Multiply by 2 and divide by tile_rd_sends to get htile memory latency @3:PERF_quad_rd_sends: Quad read reqs. Each is 32B to 256B 4JPERF_quad_rd_busy: Cycles quad read interface is trying to send requests hЫ5VPERF_quad_rd_mi_stall: Cycles quad read interface is stalled by the memory interface H6XPERF_quad_rd_rw_collision: Cycles a quad read is stalled waiting for a write to finish 87ePERF_quad_rd_tag_stall: Cycles a quad read is stalled because the read latency hiding fifo is full. 8@PERF_quad_rd_32byte_reqs: Number of 32 Byte quad read requests ȯH9>PERF_quad_rd_panic: Cycles DB is panicing for quad read data Ȱ:vPERF_mi_quad_rd_outstanding_sum: Multiply by 16 and divide by quad_rd_32byte_reqs to get depth buffer memory latency ;<PERF_quad_rdret_sends: Number of 32 byte quad read returns Pб<>PERF_quad_rdret_busy: Cycles the quad read data is returning =*PERF_tile_wr_sends: 32 Byte HTile writes H>-PERF_tile_wr_acks: 32 Byte Htile write acks ?nPERF_mi_tile_wr_outstanding_sum: Multiply by 16 and divide by tile_wr_sends to get tile write memory latency @cPERF_quad_wr_sends: Cycles quad is sending write requests to the memory interface block of the DB hAKPERF_quad_wr_busy: Cycles quad is trying to write to the memory interface HBUPERF_quad_wr_mi_stall: Cycles quad is stalled while writing to the memory interface HCwPERF_quad_wr_coherency_stall: Cycles quad write is stalled waiting for a previous write to finish on the same address D6PERF_quad_wr_acks: Number of 32 Byte quad write acks PErPERF_mi_quad_wr_outstanding_sum: Multiply by 16 and divide by the quad_wr_sends to get quad memory write latency HF,PERF_Tile_Cache_misses: Htile Cache misses `G(PERF_Tile_Cache_hits: Htile Cache hits H.PERF_Tile_Cache_flushes: Htile Cache flushes `I[PERF_Tile_Cache_surface_stall: Tile stalls waiting for an htile surface to flush and free н@JMPERF_Tile_Cache_starves: Tile stalls waiting for an htile cacheline to free K[PERF_Tile_Cache_mem_return_starve: Tile stalls waiting for an htile memory read to return LYPERF_tcp_dispatcher_reads: Number of htile cachelines fetched by the normal tile stream hؿMQPERF_tcp_prefetcher_reads: Number of htile cachelines fetched by the prefetcher @NOPERF_tcp_preloader_reads: Number of htile cachelines fetched by the preloader OXPERF_tcp_dispatcher_flushes: Number of htile flushes caused byt the normal tile stream hPWPERF_tcp_prefetcher_flushes: Number of htile flushes caused byt the normal prefetcher HQUPERF_tcp_preloader_flushes: Number of htile flushes caused byt the normal preloader (RHPERF_Depth_Tile_Cache_sends: Tiles/Events through the Depth Tile Cache SbPERF_Depth_Tile_Cache_busy: Cycles the Depth Tile Cache is busy testing hit/miss on tiles/events T_PERF_Depth_Tile_Cache_starves: Cycles starved waiting for a depth surface tile tag to free up pUgPERF_Depth_Tile_Cache_dtile_locked: Cycles stalled waiting for a forced flush or invalidate to finish HVTPERF_Depth_Tile_Cache_alloc_stall: Cycles depth tile stalled while allocating data W?PERF_Depth_Tile_Cache_misses: Depth/Stencil Cache tile misses XX;PERF_Depth_Tile_Cache_hits: Depth/Stencil Cache tile hits YAPERF_Depth_Tile_Cache_flushes: Depth/Stencil Cache tile flushes hZJPERF_Depth_Tile_Cache_noop_tile: Noop tiles through the depth tile cache H[VPERF_Depth_Tile_Cache_detailed_noop: Detail walked noops though the depth tile cache \%PERF_Depth_Tile_Cache_event: Events @]4PERF_Depth_Tile_Cache_tile_frees: Depth tile frees ^cPERF_Depth_Tile_Cache_data_frees: Depth tile data frees (may free data without freeing the dtile) _ePERF_Depth_Tile_Cache_mem_return_starve: Cycles depth/stencil cache is waiting for memory to return @`/PERF_Stencil_Cache_misses: 512 bit allocation aPERF_Stencil_Cache_hits: (bpPERF_Stencil_Cache_flushes: 256 bit flushes. Two per cacheline unless it is compressed, in which case it is 1. cmPERF_Stencil_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate pdPERF_Stencil_Cache_frees: e"PERF_Z_Cache_separate_Z_misses: `f PERF_Z_Cache_separate_Z_hits: hg#PERF_Z_Cache_separate_Z_flushes: `hrPERF_Z_Cache_separate_Z_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate iPERF_Z_Cache_pmask_misses: PjPERF_Z_Cache_pmask_hits: PkPERF_Z_Cache_pmask_flushes: HlmPERF_Z_Cache_pmask_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate mPERF_Z_Cache_frees: 0nPERF_Plane_Cache_misses: (oPERF_Plane_Cache_hits: ppPERF_Plane_Cache_flushes: qkPERF_Plane_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate XrPERF_Plane_Cache_frees: (sGPERF_flush_expanded_stencil: Tiles flushed with with expanded stencil ptKPERF_flush_compressed_stencil: Tiles flushed with with compressed stencil @uCPERF_flush_single_stencil: Tiles flushed with with single stencil xv0PERF_flush_1plane: Tiles flushed with 1 ZPlane 0w1PERF_flush_2plane: Tiles flushed with 2 ZPlanes xx1PERF_flush_3plane: Tiles flushed with 3 ZPlanes 0y1PERF_flush_4plane: Tiles flushed with 4 ZPlanes Xz1PERF_flush_5plane: Tiles flushed with 5 ZPlanes {1PERF_flush_6plane: Tiles flushed with 6 ZPlanes X|1PERF_flush_7plane: Tiles flushed with 7 ZPlanes }1PERF_flush_8plane: Tiles flushed with 8 ZPlanes 8~1PERF_flush_9plane: Tiles flushed with 9 ZPlanes 3PERF_flush_10plane: Tiles flushed with 10 ZPlanes 83PERF_flush_11plane: Tiles flushed with 11 ZPlanes `3PERF_flush_12plane: Tiles flushed with 12 ZPlanes 3PERF_flush_13plane: Tiles flushed with 13 ZPlanes `3PERF_flush_14plane: Tiles flushed with 14 ZPlanes 3PERF_flush_15plane: Tiles flushed with 15 ZPlanes @3PERF_flush_16plane: Tiles flushed with 16 ZPlanes 6PERF_flush_expanded_z: Tiles flushed with expanded Z H`PERF_earlyZ_waiting_for_postZ_done: Cycles stalled while transitioning from Late/ReZ to EarlyZ 0rPERF_reZ_waiting_for_postZ_done: Cycles stalled while transitioning to ReZ from an incompatible Z mode/func/etc. (@PERF_dk_tile_sends: Detail kill block tiles/squads/events sent `2PERF_dk_tile_busy: Cycles Detail Kill block busy @ZPERF_dk_tile_quad_starves: Cycles Detail Kill has tile, but no quads from the SC_DB_quad ?PERF_dk_tile_stalls: Cycles Detail Kill is stalled from below P)PERF_dk_squad_sends: Detail Kill squads @PERF_dk_squad_busy: Cycles the squad Detail Kill input is busy H=PERF_dk_squad_stalls: Cycles squads are stalled from below. @rPERF_Op_Pipe_Busy: Cycles the quad OP pipe of the DB is busy (including memory fetches, but not initial startup) 0kPERF_Op_Pipe_MC_Read_stall: Cycles the Op Pipe is waiting for memory to return (ignoring initial startup) x1PERF_qc_busy: Cycles the Quad Coherency is busy 0CPERF_qc_xfc: Number of transfers through the Quad Coherency block PERF_qc_conflicts: Stalls on a squad input because of a coherency check conflict (the same sample ahead of it could affect the dest data) KPERF_qc_full_stall: Quad Coherency is stalled because it is out of slots. PERF_qc_in_preZ_tile_stalls_postZ: Cycles postZ squad inputs are stalled because the OP pipe is operating on a preZ tile, and there is no PreZ squad input available PERF_qc_in_postZ_tile_stalls_preZ: Cycles preZ squad inputs are stalled because the OP pipe is operating on a postZ tile, and there is no PostZ squad input available 8rPERF_tsc_insert_summarize_stall: Cycles the op pipe is stalled by the tile summarizer inserting summarize squads 0-PERF_tl_busy: Cycles Tile Lookup block busy X4PERF_tl_dtc_read_starved: Cycles Tile Lookup block (IPERF_tl_z_fetch_stall: Cycles Tile Lookup block stalled by zfetch block pOPERF_tl_stencil_stall: Cycles Tile Lookup block stalled by stencil test block HTPERF_tl_z_decompress_stall: Cycles Tile Lookup block stalled by z decompress block XPERF_tl_stencil_locked_stall: Cycles Tile Lookup block stalled by stencil being locked x;PERF_tl_events: Cycles Tile Lookup block sends out events POPERF_tl_summarize_squads: Cycles Tile Lookup block sends out summarize squads 0UPERF_tl_flush_expand_squads: Cycles Tile Lookup block sends out flush expand squads xIPERF_tl_expand_squads: Cycles Tile Lookup block sends out expand squads HEPERF_tl_preZ_squads: Cycles Tile Lookup block sends out preZ squads GPERF_tl_postZ_squads: Cycles Tile Lookup block sends out postZ squads UPERF_tl_preZ_noop_squads: Cycles Tile Lookup block sends out noops on the preZ path `WPERF_tl_postZ_noop_squads: Cycles Tile Lookup block sends out noops on the postZ path 8NPERF_tl_getZ_squads: Cycles Tile Lookup block sends out z import pass squads  EPERF_tl_tile_ops: Cycles Tile Lookup block sends out tile op squads P =PERF_tl_in_xfc: Cycles Tile Lookup block receives any input  nPERF_tl_in_single_stencil_expand_stall: Cycles Tile Lookup block is stalling due to expanding single stencil  ePERF_tl_in_constant_stencil_walk_stall: Cycles Tile Lookup block is stalling due to walking stencil LPERF_tl_in_fast_z_stall: Cycles Tile Lookup block is stalling due to fastZ P CPERF_tl_out_xfc: Cycles Tile Lookup block is sending anything out  DPERF_tl_out_squads: Cycles Tile Lookup block is sending squads out 0`PERF_zf_plane_multicycle: Cycles the z fetch is multicycling a squad because it needs to fetch more than 2 planes from the cache for compressed Z xJPERF_PostZ_Samples_passing_Z: Samples passing Z test during a PostZ pass PJPERF_PostZ_Samples_failing_Z: Samples failing Z test during a PostZ pass  PPERF_PostZ_Samples_failing_S: Samples failing Stencil test during a PostZ pass HPERF_PreZ_Samples_passing_Z: Samples passing Z test during a PreZ pass PHPERF_PreZ_Samples_failing_Z: Samples failing Z test during a PreZ pass (NPERF_PreZ_Samples_failing_S: Samples failing Stencil test during a PreZ pass pZPERF_ts_tc_update_stall: Cycles Tile Summarizer to Tile Cache write interface is stalled P>PERF_sc_kick_start: Times the DB sent a hang panic to the SC 7PERF_sc_kick_end: Times the DB completed a hang panic X>PERF_SX_DB_mem_exports: Number of memory exports from the SX 0PPERF_SX_DB_mem_exports_acked: Number of memory export writes acked from the MC xPPERF_SX_DB_ack_mem_exports: Number of ack requested memory exports from the SX PSPERF_SX_DB_ack_mem_exports_acked: Number of memory export acks returned to the SX (5PERF_mem_export_busy: Cycles writing memory exports sPERF_mem_export_mi_stall: Cycles mem exports are stalled waiting for other DB writes or MC write bus arbitration. dPERF_mem_export_tag_stall: Cycles mem exports are stalled waiting for a free mem export write tag. @<PERF_clock_reg_active: Cycles register part of DB is awake 9PERF_clock_main_active: Cycles core part of DB is awake HEPERF_clock_mem_export_active: Cycles mem export part of DB is awake 7PERF_esr_out_busy: Early Squad Router Out cycles busy P ;PERF_esr_out_sc_stall: Early Squad Router Out to SC stall 0! ZPERF_esr_out_lquad_fifo_full_stall: Early Squad Router Out to Late Quad Fifo full stalls !x!0PERF_etr_out_send: Early Tile Router Out sends "0"6PERF_etr_out_busy: Early Tile Router Out cycles busy #"ePERF_etr_out_ltile_probe_fifo_full_stall: Early Tile Router Out to Late Tile Probe Fifo full stalls `$#APERF_etr_out_cb_tile_stall: Early Tile Router to CB tile stalls $IPERF_etr_out_esr_stall: Early Tile Router to Early Squad Router stalls. 9ݿ̘̘""H޿DB3_PERFCOUNTER1_SELECT޿޿ PERF_SEL߿0߿4PERF_SC_DB_tile_sends: Cycles Interface is sending X߿0PERF_SC_DB_tile_busy: Cycles Interface is busy 5PERF_SC_DB_tile_stalls: Cycles Interface is stalled `4PERF_SC_DB_tile_events: Events sent over interface 2PERF_SC_DB_tile_tiles: Tiles sent over interface @.PERF_SC_DB_tile_covered: Fully covered tiles IPERF_hiz_tc_read_starved: HiZ starved waiting for htile data from cache X=PERF_hiz_tc_write_stall: HiZ stalled writing to htile cache 5PERF_hiz_qtiles_culled: Quarter tiles culled by hiZ X 5PERF_his_qtiles_culled: Quarter tiles culled by HiS  4PERF_DB_SC_tile_sends: Cycles Interface is sending X 0PERF_DB_SC_tile_busy: Cycles Interface is busy  ;PERF_DB_SC_tile_stalls: Cycles Interface is stalled by SC ` QPERF_DB_SC_tile_df_stalls: Cycles Interface is stalled by detail walk tile fifo 2PERF_DB_SC_tile_tiles: Tiles sent over interface `/PERF_DB_SC_tile_culled: Tiles culled in total IPERF_DB_SC_tile_hier_kill: Tiles culled due to a hierarchical fail test xSPERF_DB_SC_tile_fast_ops: Tiles culled because they were accerated fast tile ops. HIPERF_DB_SC_tile_no_ops: Tiles culled because they would not do anything TPERF_DB_SC_tile_pixel_rate: Tiles run at pixel rate as opposed to sample rate tile hqPERF_DB_SC_tile_ssaa_kill: Tiles culled because they were supersample tiles that are merged into a fast tile op `tPERF_DB_SC_tile_fast_z_ops: Tiles that operate on Z in 1 clock. Can be inside a slow, pixel rate, or fast tile op XPERF_DB_SC_tile_fast_stencil_ops: Tiles that operate on stencil in 1 clock. Can be inside a slow, pixel rate, or fast tile op `4PERF_SC_DB_quad_sends: Cycles Interface is sending 0PERF_SC_DB_quad_busy: Cycles Interface is busy H;PERF_SC_DB_quad_squads: Squads transferred over interface 2PERF_SC_DB_quad_tiles: Tiles sent over interface H:PERF_SC_DB_quad_pixels: Pixels transfered over interface =PERF_SC_DB_quad_killed_tiles: Number of detail killed tiles @4PERF_DB_SC_quad_sends: Cycles Interface is sending 0PERF_DB_SC_quad_busy: Cycles Interface is busy @5PERF_DB_SC_quad_stalls: Cycles Interface is stalled p 4PERF_DB_SC_quad_squads: Squads sent over interface (!2PERF_DB_SC_quad_tiles: Tiles sent over interface p"HPERF_DB_SC_quad_quads: Quads transferred over the DB_SC_quad interface @#nPERF_DB_CB_tile_sends: Cycles sending tiles/events to CB. Tiles not shaded or needed by the CB are not sent. 8$PERF_DB_CB_tile_busy: 0%PERF_DB_CB_tile_stalls: x&4PERF_SX_DB_quad_sends: Cycles Interface is sending 0'0PERF_SX_DB_quad_busy: Cycles Interface is busy `(5PERF_SX_DB_quad_stalls: Cycles Interface is stalled )2PERF_SX_DB_quad_quads: Quads sent over interface `*4PERF_SX_DB_quad_pixels: Pixels sent over interface +APERF_SX_DB_quad_exports: Each MRT of a quad sent over interface ,bPERF_SH_quads_outstanding_sum: Multiple by 128 and divide by DB_SC_quad_quads to get PS latency. @-5PERF_DB_CB_lquad_sends: Cycles Interface is sending .1PERF_DB_CB_lquad_busy: Cycles Interface is busy @/6PERF_DB_CB_lquad_stalls: Cycles Interface is stalled p03PERF_DB_CB_lquad_quads: Quads sent over interface (1/PERF_tile_rd_sends: HTile reads. Each is 256B p2hPERF_mi_tile_rd_outstanding_sum: Multiply by 2 and divide by tile_rd_sends to get htile memory latency `3:PERF_quad_rd_sends: Quad read reqs. Each is 32B to 256B  4JPERF_quad_rd_busy: Cycles quad read interface is trying to send requests 5VPERF_quad_rd_mi_stall: Cycles quad read interface is stalled by the memory interface h 6XPERF_quad_rd_rw_collision: Cycles a quad read is stalled waiting for a write to finish X 7ePERF_quad_rd_tag_stall: Cycles a quad read is stalled because the read latency hiding fifo is full. 8@PERF_quad_rd_32byte_reqs: Number of 32 Byte quad read requests h 9>PERF_quad_rd_panic: Cycles DB is panicing for quad read data 0 :vPERF_mi_quad_rd_outstanding_sum: Multiply by 16 and divide by quad_rd_32byte_reqs to get depth buffer memory latency 0 ;<PERF_quad_rdret_sends: Number of 32 byte quad read returns p <>PERF_quad_rdret_busy: Cycles the quad read data is returning =*PERF_tile_wr_sends: 32 Byte HTile writes h>-PERF_tile_wr_acks: 32 Byte Htile write acks  ?nPERF_mi_tile_wr_outstanding_sum: Multiply by 16 and divide by tile_wr_sends to get tile write memory latency @cPERF_quad_wr_sends: Cycles quad is sending write requests to the memory interface block of the DB AKPERF_quad_wr_busy: Cycles quad is trying to write to the memory interface hBUPERF_quad_wr_mi_stall: Cycles quad is stalled while writing to the memory interface hCwPERF_quad_wr_coherency_stall: Cycles quad write is stalled waiting for a previous write to finish on the same address (D6PERF_quad_wr_acks: Number of 32 Byte quad write acks pErPERF_mi_quad_wr_outstanding_sum: Multiply by 16 and divide by the quad_wr_sends to get quad memory write latency hF,PERF_Tile_Cache_misses: Htile Cache misses G(PERF_Tile_Cache_hits: Htile Cache hits 8H.PERF_Tile_Cache_flushes: Htile Cache flushes I[PERF_Tile_Cache_surface_stall: Tile stalls waiting for an htile surface to flush and free `JMPERF_Tile_Cache_starves: Tile stalls waiting for an htile cacheline to free 8K[PERF_Tile_Cache_mem_return_starve: Tile stalls waiting for an htile memory read to return LYPERF_tcp_dispatcher_reads: Number of htile cachelines fetched by the normal tile stream MQPERF_tcp_prefetcher_reads: Number of htile cachelines fetched by the prefetcher `NOPERF_tcp_preloader_reads: Number of htile cachelines fetched by the preloader @OXPERF_tcp_dispatcher_flushes: Number of htile flushes caused byt the normal tile stream PWPERF_tcp_prefetcher_flushes: Number of htile flushes caused byt the normal prefetcher  hQUPERF_tcp_preloader_flushes: Number of htile flushes caused byt the normal preloader P RHPERF_Depth_Tile_Cache_sends: Tiles/Events through the Depth Tile Cache ! !SbPERF_Depth_Tile_Cache_busy: Cycles the Depth Tile Cache is busy testing hit/miss on tiles/events ""T_PERF_Depth_Tile_Cache_starves: Cycles starved waiting for a depth surface tile tag to free up #"UgPERF_Depth_Tile_Cache_dtile_locked: Cycles stalled waiting for a forced flush or invalidate to finish p$#VTPERF_Depth_Tile_Cache_alloc_stall: Cycles depth tile stalled while allocating data 8%$W?PERF_Depth_Tile_Cache_misses: Depth/Stencil Cache tile misses %%X;PERF_Depth_Tile_Cache_hits: Depth/Stencil Cache tile hits &@&YAPERF_Depth_Tile_Cache_flushes: Depth/Stencil Cache tile flushes ''ZJPERF_Depth_Tile_Cache_noop_tile: Noop tiles through the depth tile cache p('[VPERF_Depth_Tile_Cache_detailed_noop: Detail walked noops though the depth tile cache )(\%PERF_Depth_Tile_Cache_event: Events )h)]4PERF_Depth_Tile_Cache_tile_frees: Depth tile frees * *^cPERF_Depth_Tile_Cache_data_frees: Depth tile data frees (may free data without freeing the dtile) ++_ePERF_Depth_Tile_Cache_mem_return_starve: Cycles depth/stencil cache is waiting for memory to return h,+`/PERF_Stencil_Cache_misses: 512 bit allocation -,aPERF_Stencil_Cache_hits: .P-bpPERF_Stencil_Cache_flushes: 256 bit flushes. Two per cacheline unless it is compressed, in which case it is 1. .H.cmPERF_Stencil_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate /@/dPERF_Stencil_Cache_frees: @0/e"PERF_Z_Cache_separate_Z_misses: 00f PERF_Z_Cache_separate_Z_hits: 101g#PERF_Z_Cache_separate_Z_flushes: 21hrPERF_Z_Cache_separate_Z_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate 032iPERF_Z_Cache_pmask_misses: 3x3jPERF_Z_Cache_pmask_hits: x44kPERF_Z_Cache_pmask_flushes: p54lmPERF_Z_Cache_pmask_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate 65mPERF_Z_Cache_frees: 6X6nPERF_Plane_Cache_misses: P76oPERF_Plane_Cache_hits: 77pPERF_Plane_Cache_flushes: 888qkPERF_Plane_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate 9(9rPERF_Plane_Cache_frees: P:9sGPERF_flush_expanded_stencil: Tiles flushed with with expanded stencil ;:tKPERF_flush_compressed_stencil: Tiles flushed with with compressed stencil ;h;uCPERF_flush_single_stencil: Tiles flushed with with single stencil <0<v0PERF_flush_1plane: Tiles flushed with 1 ZPlane X=<w1PERF_flush_2plane: Tiles flushed with 2 ZPlanes >=x1PERF_flush_3plane: Tiles flushed with 3 ZPlanes >X>y1PERF_flush_4plane: Tiles flushed with 4 ZPlanes ??z1PERF_flush_5plane: Tiles flushed with 5 ZPlanes 8@?{1PERF_flush_6plane: Tiles flushed with 6 ZPlanes @@|1PERF_flush_7plane: Tiles flushed with 7 ZPlanes A8A}1PERF_flush_8plane: Tiles flushed with 8 ZPlanes `BA~1PERF_flush_9plane: Tiles flushed with 9 ZPlanes CB3PERF_flush_10plane: Tiles flushed with 10 ZPlanes C`C3PERF_flush_11plane: Tiles flushed with 11 ZPlanes DD3PERF_flush_12plane: Tiles flushed with 12 ZPlanes @ED3PERF_flush_13plane: Tiles flushed with 13 ZPlanes EE3PERF_flush_14plane: Tiles flushed with 14 ZPlanes F@F3PERF_flush_15plane: Tiles flushed with 15 ZPlanes hGF3PERF_flush_16plane: Tiles flushed with 16 ZPlanes (HG6PERF_flush_expanded_z: Tiles flushed with expanded Z IpH`PERF_earlyZ_waiting_for_postZ_done: Cycles stalled while transitioning from Late/ReZ to EarlyZ JXIrPERF_reZ_waiting_for_postZ_done: Cycles stalled while transitioning to ReZ from an incompatible Z mode/func/etc. JPJ@PERF_dk_tile_sends: Detail kill block tiles/squads/events sent KK2PERF_dk_tile_busy: Cycles Detail Kill block busy hLKZPERF_dk_tile_quad_starves: Cycles Detail Kill has tile, but no quads from the SC_DB_quad 0ML?PERF_dk_tile_stalls: Cycles Detail Kill is stalled from below MxM)PERF_dk_squad_sends: Detail Kill squads N(N@PERF_dk_squad_busy: Cycles the squad Detail Kill input is busy pON=PERF_dk_squad_stalls: Cycles squads are stalled from below. hPOrPERF_Op_Pipe_Busy: Cycles the quad OP pipe of the DB is busy (including memory fetches, but not initial startup) XQPkPERF_Op_Pipe_MC_Read_stall: Cycles the Op Pipe is waiting for memory to return (ignoring initial startup) RQ1PERF_qc_busy: Cycles the Quad Coherency is busy RXRCPERF_qc_xfc: Number of transfers through the Quad Coherency block S SPERF_qc_conflicts: Stalls on a squad input because of a coherency check conflict (the same sample ahead of it could affect the dest data) T0TKPERF_qc_full_stall: Quad Coherency is stalled because it is out of slots. UUPERF_qc_in_preZ_tile_stalls_postZ: Cycles postZ squad inputs are stalled because the OP pipe is operating on a preZ tile, and there is no PreZ squad input available W0VPERF_qc_in_postZ_tile_stalls_preZ: Cycles preZ squad inputs are stalled because the OP pipe is operating on a postZ tile, and there is no PostZ squad input available X`WrPERF_tsc_insert_summarize_stall: Cycles the op pipe is stalled by the tile summarizer inserting summarize squads XXX-PERF_tl_busy: Cycles Tile Lookup block busy YY4PERF_tl_dtc_read_starved: Cycles Tile Lookup block PZYIPERF_tl_z_fetch_stall: Cycles Tile Lookup block stalled by zfetch block ([ZOPERF_tl_stencil_stall: Cycles Tile Lookup block stalled by stencil test block \p[TPERF_tl_z_decompress_stall: Cycles Tile Lookup block stalled by z decompress block \H\XPERF_tl_stencil_locked_stall: Cycles Tile Lookup block stalled by stencil being locked ](];PERF_tl_events: Cycles Tile Lookup block sends out events x^]OPERF_tl_summarize_squads: Cycles Tile Lookup block sends out summarize squads X_^UPERF_tl_flush_expand_squads: Cycles Tile Lookup block sends out flush expand squads (`_IPERF_tl_expand_squads: Cycles Tile Lookup block sends out expand squads `p`EPERF_tl_preZ_squads: Cycles Tile Lookup block sends out preZ squads a@aGPERF_tl_postZ_squads: Cycles Tile Lookup block sends out postZ squads bbUPERF_tl_preZ_noop_squads: Cycles Tile Lookup block sends out noops on the preZ path cbWPERF_tl_postZ_noop_squads: Cycles Tile Lookup block sends out noops on the postZ path `dcNPERF_tl_getZ_squads: Cycles Tile Lookup block sends out z import pass squads 0edEPERF_tl_tile_ops: Cycles Tile Lookup block sends out tile op squads exe=PERF_tl_in_xfc: Cycles Tile Lookup block receives any input f@fnPERF_tl_in_single_stencil_expand_stall: Cycles Tile Lookup block is stalling due to expanding single stencil g8gePERF_tl_in_constant_stencil_walk_stall: Cycles Tile Lookup block is stalling due to walking stencil h(hLPERF_tl_in_fast_z_stall: Cycles Tile Lookup block is stalling due to fastZ xihCPERF_tl_out_xfc: Cycles Tile Lookup block is sending anything out @jiDPERF_tl_out_squads: Cycles Tile Lookup block is sending squads out XkjPERF_zf_plane_multicycle: Cycles the z fetch is multicycling a squad because it needs to fetch more than 2 planes from the cache for compressed Z (lkJPERF_PostZ_Samples_passing_Z: Samples passing Z test during a PostZ pass lplJPERF_PostZ_Samples_failing_Z: Samples failing Z test during a PostZ pass m@mPPERF_PostZ_Samples_failing_S: Samples failing Stencil test during a PostZ pass nnHPERF_PreZ_Samples_passing_Z: Samples passing Z test during a PreZ pass ponHPERF_PreZ_Samples_failing_Z: Samples failing Z test during a PreZ pass HpoNPERF_PreZ_Samples_failing_S: Samples failing Stencil test during a PreZ pass (qpZPERF_ts_tc_update_stall: Cycles Tile Summarizer to Tile Cache write interface is stalled qpq>PERF_sc_kick_start: Times the DB sent a hang panic to the SC r8r7PERF_sc_kick_end: Times the DB completed a hang panic xsr>PERF_SX_DB_mem_exports: Number of memory exports from the SX PtsPPERF_SX_DB_mem_exports_acked: Number of memory export writes acked from the MC (utPPERF_SX_DB_ack_mem_exports: Number of ack requested memory exports from the SX vpuSPERF_SX_DB_ack_mem_exports_acked: Number of memory export acks returned to the SX vHv5PERF_mem_export_busy: Cycles writing memory exports wwsPERF_mem_export_mi_stall: Cycles mem exports are stalled waiting for other DB writes or MC write bus arbitration. xxdPERF_mem_export_tag_stall: Cycles mem exports are stalled waiting for a free mem export write tag. `yx<PERF_clock_reg_active: Cycles register part of DB is awake zy9PERF_clock_main_active: Cycles core part of DB is awake zhzEPERF_clock_mem_export_active: Cycles mem export part of DB is awake {8{7PERF_esr_out_busy: Early Squad Router Out cycles busy p|{;PERF_esr_out_sc_stall: Early Squad Router Out to SC stall P}|ZPERF_esr_out_lquad_fifo_full_stall: Early Squad Router Out to Late Quad Fifo full stalls ~}0PERF_etr_out_send: Early Tile Router Out sends ~P~6PERF_etr_out_busy: Early Tile Router Out cycles busy ePERF_etr_out_ltile_probe_fifo_full_stall: Early Tile Router Out to Late Tile Probe Fifo full stalls APERF_etr_out_cb_tile_stall: Early Tile Router to CB tile stalls ЀIPERF_etr_out_esr_stall: Early Tile Router to Early Squad Router stalls. 88:""p:DB3_PERFCOUNTER0_SELECT:; PERF_SEL;X;4PERF_SC_DB_tile_sends: Cycles Interface is sending <<0PERF_SC_DB_tile_busy: Cycles Interface is busy @=<5PERF_SC_DB_tile_stalls: Cycles Interface is stalled ==4PERF_SC_DB_tile_events: Events sent over interface >@>2PERF_SC_DB_tile_tiles: Tiles sent over interface h?>.PERF_SC_DB_tile_covered: Fully covered tiles 8@?IPERF_hiz_tc_read_starved: HiZ starved waiting for htile data from cache A@=PERF_hiz_tc_write_stall: HiZ stalled writing to htile cache AHA5PERF_hiz_qtiles_culled: Quarter tiles culled by hiZ BB 5PERF_his_qtiles_culled: Quarter tiles culled by HiS 8CB 4PERF_DB_SC_tile_sends: Cycles Interface is sending CC 0PERF_DB_SC_tile_busy: Cycles Interface is busy D8D ;PERF_DB_SC_tile_stalls: Cycles Interface is stalled by SC ED QPERF_DB_SC_tile_df_stalls: Cycles Interface is stalled by detail walk tile fifo @FE2PERF_DB_SC_tile_tiles: Tiles sent over interface FF/PERF_DB_SC_tile_culled: Tiles culled in total G@GIPERF_DB_SC_tile_hier_kill: Tiles culled due to a hierarchical fail test HHSPERF_DB_SC_tile_fast_ops: Tiles culled because they were accerated fast tile ops. pIHIPERF_DB_SC_tile_no_ops: Tiles culled because they would not do anything HJITPERF_DB_SC_tile_pixel_rate: Tiles run at pixel rate as opposed to sample rate tile @KJqPERF_DB_SC_tile_ssaa_kill: Tiles culled because they were supersample tiles that are merged into a fast tile op 8LKtPERF_DB_SC_tile_fast_z_ops: Tiles that operate on Z in 1 clock. Can be inside a slow, pixel rate, or fast tile op @MLPERF_DB_SC_tile_fast_stencil_ops: Tiles that operate on stencil in 1 clock. Can be inside a slow, pixel rate, or fast tile op MM4PERF_SC_DB_quad_sends: Cycles Interface is sending N@N0PERF_SC_DB_quad_busy: Cycles Interface is busy pON;PERF_SC_DB_quad_squads: Squads transferred over interface (PO2PERF_SC_DB_quad_tiles: Tiles sent over interface PpP:PERF_SC_DB_quad_pixels: Pixels transfered over interface Q0Q=PERF_SC_DB_quad_killed_tiles: Number of detail killed tiles hRQ4PERF_DB_SC_quad_sends: Cycles Interface is sending SR0PERF_DB_SC_quad_busy: Cycles Interface is busy ShS5PERF_DB_SC_quad_stalls: Cycles Interface is stalled T(T 4PERF_DB_SC_quad_squads: Squads sent over interface PUT!2PERF_DB_SC_quad_tiles: Tiles sent over interface VU"HPERF_DB_SC_quad_quads: Quads transferred over the DB_SC_quad interface WhV#nPERF_DB_CB_tile_sends: Cycles sending tiles/events to CB. Tiles not shaded or needed by the CB are not sent. W`W$PERF_DB_CB_tile_busy: XXX%PERF_DB_CB_tile_stalls: YX&4PERF_SX_DB_quad_sends: Cycles Interface is sending YXY'0PERF_SX_DB_quad_busy: Cycles Interface is busy ZZ(5PERF_SX_DB_quad_stalls: Cycles Interface is stalled @[Z)2PERF_SX_DB_quad_quads: Quads sent over interface [[*4PERF_SX_DB_quad_pixels: Pixels sent over interface \@\+APERF_SX_DB_quad_exports: Each MRT of a quad sent over interface ]],bPERF_SH_quads_outstanding_sum: Multiple by 128 and divide by DB_SC_quad_quads to get PS latency. h^]-5PERF_DB_CB_lquad_sends: Cycles Interface is sending _^.1PERF_DB_CB_lquad_busy: Cycles Interface is busy _h_/6PERF_DB_CB_lquad_stalls: Cycles Interface is stalled `(`03PERF_DB_CB_lquad_quads: Quads sent over interface Pa`1/PERF_tile_rd_sends: HTile reads. Each is 256B @ba2hPERF_mi_tile_rd_outstanding_sum: Multiply by 2 and divide by tile_rd_sends to get htile memory latency cb3:PERF_quad_rd_sends: Quad read reqs. Each is 32B to 256B cHc4JPERF_quad_rd_busy: Cycles quad read interface is trying to send requests dd5VPERF_quad_rd_mi_stall: Cycles quad read interface is stalled by the memory interface ed6XPERF_quad_rd_rw_collision: Cycles a quad read is stalled waiting for a write to finish fe7ePERF_quad_rd_tag_stall: Cycles a quad read is stalled because the read latency hiding fifo is full. Hgf8@PERF_quad_rd_32byte_reqs: Number of 32 Byte quad read requests hg9>PERF_quad_rd_panic: Cycles DB is panicing for quad read data iXh:vPERF_mi_quad_rd_outstanding_sum: Multiply by 16 and divide by quad_rd_32byte_reqs to get depth buffer memory latency iXi;<PERF_quad_rdret_sends: Number of 32 byte quad read returns jj<>PERF_quad_rdret_busy: Cycles the quad read data is returning Hkj=*PERF_tile_wr_sends: 32 Byte HTile writes lk>-PERF_tile_wr_acks: 32 Byte Htile write acks lHl?nPERF_mi_tile_wr_outstanding_sum: Multiply by 16 and divide by tile_wr_sends to get tile write memory latency m@m@cPERF_quad_wr_sends: Cycles quad is sending write requests to the memory interface block of the DB n(nAKPERF_quad_wr_busy: Cycles quad is trying to write to the memory interface onBUPERF_quad_wr_mi_stall: Cycles quad is stalled while writing to the memory interface poCwPERF_quad_wr_coherency_stall: Cycles quad write is stalled waiting for a previous write to finish on the same address PqpD6PERF_quad_wr_acks: Number of 32 Byte quad write acks HrqErPERF_mi_quad_wr_outstanding_sum: Multiply by 16 and divide by the quad_wr_sends to get quad memory write latency rrF,PERF_Tile_Cache_misses: Htile Cache misses s@sG(PERF_Tile_Cache_hits: Htile Cache hits `tsH.PERF_Tile_Cache_flushes: Htile Cache flushes @utI[PERF_Tile_Cache_surface_stall: Tile stalls waiting for an htile surface to flush and free vuJMPERF_Tile_Cache_starves: Tile stalls waiting for an htile cacheline to free v`vK[PERF_Tile_Cache_mem_return_starve: Tile stalls waiting for an htile memory read to return w@wLYPERF_tcp_dispatcher_reads: Number of htile cachelines fetched by the normal tile stream x xMQPERF_tcp_prefetcher_reads: Number of htile cachelines fetched by the prefetcher yxNOPERF_tcp_preloader_reads: Number of htile cachelines fetched by the preloader hzyOXPERF_tcp_dispatcher_flushes: Number of htile flushes caused byt the normal tile stream H{zPWPERF_tcp_prefetcher_flushes: Number of htile flushes caused byt the normal prefetcher (|{QUPERF_tcp_preloader_flushes: Number of htile flushes caused byt the normal preloader |p|RHPERF_Depth_Tile_Cache_sends: Tiles/Events through the Depth Tile Cache }@}SbPERF_Depth_Tile_Cache_busy: Cycles the Depth Tile Cache is busy testing hit/miss on tiles/events ~(~T_PERF_Depth_Tile_Cache_starves: Cycles starved waiting for a depth surface tile tag to free up UgPERF_Depth_Tile_Cache_dtile_locked: Cycles stalled waiting for a forced flush or invalidate to finish VTPERF_Depth_Tile_Cache_alloc_stall: Cycles depth tile stalled while allocating data `W?PERF_Depth_Tile_Cache_misses: Depth/Stencil Cache tile misses X;PERF_Depth_Tile_Cache_hits: Depth/Stencil Cache tile hits 肿hYAPERF_Depth_Tile_Cache_flushes: Depth/Stencil Cache tile flushes 0ZJPERF_Depth_Tile_Cache_noop_tile: Noop tiles through the depth tile cache [VPERF_Depth_Tile_Cache_detailed_noop: Detail walked noops though the depth tile cache H\%PERF_Depth_Tile_Cache_event: Events ]4PERF_Depth_Tile_Cache_tile_frees: Depth tile frees 膿H^cPERF_Depth_Tile_Cache_data_frees: Depth tile data frees (may free data without freeing the dtile) ؇0_ePERF_Depth_Tile_Cache_mem_return_starve: Cycles depth/stencil cache is waiting for memory to return `/PERF_Stencil_Cache_misses: 512 bit allocation 0؈aPERF_Stencil_Cache_hits: (xbpPERF_Stencil_Cache_flushes: 256 bit flushes. Two per cacheline unless it is compressed, in which case it is 1. pcmPERF_Stencil_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate hdPERF_Stencil_Cache_frees: he"PERF_Z_Cache_separate_Z_misses: f PERF_Z_Cache_separate_Z_hits: Xg#PERF_Z_Cache_separate_Z_flushes: hrPERF_Z_Cache_separate_Z_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate XiPERF_Z_Cache_pmask_misses: jPERF_Z_Cache_pmask_hits: @kPERF_Z_Cache_pmask_flushes: 萿lmPERF_Z_Cache_pmask_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate 8mPERF_Z_Cache_frees: ؒnPERF_Plane_Cache_misses: x oPERF_Plane_Cache_hits: pPERF_Plane_Cache_flushes: `qkPERF_Plane_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate PrPERF_Plane_Cache_frees: xsGPERF_flush_expanded_stencil: Tiles flushed with with expanded stencil HtKPERF_flush_compressed_stencil: Tiles flushed with with compressed stencil uCPERF_flush_single_stencil: Tiles flushed with with single stencil ȘXv0PERF_flush_1plane: Tiles flushed with 1 ZPlane w1PERF_flush_2plane: Tiles flushed with 2 ZPlanes 8șx1PERF_flush_3plane: Tiles flushed with 3 ZPlanes y1PERF_flush_4plane: Tiles flushed with 4 ZPlanes 8z1PERF_flush_5plane: Tiles flushed with 5 ZPlanes `{1PERF_flush_6plane: Tiles flushed with 6 ZPlanes |1PERF_flush_7plane: Tiles flushed with 7 ZPlanes Н`}1PERF_flush_8plane: Tiles flushed with 8 ZPlanes ~1PERF_flush_9plane: Tiles flushed with 9 ZPlanes @О3PERF_flush_10plane: Tiles flushed with 10 ZPlanes 3PERF_flush_11plane: Tiles flushed with 11 ZPlanes @3PERF_flush_12plane: Tiles flushed with 12 ZPlanes h3PERF_flush_13plane: Tiles flushed with 13 ZPlanes 3PERF_flush_14plane: Tiles flushed with 14 ZPlanes آh3PERF_flush_15plane: Tiles flushed with 15 ZPlanes 3PERF_flush_16plane: Tiles flushed with 16 ZPlanes Pأ6PERF_flush_expanded_z: Tiles flushed with expanded Z 8`PERF_earlyZ_waiting_for_postZ_done: Cycles stalled while transitioning from Late/ReZ to EarlyZ 0rPERF_reZ_waiting_for_postZ_done: Cycles stalled while transitioning to ReZ from an incompatible Z mode/func/etc. x@PERF_dk_tile_sends: Detail kill block tiles/squads/events sent @2PERF_dk_tile_busy: Cycles Detail Kill block busy ZPERF_dk_tile_quad_starves: Cycles Detail Kill has tile, but no quads from the SC_DB_quad Xب?PERF_dk_tile_stalls: Cycles Detail Kill is stalled from below )PERF_dk_squad_sends: Detail Kill squads ЪP@PERF_dk_squad_busy: Cycles the squad Detail Kill input is busy =PERF_dk_squad_stalls: Cycles squads are stalled from below. ૿rPERF_Op_Pipe_Busy: Cycles the quad OP pipe of the DB is busy (including memory fetches, but not initial startup) جkPERF_Op_Pipe_MC_Read_stall: Cycles the Op Pipe is waiting for memory to return (ignoring initial startup) 8ȭ1PERF_qc_busy: Cycles the Quad Coherency is busy CPERF_qc_xfc: Number of transfers through the Quad Coherency block HPERF_qc_conflicts: Stalls on a squad input because of a coherency check conflict (the same sample ahead of it could affect the dest data) ిXKPERF_qc_full_stall: Quad Coherency is stalled because it is out of slots. (PERF_qc_in_preZ_tile_stalls_postZ: Cycles postZ squad inputs are stalled because the OP pipe is operating on a preZ tile, and there is no PreZ squad input available @XPERF_qc_in_postZ_tile_stalls_preZ: Cycles preZ squad inputs are stalled because the OP pipe is operating on a postZ tile, and there is no PostZ squad input available 8rPERF_tsc_insert_summarize_stall: Cycles the op pipe is stalled by the tile summarizer inserting summarize squads -PERF_tl_busy: Cycles Tile Lookup block busy 84PERF_tl_dtc_read_starved: Cycles Tile Lookup block xIPERF_tl_z_fetch_stall: Cycles Tile Lookup block stalled by zfetch block POPERF_tl_stencil_stall: Cycles Tile Lookup block stalled by stencil test block (TPERF_tl_z_decompress_stall: Cycles Tile Lookup block stalled by z decompress block pXPERF_tl_stencil_locked_stall: Cycles Tile Lookup block stalled by stencil being locked ȹP;PERF_tl_events: Cycles Tile Lookup block sends out events OPERF_tl_summarize_squads: Cycles Tile Lookup block sends out summarize squads 躿UPERF_tl_flush_expand_squads: Cycles Tile Lookup block sends out flush expand squads PȻIPERF_tl_expand_squads: Cycles Tile Lookup block sends out expand squads EPERF_tl_preZ_squads: Cycles Tile Lookup block sends out preZ squads hGPERF_tl_postZ_squads: Cycles Tile Lookup block sends out postZ squads о8UPERF_tl_preZ_noop_squads: Cycles Tile Lookup block sends out noops on the preZ path WPERF_tl_postZ_noop_squads: Cycles Tile Lookup block sends out noops on the postZ path NPERF_tl_getZ_squads: Cycles Tile Lookup block sends out z import pass squads XEPERF_tl_tile_ops: Cycles Tile Lookup block sends out tile op squads ¿=PERF_tl_in_xfc: Cycles Tile Lookup block receives any input ÿh¿nPERF_tl_in_single_stencil_expand_stall: Cycles Tile Lookup block is stalling due to expanding single stencil Ŀ`ÿePERF_tl_in_constant_stencil_walk_stall: Cycles Tile Lookup block is stalling due to walking stencil ĿPĿLPERF_tl_in_fast_z_stall: Cycles Tile Lookup block is stalling due to fastZ ſ ſCPERF_tl_out_xfc: Cycles Tile Lookup block is sending anything out hƿſDPERF_tl_out_squads: Cycles Tile Lookup block is sending squads out ǿƿPERF_zf_plane_multicycle: Cycles the z fetch is multicycling a squad because it needs to fetch more than 2 planes from the cache for compressed Z PȿǿJPERF_PostZ_Samples_passing_Z: Samples passing Z test during a PostZ pass ɿȿJPERF_PostZ_Samples_failing_Z: Samples failing Z test during a PostZ pass ɿhɿPPERF_PostZ_Samples_failing_S: Samples failing Stencil test during a PostZ pass ʿ@ʿHPERF_PreZ_Samples_passing_Z: Samples passing Z test during a PreZ pass ˿˿HPERF_PreZ_Samples_failing_Z: Samples failing Z test during a PreZ pass p̿˿NPERF_PreZ_Samples_failing_S: Samples failing Stencil test during a PreZ pass PͿ̿ZPERF_ts_tc_update_stall: Cycles Tile Summarizer to Tile Cache write interface is stalled οͿ>PERF_sc_kick_start: Times the DB sent a hang panic to the SC ο`ο7PERF_sc_kick_end: Times the DB completed a hang panic Ͽ Ͽ>PERF_SX_DB_mem_exports: Number of memory exports from the SX xпϿPPERF_SX_DB_mem_exports_acked: Number of memory export writes acked from the MC PѿпPPERF_SX_DB_ack_mem_exports: Number of ack requested memory exports from the SX (ҿѿSPERF_SX_DB_ack_mem_exports_acked: Number of memory export acks returned to the SX ҿpҿ5PERF_mem_export_busy: Cycles writing memory exports ӿ0ӿsPERF_mem_export_mi_stall: Cycles mem exports are stalled waiting for other DB writes or MC write bus arbitration. Կ(ԿdPERF_mem_export_tag_stall: Cycles mem exports are stalled waiting for a free mem export write tag. տտ<PERF_clock_reg_active: Cycles register part of DB is awake Hֿտ9PERF_clock_main_active: Cycles core part of DB is awake ׿ֿEPERF_clock_mem_export_active: Cycles mem export part of DB is awake ׿`׿7PERF_esr_out_busy: Early Squad Router Out cycles busy ؿ ؿ;PERF_esr_out_sc_stall: Early Squad Router Out to SC stall xٿؿZPERF_esr_out_lquad_fifo_full_stall: Early Squad Router Out to Late Quad Fifo full stalls 0ڿٿ0PERF_etr_out_send: Early Tile Router Out sends ڿxڿ6PERF_etr_out_busy: Early Tile Router Out cycles busy ۿ8ۿePERF_etr_out_ltile_probe_fifo_full_stall: Early Tile Router Out to Late Tile Probe Fifo full stalls ܿ(ܿAPERF_etr_out_cb_tile_stall: Early Tile Router to CB tile stalls ܿIPERF_etr_out_esr_stall: Early Tile Router to Early Squad Router stalls. 68""9DB2_PERFCOUNTER3_HIX9 PERF_COUNT"h5H7""7DB2_PERFCOUNTER2_HI7 PERF_COUNT"45""06DB2_PERFCOUNTER1_HI6 PERF_COUNT"2x4""4DB2_PERFCOUNTER0_HI 5 PERF_COUNT" 13""`3DB2_PERFCOUNTER3_LOW3 PERF_COUNT"/1""1DB2_PERFCOUNTER2_LOWH2 PERF_COUNT"@.(0""0DB2_PERFCOUNTER1_LOW0 PERF_COUNT"h.""/DB2_PERFCOUNTER0_LOWh/ PERF_COUNT"""8DB2_PERFCOUNTER3_SELECT؋ PERF_SEL 4PERF_SC_DB_tile_sends: Cycles Interface is sending H،0PERF_SC_DB_tile_busy: Cycles Interface is busy 5PERF_SC_DB_tile_stalls: Cycles Interface is stalled P4PERF_SC_DB_tile_events: Events sent over interface x2PERF_SC_DB_tile_tiles: Tiles sent over interface 0.PERF_SC_DB_tile_covered: Fully covered tiles xIPERF_hiz_tc_read_starved: HiZ starved waiting for htile data from cache ȑH=PERF_hiz_tc_write_stall: HiZ stalled writing to htile cache 5PERF_hiz_qtiles_culled: Quarter tiles culled by hiZ HВ 5PERF_his_qtiles_culled: Quarter tiles culled by HiS 4PERF_DB_SC_tile_sends: Cycles Interface is sending H 0PERF_DB_SC_tile_busy: Cycles Interface is busy x ;PERF_DB_SC_tile_stalls: Cycles Interface is stalled by SC P QPERF_DB_SC_tile_df_stalls: Cycles Interface is stalled by detail walk tile fifo 2PERF_DB_SC_tile_tiles: Tiles sent over interface P/PERF_DB_SC_tile_culled: Tiles culled in total IPERF_DB_SC_tile_hier_kill: Tiles culled due to a hierarchical fail test hؘSPERF_DB_SC_tile_fast_ops: Tiles culled because they were accerated fast tile ops. 8IPERF_DB_SC_tile_no_ops: Tiles culled because they would not do anything TPERF_DB_SC_tile_pixel_rate: Tiles run at pixel rate as opposed to sample rate tile XqPERF_DB_SC_tile_ssaa_kill: Tiles culled because they were supersample tiles that are merged into a fast tile op PtPERF_DB_SC_tile_fast_z_ops: Tiles that operate on Z in 1 clock. Can be inside a slow, pixel rate, or fast tile op HPERF_DB_SC_tile_fast_stencil_ops: Tiles that operate on stencil in 1 clock. Can be inside a slow, pixel rate, or fast tile op P4PERF_SC_DB_quad_sends: Cycles Interface is sending x0PERF_SC_DB_quad_busy: Cycles Interface is busy 8;PERF_SC_DB_quad_squads: Squads transferred over interface 2PERF_SC_DB_quad_tiles: Tiles sent over interface 8:PERF_SC_DB_quad_pixels: Pixels transfered over interface x=PERF_SC_DB_quad_killed_tiles: Number of detail killed tiles 04PERF_DB_SC_quad_sends: Cycles Interface is sending 裾x0PERF_DB_SC_quad_busy: Cycles Interface is busy 05PERF_DB_SC_quad_stalls: Cycles Interface is stalled ` 4PERF_DB_SC_quad_squads: Squads sent over interface !2PERF_DB_SC_quad_tiles: Tiles sent over interface 覾`"HPERF_DB_SC_quad_quads: Quads transferred over the DB_SC_quad interface ৾0#nPERF_DB_CB_tile_sends: Cycles sending tiles/events to CB. Tiles not shaded or needed by the CB are not sent. ($PERF_DB_CB_tile_busy: Ȩ%PERF_DB_CB_tile_stalls: ةh&4PERF_SX_DB_quad_sends: Cycles Interface is sending '0PERF_SX_DB_quad_busy: Cycles Interface is busy Pت(5PERF_SX_DB_quad_stalls: Cycles Interface is stalled )2PERF_SX_DB_quad_quads: Quads sent over interface P*4PERF_SX_DB_quad_pixels: Pixels sent over interface +APERF_SX_DB_quad_exports: Each MRT of a quad sent over interface pЭ,bPERF_SH_quads_outstanding_sum: Multiple by 128 and divide by DB_SC_quad_quads to get PS latency. 0-5PERF_DB_CB_lquad_sends: Cycles Interface is sending 课x.1PERF_DB_CB_lquad_busy: Cycles Interface is busy 0/6PERF_DB_CB_lquad_stalls: Cycles Interface is stalled `03PERF_DB_CB_lquad_quads: Quads sent over interface 1/PERF_tile_rd_sends: HTile reads. Each is 256B `2hPERF_mi_tile_rd_outstanding_sum: Multiply by 2 and divide by tile_rd_sends to get htile memory latency ȳP3:PERF_quad_rd_sends: Quad read reqs. Each is 32B to 256B 4JPERF_quad_rd_busy: Cycles quad read interface is trying to send requests xാ5VPERF_quad_rd_mi_stall: Cycles quad read interface is stalled by the memory interface X6XPERF_quad_rd_rw_collision: Cycles a quad read is stalled waiting for a write to finish H7ePERF_quad_rd_tag_stall: Cycles a quad read is stalled because the read latency hiding fifo is full. 8@PERF_quad_rd_32byte_reqs: Number of 32 Byte quad read requests ظX9>PERF_quad_rd_panic: Cycles DB is panicing for quad read data ع :vPERF_mi_quad_rd_outstanding_sum: Multiply by 16 and divide by quad_rd_32byte_reqs to get depth buffer memory latency ;<PERF_quad_rdret_sends: Number of 32 byte quad read returns `຾<>PERF_quad_rdret_busy: Cycles the quad read data is returning =*PERF_tile_wr_sends: 32 Byte HTile writes ȼX>-PERF_tile_wr_acks: 32 Byte Htile write acks ?nPERF_mi_tile_wr_outstanding_sum: Multiply by 16 and divide by tile_wr_sends to get tile write memory latency @cPERF_quad_wr_sends: Cycles quad is sending write requests to the memory interface block of the DB xAKPERF_quad_wr_busy: Cycles quad is trying to write to the memory interface XBUPERF_quad_wr_mi_stall: Cycles quad is stalled while writing to the memory interface XCwPERF_quad_wr_coherency_stall: Cycles quad write is stalled waiting for a previous write to finish on the same address ¾D6PERF_quad_wr_acks: Number of 32 Byte quad write acks þ`¾ErPERF_mi_quad_wr_outstanding_sum: Multiply by 16 and divide by the quad_wr_sends to get quad memory write latency þXþF,PERF_Tile_Cache_misses: Htile Cache misses pľľG(PERF_Tile_Cache_hits: Htile Cache hits (žľH.PERF_Tile_Cache_flushes: Htile Cache flushes ƾpžI[PERF_Tile_Cache_surface_stall: Tile stalls waiting for an htile surface to flush and free ƾPƾJMPERF_Tile_Cache_starves: Tile stalls waiting for an htile cacheline to free Ǿ(ǾK[PERF_Tile_Cache_mem_return_starve: Tile stalls waiting for an htile memory read to return ȾȾLYPERF_tcp_dispatcher_reads: Number of htile cachelines fetched by the normal tile stream xɾȾMQPERF_tcp_prefetcher_reads: Number of htile cachelines fetched by the prefetcher PʾɾNOPERF_tcp_preloader_reads: Number of htile cachelines fetched by the preloader 0˾ʾOXPERF_tcp_dispatcher_flushes: Number of htile flushes caused byt the normal tile stream ̾x˾PWPERF_tcp_prefetcher_flushes: Number of htile flushes caused byt the normal prefetcher ̾X̾QUPERF_tcp_preloader_flushes: Number of htile flushes caused byt the normal preloader ;8;RHPERF_Depth_Tile_Cache_sends: Tiles/Events through the Depth Tile Cache ξξSbPERF_Depth_Tile_Cache_busy: Cycles the Depth Tile Cache is busy testing hit/miss on tiles/events ϾξT_PERF_Depth_Tile_Cache_starves: Cycles starved waiting for a depth surface tile tag to free up оϾUgPERF_Depth_Tile_Cache_dtile_locked: Cycles stalled waiting for a forced flush or invalidate to finish XѾоVTPERF_Depth_Tile_Cache_alloc_stall: Cycles depth tile stalled while allocating data ҾѾW?PERF_Depth_Tile_Cache_misses: Depth/Stencil Cache tile misses ҾhҾX;PERF_Depth_Tile_Cache_hits: Depth/Stencil Cache tile hits Ӿ(ӾYAPERF_Depth_Tile_Cache_flushes: Depth/Stencil Cache tile flushes xԾӾZJPERF_Depth_Tile_Cache_noop_tile: Noop tiles through the depth tile cache XվԾ[VPERF_Depth_Tile_Cache_detailed_noop: Detail walked noops though the depth tile cache ־վ\%PERF_Depth_Tile_Cache_event: Events ־P־]4PERF_Depth_Tile_Cache_tile_frees: Depth tile frees ׾׾^cPERF_Depth_Tile_Cache_data_frees: Depth tile data frees (may free data without freeing the dtile) ؾ׾_ePERF_Depth_Tile_Cache_mem_return_starve: Cycles depth/stencil cache is waiting for memory to return Pپؾ`/PERF_Stencil_Cache_misses: 512 bit allocation پپaPERF_Stencil_Cache_hits: ھ8ھbpPERF_Stencil_Cache_flushes: 256 bit flushes. Two per cacheline unless it is compressed, in which case it is 1. ۾0۾cmPERF_Stencil_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate ܾ(ܾdPERF_Stencil_Cache_frees: (ݾܾe"PERF_Z_Cache_separate_Z_misses: ݾpݾf PERF_Z_Cache_separate_Z_hits: x޾޾g#PERF_Z_Cache_separate_Z_flushes: p߾޾hrPERF_Z_Cache_separate_Z_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate ߾iPERF_Z_Cache_pmask_misses: `jPERF_Z_Cache_pmask_hits: `kPERF_Z_Cache_pmask_flushes: XlmPERF_Z_Cache_pmask_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate mPERF_Z_Cache_frees: @nPERF_Plane_Cache_misses: 8oPERF_Plane_Cache_hits: pPERF_Plane_Cache_flushes: qkPERF_Plane_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate hrPERF_Plane_Cache_frees: 8sGPERF_flush_expanded_stencil: Tiles flushed with with expanded stencil tKPERF_flush_compressed_stencil: Tiles flushed with with compressed stencil PuCPERF_flush_single_stencil: Tiles flushed with with single stencil v0PERF_flush_1plane: Tiles flushed with 1 ZPlane @w1PERF_flush_2plane: Tiles flushed with 2 ZPlanes x1PERF_flush_3plane: Tiles flushed with 3 ZPlanes @y1PERF_flush_4plane: Tiles flushed with 4 ZPlanes hz1PERF_flush_5plane: Tiles flushed with 5 ZPlanes {1PERF_flush_6plane: Tiles flushed with 6 ZPlanes h|1PERF_flush_7plane: Tiles flushed with 7 ZPlanes }1PERF_flush_8plane: Tiles flushed with 8 ZPlanes H~1PERF_flush_9plane: Tiles flushed with 9 ZPlanes 3PERF_flush_10plane: Tiles flushed with 10 ZPlanes P3PERF_flush_11plane: Tiles flushed with 11 ZPlanes x3PERF_flush_12plane: Tiles flushed with 12 ZPlanes 03PERF_flush_13plane: Tiles flushed with 13 ZPlanes x3PERF_flush_14plane: Tiles flushed with 14 ZPlanes 03PERF_flush_15plane: Tiles flushed with 15 ZPlanes X3PERF_flush_16plane: Tiles flushed with 16 ZPlanes 6PERF_flush_expanded_z: Tiles flushed with expanded Z ``PERF_earlyZ_waiting_for_postZ_done: Cycles stalled while transitioning from Late/ReZ to EarlyZ HrPERF_reZ_waiting_for_postZ_done: Cycles stalled while transitioning to ReZ from an incompatible Z mode/func/etc. @@PERF_dk_tile_sends: Detail kill block tiles/squads/events sent x2PERF_dk_tile_busy: Cycles Detail Kill block busy XZPERF_dk_tile_quad_starves: Cycles Detail Kill has tile, but no quads from the SC_DB_quad ?PERF_dk_tile_stalls: Cycles Detail Kill is stalled from below h)PERF_dk_squad_sends: Detail Kill squads @PERF_dk_squad_busy: Cycles the squad Detail Kill input is busy `=PERF_dk_squad_stalls: Cycles squads are stalled from below. XrPERF_Op_Pipe_Busy: Cycles the quad OP pipe of the DB is busy (including memory fetches, but not initial startup) HkPERF_Op_Pipe_MC_Read_stall: Cycles the Op Pipe is waiting for memory to return (ignoring initial startup) 1PERF_qc_busy: Cycles the Quad Coherency is busy HCPERF_qc_xfc: Number of transfers through the Quad Coherency block PERF_qc_conflicts: Stalls on a squad input because of a coherency check conflict (the same sample ahead of it could affect the dest data)  KPERF_qc_full_stall: Quad Coherency is stalled because it is out of slots. PERF_qc_in_preZ_tile_stalls_postZ: Cycles postZ squad inputs are stalled because the OP pipe is operating on a preZ tile, and there is no PreZ squad input available  PERF_qc_in_postZ_tile_stalls_preZ: Cycles preZ squad inputs are stalled because the OP pipe is operating on a postZ tile, and there is no PostZ squad input available PrPERF_tsc_insert_summarize_stall: Cycles the op pipe is stalled by the tile summarizer inserting summarize squads H-PERF_tl_busy: Cycles Tile Lookup block busy p4PERF_tl_dtc_read_starved: Cycles Tile Lookup block @IPERF_tl_z_fetch_stall: Cycles Tile Lookup block stalled by zfetch block OPERF_tl_stencil_stall: Cycles Tile Lookup block stalled by stencil test block `TPERF_tl_z_decompress_stall: Cycles Tile Lookup block stalled by z decompress block 8 XPERF_tl_stencil_locked_stall: Cycles Tile Lookup block stalled by stencil being locked  ;PERF_tl_events: Cycles Tile Lookup block sends out events h OPERF_tl_summarize_squads: Cycles Tile Lookup block sends out summarize squads H UPERF_tl_flush_expand_squads: Cycles Tile Lookup block sends out flush expand squads  IPERF_tl_expand_squads: Cycles Tile Lookup block sends out expand squads ` EPERF_tl_preZ_squads: Cycles Tile Lookup block sends out preZ squads 0GPERF_tl_postZ_squads: Cycles Tile Lookup block sends out postZ squads UPERF_tl_preZ_noop_squads: Cycles Tile Lookup block sends out noops on the preZ path xWPERF_tl_postZ_noop_squads: Cycles Tile Lookup block sends out noops on the postZ path PNPERF_tl_getZ_squads: Cycles Tile Lookup block sends out z import pass squads EPERF_tl_tile_ops: Cycles Tile Lookup block sends out tile op squads h=PERF_tl_in_xfc: Cycles Tile Lookup block receives any input 0nPERF_tl_in_single_stencil_expand_stall: Cycles Tile Lookup block is stalling due to expanding single stencil (ePERF_tl_in_constant_stencil_walk_stall: Cycles Tile Lookup block is stalling due to walking stencil LPERF_tl_in_fast_z_stall: Cycles Tile Lookup block is stalling due to fastZ hCPERF_tl_out_xfc: Cycles Tile Lookup block is sending anything out 0DPERF_tl_out_squads: Cycles Tile Lookup block is sending squads out HxPERF_zf_plane_multicycle: Cycles the z fetch is multicycling a squad because it needs to fetch more than 2 planes from the cache for compressed Z JPERF_PostZ_Samples_passing_Z: Samples passing Z test during a PostZ pass `JPERF_PostZ_Samples_failing_Z: Samples failing Z test during a PostZ pass 0PPERF_PostZ_Samples_failing_S: Samples failing Stencil test during a PostZ pass HPERF_PreZ_Samples_passing_Z: Samples passing Z test during a PreZ pass `HPERF_PreZ_Samples_failing_Z: Samples failing Z test during a PreZ pass 8NPERF_PreZ_Samples_failing_S: Samples failing Stencil test during a PreZ pass ZPERF_ts_tc_update_stall: Cycles Tile Summarizer to Tile Cache write interface is stalled `>PERF_sc_kick_start: Times the DB sent a hang panic to the SC (7PERF_sc_kick_end: Times the DB completed a hang panic h >PERF_SX_DB_mem_exports: Number of memory exports from the SX @! PPERF_SX_DB_mem_exports_acked: Number of memory export writes acked from the MC "!PPERF_SX_DB_ack_mem_exports: Number of ack requested memory exports from the SX "`"SPERF_SX_DB_ack_mem_exports_acked: Number of memory export acks returned to the SX #8#5PERF_mem_export_busy: Cycles writing memory exports $#sPERF_mem_export_mi_stall: Cycles mem exports are stalled waiting for other DB writes or MC write bus arbitration. %$dPERF_mem_export_tag_stall: Cycles mem exports are stalled waiting for a free mem export write tag. P&%<PERF_clock_reg_active: Cycles register part of DB is awake '&9PERF_clock_main_active: Cycles core part of DB is awake 'X'EPERF_clock_mem_export_active: Cycles mem export part of DB is awake (((7PERF_esr_out_busy: Early Squad Router Out cycles busy `)(;PERF_esr_out_sc_stall: Early Squad Router Out to SC stall @*)ZPERF_esr_out_lquad_fifo_full_stall: Early Squad Router Out to Late Quad Fifo full stalls **0PERF_etr_out_send: Early Tile Router Out sends +@+6PERF_etr_out_busy: Early Tile Router Out cycles busy ,,ePERF_etr_out_ltile_probe_fifo_full_stall: Early Tile Router Out to Late Tile Probe Fifo full stalls p-,APERF_etr_out_cb_tile_stall: Early Tile Router to CB tile stalls -IPERF_etr_out_esr_stall: Early Tile Router to Early Squad Router stalls. B""XDB2_PERFCOUNTER2_SELECT PERF_SEL@4PERF_SC_DB_tile_sends: Cycles Interface is sending h0PERF_SC_DB_tile_busy: Cycles Interface is busy (5PERF_SC_DB_tile_stalls: Cycles Interface is stalled p4PERF_SC_DB_tile_events: Events sent over interface (2PERF_SC_DB_tile_tiles: Tiles sent over interface P.PERF_SC_DB_tile_covered: Fully covered tiles IPERF_hiz_tc_read_starved: HiZ starved waiting for htile data from cache h=PERF_hiz_tc_write_stall: HiZ stalled writing to htile cache 05PERF_hiz_qtiles_culled: Quarter tiles culled by hiZ h 5PERF_his_qtiles_culled: Quarter tiles culled by HiS 4PERF_DB_SC_tile_sends: Cycles Interface is sending h 0PERF_DB_SC_tile_busy: Cycles Interface is busy ;PERF_DB_SC_tile_stalls: Cycles Interface is stalled by SC p QPERF_DB_SC_tile_df_stalls: Cycles Interface is stalled by detail walk tile fifo (2PERF_DB_SC_tile_tiles: Tiles sent over interface p/PERF_DB_SC_tile_culled: Tiles culled in total (IPERF_DB_SC_tile_hier_kill: Tiles culled due to a hierarchical fail test SPERF_DB_SC_tile_fast_ops: Tiles culled because they were accerated fast tile ops. XIPERF_DB_SC_tile_no_ops: Tiles culled because they would not do anything 0TPERF_DB_SC_tile_pixel_rate: Tiles run at pixel rate as opposed to sample rate tile (xqPERF_DB_SC_tile_ssaa_kill: Tiles culled because they were supersample tiles that are merged into a fast tile op ptPERF_DB_SC_tile_fast_z_ops: Tiles that operate on Z in 1 clock. Can be inside a slow, pixel rate, or fast tile op (hPERF_DB_SC_tile_fast_stencil_ops: Tiles that operate on stencil in 1 clock. Can be inside a slow, pixel rate, or fast tile op p4PERF_SC_DB_quad_sends: Cycles Interface is sending (0PERF_SC_DB_quad_busy: Cycles Interface is busy X;PERF_SC_DB_quad_squads: Squads transferred over interface 2PERF_SC_DB_quad_tiles: Tiles sent over interface X:PERF_SC_DB_quad_pixels: Pixels transfered over interface =PERF_SC_DB_quad_killed_tiles: Number of detail killed tiles P4PERF_DB_SC_quad_sends: Cycles Interface is sending 0PERF_DB_SC_quad_busy: Cycles Interface is busy P5PERF_DB_SC_quad_stalls: Cycles Interface is stalled  4PERF_DB_SC_quad_squads: Squads sent over interface 8!2PERF_DB_SC_quad_tiles: Tiles sent over interface "HPERF_DB_SC_quad_quads: Quads transferred over the DB_SC_quad interface P#nPERF_DB_CB_tile_sends: Cycles sending tiles/events to CB. Tiles not shaded or needed by the CB are not sent. H$PERF_DB_CB_tile_busy: @%PERF_DB_CB_tile_stalls: &4PERF_SX_DB_quad_sends: Cycles Interface is sending @'0PERF_SX_DB_quad_busy: Cycles Interface is busy p(5PERF_SX_DB_quad_stalls: Cycles Interface is stalled ()2PERF_SX_DB_quad_quads: Quads sent over interface p*4PERF_SX_DB_quad_pixels: Pixels sent over interface ( +APERF_SX_DB_quad_exports: Each MRT of a quad sent over interface ,bPERF_SH_quads_outstanding_sum: Multiple by 128 and divide by DB_SC_quad_quads to get PS latency. P -5PERF_DB_CB_lquad_sends: Cycles Interface is sending  .1PERF_DB_CB_lquad_busy: Cycles Interface is busy P /6PERF_DB_CB_lquad_stalls: Cycles Interface is stalled  03PERF_DB_CB_lquad_quads: Quads sent over interface 8 1/PERF_tile_rd_sends: HTile reads. Each is 256B (2hPERF_mi_tile_rd_outstanding_sum: Multiply by 2 and divide by tile_rd_sends to get htile memory latency p3:PERF_quad_rd_sends: Quad read reqs. Each is 32B to 256B 04JPERF_quad_rd_busy: Cycles quad read interface is trying to send requests 5VPERF_quad_rd_mi_stall: Cycles quad read interface is stalled by the memory interface x6XPERF_quad_rd_rw_collision: Cycles a quad read is stalled waiting for a write to finish h7ePERF_quad_rd_tag_stall: Cycles a quad read is stalled because the read latency hiding fifo is full. 08@PERF_quad_rd_32byte_reqs: Number of 32 Byte quad read requests x9>PERF_quad_rd_panic: Cycles DB is panicing for quad read data @:vPERF_mi_quad_rd_outstanding_sum: Multiply by 16 and divide by quad_rd_32byte_reqs to get depth buffer memory latency @;<PERF_quad_rdret_sends: Number of 32 byte quad read returns <>PERF_quad_rdret_busy: Cycles the quad read data is returning 0=*PERF_tile_wr_sends: 32 Byte HTile writes x>-PERF_tile_wr_acks: 32 Byte Htile write acks 0?nPERF_mi_tile_wr_outstanding_sum: Multiply by 16 and divide by tile_wr_sends to get tile write memory latency (@cPERF_quad_wr_sends: Cycles quad is sending write requests to the memory interface block of the DB AKPERF_quad_wr_busy: Cycles quad is trying to write to the memory interface xBUPERF_quad_wr_mi_stall: Cycles quad is stalled while writing to the memory interface xCwPERF_quad_wr_coherency_stall: Cycles quad write is stalled waiting for a previous write to finish on the same address 8D6PERF_quad_wr_acks: Number of 32 Byte quad write acks 0ErPERF_mi_quad_wr_outstanding_sum: Multiply by 16 and divide by the quad_wr_sends to get quad memory write latency xF,PERF_Tile_Cache_misses: Htile Cache misses ( G(PERF_Tile_Cache_hits: Htile Cache hits H! H.PERF_Tile_Cache_flushes: Htile Cache flushes ("!I[PERF_Tile_Cache_surface_stall: Tile stalls waiting for an htile surface to flush and free #p"JMPERF_Tile_Cache_starves: Tile stalls waiting for an htile cacheline to free #H#K[PERF_Tile_Cache_mem_return_starve: Tile stalls waiting for an htile memory read to return $($LYPERF_tcp_dispatcher_reads: Number of htile cachelines fetched by the normal tile stream %%MQPERF_tcp_prefetcher_reads: Number of htile cachelines fetched by the prefetcher p&%NOPERF_tcp_preloader_reads: Number of htile cachelines fetched by the preloader P'&OXPERF_tcp_dispatcher_flushes: Number of htile flushes caused byt the normal tile stream 0('PWPERF_tcp_prefetcher_flushes: Number of htile flushes caused byt the normal prefetcher )x(QUPERF_tcp_preloader_flushes: Number of htile flushes caused byt the normal preloader )X)RHPERF_Depth_Tile_Cache_sends: Tiles/Events through the Depth Tile Cache *(*SbPERF_Depth_Tile_Cache_busy: Cycles the Depth Tile Cache is busy testing hit/miss on tiles/events ++T_PERF_Depth_Tile_Cache_starves: Cycles starved waiting for a depth surface tile tag to free up ,+UgPERF_Depth_Tile_Cache_dtile_locked: Cycles stalled waiting for a forced flush or invalidate to finish x-,VTPERF_Depth_Tile_Cache_alloc_stall: Cycles depth tile stalled while allocating data @.-W?PERF_Depth_Tile_Cache_misses: Depth/Stencil Cache tile misses /.X;PERF_Depth_Tile_Cache_hits: Depth/Stencil Cache tile hits /H/YAPERF_Depth_Tile_Cache_flushes: Depth/Stencil Cache tile flushes 00ZJPERF_Depth_Tile_Cache_noop_tile: Noop tiles through the depth tile cache x10[VPERF_Depth_Tile_Cache_detailed_noop: Detail walked noops though the depth tile cache (21\%PERF_Depth_Tile_Cache_event: Events 2p2]4PERF_Depth_Tile_Cache_tile_frees: Depth tile frees 3(3^cPERF_Depth_Tile_Cache_data_frees: Depth tile data frees (may free data without freeing the dtile) 44_ePERF_Depth_Tile_Cache_mem_return_starve: Cycles depth/stencil cache is waiting for memory to return p55`/PERF_Stencil_Cache_misses: 512 bit allocation 65aPERF_Stencil_Cache_hits: 7X6bpPERF_Stencil_Cache_flushes: 256 bit flushes. Two per cacheline unless it is compressed, in which case it is 1. 8P7cmPERF_Stencil_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate 8H8dPERF_Stencil_Cache_frees: H98e"PERF_Z_Cache_separate_Z_misses: 99f PERF_Z_Cache_separate_Z_hits: :8:g#PERF_Z_Cache_separate_Z_flushes: ;:hrPERF_Z_Cache_separate_Z_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate 8<;iPERF_Z_Cache_pmask_misses: <<jPERF_Z_Cache_pmask_hits: = =kPERF_Z_Cache_pmask_flushes: x>=lmPERF_Z_Cache_pmask_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate ?>mPERF_Z_Cache_frees: ?`?nPERF_Plane_Cache_misses: `@@oPERF_Plane_Cache_hits: A@pPERF_Plane_Cache_flushes: AHAqkPERF_Plane_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate B8BrPERF_Plane_Cache_frees: `CBsGPERF_flush_expanded_stencil: Tiles flushed with with expanded stencil 0DCtKPERF_flush_compressed_stencil: Tiles flushed with with compressed stencil DxDuCPERF_flush_single_stencil: Tiles flushed with with single stencil E@Ev0PERF_flush_1plane: Tiles flushed with 1 ZPlane hFEw1PERF_flush_2plane: Tiles flushed with 2 ZPlanes GFx1PERF_flush_3plane: Tiles flushed with 3 ZPlanes GhGy1PERF_flush_4plane: Tiles flushed with 4 ZPlanes H Hz1PERF_flush_5plane: Tiles flushed with 5 ZPlanes HIH{1PERF_flush_6plane: Tiles flushed with 6 ZPlanes JI|1PERF_flush_7plane: Tiles flushed with 7 ZPlanes JHJ}1PERF_flush_8plane: Tiles flushed with 8 ZPlanes pKK~1PERF_flush_9plane: Tiles flushed with 9 ZPlanes (LK3PERF_flush_10plane: Tiles flushed with 10 ZPlanes LpL3PERF_flush_11plane: Tiles flushed with 11 ZPlanes M(M3PERF_flush_12plane: Tiles flushed with 12 ZPlanes PNM3PERF_flush_13plane: Tiles flushed with 13 ZPlanes ON3PERF_flush_14plane: Tiles flushed with 14 ZPlanes OPO3PERF_flush_15plane: Tiles flushed with 15 ZPlanes xPP3PERF_flush_16plane: Tiles flushed with 16 ZPlanes 8QP6PERF_flush_expanded_z: Tiles flushed with expanded Z RQ`PERF_earlyZ_waiting_for_postZ_done: Cycles stalled while transitioning from Late/ReZ to EarlyZ ShRrPERF_reZ_waiting_for_postZ_done: Cycles stalled while transitioning to ReZ from an incompatible Z mode/func/etc. S`S@PERF_dk_tile_sends: Detail kill block tiles/squads/events sent T(T2PERF_dk_tile_busy: Cycles Detail Kill block busy xUTZPERF_dk_tile_quad_starves: Cycles Detail Kill has tile, but no quads from the SC_DB_quad @VU?PERF_dk_tile_stalls: Cycles Detail Kill is stalled from below VV)PERF_dk_squad_sends: Detail Kill squads W8W@PERF_dk_squad_busy: Cycles the squad Detail Kill input is busy XX=PERF_dk_squad_stalls: Cycles squads are stalled from below. xYXrPERF_Op_Pipe_Busy: Cycles the quad OP pipe of the DB is busy (including memory fetches, but not initial startup) hZYkPERF_Op_Pipe_MC_Read_stall: Cycles the Op Pipe is waiting for memory to return (ignoring initial startup) [Z1PERF_qc_busy: Cycles the Quad Coherency is busy [h[CPERF_qc_xfc: Number of transfers through the Quad Coherency block \0\PERF_qc_conflicts: Stalls on a squad input because of a coherency check conflict (the same sample ahead of it could affect the dest data) ]@]KPERF_qc_full_stall: Quad Coherency is stalled because it is out of slots. ^^PERF_qc_in_preZ_tile_stalls_postZ: Cycles postZ squad inputs are stalled because the OP pipe is operating on a preZ tile, and there is no PreZ squad input available (`@_PERF_qc_in_postZ_tile_stalls_preZ: Cycles preZ squad inputs are stalled because the OP pipe is operating on a postZ tile, and there is no PostZ squad input available ap`rPERF_tsc_insert_summarize_stall: Cycles the op pipe is stalled by the tile summarizer inserting summarize squads aha-PERF_tl_busy: Cycles Tile Lookup block busy b b4PERF_tl_dtc_read_starved: Cycles Tile Lookup block `cbIPERF_tl_z_fetch_stall: Cycles Tile Lookup block stalled by zfetch block 8dcOPERF_tl_stencil_stall: Cycles Tile Lookup block stalled by stencil test block edTPERF_tl_z_decompress_stall: Cycles Tile Lookup block stalled by z decompress block eXeXPERF_tl_stencil_locked_stall: Cycles Tile Lookup block stalled by stencil being locked f8f;PERF_tl_events: Cycles Tile Lookup block sends out events gfOPERF_tl_summarize_squads: Cycles Tile Lookup block sends out summarize squads hhgUPERF_tl_flush_expand_squads: Cycles Tile Lookup block sends out flush expand squads 8ihIPERF_tl_expand_squads: Cycles Tile Lookup block sends out expand squads jiEPERF_tl_preZ_squads: Cycles Tile Lookup block sends out preZ squads jPjGPERF_tl_postZ_squads: Cycles Tile Lookup block sends out postZ squads k kUPERF_tl_preZ_noop_squads: Cycles Tile Lookup block sends out noops on the preZ path llWPERF_tl_postZ_noop_squads: Cycles Tile Lookup block sends out noops on the postZ path pmlNPERF_tl_getZ_squads: Cycles Tile Lookup block sends out z import pass squads @nmEPERF_tl_tile_ops: Cycles Tile Lookup block sends out tile op squads on=PERF_tl_in_xfc: Cycles Tile Lookup block receives any input pPonPERF_tl_in_single_stencil_expand_stall: Cycles Tile Lookup block is stalling due to expanding single stencil pPpePERF_tl_in_constant_stencil_walk_stall: Cycles Tile Lookup block is stalling due to walking stencil q@qLPERF_tl_in_fast_z_stall: Cycles Tile Lookup block is stalling due to fastZ rrCPERF_tl_out_xfc: Cycles Tile Lookup block is sending anything out XsrDPERF_tl_out_squads: Cycles Tile Lookup block is sending squads out ptsPERF_zf_plane_multicycle: Cycles the z fetch is multicycling a squad because it needs to fetch more than 2 planes from the cache for compressed Z @utJPERF_PostZ_Samples_passing_Z: Samples passing Z test during a PostZ pass vuJPERF_PostZ_Samples_failing_Z: Samples failing Z test during a PostZ pass vXvPPERF_PostZ_Samples_failing_S: Samples failing Stencil test during a PostZ pass w0wHPERF_PreZ_Samples_passing_Z: Samples passing Z test during a PreZ pass xxHPERF_PreZ_Samples_failing_Z: Samples failing Z test during a PreZ pass `yxNPERF_PreZ_Samples_failing_S: Samples failing Stencil test during a PreZ pass @zyZPERF_ts_tc_update_stall: Cycles Tile Summarizer to Tile Cache write interface is stalled {z>PERF_sc_kick_start: Times the DB sent a hang panic to the SC {P{7PERF_sc_kick_end: Times the DB completed a hang panic ||>PERF_SX_DB_mem_exports: Number of memory exports from the SX h}|PPERF_SX_DB_mem_exports_acked: Number of memory export writes acked from the MC @~}PPERF_SX_DB_ack_mem_exports: Number of ack requested memory exports from the SX ~SPERF_SX_DB_ack_mem_exports_acked: Number of memory export acks returned to the SX `5PERF_mem_export_busy: Cycles writing memory exports Ѐ sPERF_mem_export_mi_stall: Cycles mem exports are stalled waiting for other DB writes or MC write bus arbitration. dPERF_mem_export_tag_stall: Cycles mem exports are stalled waiting for a free mem export write tag. x<PERF_clock_reg_active: Cycles register part of DB is awake 89PERF_clock_main_active: Cycles core part of DB is awake EPERF_clock_mem_export_active: Cycles mem export part of DB is awake ȄP7PERF_esr_out_busy: Early Squad Router Out cycles busy ;PERF_esr_out_sc_stall: Early Squad Router Out to SC stall hЅZPERF_esr_out_lquad_fifo_full_stall: Early Squad Router Out to Late Quad Fifo full stalls 0PERF_etr_out_send: Early Tile Router Out sends h6PERF_etr_out_busy: Early Tile Router Out cycles busy Ј(ePERF_etr_out_ltile_probe_fifo_full_stall: Early Tile Router Out to Late Tile Probe Fifo full stalls APERF_etr_out_cb_tile_stall: Early Tile Router to CB tile stalls IPERF_etr_out_esr_stall: Early Tile Router to Early Squad Router stalls. 螼0C""CDB2_PERFCOUNTER1_SELECTC(D PERF_SELDpD4PERF_SC_DB_tile_sends: Cycles Interface is sending E(E0PERF_SC_DB_tile_busy: Cycles Interface is busy XFE5PERF_SC_DB_tile_stalls: Cycles Interface is stalled GF4PERF_SC_DB_tile_events: Events sent over interface GXG2PERF_SC_DB_tile_tiles: Tiles sent over interface HH.PERF_SC_DB_tile_covered: Fully covered tiles PIHIPERF_hiz_tc_read_starved: HiZ starved waiting for htile data from cache JI=PERF_hiz_tc_write_stall: HiZ stalled writing to htile cache J`J5PERF_hiz_qtiles_culled: Quarter tiles culled by hiZ K K 5PERF_his_qtiles_culled: Quarter tiles culled by HiS PLK 4PERF_DB_SC_tile_sends: Cycles Interface is sending ML 0PERF_DB_SC_tile_busy: Cycles Interface is busy MPM ;PERF_DB_SC_tile_stalls: Cycles Interface is stalled by SC NN QPERF_DB_SC_tile_df_stalls: Cycles Interface is stalled by detail walk tile fifo XON2PERF_DB_SC_tile_tiles: Tiles sent over interface PO/PERF_DB_SC_tile_culled: Tiles culled in total PXPIPERF_DB_SC_tile_hier_kill: Tiles culled due to a hierarchical fail test Q(QSPERF_DB_SC_tile_fast_ops: Tiles culled because they were accerated fast tile ops. RRIPERF_DB_SC_tile_no_ops: Tiles culled because they would not do anything `SRTPERF_DB_SC_tile_pixel_rate: Tiles run at pixel rate as opposed to sample rate tile XTSqPERF_DB_SC_tile_ssaa_kill: Tiles culled because they were supersample tiles that are merged into a fast tile op PUTtPERF_DB_SC_tile_fast_z_ops: Tiles that operate on Z in 1 clock. Can be inside a slow, pixel rate, or fast tile op XVUPERF_DB_SC_tile_fast_stencil_ops: Tiles that operate on stencil in 1 clock. Can be inside a slow, pixel rate, or fast tile op WV4PERF_SC_DB_quad_sends: Cycles Interface is sending WXW0PERF_SC_DB_quad_busy: Cycles Interface is busy XX;PERF_SC_DB_quad_squads: Squads transferred over interface @YX2PERF_SC_DB_quad_tiles: Tiles sent over interface ZY:PERF_SC_DB_quad_pixels: Pixels transfered over interface ZHZ=PERF_SC_DB_quad_killed_tiles: Number of detail killed tiles [[4PERF_DB_SC_quad_sends: Cycles Interface is sending 8\[0PERF_DB_SC_quad_busy: Cycles Interface is busy \\5PERF_DB_SC_quad_stalls: Cycles Interface is stalled ]@] 4PERF_DB_SC_quad_squads: Squads sent over interface h^]!2PERF_DB_SC_quad_tiles: Tiles sent over interface 8_^"HPERF_DB_SC_quad_quads: Quads transferred over the DB_SC_quad interface 0`_#nPERF_DB_CB_tile_sends: Cycles sending tiles/events to CB. Tiles not shaded or needed by the CB are not sent. `x`$PERF_DB_CB_tile_busy: paa%PERF_DB_CB_tile_stalls: (ba&4PERF_SX_DB_quad_sends: Cycles Interface is sending bpb'0PERF_SX_DB_quad_busy: Cycles Interface is busy c(c(5PERF_SX_DB_quad_stalls: Cycles Interface is stalled Xdc)2PERF_SX_DB_quad_quads: Quads sent over interface ed*4PERF_SX_DB_quad_pixels: Pixels sent over interface eXe+APERF_SX_DB_quad_exports: Each MRT of a quad sent over interface f f,bPERF_SH_quads_outstanding_sum: Multiple by 128 and divide by DB_SC_quad_quads to get PS latency. gg-5PERF_DB_CB_lquad_sends: Cycles Interface is sending 8hg.1PERF_DB_CB_lquad_busy: Cycles Interface is busy hh/6PERF_DB_CB_lquad_stalls: Cycles Interface is stalled i@i03PERF_DB_CB_lquad_quads: Quads sent over interface hji1/PERF_tile_rd_sends: HTile reads. Each is 256B Xkj2hPERF_mi_tile_rd_outstanding_sum: Multiply by 2 and divide by tile_rd_sends to get htile memory latency lk3:PERF_quad_rd_sends: Quad read reqs. Each is 32B to 256B l`l4JPERF_quad_rd_busy: Cycles quad read interface is trying to send requests m0m5VPERF_quad_rd_mi_stall: Cycles quad read interface is stalled by the memory interface nn6XPERF_quad_rd_rw_collision: Cycles a quad read is stalled waiting for a write to finish on7ePERF_quad_rd_tag_stall: Cycles a quad read is stalled because the read latency hiding fifo is full. `po8@PERF_quad_rd_32byte_reqs: Number of 32 Byte quad read requests (qp9>PERF_quad_rd_panic: Cycles DB is panicing for quad read data (rpq:vPERF_mi_quad_rd_outstanding_sum: Multiply by 16 and divide by quad_rd_32byte_reqs to get depth buffer memory latency rpr;<PERF_quad_rdret_sends: Number of 32 byte quad read returns s0s<>PERF_quad_rdret_busy: Cycles the quad read data is returning `ts=*PERF_tile_wr_sends: 32 Byte HTile writes ut>-PERF_tile_wr_acks: 32 Byte Htile write acks v`u?nPERF_mi_tile_wr_outstanding_sum: Multiply by 16 and divide by tile_wr_sends to get tile write memory latency vXv@cPERF_quad_wr_sends: Cycles quad is sending write requests to the memory interface block of the DB w@wAKPERF_quad_wr_busy: Cycles quad is trying to write to the memory interface xxBUPERF_quad_wr_mi_stall: Cycles quad is stalled while writing to the memory interface yxCwPERF_quad_wr_coherency_stall: Cycles quad write is stalled waiting for a previous write to finish on the same address hzyD6PERF_quad_wr_acks: Number of 32 Byte quad write acks `{zErPERF_mi_quad_wr_outstanding_sum: Multiply by 16 and divide by the quad_wr_sends to get quad memory write latency |{F,PERF_Tile_Cache_misses: Htile Cache misses |X|G(PERF_Tile_Cache_hits: Htile Cache hits x}}H.PERF_Tile_Cache_flushes: Htile Cache flushes X~}I[PERF_Tile_Cache_surface_stall: Tile stalls waiting for an htile surface to flush and free 0~JMPERF_Tile_Cache_starves: Tile stalls waiting for an htile cacheline to free xK[PERF_Tile_Cache_mem_return_starve: Tile stalls waiting for an htile memory read to return XLYPERF_tcp_dispatcher_reads: Number of htile cachelines fetched by the normal tile stream ȁ8MQPERF_tcp_prefetcher_reads: Number of htile cachelines fetched by the prefetcher NOPERF_tcp_preloader_reads: Number of htile cachelines fetched by the preloader 肽OXPERF_tcp_dispatcher_flushes: Number of htile flushes caused byt the normal tile stream `ȃPWPERF_tcp_prefetcher_flushes: Number of htile flushes caused byt the normal prefetcher @QUPERF_tcp_preloader_flushes: Number of htile flushes caused byt the normal preloader RHPERF_Depth_Tile_Cache_sends: Tiles/Events through the Depth Tile Cache XSbPERF_Depth_Tile_Cache_busy: Cycles the Depth Tile Cache is busy testing hit/miss on tiles/events @T_PERF_Depth_Tile_Cache_starves: Cycles starved waiting for a depth surface tile tag to free up Ј(UgPERF_Depth_Tile_Cache_dtile_locked: Cycles stalled waiting for a forced flush or invalidate to finish VTPERF_Depth_Tile_Cache_alloc_stall: Cycles depth tile stalled while allocating data pW?PERF_Depth_Tile_Cache_misses: Depth/Stencil Cache tile misses 0X;PERF_Depth_Tile_Cache_hits: Depth/Stencil Cache tile hits xYAPERF_Depth_Tile_Cache_flushes: Depth/Stencil Cache tile flushes Ȍ@ZJPERF_Depth_Tile_Cache_noop_tile: Noop tiles through the depth tile cache [VPERF_Depth_Tile_Cache_detailed_noop: Detail walked noops though the depth tile cache X\%PERF_Depth_Tile_Cache_event: Events ]4PERF_Depth_Tile_Cache_tile_frees: Depth tile frees X^cPERF_Depth_Tile_Cache_data_frees: Depth tile data frees (may free data without freeing the dtile) 落@_ePERF_Depth_Tile_Cache_mem_return_starve: Cycles depth/stencil cache is waiting for memory to return 0`/PERF_Stencil_Cache_misses: 512 bit allocation @葽aPERF_Stencil_Cache_hits: 8bpPERF_Stencil_Cache_flushes: 256 bit flushes. Two per cacheline unless it is compressed, in which case it is 1. 0cmPERF_Stencil_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate ДxdPERF_Stencil_Cache_frees: xe"PERF_Z_Cache_separate_Z_misses: f PERF_Z_Cache_separate_Z_hits: Ȗhg#PERF_Z_Cache_separate_Z_flushes: hrPERF_Z_Cache_separate_Z_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate hiPERF_Z_Cache_pmask_misses: jPERF_Z_Cache_pmask_hits: PkPERF_Z_Cache_pmask_flushes: lmPERF_Z_Cache_pmask_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate HmPERF_Z_Cache_frees: 蛽nPERF_Plane_Cache_misses: 0oPERF_Plane_Cache_hits: (МpPERF_Plane_Cache_flushes: pqkPERF_Plane_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate `rPERF_Plane_Cache_frees: sGPERF_flush_expanded_stencil: Tiles flushed with with expanded stencil XПtKPERF_flush_compressed_stencil: Tiles flushed with with compressed stencil uCPERF_flush_single_stencil: Tiles flushed with with single stencil ءhv0PERF_flush_1plane: Tiles flushed with 1 ZPlane w1PERF_flush_2plane: Tiles flushed with 2 ZPlanes Hآx1PERF_flush_3plane: Tiles flushed with 3 ZPlanes y1PERF_flush_4plane: Tiles flushed with 4 ZPlanes Hz1PERF_flush_5plane: Tiles flushed with 5 ZPlanes p{1PERF_flush_6plane: Tiles flushed with 6 ZPlanes (|1PERF_flush_7plane: Tiles flushed with 7 ZPlanes ঽp}1PERF_flush_8plane: Tiles flushed with 8 ZPlanes (~1PERF_flush_9plane: Tiles flushed with 9 ZPlanes P৽3PERF_flush_10plane: Tiles flushed with 10 ZPlanes 3PERF_flush_11plane: Tiles flushed with 11 ZPlanes P3PERF_flush_12plane: Tiles flushed with 12 ZPlanes x3PERF_flush_13plane: Tiles flushed with 13 ZPlanes 03PERF_flush_14plane: Tiles flushed with 14 ZPlanes 諽x3PERF_flush_15plane: Tiles flushed with 15 ZPlanes 03PERF_flush_16plane: Tiles flushed with 16 ZPlanes `謽6PERF_flush_expanded_z: Tiles flushed with expanded Z H`PERF_earlyZ_waiting_for_postZ_done: Cycles stalled while transitioning from Late/ReZ to EarlyZ @rPERF_reZ_waiting_for_postZ_done: Cycles stalled while transitioning to ReZ from an incompatible Z mode/func/etc. @PERF_dk_tile_sends: Detail kill block tiles/squads/events sent P2PERF_dk_tile_busy: Cycles Detail Kill block busy ZPERF_dk_tile_quad_starves: Cycles Detail Kill has tile, but no quads from the SC_DB_quad h豽?PERF_dk_tile_stalls: Cycles Detail Kill is stalled from below )PERF_dk_squad_sends: Detail Kill squads ೽`@PERF_dk_squad_busy: Cycles the squad Detail Kill input is busy (=PERF_dk_squad_stalls: Cycles squads are stalled from below. rPERF_Op_Pipe_Busy: Cycles the quad OP pipe of the DB is busy (including memory fetches, but not initial startup) 赽kPERF_Op_Pipe_MC_Read_stall: Cycles the Op Pipe is waiting for memory to return (ignoring initial startup) Hض1PERF_qc_busy: Cycles the Quad Coherency is busy CPERF_qc_xfc: Number of transfers through the Quad Coherency block XPERF_qc_conflicts: Stalls on a squad input because of a coherency check conflict (the same sample ahead of it could affect the dest data) hKPERF_qc_full_stall: Quad Coherency is stalled because it is out of slots. 8PERF_qc_in_preZ_tile_stalls_postZ: Cycles postZ squad inputs are stalled because the OP pipe is operating on a preZ tile, and there is no PreZ squad input available PhPERF_qc_in_postZ_tile_stalls_preZ: Cycles preZ squad inputs are stalled because the OP pipe is operating on a postZ tile, and there is no PostZ squad input available HrPERF_tsc_insert_summarize_stall: Cycles the op pipe is stalled by the tile summarizer inserting summarize squads -PERF_tl_busy: Cycles Tile Lookup block busy H4PERF_tl_dtc_read_starved: Cycles Tile Lookup block IPERF_tl_z_fetch_stall: Cycles Tile Lookup block stalled by zfetch block `пOPERF_tl_stencil_stall: Cycles Tile Lookup block stalled by stencil test block 8TPERF_tl_z_decompress_stall: Cycles Tile Lookup block stalled by z decompress block ½XPERF_tl_stencil_locked_stall: Cycles Tile Lookup block stalled by stencil being locked ½`½;PERF_tl_events: Cycles Tile Lookup block sends out events ý ýOPERF_tl_summarize_squads: Cycles Tile Lookup block sends out summarize squads ĽýUPERF_tl_flush_expand_squads: Cycles Tile Lookup block sends out flush expand squads `ŽĽIPERF_tl_expand_squads: Cycles Tile Lookup block sends out expand squads 0ƽŽEPERF_tl_preZ_squads: Cycles Tile Lookup block sends out preZ squads ǽxƽGPERF_tl_postZ_squads: Cycles Tile Lookup block sends out postZ squads ǽHǽUPERF_tl_preZ_noop_squads: Cycles Tile Lookup block sends out noops on the preZ path Ƚ(ȽWPERF_tl_postZ_noop_squads: Cycles Tile Lookup block sends out noops on the postZ path ɽɽNPERF_tl_getZ_squads: Cycles Tile Lookup block sends out z import pass squads hʽɽEPERF_tl_tile_ops: Cycles Tile Lookup block sends out tile op squads 0˽ʽ=PERF_tl_in_xfc: Cycles Tile Lookup block receives any input (̽x˽nPERF_tl_in_single_stencil_expand_stall: Cycles Tile Lookup block is stalling due to expanding single stencil ͽp̽ePERF_tl_in_constant_stencil_walk_stall: Cycles Tile Lookup block is stalling due to walking stencil ͽ`ͽLPERF_tl_in_fast_z_stall: Cycles Tile Lookup block is stalling due to fastZ ν0νCPERF_tl_out_xfc: Cycles Tile Lookup block is sending anything out xϽνDPERF_tl_out_squads: Cycles Tile Lookup block is sending squads out нϽPERF_zf_plane_multicycle: Cycles the z fetch is multicycling a squad because it needs to fetch more than 2 planes from the cache for compressed Z `ѽнJPERF_PostZ_Samples_passing_Z: Samples passing Z test during a PostZ pass 0ҽѽJPERF_PostZ_Samples_failing_Z: Samples failing Z test during a PostZ pass ӽxҽPPERF_PostZ_Samples_failing_S: Samples failing Stencil test during a PostZ pass ӽPӽHPERF_PreZ_Samples_passing_Z: Samples passing Z test during a PreZ pass Խ ԽHPERF_PreZ_Samples_failing_Z: Samples failing Z test during a PreZ pass սԽNPERF_PreZ_Samples_failing_S: Samples failing Stencil test during a PreZ pass `ֽսZPERF_ts_tc_update_stall: Cycles Tile Summarizer to Tile Cache write interface is stalled (׽ֽ>PERF_sc_kick_start: Times the DB sent a hang panic to the SC ׽p׽7PERF_sc_kick_end: Times the DB completed a hang panic ؽ0ؽ>PERF_SX_DB_mem_exports: Number of memory exports from the SX ٽؽPPERF_SX_DB_mem_exports_acked: Number of memory export writes acked from the MC `ڽٽPPERF_SX_DB_ack_mem_exports: Number of ack requested memory exports from the SX 8۽ڽSPERF_SX_DB_ack_mem_exports_acked: Number of memory export acks returned to the SX ۽۽5PERF_mem_export_busy: Cycles writing memory exports ܽ@ܽsPERF_mem_export_mi_stall: Cycles mem exports are stalled waiting for other DB writes or MC write bus arbitration. ݽ8ݽdPERF_mem_export_tag_stall: Cycles mem exports are stalled waiting for a free mem export write tag. ޽ ޽<PERF_clock_reg_active: Cycles register part of DB is awake X߽޽9PERF_clock_main_active: Cycles core part of DB is awake (߽EPERF_clock_mem_export_active: Cycles mem export part of DB is awake p7PERF_esr_out_busy: Early Squad Router Out cycles busy 0;PERF_esr_out_sc_stall: Early Squad Router Out to SC stall ZPERF_esr_out_lquad_fifo_full_stall: Early Squad Router Out to Late Quad Fifo full stalls @0PERF_etr_out_send: Early Tile Router Out sends 6PERF_etr_out_busy: Early Tile Router Out cycles busy HePERF_etr_out_ltile_probe_fifo_full_stall: Early Tile Router Out to Late Tile Probe Fifo full stalls 8APERF_etr_out_cb_tile_stall: Early Tile Router to CB tile stalls IPERF_etr_out_esr_stall: Early Tile Router to Early Squad Router stalls. `""DB2_PERFCOUNTER0_SELECTX PERF_SEL4PERF_SC_DB_tile_sends: Cycles Interface is sending ȡX0PERF_SC_DB_tile_busy: Cycles Interface is busy 5PERF_SC_DB_tile_stalls: Cycles Interface is stalled @Т4PERF_SC_DB_tile_events: Events sent over interface 2PERF_SC_DB_tile_tiles: Tiles sent over interface @.PERF_SC_DB_tile_covered: Fully covered tiles IPERF_hiz_tc_read_starved: HiZ starved waiting for htile data from cache Hȥ=PERF_hiz_tc_write_stall: HiZ stalled writing to htile cache 5PERF_hiz_qtiles_culled: Quarter tiles culled by hiZ ȧP 5PERF_his_qtiles_culled: Quarter tiles culled by HiS  4PERF_DB_SC_tile_sends: Cycles Interface is sending 8Ȩ 0PERF_DB_SC_tile_busy: Cycles Interface is busy ;PERF_DB_SC_tile_stalls: Cycles Interface is stalled by SC Ъ@ QPERF_DB_SC_tile_df_stalls: Cycles Interface is stalled by detail walk tile fifo 2PERF_DB_SC_tile_tiles: Tiles sent over interface @Ы/PERF_DB_SC_tile_culled: Tiles culled in total IPERF_DB_SC_tile_hier_kill: Tiles culled due to a hierarchical fail test 譼XSPERF_DB_SC_tile_fast_ops: Tiles culled because they were accerated fast tile ops. 0IPERF_DB_SC_tile_no_ops: Tiles culled because they would not do anything TPERF_DB_SC_tile_pixel_rate: Tiles run at pixel rate as opposed to sample rate tile دqPERF_DB_SC_tile_ssaa_kill: Tiles culled because they were supersample tiles that are merged into a fast tile op аtPERF_DB_SC_tile_fast_z_ops: Tiles that operate on Z in 1 clock. Can be inside a slow, pixel rate, or fast tile op ȱPERF_DB_SC_tile_fast_stencil_ops: Tiles that operate on stencil in 1 clock. Can be inside a slow, pixel rate, or fast tile op @в4PERF_SC_DB_quad_sends: Cycles Interface is sending 0PERF_SC_DB_quad_busy: Cycles Interface is busy @;PERF_SC_DB_quad_squads: Squads transferred over interface p2PERF_SC_DB_quad_tiles: Tiles sent over interface 0:PERF_SC_DB_quad_pixels: Pixels transfered over interface x=PERF_SC_DB_quad_killed_tiles: Number of detail killed tiles @4PERF_DB_SC_quad_sends: Cycles Interface is sending h0PERF_DB_SC_quad_busy: Cycles Interface is busy (5PERF_DB_SC_quad_stalls: Cycles Interface is stalled ๼p 4PERF_DB_SC_quad_squads: Squads sent over interface (!2PERF_DB_SC_quad_tiles: Tiles sent over interface hຼ"HPERF_DB_SC_quad_quads: Quads transferred over the DB_SC_quad interface `#nPERF_DB_CB_tile_sends: Cycles sending tiles/events to CB. Tiles not shaded or needed by the CB are not sent. $PERF_DB_CB_tile_busy: H%PERF_DB_CB_tile_stalls: X轼&4PERF_SX_DB_quad_sends: Cycles Interface is sending '0PERF_SX_DB_quad_busy: Cycles Interface is busy пX(5PERF_SX_DB_quad_stalls: Cycles Interface is stalled )2PERF_SX_DB_quad_quads: Quads sent over interface @*4PERF_SX_DB_quad_pixels: Pixels sent over interface ¼+APERF_SX_DB_quad_exports: Each MRT of a quad sent over interface ¼P¼,bPERF_SH_quads_outstanding_sum: Multiple by 128 and divide by DB_SC_quad_quads to get PS latency. ü8ü-5PERF_DB_CB_lquad_sends: Cycles Interface is sending hļü.1PERF_DB_CB_lquad_busy: Cycles Interface is busy (żļ/6PERF_DB_CB_lquad_stalls: Cycles Interface is stalled żpż03PERF_DB_CB_lquad_quads: Quads sent over interface Ƽ(Ƽ1/PERF_tile_rd_sends: HTile reads. Each is 256B ǼƼ2hPERF_mi_tile_rd_outstanding_sum: Multiply by 2 and divide by tile_rd_sends to get htile memory latency HȼǼ3:PERF_quad_rd_sends: Quad read reqs. Each is 32B to 256B ɼȼ4JPERF_quad_rd_busy: Cycles quad read interface is trying to send requests ɼ`ɼ5VPERF_quad_rd_mi_stall: Cycles quad read interface is stalled by the memory interface ʼ@ʼ6XPERF_quad_rd_rw_collision: Cycles a quad read is stalled waiting for a write to finish ˼ ˼7ePERF_quad_rd_tag_stall: Cycles a quad read is stalled because the read latency hiding fifo is full. ̼̼8@PERF_quad_rd_32byte_reqs: Number of 32 Byte quad read requests Xͼ̼9>PERF_quad_rd_panic: Cycles DB is panicing for quad read data Xμͼ:vPERF_mi_quad_rd_outstanding_sum: Multiply by 16 and divide by quad_rd_32byte_reqs to get depth buffer memory latency ϼμ;<PERF_quad_rdret_sends: Number of 32 byte quad read returns ϼ`ϼ<>PERF_quad_rdret_busy: Cycles the quad read data is returning м(м=*PERF_tile_wr_sends: 32 Byte HTile writes HѼм>-PERF_tile_wr_acks: 32 Byte Htile write acks @ҼѼ?nPERF_mi_tile_wr_outstanding_sum: Multiply by 16 and divide by tile_wr_sends to get tile write memory latency (ӼҼ@cPERF_quad_wr_sends: Cycles quad is sending write requests to the memory interface block of the DB ӼpӼAKPERF_quad_wr_busy: Cycles quad is trying to write to the memory interface Լ@ԼBUPERF_quad_wr_mi_stall: Cycles quad is stalled while writing to the memory interface ռ ռCwPERF_quad_wr_coherency_stall: Cycles quad write is stalled waiting for a previous write to finish on the same address ּ ּD6PERF_quad_wr_acks: Number of 32 Byte quad write acks ׼ּErPERF_mi_quad_wr_outstanding_sum: Multiply by 16 and divide by the quad_wr_sends to get quad memory write latency @ؼ׼F,PERF_Tile_Cache_misses: Htile Cache misses ؼؼG(PERF_Tile_Cache_hits: Htile Cache hits ټ8ټH.PERF_Tile_Cache_flushes: Htile Cache flushes ڼټI[PERF_Tile_Cache_surface_stall: Tile stalls waiting for an htile surface to flush and free `ۼڼJMPERF_Tile_Cache_starves: Tile stalls waiting for an htile cacheline to free @ܼۼK[PERF_Tile_Cache_mem_return_starve: Tile stalls waiting for an htile memory read to return ݼܼLYPERF_tcp_dispatcher_reads: Number of htile cachelines fetched by the normal tile stream ݼhݼMQPERF_tcp_prefetcher_reads: Number of htile cachelines fetched by the prefetcher ޼@޼NOPERF_tcp_preloader_reads: Number of htile cachelines fetched by the preloader ߼߼OXPERF_tcp_dispatcher_flushes: Number of htile flushes caused byt the normal tile stream ߼PWPERF_tcp_prefetcher_flushes: Number of htile flushes caused byt the normal prefetcher pQUPERF_tcp_preloader_flushes: Number of htile flushes caused byt the normal preloader @RHPERF_Depth_Tile_Cache_sends: Tiles/Events through the Depth Tile Cache (SbPERF_Depth_Tile_Cache_busy: Cycles the Depth Tile Cache is busy testing hit/miss on tiles/events pT_PERF_Depth_Tile_Cache_starves: Cycles starved waiting for a depth surface tile tag to free up XUgPERF_Depth_Tile_Cache_dtile_locked: Cycles stalled waiting for a forced flush or invalidate to finish HVTPERF_Depth_Tile_Cache_alloc_stall: Cycles depth tile stalled while allocating data W?PERF_Depth_Tile_Cache_misses: Depth/Stencil Cache tile misses `X;PERF_Depth_Tile_Cache_hits: Depth/Stencil Cache tile hits (YAPERF_Depth_Tile_Cache_flushes: Depth/Stencil Cache tile flushes pZJPERF_Depth_Tile_Cache_noop_tile: Noop tiles through the depth tile cache @[VPERF_Depth_Tile_Cache_detailed_noop: Detail walked noops though the depth tile cache \%PERF_Depth_Tile_Cache_event: Events @]4PERF_Depth_Tile_Cache_tile_frees: Depth tile frees (^cPERF_Depth_Tile_Cache_data_frees: Depth tile data frees (may free data without freeing the dtile) p_ePERF_Depth_Tile_Cache_mem_return_starve: Cycles depth/stencil cache is waiting for memory to return ``/PERF_Stencil_Cache_misses: 512 bit allocation paPERF_Stencil_Cache_hits: hbpPERF_Stencil_Cache_flushes: 256 bit flushes. Two per cacheline unless it is compressed, in which case it is 1. `cmPERF_Stencil_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate dPERF_Stencil_Cache_frees: He"PERF_Z_Cache_separate_Z_misses: Pf PERF_Z_Cache_separate_Z_hits: g#PERF_Z_Cache_separate_Z_flushes: @hrPERF_Z_Cache_separate_Z_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate 8iPERF_Z_Cache_pmask_misses: 8jPERF_Z_Cache_pmask_hits: kPERF_Z_Cache_pmask_flushes: (lmPERF_Z_Cache_pmask_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate x mPERF_Z_Cache_frees: nPERF_Plane_Cache_misses: `oPERF_Plane_Cache_hits: XpPERF_Plane_Cache_flushes: HqkPERF_Plane_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate rPERF_Plane_Cache_frees: 0sGPERF_flush_expanded_stencil: Tiles flushed with with expanded stencil tKPERF_flush_compressed_stencil: Tiles flushed with with compressed stencil PuCPERF_flush_single_stencil: Tiles flushed with with single stencil v0PERF_flush_1plane: Tiles flushed with 1 ZPlane Pw1PERF_flush_2plane: Tiles flushed with 2 ZPlanes xx1PERF_flush_3plane: Tiles flushed with 3 ZPlanes 0y1PERF_flush_4plane: Tiles flushed with 4 ZPlanes xz1PERF_flush_5plane: Tiles flushed with 5 ZPlanes 0{1PERF_flush_6plane: Tiles flushed with 6 ZPlanes X|1PERF_flush_7plane: Tiles flushed with 7 ZPlanes }1PERF_flush_8plane: Tiles flushed with 8 ZPlanes X~1PERF_flush_9plane: Tiles flushed with 9 ZPlanes 3PERF_flush_10plane: Tiles flushed with 10 ZPlanes 83PERF_flush_11plane: Tiles flushed with 11 ZPlanes 3PERF_flush_12plane: Tiles flushed with 12 ZPlanes 83PERF_flush_13plane: Tiles flushed with 13 ZPlanes `3PERF_flush_14plane: Tiles flushed with 14 ZPlanes 3PERF_flush_15plane: Tiles flushed with 15 ZPlanes `3PERF_flush_16plane: Tiles flushed with 16 ZPlanes  6PERF_flush_expanded_z: Tiles flushed with expanded Z x `PERF_earlyZ_waiting_for_postZ_done: Cycles stalled while transitioning from Late/ReZ to EarlyZ p rPERF_reZ_waiting_for_postZ_done: Cycles stalled while transitioning to ReZ from an incompatible Z mode/func/etc. 8 @PERF_dk_tile_sends: Detail kill block tiles/squads/events sent 2PERF_dk_tile_busy: Cycles Detail Kill block busy 8 ZPERF_dk_tile_quad_starves: Cycles Detail Kill has tile, but no quads from the SC_DB_quad ?PERF_dk_tile_stalls: Cycles Detail Kill is stalled from below H)PERF_dk_squad_sends: Detail Kill squads @PERF_dk_squad_busy: Cycles the squad Detail Kill input is busy X=PERF_dk_squad_stalls: Cycles squads are stalled from below.  rPERF_Op_Pipe_Busy: Cycles the quad OP pipe of the DB is busy (including memory fetches, but not initial startup) kPERF_Op_Pipe_MC_Read_stall: Cycles the Op Pipe is waiting for memory to return (ignoring initial startup) x1PERF_qc_busy: Cycles the Quad Coherency is busy @CPERF_qc_xfc: Number of transfers through the Quad Coherency block PPERF_qc_conflicts: Stalls on a squad input because of a coherency check conflict (the same sample ahead of it could affect the dest data) KPERF_qc_full_stall: Quad Coherency is stalled because it is out of slots. PhPERF_qc_in_preZ_tile_stalls_postZ: Cycles postZ squad inputs are stalled because the OP pipe is operating on a preZ tile, and there is no PreZ squad input available PERF_qc_in_postZ_tile_stalls_preZ: Cycles preZ squad inputs are stalled because the OP pipe is operating on a postZ tile, and there is no PostZ squad input available xrPERF_tsc_insert_summarize_stall: Cycles the op pipe is stalled by the tile summarizer inserting summarize squads 0-PERF_tl_busy: Cycles Tile Lookup block busy x4PERF_tl_dtc_read_starved: Cycles Tile Lookup block 0IPERF_tl_z_fetch_stall: Cycles Tile Lookup block stalled by zfetch block OPERF_tl_stencil_stall: Cycles Tile Lookup block stalled by stencil test block hTPERF_tl_z_decompress_stall: Cycles Tile Lookup block stalled by z decompress block HXPERF_tl_stencil_locked_stall: Cycles Tile Lookup block stalled by stencil being locked ;PERF_tl_events: Cycles Tile Lookup block sends out events POPERF_tl_summarize_squads: Cycles Tile Lookup block sends out summarize squads ( UPERF_tl_flush_expand_squads: Cycles Tile Lookup block sends out flush expand squads !!IPERF_tl_expand_squads: Cycles Tile Lookup block sends out expand squads `"!EPERF_tl_preZ_squads: Cycles Tile Lookup block sends out preZ squads 0#"GPERF_tl_postZ_squads: Cycles Tile Lookup block sends out postZ squads $x#UPERF_tl_preZ_noop_squads: Cycles Tile Lookup block sends out noops on the preZ path $X$WPERF_tl_postZ_noop_squads: Cycles Tile Lookup block sends out noops on the postZ path %8%NPERF_tl_getZ_squads: Cycles Tile Lookup block sends out z import pass squads &&EPERF_tl_tile_ops: Cycles Tile Lookup block sends out tile op squads `'&=PERF_tl_in_xfc: Cycles Tile Lookup block receives any input X('nPERF_tl_in_single_stencil_expand_stall: Cycles Tile Lookup block is stalling due to expanding single stencil H)(ePERF_tl_in_constant_stencil_walk_stall: Cycles Tile Lookup block is stalling due to walking stencil *)LPERF_tl_in_fast_z_stall: Cycles Tile Lookup block is stalling due to fastZ *`*CPERF_tl_out_xfc: Cycles Tile Lookup block is sending anything out +(+DPERF_tl_out_squads: Cycles Tile Lookup block is sending squads out ,+PERF_zf_plane_multicycle: Cycles the z fetch is multicycling a squad because it needs to fetch more than 2 planes from the cache for compressed Z --JPERF_PostZ_Samples_passing_Z: Samples passing Z test during a PostZ pass `.-JPERF_PostZ_Samples_failing_Z: Samples failing Z test during a PostZ pass 8/.PPERF_PostZ_Samples_failing_S: Samples failing Stencil test during a PostZ pass 0/HPERF_PreZ_Samples_passing_Z: Samples passing Z test during a PreZ pass 0P0HPERF_PreZ_Samples_failing_Z: Samples failing Z test during a PreZ pass 1 1NPERF_PreZ_Samples_failing_S: Samples failing Stencil test during a PreZ pass 21ZPERF_ts_tc_update_stall: Cycles Tile Summarizer to Tile Cache write interface is stalled X32>PERF_sc_kick_start: Times the DB sent a hang panic to the SC 437PERF_sc_kick_end: Times the DB completed a hang panic 4`4>PERF_SX_DB_mem_exports: Number of memory exports from the SX 5(5PPERF_SX_DB_mem_exports_acked: Number of memory export writes acked from the MC 66PPERF_SX_DB_ack_mem_exports: Number of ack requested memory exports from the SX h76SPERF_SX_DB_ack_mem_exports_acked: Number of memory export acks returned to the SX (875PERF_mem_export_busy: Cycles writing memory exports 9p8sPERF_mem_export_mi_stall: Cycles mem exports are stalled waiting for other DB writes or MC write bus arbitration. :h9dPERF_mem_export_tag_stall: Cycles mem exports are stalled waiting for a free mem export write tag. :P:<PERF_clock_reg_active: Cycles register part of DB is awake ;;9PERF_clock_main_active: Cycles core part of DB is awake X<;EPERF_clock_mem_export_active: Cycles mem export part of DB is awake =<7PERF_esr_out_busy: Early Squad Router Out cycles busy =`=;PERF_esr_out_sc_stall: Early Squad Router Out to SC stall > >ZPERF_esr_out_lquad_fifo_full_stall: Early Squad Router Out to Late Quad Fifo full stalls p??0PERF_etr_out_send: Early Tile Router Out sends 0@?6PERF_etr_out_busy: Early Tile Router Out cycles busy Ax@ePERF_etr_out_ltile_probe_fifo_full_stall: Early Tile Router Out to Late Tile Probe Fifo full stalls AhAAPERF_etr_out_cb_tile_stall: Early Tile Router to CB tile stalls 0BIPERF_etr_out_esr_stall: Early Tile Router to Early Squad Router stalls. ll""HDB1_PERFCOUNTER3_HI PERF_COUNT"``""DB1_PERFCOUNTER2_HI8 PERF_COUNT"H(TT""xDB1_PERFCOUNTER1_HIЛ PERF_COUNT"ؗHH""DB1_PERFCOUNTER0_HIh PERF_COUNT"hPhh""DB1_PERFCOUNTER3_LOW PERF_COUNT"\\""8DB1_PERFCOUNTER2_LOW PERF_COUNT"pPP""ȕDB1_PERFCOUNTER1_LOW  PERF_COUNT"DD""XDB1_PERFCOUNTER0_LOW PERF_COUNT"K0dd""DB1_PERFCOUNTER3_SELECT( PERF_SELp4PERF_SC_DB_tile_sends: Cycles Interface is sending (0PERF_SC_DB_tile_busy: Cycles Interface is busy X5PERF_SC_DB_tile_stalls: Cycles Interface is stalled 4PERF_SC_DB_tile_events: Events sent over interface X2PERF_SC_DB_tile_tiles: Tiles sent over interface .PERF_SC_DB_tile_covered: Fully covered tiles PIPERF_hiz_tc_read_starved: HiZ starved waiting for htile data from cache =PERF_hiz_tc_write_stall: HiZ stalled writing to htile cache `5PERF_hiz_qtiles_culled: Quarter tiles culled by hiZ 5PERF_his_qtiles_culled: Quarter tiles culled by HiS P 4PERF_DB_SC_tile_sends: Cycles Interface is sending  0PERF_DB_SC_tile_busy: Cycles Interface is busy P ;PERF_DB_SC_tile_stalls: Cycles Interface is stalled by SC  QPERF_DB_SC_tile_df_stalls: Cycles Interface is stalled by detail walk tile fifo X2PERF_DB_SC_tile_tiles: Tiles sent over interface /PERF_DB_SC_tile_culled: Tiles culled in total XIPERF_DB_SC_tile_hier_kill: Tiles culled due to a hierarchical fail test (SPERF_DB_SC_tile_fast_ops: Tiles culled because they were accerated fast tile ops. IPERF_DB_SC_tile_no_ops: Tiles culled because they would not do anything `TPERF_DB_SC_tile_pixel_rate: Tiles run at pixel rate as opposed to sample rate tile XqPERF_DB_SC_tile_ssaa_kill: Tiles culled because they were supersample tiles that are merged into a fast tile op PtPERF_DB_SC_tile_fast_z_ops: Tiles that operate on Z in 1 clock. Can be inside a slow, pixel rate, or fast tile op XPERF_DB_SC_tile_fast_stencil_ops: Tiles that operate on stencil in 1 clock. Can be inside a slow, pixel rate, or fast tile op 4PERF_SC_DB_quad_sends: Cycles Interface is sending X0PERF_SC_DB_quad_busy: Cycles Interface is busy ;PERF_SC_DB_quad_squads: Squads transferred over interface @2PERF_SC_DB_quad_tiles: Tiles sent over interface :PERF_SC_DB_quad_pixels: Pixels transfered over interface H=PERF_SC_DB_quad_killed_tiles: Number of detail killed tiles 4PERF_DB_SC_quad_sends: Cycles Interface is sending 8 0PERF_DB_SC_quad_busy: Cycles Interface is busy 5PERF_DB_SC_quad_stalls: Cycles Interface is stalled @ 4PERF_DB_SC_quad_squads: Squads sent over interface h !2PERF_DB_SC_quad_tiles: Tiles sent over interface 8 "HPERF_DB_SC_quad_quads: Quads transferred over the DB_SC_quad interface 0 #nPERF_DB_CB_tile_sends: Cycles sending tiles/events to CB. Tiles not shaded or needed by the CB are not sent. x $PERF_DB_CB_tile_busy: p%PERF_DB_CB_tile_stalls: (&4PERF_SX_DB_quad_sends: Cycles Interface is sending p'0PERF_SX_DB_quad_busy: Cycles Interface is busy ((5PERF_SX_DB_quad_stalls: Cycles Interface is stalled X)2PERF_SX_DB_quad_quads: Quads sent over interface *4PERF_SX_DB_quad_pixels: Pixels sent over interface X+APERF_SX_DB_quad_exports: Each MRT of a quad sent over interface  ,bPERF_SH_quads_outstanding_sum: Multiple by 128 and divide by DB_SC_quad_quads to get PS latency. -5PERF_DB_CB_lquad_sends: Cycles Interface is sending 8.1PERF_DB_CB_lquad_busy: Cycles Interface is busy /6PERF_DB_CB_lquad_stalls: Cycles Interface is stalled @03PERF_DB_CB_lquad_quads: Quads sent over interface h1/PERF_tile_rd_sends: HTile reads. Each is 256B X2hPERF_mi_tile_rd_outstanding_sum: Multiply by 2 and divide by tile_rd_sends to get htile memory latency 3:PERF_quad_rd_sends: Quad read reqs. Each is 32B to 256B `4JPERF_quad_rd_busy: Cycles quad read interface is trying to send requests 05VPERF_quad_rd_mi_stall: Cycles quad read interface is stalled by the memory interface 6XPERF_quad_rd_rw_collision: Cycles a quad read is stalled waiting for a write to finish 7ePERF_quad_rd_tag_stall: Cycles a quad read is stalled because the read latency hiding fifo is full. `8@PERF_quad_rd_32byte_reqs: Number of 32 Byte quad read requests (9>PERF_quad_rd_panic: Cycles DB is panicing for quad read data (p:vPERF_mi_quad_rd_outstanding_sum: Multiply by 16 and divide by quad_rd_32byte_reqs to get depth buffer memory latency p;<PERF_quad_rdret_sends: Number of 32 byte quad read returns 0 <>PERF_quad_rdret_busy: Cycles the quad read data is returning `! =*PERF_tile_wr_sends: 32 Byte HTile writes "!>-PERF_tile_wr_acks: 32 Byte Htile write acks #`"?nPERF_mi_tile_wr_outstanding_sum: Multiply by 16 and divide by tile_wr_sends to get tile write memory latency #X#@cPERF_quad_wr_sends: Cycles quad is sending write requests to the memory interface block of the DB $@$AKPERF_quad_wr_busy: Cycles quad is trying to write to the memory interface %%BUPERF_quad_wr_mi_stall: Cycles quad is stalled while writing to the memory interface &%CwPERF_quad_wr_coherency_stall: Cycles quad write is stalled waiting for a previous write to finish on the same address h'&D6PERF_quad_wr_acks: Number of 32 Byte quad write acks `('ErPERF_mi_quad_wr_outstanding_sum: Multiply by 16 and divide by the quad_wr_sends to get quad memory write latency )(F,PERF_Tile_Cache_misses: Htile Cache misses )X)G(PERF_Tile_Cache_hits: Htile Cache hits x**H.PERF_Tile_Cache_flushes: Htile Cache flushes X+*I[PERF_Tile_Cache_surface_stall: Tile stalls waiting for an htile surface to flush and free 0,+JMPERF_Tile_Cache_starves: Tile stalls waiting for an htile cacheline to free -x,K[PERF_Tile_Cache_mem_return_starve: Tile stalls waiting for an htile memory read to return -X-LYPERF_tcp_dispatcher_reads: Number of htile cachelines fetched by the normal tile stream .8.MQPERF_tcp_prefetcher_reads: Number of htile cachelines fetched by the prefetcher //NOPERF_tcp_preloader_reads: Number of htile cachelines fetched by the preloader 0/OXPERF_tcp_dispatcher_flushes: Number of htile flushes caused byt the normal tile stream `10PWPERF_tcp_prefetcher_flushes: Number of htile flushes caused byt the normal prefetcher @21QUPERF_tcp_preloader_flushes: Number of htile flushes caused byt the normal preloader 32RHPERF_Depth_Tile_Cache_sends: Tiles/Events through the Depth Tile Cache 3X3SbPERF_Depth_Tile_Cache_busy: Cycles the Depth Tile Cache is busy testing hit/miss on tiles/events 4@4T_PERF_Depth_Tile_Cache_starves: Cycles starved waiting for a depth surface tile tag to free up 5(5UgPERF_Depth_Tile_Cache_dtile_locked: Cycles stalled waiting for a forced flush or invalidate to finish 66VTPERF_Depth_Tile_Cache_alloc_stall: Cycles depth tile stalled while allocating data p76W?PERF_Depth_Tile_Cache_misses: Depth/Stencil Cache tile misses 087X;PERF_Depth_Tile_Cache_hits: Depth/Stencil Cache tile hits 8x8YAPERF_Depth_Tile_Cache_flushes: Depth/Stencil Cache tile flushes 9@9ZJPERF_Depth_Tile_Cache_noop_tile: Noop tiles through the depth tile cache ::[VPERF_Depth_Tile_Cache_detailed_noop: Detail walked noops though the depth tile cache X;:\%PERF_Depth_Tile_Cache_event: Events <;]4PERF_Depth_Tile_Cache_tile_frees: Depth tile frees <X<^cPERF_Depth_Tile_Cache_data_frees: Depth tile data frees (may free data without freeing the dtile) =@=_ePERF_Depth_Tile_Cache_mem_return_starve: Cycles depth/stencil cache is waiting for memory to return >0>`/PERF_Stencil_Cache_misses: 512 bit allocation @?>aPERF_Stencil_Cache_hits: 8@?bpPERF_Stencil_Cache_flushes: 256 bit flushes. Two per cacheline unless it is compressed, in which case it is 1. 0A@cmPERF_Stencil_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate AxAdPERF_Stencil_Cache_frees: xBBe"PERF_Z_Cache_separate_Z_misses: CBf PERF_Z_Cache_separate_Z_hits: ChCg#PERF_Z_Cache_separate_Z_flushes: DDhrPERF_Z_Cache_separate_Z_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate hEEiPERF_Z_Cache_pmask_misses: FEjPERF_Z_Cache_pmask_hits: FPFkPERF_Z_Cache_pmask_flushes: GFlmPERF_Z_Cache_pmask_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate HHGmPERF_Z_Cache_frees: HHnPERF_Plane_Cache_misses: I0IoPERF_Plane_Cache_hits: (JIpPERF_Plane_Cache_flushes: KpJqkPERF_Plane_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate K`KrPERF_Plane_Cache_frees: LLsGPERF_flush_expanded_stencil: Tiles flushed with with expanded stencil XMLtKPERF_flush_compressed_stencil: Tiles flushed with with compressed stencil NMuCPERF_flush_single_stencil: Tiles flushed with with single stencil NhNv0PERF_flush_1plane: Tiles flushed with 1 ZPlane O Ow1PERF_flush_2plane: Tiles flushed with 2 ZPlanes HPOx1PERF_flush_3plane: Tiles flushed with 3 ZPlanes QPy1PERF_flush_4plane: Tiles flushed with 4 ZPlanes QHQz1PERF_flush_5plane: Tiles flushed with 5 ZPlanes pRR{1PERF_flush_6plane: Tiles flushed with 6 ZPlanes (SR|1PERF_flush_7plane: Tiles flushed with 7 ZPlanes SpS}1PERF_flush_8plane: Tiles flushed with 8 ZPlanes T(T~1PERF_flush_9plane: Tiles flushed with 9 ZPlanes PUT3PERF_flush_10plane: Tiles flushed with 10 ZPlanes VU3PERF_flush_11plane: Tiles flushed with 11 ZPlanes VPV3PERF_flush_12plane: Tiles flushed with 12 ZPlanes xWW3PERF_flush_13plane: Tiles flushed with 13 ZPlanes 0XW3PERF_flush_14plane: Tiles flushed with 14 ZPlanes XxX3PERF_flush_15plane: Tiles flushed with 15 ZPlanes Y0Y3PERF_flush_16plane: Tiles flushed with 16 ZPlanes `ZY6PERF_flush_expanded_z: Tiles flushed with expanded Z H[Z`PERF_earlyZ_waiting_for_postZ_done: Cycles stalled while transitioning from Late/ReZ to EarlyZ @\[rPERF_reZ_waiting_for_postZ_done: Cycles stalled while transitioning to ReZ from an incompatible Z mode/func/etc. ]\@PERF_dk_tile_sends: Detail kill block tiles/squads/events sent ]P]2PERF_dk_tile_busy: Cycles Detail Kill block busy ^^ZPERF_dk_tile_quad_starves: Cycles Detail Kill has tile, but no quads from the SC_DB_quad h_^?PERF_dk_tile_stalls: Cycles Detail Kill is stalled from below `_)PERF_dk_squad_sends: Detail Kill squads ```@PERF_dk_squad_busy: Cycles the squad Detail Kill input is busy a(a=PERF_dk_squad_stalls: Cycles squads are stalled from below. barPERF_Op_Pipe_Busy: Cycles the quad OP pipe of the DB is busy (including memory fetches, but not initial startup) cbkPERF_Op_Pipe_MC_Read_stall: Cycles the Op Pipe is waiting for memory to return (ignoring initial startup) Hdc1PERF_qc_busy: Cycles the Quad Coherency is busy edCPERF_qc_xfc: Number of transfers through the Quad Coherency block fXePERF_qc_conflicts: Stalls on a squad input because of a coherency check conflict (the same sample ahead of it could affect the dest data) fhfKPERF_qc_full_stall: Quad Coherency is stalled because it is out of slots. h8gPERF_qc_in_preZ_tile_stalls_postZ: Cycles postZ squad inputs are stalled because the OP pipe is operating on a preZ tile, and there is no PreZ squad input available PihhPERF_qc_in_postZ_tile_stalls_preZ: Cycles preZ squad inputs are stalled because the OP pipe is operating on a postZ tile, and there is no PostZ squad input available HjirPERF_tsc_insert_summarize_stall: Cycles the op pipe is stalled by the tile summarizer inserting summarize squads kj-PERF_tl_busy: Cycles Tile Lookup block busy kHk4PERF_tl_dtc_read_starved: Cycles Tile Lookup block llIPERF_tl_z_fetch_stall: Cycles Tile Lookup block stalled by zfetch block `mlOPERF_tl_stencil_stall: Cycles Tile Lookup block stalled by stencil test block 8nmTPERF_tl_z_decompress_stall: Cycles Tile Lookup block stalled by z decompress block onXPERF_tl_stencil_locked_stall: Cycles Tile Lookup block stalled by stencil being locked o`o;PERF_tl_events: Cycles Tile Lookup block sends out events p pOPERF_tl_summarize_squads: Cycles Tile Lookup block sends out summarize squads qpUPERF_tl_flush_expand_squads: Cycles Tile Lookup block sends out flush expand squads `rqIPERF_tl_expand_squads: Cycles Tile Lookup block sends out expand squads 0srEPERF_tl_preZ_squads: Cycles Tile Lookup block sends out preZ squads txsGPERF_tl_postZ_squads: Cycles Tile Lookup block sends out postZ squads tHtUPERF_tl_preZ_noop_squads: Cycles Tile Lookup block sends out noops on the preZ path u(uWPERF_tl_postZ_noop_squads: Cycles Tile Lookup block sends out noops on the postZ path vvNPERF_tl_getZ_squads: Cycles Tile Lookup block sends out z import pass squads hwvEPERF_tl_tile_ops: Cycles Tile Lookup block sends out tile op squads 0xw=PERF_tl_in_xfc: Cycles Tile Lookup block receives any input (yxxnPERF_tl_in_single_stencil_expand_stall: Cycles Tile Lookup block is stalling due to expanding single stencil zpyePERF_tl_in_constant_stencil_walk_stall: Cycles Tile Lookup block is stalling due to walking stencil z`zLPERF_tl_in_fast_z_stall: Cycles Tile Lookup block is stalling due to fastZ {0{CPERF_tl_out_xfc: Cycles Tile Lookup block is sending anything out x|{DPERF_tl_out_squads: Cycles Tile Lookup block is sending squads out }|PERF_zf_plane_multicycle: Cycles the z fetch is multicycling a squad because it needs to fetch more than 2 planes from the cache for compressed Z `~}JPERF_PostZ_Samples_passing_Z: Samples passing Z test during a PostZ pass 0~JPERF_PostZ_Samples_failing_Z: Samples failing Z test during a PostZ pass xPPERF_PostZ_Samples_failing_S: Samples failing Stencil test during a PostZ pass ؀PHPERF_PreZ_Samples_passing_Z: Samples passing Z test during a PreZ pass HPERF_PreZ_Samples_failing_Z: Samples failing Z test during a PreZ pass NPERF_PreZ_Samples_failing_S: Samples failing Stencil test during a PreZ pass `ȂZPERF_ts_tc_update_stall: Cycles Tile Summarizer to Tile Cache write interface is stalled (>PERF_sc_kick_start: Times the DB sent a hang panic to the SC 脼p7PERF_sc_kick_end: Times the DB completed a hang panic 0>PERF_SX_DB_mem_exports: Number of memory exports from the SX PPERF_SX_DB_mem_exports_acked: Number of memory export writes acked from the MC `ІPPERF_SX_DB_ack_mem_exports: Number of ack requested memory exports from the SX 8SPERF_SX_DB_ack_mem_exports_acked: Number of memory export acks returned to the SX 5PERF_mem_export_busy: Cycles writing memory exports @sPERF_mem_export_mi_stall: Cycles mem exports are stalled waiting for other DB writes or MC write bus arbitration. ؊8dPERF_mem_export_tag_stall: Cycles mem exports are stalled waiting for a free mem export write tag. <PERF_clock_reg_active: Cycles register part of DB is awake X9PERF_clock_main_active: Cycles core part of DB is awake (EPERF_clock_mem_export_active: Cycles mem export part of DB is awake 荼p7PERF_esr_out_busy: Early Squad Router Out cycles busy 0;PERF_esr_out_sc_stall: Early Squad Router Out to SC stall ZPERF_esr_out_lquad_fifo_full_stall: Early Squad Router Out to Late Quad Fifo full stalls @Џ0PERF_etr_out_send: Early Tile Router Out sends 6PERF_etr_out_busy: Early Tile Router Out cycles busy HePERF_etr_out_ltile_probe_fifo_full_stall: Early Tile Router Out to Late Tile Probe Fifo full stalls 8APERF_etr_out_cb_tile_stall: Early Tile Router to CB tile stalls IPERF_etr_out_esr_stall: Early Tile Router to Early Squad Router stalls. `LXX""LDB1_PERFCOUNTER2_SELECTMXM PERF_SELNM4PERF_SC_DB_tile_sends: Cycles Interface is sending NXN0PERF_SC_DB_tile_busy: Cycles Interface is busy OO5PERF_SC_DB_tile_stalls: Cycles Interface is stalled @PO4PERF_SC_DB_tile_events: Events sent over interface PP2PERF_SC_DB_tile_tiles: Tiles sent over interface Q@Q.PERF_SC_DB_tile_covered: Fully covered tiles RQIPERF_hiz_tc_read_starved: HiZ starved waiting for htile data from cache HSR=PERF_hiz_tc_write_stall: HiZ stalled writing to htile cache TS5PERF_hiz_qtiles_culled: Quarter tiles culled by hiZ TPT 5PERF_his_qtiles_culled: Quarter tiles culled by HiS UU 4PERF_DB_SC_tile_sends: Cycles Interface is sending 8VU 0PERF_DB_SC_tile_busy: Cycles Interface is busy VV ;PERF_DB_SC_tile_stalls: Cycles Interface is stalled by SC W@W QPERF_DB_SC_tile_df_stalls: Cycles Interface is stalled by detail walk tile fifo XX2PERF_DB_SC_tile_tiles: Tiles sent over interface @YX/PERF_DB_SC_tile_culled: Tiles culled in total ZYIPERF_DB_SC_tile_hier_kill: Tiles culled due to a hierarchical fail test ZXZSPERF_DB_SC_tile_fast_ops: Tiles culled because they were accerated fast tile ops. [0[IPERF_DB_SC_tile_no_ops: Tiles culled because they would not do anything \\TPERF_DB_SC_tile_pixel_rate: Tiles run at pixel rate as opposed to sample rate tile ]\qPERF_DB_SC_tile_ssaa_kill: Tiles culled because they were supersample tiles that are merged into a fast tile op ^]tPERF_DB_SC_tile_fast_z_ops: Tiles that operate on Z in 1 clock. Can be inside a slow, pixel rate, or fast tile op _^PERF_DB_SC_tile_fast_stencil_ops: Tiles that operate on stencil in 1 clock. Can be inside a slow, pixel rate, or fast tile op @`_4PERF_SC_DB_quad_sends: Cycles Interface is sending ``0PERF_SC_DB_quad_busy: Cycles Interface is busy a@a;PERF_SC_DB_quad_squads: Squads transferred over interface pbb2PERF_SC_DB_quad_tiles: Tiles sent over interface 0cb:PERF_SC_DB_quad_pixels: Pixels transfered over interface cxc=PERF_SC_DB_quad_killed_tiles: Number of detail killed tiles d@d4PERF_DB_SC_quad_sends: Cycles Interface is sending hed0PERF_DB_SC_quad_busy: Cycles Interface is busy (fe5PERF_DB_SC_quad_stalls: Cycles Interface is stalled fpf 4PERF_DB_SC_quad_squads: Squads sent over interface g(g!2PERF_DB_SC_quad_tiles: Tiles sent over interface hhg"HPERF_DB_SC_quad_quads: Quads transferred over the DB_SC_quad interface `ih#nPERF_DB_CB_tile_sends: Cycles sending tiles/events to CB. Tiles not shaded or needed by the CB are not sent. ji$PERF_DB_CB_tile_busy: jHj%PERF_DB_CB_tile_stalls: Xkj&4PERF_SX_DB_quad_sends: Cycles Interface is sending lk'0PERF_SX_DB_quad_busy: Cycles Interface is busy lXl(5PERF_SX_DB_quad_stalls: Cycles Interface is stalled mm)2PERF_SX_DB_quad_quads: Quads sent over interface @nm*4PERF_SX_DB_quad_pixels: Pixels sent over interface on+APERF_SX_DB_quad_exports: Each MRT of a quad sent over interface oPo,bPERF_SH_quads_outstanding_sum: Multiple by 128 and divide by DB_SC_quad_quads to get PS latency. p8p-5PERF_DB_CB_lquad_sends: Cycles Interface is sending hqp.1PERF_DB_CB_lquad_busy: Cycles Interface is busy (rq/6PERF_DB_CB_lquad_stalls: Cycles Interface is stalled rpr03PERF_DB_CB_lquad_quads: Quads sent over interface s(s1/PERF_tile_rd_sends: HTile reads. Each is 256B ts2hPERF_mi_tile_rd_outstanding_sum: Multiply by 2 and divide by tile_rd_sends to get htile memory latency Hut3:PERF_quad_rd_sends: Quad read reqs. Each is 32B to 256B vu4JPERF_quad_rd_busy: Cycles quad read interface is trying to send requests v`v5VPERF_quad_rd_mi_stall: Cycles quad read interface is stalled by the memory interface w@w6XPERF_quad_rd_rw_collision: Cycles a quad read is stalled waiting for a write to finish x x7ePERF_quad_rd_tag_stall: Cycles a quad read is stalled because the read latency hiding fifo is full. yy8@PERF_quad_rd_32byte_reqs: Number of 32 Byte quad read requests Xzy9>PERF_quad_rd_panic: Cycles DB is panicing for quad read data X{z:vPERF_mi_quad_rd_outstanding_sum: Multiply by 16 and divide by quad_rd_32byte_reqs to get depth buffer memory latency |{;<PERF_quad_rdret_sends: Number of 32 byte quad read returns |`|<>PERF_quad_rdret_busy: Cycles the quad read data is returning }(}=*PERF_tile_wr_sends: 32 Byte HTile writes H~}>-PERF_tile_wr_acks: 32 Byte Htile write acks @~?nPERF_mi_tile_wr_outstanding_sum: Multiply by 16 and divide by tile_wr_sends to get tile write memory latency (@cPERF_quad_wr_sends: Cycles quad is sending write requests to the memory interface block of the DB pAKPERF_quad_wr_busy: Cycles quad is trying to write to the memory interface ؁@BUPERF_quad_wr_mi_stall: Cycles quad is stalled while writing to the memory interface ؂ CwPERF_quad_wr_coherency_stall: Cycles quad write is stalled waiting for a previous write to finish on the same address D6PERF_quad_wr_acks: Number of 32 Byte quad write acks ErPERF_mi_quad_wr_outstanding_sum: Multiply by 16 and divide by the quad_wr_sends to get quad memory write latency @؄F,PERF_Tile_Cache_misses: Htile Cache misses G(PERF_Tile_Cache_hits: Htile Cache hits 8H.PERF_Tile_Cache_flushes: Htile Cache flushes I[PERF_Tile_Cache_surface_stall: Tile stalls waiting for an htile surface to flush and free `ЇJMPERF_Tile_Cache_starves: Tile stalls waiting for an htile cacheline to free @K[PERF_Tile_Cache_mem_return_starve: Tile stalls waiting for an htile memory read to return LYPERF_tcp_dispatcher_reads: Number of htile cachelines fetched by the normal tile stream hMQPERF_tcp_prefetcher_reads: Number of htile cachelines fetched by the prefetcher Ћ@NOPERF_tcp_preloader_reads: Number of htile cachelines fetched by the preloader OXPERF_tcp_dispatcher_flushes: Number of htile flushes caused byt the normal tile stream PWPERF_tcp_prefetcher_flushes: Number of htile flushes caused byt the normal prefetcher p؍QUPERF_tcp_preloader_flushes: Number of htile flushes caused byt the normal preloader @RHPERF_Depth_Tile_Cache_sends: Tiles/Events through the Depth Tile Cache (SbPERF_Depth_Tile_Cache_busy: Cycles the Depth Tile Cache is busy testing hit/miss on tiles/events pT_PERF_Depth_Tile_Cache_starves: Cycles starved waiting for a depth surface tile tag to free up XUgPERF_Depth_Tile_Cache_dtile_locked: Cycles stalled waiting for a forced flush or invalidate to finish ؒHVTPERF_Depth_Tile_Cache_alloc_stall: Cycles depth tile stalled while allocating data W?PERF_Depth_Tile_Cache_misses: Depth/Stencil Cache tile misses `蓻X;PERF_Depth_Tile_Cache_hits: Depth/Stencil Cache tile hits (YAPERF_Depth_Tile_Cache_flushes: Depth/Stencil Cache tile flushes pZJPERF_Depth_Tile_Cache_noop_tile: Noop tiles through the depth tile cache ؖ@[VPERF_Depth_Tile_Cache_detailed_noop: Detail walked noops though the depth tile cache \%PERF_Depth_Tile_Cache_event: Events @З]4PERF_Depth_Tile_Cache_tile_frees: Depth tile frees (^cPERF_Depth_Tile_Cache_data_frees: Depth tile data frees (may free data without freeing the dtile) p_ePERF_Depth_Tile_Cache_mem_return_starve: Cycles depth/stencil cache is waiting for memory to return К``/PERF_Stencil_Cache_misses: 512 bit allocation paPERF_Stencil_Cache_hits: hbpPERF_Stencil_Cache_flushes: 256 bit flushes. Two per cacheline unless it is compressed, in which case it is 1. `cmPERF_Stencil_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate dPERF_Stencil_Cache_frees: He"PERF_Z_Cache_separate_Z_misses: Pf PERF_Z_Cache_separate_Z_hits: g#PERF_Z_Cache_separate_Z_flushes: @hrPERF_Z_Cache_separate_Z_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate 8iPERF_Z_Cache_pmask_misses: 8ࡻjPERF_Z_Cache_pmask_hits: ࢻkPERF_Z_Cache_pmask_flushes: أ(lmPERF_Z_Cache_pmask_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate x mPERF_Z_Cache_frees: nPERF_Plane_Cache_misses: `oPERF_Plane_Cache_hits: XpPERF_Plane_Cache_flushes: HqkPERF_Plane_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate 觻rPERF_Plane_Cache_frees: 0sGPERF_flush_expanded_stencil: Tiles flushed with with expanded stencil tKPERF_flush_compressed_stencil: Tiles flushed with with compressed stencil PЩuCPERF_flush_single_stencil: Tiles flushed with with single stencil v0PERF_flush_1plane: Tiles flushed with 1 ZPlane Pw1PERF_flush_2plane: Tiles flushed with 2 ZPlanes xx1PERF_flush_3plane: Tiles flushed with 3 ZPlanes 0y1PERF_flush_4plane: Tiles flushed with 4 ZPlanes 譻xz1PERF_flush_5plane: Tiles flushed with 5 ZPlanes 0{1PERF_flush_6plane: Tiles flushed with 6 ZPlanes X讻|1PERF_flush_7plane: Tiles flushed with 7 ZPlanes }1PERF_flush_8plane: Tiles flushed with 8 ZPlanes ȰX~1PERF_flush_9plane: Tiles flushed with 9 ZPlanes 3PERF_flush_10plane: Tiles flushed with 10 ZPlanes 8ȱ3PERF_flush_11plane: Tiles flushed with 11 ZPlanes 3PERF_flush_12plane: Tiles flushed with 12 ZPlanes 83PERF_flush_13plane: Tiles flushed with 13 ZPlanes `3PERF_flush_14plane: Tiles flushed with 14 ZPlanes 3PERF_flush_15plane: Tiles flushed with 15 ZPlanes е`3PERF_flush_16plane: Tiles flushed with 16 ZPlanes 6PERF_flush_expanded_z: Tiles flushed with expanded Z xض`PERF_earlyZ_waiting_for_postZ_done: Cycles stalled while transitioning from Late/ReZ to EarlyZ prPERF_reZ_waiting_for_postZ_done: Cycles stalled while transitioning to ReZ from an incompatible Z mode/func/etc. 8@PERF_dk_tile_sends: Detail kill block tiles/squads/events sent 2PERF_dk_tile_busy: Cycles Detail Kill block busy к8ZPERF_dk_tile_quad_starves: Cycles Detail Kill has tile, but no quads from the SC_DB_quad ?PERF_dk_tile_stalls: Cycles Detail Kill is stalled from below H໻)PERF_dk_squad_sends: Detail Kill squads @PERF_dk_squad_busy: Cycles the squad Detail Kill input is busy ؽX=PERF_dk_squad_stalls: Cycles squads are stalled from below. о rPERF_Op_Pipe_Busy: Cycles the quad OP pipe of the DB is busy (including memory fetches, but not initial startup) kPERF_Op_Pipe_MC_Read_stall: Cycles the Op Pipe is waiting for memory to return (ignoring initial startup) x1PERF_qc_busy: Cycles the Quad Coherency is busy @CPERF_qc_xfc: Number of transfers through the Quad Coherency block P»PERF_qc_conflicts: Stalls on a squad input because of a coherency check conflict (the same sample ahead of it could affect the dest data) û»KPERF_qc_full_stall: Quad Coherency is stalled because it is out of slots. PĻhûPERF_qc_in_preZ_tile_stalls_postZ: Cycles postZ squad inputs are stalled because the OP pipe is operating on a preZ tile, and there is no PreZ squad input available ŻĻPERF_qc_in_postZ_tile_stalls_preZ: Cycles preZ squad inputs are stalled because the OP pipe is operating on a postZ tile, and there is no PostZ squad input available xƻŻrPERF_tsc_insert_summarize_stall: Cycles the op pipe is stalled by the tile summarizer inserting summarize squads 0ǻƻ-PERF_tl_busy: Cycles Tile Lookup block busy ǻxǻ4PERF_tl_dtc_read_starved: Cycles Tile Lookup block Ȼ0ȻIPERF_tl_z_fetch_stall: Cycles Tile Lookup block stalled by zfetch block ɻɻOPERF_tl_stencil_stall: Cycles Tile Lookup block stalled by stencil test block hʻɻTPERF_tl_z_decompress_stall: Cycles Tile Lookup block stalled by z decompress block H˻ʻXPERF_tl_stencil_locked_stall: Cycles Tile Lookup block stalled by stencil being locked ̻˻;PERF_tl_events: Cycles Tile Lookup block sends out events ̻P̻OPERF_tl_summarize_squads: Cycles Tile Lookup block sends out summarize squads ͻ(ͻUPERF_tl_flush_expand_squads: Cycles Tile Lookup block sends out flush expand squads λλIPERF_tl_expand_squads: Cycles Tile Lookup block sends out expand squads `ϻλEPERF_tl_preZ_squads: Cycles Tile Lookup block sends out preZ squads 0лϻGPERF_tl_postZ_squads: Cycles Tile Lookup block sends out postZ squads ѻxлUPERF_tl_preZ_noop_squads: Cycles Tile Lookup block sends out noops on the preZ path ѻXѻWPERF_tl_postZ_noop_squads: Cycles Tile Lookup block sends out noops on the postZ path һ8һNPERF_tl_getZ_squads: Cycles Tile Lookup block sends out z import pass squads ӻӻEPERF_tl_tile_ops: Cycles Tile Lookup block sends out tile op squads `Իӻ=PERF_tl_in_xfc: Cycles Tile Lookup block receives any input XջԻnPERF_tl_in_single_stencil_expand_stall: Cycles Tile Lookup block is stalling due to expanding single stencil HֻջePERF_tl_in_constant_stencil_walk_stall: Cycles Tile Lookup block is stalling due to walking stencil ׻ֻLPERF_tl_in_fast_z_stall: Cycles Tile Lookup block is stalling due to fastZ ׻`׻CPERF_tl_out_xfc: Cycles Tile Lookup block is sending anything out ػ(ػDPERF_tl_out_squads: Cycles Tile Lookup block is sending squads out ٻػPERF_zf_plane_multicycle: Cycles the z fetch is multicycling a squad because it needs to fetch more than 2 planes from the cache for compressed Z ڻڻJPERF_PostZ_Samples_passing_Z: Samples passing Z test during a PostZ pass `ۻڻJPERF_PostZ_Samples_failing_Z: Samples failing Z test during a PostZ pass 8ܻۻPPERF_PostZ_Samples_failing_S: Samples failing Stencil test during a PostZ pass ݻܻHPERF_PreZ_Samples_passing_Z: Samples passing Z test during a PreZ pass ݻPݻHPERF_PreZ_Samples_failing_Z: Samples failing Z test during a PreZ pass ޻ ޻NPERF_PreZ_Samples_failing_S: Samples failing Stencil test during a PreZ pass ߻޻ZPERF_ts_tc_update_stall: Cycles Tile Summarizer to Tile Cache write interface is stalled X߻>PERF_sc_kick_start: Times the DB sent a hang panic to the SC 7PERF_sc_kick_end: Times the DB completed a hang panic `>PERF_SX_DB_mem_exports: Number of memory exports from the SX (PPERF_SX_DB_mem_exports_acked: Number of memory export writes acked from the MC PPERF_SX_DB_ack_mem_exports: Number of ack requested memory exports from the SX hSPERF_SX_DB_ack_mem_exports_acked: Number of memory export acks returned to the SX (5PERF_mem_export_busy: Cycles writing memory exports psPERF_mem_export_mi_stall: Cycles mem exports are stalled waiting for other DB writes or MC write bus arbitration. hdPERF_mem_export_tag_stall: Cycles mem exports are stalled waiting for a free mem export write tag. P<PERF_clock_reg_active: Cycles register part of DB is awake 9PERF_clock_main_active: Cycles core part of DB is awake XEPERF_clock_mem_export_active: Cycles mem export part of DB is awake 7PERF_esr_out_busy: Early Squad Router Out cycles busy `;PERF_esr_out_sc_stall: Early Squad Router Out to SC stall ZPERF_esr_out_lquad_fifo_full_stall: Early Squad Router Out to Late Quad Fifo full stalls p0PERF_etr_out_send: Early Tile Router Out sends 06PERF_etr_out_busy: Early Tile Router Out cycles busy xePERF_etr_out_ltile_probe_fifo_full_stall: Early Tile Router Out to Late Tile Probe Fifo full stalls hAPERF_etr_out_cb_tile_stall: Early Tile Router to CB tile stalls 0IPERF_etr_out_esr_stall: Early Tile Router to Early Squad Router stalls. 0xLL""ШDB1_PERFCOUNTER1_SELECT(p PERF_SEL(4PERF_SC_DB_tile_sends: Cycles Interface is sending ઺p0PERF_SC_DB_tile_busy: Cycles Interface is busy (5PERF_SC_DB_tile_stalls: Cycles Interface is stalled X諺4PERF_SC_DB_tile_events: Events sent over interface 2PERF_SC_DB_tile_tiles: Tiles sent over interface ȭX.PERF_SC_DB_tile_covered: Fully covered tiles IPERF_hiz_tc_read_starved: HiZ starved waiting for htile data from cache `஺=PERF_hiz_tc_write_stall: HiZ stalled writing to htile cache 5PERF_hiz_qtiles_culled: Quarter tiles culled by hiZ ఺h 5PERF_his_qtiles_culled: Quarter tiles culled by HiS ( 4PERF_DB_SC_tile_sends: Cycles Interface is sending P౺ 0PERF_DB_SC_tile_busy: Cycles Interface is busy  ;PERF_DB_SC_tile_stalls: Cycles Interface is stalled by SC 賺X QPERF_DB_SC_tile_df_stalls: Cycles Interface is stalled by detail walk tile fifo 02PERF_DB_SC_tile_tiles: Tiles sent over interface X贺/PERF_DB_SC_tile_culled: Tiles culled in total (IPERF_DB_SC_tile_hier_kill: Tiles culled due to a hierarchical fail test pSPERF_DB_SC_tile_fast_ops: Tiles culled because they were accerated fast tile ops. зHIPERF_DB_SC_tile_no_ops: Tiles culled because they would not do anything TPERF_DB_SC_tile_pixel_rate: Tiles run at pixel rate as opposed to sample rate tile qPERF_DB_SC_tile_ssaa_kill: Tiles culled because they were supersample tiles that are merged into a fast tile op 蹺tPERF_DB_SC_tile_fast_z_ops: Tiles that operate on Z in 1 clock. Can be inside a slow, pixel rate, or fast tile op ຺PERF_DB_SC_tile_fast_stencil_ops: Tiles that operate on stencil in 1 clock. Can be inside a slow, pixel rate, or fast tile op X軺4PERF_SC_DB_quad_sends: Cycles Interface is sending 0PERF_SC_DB_quad_busy: Cycles Interface is busy нX;PERF_SC_DB_quad_squads: Squads transferred over interface 2PERF_SC_DB_quad_tiles: Tiles sent over interface Hо:PERF_SC_DB_quad_pixels: Pixels transfered over interface =PERF_SC_DB_quad_killed_tiles: Number of detail killed tiles X4PERF_DB_SC_quad_sends: Cycles Interface is sending 0PERF_DB_SC_quad_busy: Cycles Interface is busy @º5PERF_DB_SC_quad_stalls: Cycles Interface is stalled ºº 4PERF_DB_SC_quad_squads: Squads sent over interface ú@ú!2PERF_DB_SC_quad_tiles: Tiles sent over interface ĺú"HPERF_DB_SC_quad_quads: Quads transferred over the DB_SC_quad interface xźĺ#nPERF_DB_CB_tile_sends: Cycles sending tiles/events to CB. Tiles not shaded or needed by the CB are not sent. ƺź$PERF_DB_CB_tile_busy: ƺ`ƺ%PERF_DB_CB_tile_stalls: pǺǺ&4PERF_SX_DB_quad_sends: Cycles Interface is sending (ȺǺ'0PERF_SX_DB_quad_busy: Cycles Interface is busy ȺpȺ(5PERF_SX_DB_quad_stalls: Cycles Interface is stalled ɺ0ɺ)2PERF_SX_DB_quad_quads: Quads sent over interface Xʺɺ*4PERF_SX_DB_quad_pixels: Pixels sent over interface ˺ʺ+APERF_SX_DB_quad_exports: Each MRT of a quad sent over interface ̺h˺,bPERF_SH_quads_outstanding_sum: Multiple by 128 and divide by DB_SC_quad_quads to get PS latency. ̺P̺-5PERF_DB_CB_lquad_sends: Cycles Interface is sending ͺͺ.1PERF_DB_CB_lquad_busy: Cycles Interface is busy @κͺ/6PERF_DB_CB_lquad_stalls: Cycles Interface is stalled κκ03PERF_DB_CB_lquad_quads: Quads sent over interface Ϻ@Ϻ1/PERF_tile_rd_sends: HTile reads. Each is 256B кϺ2hPERF_mi_tile_rd_outstanding_sum: Multiply by 2 and divide by tile_rd_sends to get htile memory latency `Ѻк3:PERF_quad_rd_sends: Quad read reqs. Each is 32B to 256B 0ҺѺ4JPERF_quad_rd_busy: Cycles quad read interface is trying to send requests ӺxҺ5VPERF_quad_rd_mi_stall: Cycles quad read interface is stalled by the memory interface ӺXӺ6XPERF_quad_rd_rw_collision: Cycles a quad read is stalled waiting for a write to finish Ժ8Ժ7ePERF_quad_rd_tag_stall: Cycles a quad read is stalled because the read latency hiding fifo is full. պ(պ8@PERF_quad_rd_32byte_reqs: Number of 32 Byte quad read requests pֺպ9>PERF_quad_rd_panic: Cycles DB is panicing for quad read data p׺ֺ:vPERF_mi_quad_rd_outstanding_sum: Multiply by 16 and divide by quad_rd_32byte_reqs to get depth buffer memory latency 0غ׺;<PERF_quad_rdret_sends: Number of 32 byte quad read returns غxغ<>PERF_quad_rdret_busy: Cycles the quad read data is returning ٺ@ٺ=*PERF_tile_wr_sends: 32 Byte HTile writes `ںٺ>-PERF_tile_wr_acks: 32 Byte Htile write acks Xۺں?nPERF_mi_tile_wr_outstanding_sum: Multiply by 16 and divide by tile_wr_sends to get tile write memory latency @ܺۺ@cPERF_quad_wr_sends: Cycles quad is sending write requests to the memory interface block of the DB ݺܺAKPERF_quad_wr_busy: Cycles quad is trying to write to the memory interface ݺXݺBUPERF_quad_wr_mi_stall: Cycles quad is stalled while writing to the memory interface ޺8޺CwPERF_quad_wr_coherency_stall: Cycles quad write is stalled waiting for a previous write to finish on the same address ߺ8ߺD6PERF_quad_wr_acks: Number of 32 Byte quad write acks ߺErPERF_mi_quad_wr_outstanding_sum: Multiply by 16 and divide by the quad_wr_sends to get quad memory write latency XF,PERF_Tile_Cache_misses: Htile Cache misses G(PERF_Tile_Cache_hits: Htile Cache hits PH.PERF_Tile_Cache_flushes: Htile Cache flushes I[PERF_Tile_Cache_surface_stall: Tile stalls waiting for an htile surface to flush and free xJMPERF_Tile_Cache_starves: Tile stalls waiting for an htile cacheline to free XK[PERF_Tile_Cache_mem_return_starve: Tile stalls waiting for an htile memory read to return 8LYPERF_tcp_dispatcher_reads: Number of htile cachelines fetched by the normal tile stream MQPERF_tcp_prefetcher_reads: Number of htile cachelines fetched by the prefetcher XNOPERF_tcp_preloader_reads: Number of htile cachelines fetched by the preloader 0OXPERF_tcp_dispatcher_flushes: Number of htile flushes caused byt the normal tile stream PWPERF_tcp_prefetcher_flushes: Number of htile flushes caused byt the normal prefetcher QUPERF_tcp_preloader_flushes: Number of htile flushes caused byt the normal preloader XRHPERF_Depth_Tile_Cache_sends: Tiles/Events through the Depth Tile Cache @SbPERF_Depth_Tile_Cache_busy: Cycles the Depth Tile Cache is busy testing hit/miss on tiles/events (T_PERF_Depth_Tile_Cache_starves: Cycles starved waiting for a depth surface tile tag to free up pUgPERF_Depth_Tile_Cache_dtile_locked: Cycles stalled waiting for a forced flush or invalidate to finish `VTPERF_Depth_Tile_Cache_alloc_stall: Cycles depth tile stalled while allocating data 8W?PERF_Depth_Tile_Cache_misses: Depth/Stencil Cache tile misses X;PERF_Depth_Tile_Cache_hits: Depth/Stencil Cache tile hits HYAPERF_Depth_Tile_Cache_flushes: Depth/Stencil Cache tile flushes ZJPERF_Depth_Tile_Cache_noop_tile: Noop tiles through the depth tile cache `[VPERF_Depth_Tile_Cache_detailed_noop: Detail walked noops though the depth tile cache @\%PERF_Depth_Tile_Cache_event: Events `]4PERF_Depth_Tile_Cache_tile_frees: Depth tile frees H^cPERF_Depth_Tile_Cache_data_frees: Depth tile data frees (may free data without freeing the dtile) 8_ePERF_Depth_Tile_Cache_mem_return_starve: Cycles depth/stencil cache is waiting for memory to return `/PERF_Stencil_Cache_misses: 512 bit allocation 8aPERF_Stencil_Cache_hits: bpPERF_Stencil_Cache_flushes: 256 bit flushes. Two per cacheline unless it is compressed, in which case it is 1. cmPERF_Stencil_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate dPERF_Stencil_Cache_frees: he"PERF_Z_Cache_separate_Z_misses: pf PERF_Z_Cache_separate_Z_hits: g#PERF_Z_Cache_separate_Z_flushes: `hrPERF_Z_Cache_separate_Z_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate XiPERF_Z_Cache_pmask_misses: XjPERF_Z_Cache_pmask_hits: kPERF_Z_Cache_pmask_flushes: HlmPERF_Z_Cache_pmask_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate @mPERF_Z_Cache_frees: 8nPERF_Plane_Cache_misses: oPERF_Plane_Cache_hits: x pPERF_Plane_Cache_flushes: hqkPERF_Plane_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate rPERF_Plane_Cache_frees: PsGPERF_flush_expanded_stencil: Tiles flushed with with expanded stencil  tKPERF_flush_compressed_stencil: Tiles flushed with with compressed stencil puCPERF_flush_single_stencil: Tiles flushed with with single stencil (v0PERF_flush_1plane: Tiles flushed with 1 ZPlane pw1PERF_flush_2plane: Tiles flushed with 2 ZPlanes (x1PERF_flush_3plane: Tiles flushed with 3 ZPlanes P y1PERF_flush_4plane: Tiles flushed with 4 ZPlanes  z1PERF_flush_5plane: Tiles flushed with 5 ZPlanes P {1PERF_flush_6plane: Tiles flushed with 6 ZPlanes x  |1PERF_flush_7plane: Tiles flushed with 7 ZPlanes 0 }1PERF_flush_8plane: Tiles flushed with 8 ZPlanes x ~1PERF_flush_9plane: Tiles flushed with 9 ZPlanes 0 3PERF_flush_10plane: Tiles flushed with 10 ZPlanes X 3PERF_flush_11plane: Tiles flushed with 11 ZPlanes 3PERF_flush_12plane: Tiles flushed with 12 ZPlanes X3PERF_flush_13plane: Tiles flushed with 13 ZPlanes 3PERF_flush_14plane: Tiles flushed with 14 ZPlanes 83PERF_flush_15plane: Tiles flushed with 15 ZPlanes 3PERF_flush_16plane: Tiles flushed with 16 ZPlanes 86PERF_flush_expanded_z: Tiles flushed with expanded Z `PERF_earlyZ_waiting_for_postZ_done: Cycles stalled while transitioning from Late/ReZ to EarlyZ rPERF_reZ_waiting_for_postZ_done: Cycles stalled while transitioning to ReZ from an incompatible Z mode/func/etc. X@PERF_dk_tile_sends: Detail kill block tiles/squads/events sent 2PERF_dk_tile_busy: Cycles Detail Kill block busy XZPERF_dk_tile_quad_starves: Cycles Detail Kill has tile, but no quads from the SC_DB_quad 8?PERF_dk_tile_stalls: Cycles Detail Kill is stalled from below h)PERF_dk_squad_sends: Detail Kill squads 0@PERF_dk_squad_busy: Cycles the squad Detail Kill input is busy x=PERF_dk_squad_stalls: Cycles squads are stalled from below. @rPERF_Op_Pipe_Busy: Cycles the quad OP pipe of the DB is busy (including memory fetches, but not initial startup) 8kPERF_Op_Pipe_MC_Read_stall: Cycles the Op Pipe is waiting for memory to return (ignoring initial startup) (1PERF_qc_busy: Cycles the Quad Coherency is busy `CPERF_qc_xfc: Number of transfers through the Quad Coherency block pPERF_qc_conflicts: Stalls on a squad input because of a coherency check conflict (the same sample ahead of it could affect the dest data) @KPERF_qc_full_stall: Quad Coherency is stalled because it is out of slots. p PERF_qc_in_preZ_tile_stalls_postZ: Cycles postZ squad inputs are stalled because the OP pipe is operating on a preZ tile, and there is no PreZ squad input available ! PERF_qc_in_postZ_tile_stalls_preZ: Cycles preZ squad inputs are stalled because the OP pipe is operating on a postZ tile, and there is no PostZ squad input available "!rPERF_tsc_insert_summarize_stall: Cycles the op pipe is stalled by the tile summarizer inserting summarize squads P#"-PERF_tl_busy: Cycles Tile Lookup block busy $#4PERF_tl_dtc_read_starved: Cycles Tile Lookup block $P$IPERF_tl_z_fetch_stall: Cycles Tile Lookup block stalled by zfetch block % %OPERF_tl_stencil_stall: Cycles Tile Lookup block stalled by stencil test block &%TPERF_tl_z_decompress_stall: Cycles Tile Lookup block stalled by z decompress block h'&XPERF_tl_stencil_locked_stall: Cycles Tile Lookup block stalled by stencil being locked ((';PERF_tl_events: Cycles Tile Lookup block sends out events )p(OPERF_tl_summarize_squads: Cycles Tile Lookup block sends out summarize squads )H)UPERF_tl_flush_expand_squads: Cycles Tile Lookup block sends out flush expand squads *(*IPERF_tl_expand_squads: Cycles Tile Lookup block sends out expand squads +*EPERF_tl_preZ_squads: Cycles Tile Lookup block sends out preZ squads P,+GPERF_tl_postZ_squads: Cycles Tile Lookup block sends out postZ squads 0-,UPERF_tl_preZ_noop_squads: Cycles Tile Lookup block sends out noops on the preZ path .x-WPERF_tl_postZ_noop_squads: Cycles Tile Lookup block sends out noops on the postZ path .X.NPERF_tl_getZ_squads: Cycles Tile Lookup block sends out z import pass squads /0/EPERF_tl_tile_ops: Cycles Tile Lookup block sends out tile op squads 00=PERF_tl_in_xfc: Cycles Tile Lookup block receives any input 10nPERF_tl_in_single_stencil_expand_stall: Cycles Tile Lookup block is stalling due to expanding single stencil p21ePERF_tl_in_constant_stencil_walk_stall: Cycles Tile Lookup block is stalling due to walking stencil @32LPERF_tl_in_fast_z_stall: Cycles Tile Lookup block is stalling due to fastZ 43CPERF_tl_out_xfc: Cycles Tile Lookup block is sending anything out 4P4DPERF_tl_out_squads: Cycles Tile Lookup block is sending squads out 55PERF_zf_plane_multicycle: Cycles the z fetch is multicycling a squad because it needs to fetch more than 2 planes from the cache for compressed Z 606JPERF_PostZ_Samples_passing_Z: Samples passing Z test during a PostZ pass 77JPERF_PostZ_Samples_failing_Z: Samples failing Z test during a PostZ pass `87PPERF_PostZ_Samples_failing_S: Samples failing Stencil test during a PostZ pass 098HPERF_PreZ_Samples_passing_Z: Samples passing Z test during a PreZ pass :x9HPERF_PreZ_Samples_failing_Z: Samples failing Z test during a PreZ pass :H:NPERF_PreZ_Samples_failing_S: Samples failing Stencil test during a PreZ pass ; ;ZPERF_ts_tc_update_stall: Cycles Tile Summarizer to Tile Cache write interface is stalled <<>PERF_sc_kick_start: Times the DB sent a hang panic to the SC @=<7PERF_sc_kick_end: Times the DB completed a hang panic >=>PERF_SX_DB_mem_exports: Number of memory exports from the SX >P>PPERF_SX_DB_mem_exports_acked: Number of memory export writes acked from the MC ?(?PPERF_SX_DB_ack_mem_exports: Number of ack requested memory exports from the SX @@SPERF_SX_DB_ack_mem_exports_acked: Number of memory export acks returned to the SX XA@5PERF_mem_export_busy: Cycles writing memory exports PBAsPERF_mem_export_mi_stall: Cycles mem exports are stalled waiting for other DB writes or MC write bus arbitration. 8CBdPERF_mem_export_tag_stall: Cycles mem exports are stalled waiting for a free mem export write tag. CC<PERF_clock_reg_active: Cycles register part of DB is awake D@D9PERF_clock_main_active: Cycles core part of DB is awake EEEPERF_clock_mem_export_active: Cycles mem export part of DB is awake HFE7PERF_esr_out_busy: Early Squad Router Out cycles busy GF;PERF_esr_out_sc_stall: Early Squad Router Out to SC stall GPGZPERF_esr_out_lquad_fifo_full_stall: Early Squad Router Out to Late Quad Fifo full stalls H0H0PERF_etr_out_send: Early Tile Router Out sends `IH6PERF_etr_out_busy: Early Tile Router Out cycles busy PJIePERF_etr_out_ltile_probe_fifo_full_stall: Early Tile Router Out to Late Tile Probe Fifo full stalls KJAPERF_etr_out_cb_tile_stall: Early Tile Router to CB tile stalls `KIPERF_etr_out_esr_stall: Early Tile Router to Early Squad Router stalls. @@""DB1_PERFCOUNTER0_SELECTX PERF_SELX4PERF_SC_DB_tile_sends: Cycles Interface is sending 0PERF_SC_DB_tile_busy: Cycles Interface is busy X5PERF_SC_DB_tile_stalls: Cycles Interface is stalled 4PERF_SC_DB_tile_events: Events sent over interface @ 2PERF_SC_DB_tile_tiles: Tiles sent over interface .PERF_SC_DB_tile_covered: Fully covered tiles @ IPERF_hiz_tc_read_starved: HiZ starved waiting for htile data from cache  =PERF_hiz_tc_write_stall: HiZ stalled writing to htile cache P 5PERF_hiz_qtiles_culled: Quarter tiles culled by hiZ  5PERF_his_qtiles_culled: Quarter tiles culled by HiS X 4PERF_DB_SC_tile_sends: Cycles Interface is sending  0PERF_DB_SC_tile_busy: Cycles Interface is busy @ ;PERF_DB_SC_tile_stalls: Cycles Interface is stalled by SC  QPERF_DB_SC_tile_df_stalls: Cycles Interface is stalled by detail walk tile fifo `2PERF_DB_SC_tile_tiles: Tiles sent over interface /PERF_DB_SC_tile_culled: Tiles culled in total XIPERF_DB_SC_tile_hier_kill: Tiles culled due to a hierarchical fail test 0SPERF_DB_SC_tile_fast_ops: Tiles culled because they were accerated fast tile ops. xIPERF_DB_SC_tile_no_ops: Tiles culled because they would not do anything HTPERF_DB_SC_tile_pixel_rate: Tiles run at pixel rate as opposed to sample rate tile  qPERF_DB_SC_tile_ssaa_kill: Tiles culled because they were supersample tiles that are merged into a fast tile op tPERF_DB_SC_tile_fast_z_ops: Tiles that operate on Z in 1 clock. Can be inside a slow, pixel rate, or fast tile op PERF_DB_SC_tile_fast_stencil_ops: Tiles that operate on stencil in 1 clock. Can be inside a slow, pixel rate, or fast tile op 4PERF_SC_DB_quad_sends: Cycles Interface is sending @0PERF_SC_DB_quad_busy: Cycles Interface is busy ;PERF_SC_DB_quad_squads: Squads transferred over interface H2PERF_SC_DB_quad_tiles: Tiles sent over interface x:PERF_SC_DB_quad_pixels: Pixels transfered over interface @=PERF_SC_DB_quad_killed_tiles: Number of detail killed tiles 4PERF_DB_SC_quad_sends: Cycles Interface is sending @0PERF_DB_SC_quad_busy: Cycles Interface is busy p5PERF_DB_SC_quad_stalls: Cycles Interface is stalled ( 4PERF_DB_SC_quad_squads: Squads sent over interface p!2PERF_DB_SC_quad_tiles: Tiles sent over interface ( "HPERF_DB_SC_quad_quads: Quads transferred over the DB_SC_quad interface ! #nPERF_DB_CB_tile_sends: Cycles sending tiles/events to CB. Tiles not shaded or needed by the CB are not sent. H"!$PERF_DB_CB_tile_busy: ""%PERF_DB_CB_tile_stalls: #0#&4PERF_SX_DB_quad_sends: Cycles Interface is sending X$#'0PERF_SX_DB_quad_busy: Cycles Interface is busy %$(5PERF_SX_DB_quad_stalls: Cycles Interface is stalled %`%)2PERF_SX_DB_quad_quads: Quads sent over interface &&*4PERF_SX_DB_quad_pixels: Pixels sent over interface P'&+APERF_SX_DB_quad_exports: Each MRT of a quad sent over interface 8(',bPERF_SH_quads_outstanding_sum: Multiple by 128 and divide by DB_SC_quad_quads to get PS latency. ((-5PERF_DB_CB_lquad_sends: Cycles Interface is sending )@).1PERF_DB_CB_lquad_busy: Cycles Interface is busy p*)/6PERF_DB_CB_lquad_stalls: Cycles Interface is stalled (+*03PERF_DB_CB_lquad_quads: Quads sent over interface +p+1/PERF_tile_rd_sends: HTile reads. Each is 256B ,(,2hPERF_mi_tile_rd_outstanding_sum: Multiply by 2 and divide by tile_rd_sends to get htile memory latency --3:PERF_quad_rd_sends: Quad read reqs. Each is 32B to 256B `.-4JPERF_quad_rd_busy: Cycles quad read interface is trying to send requests @/.5VPERF_quad_rd_mi_stall: Cycles quad read interface is stalled by the memory interface 0/6XPERF_quad_rd_rw_collision: Cycles a quad read is stalled waiting for a write to finish 1h07ePERF_quad_rd_tag_stall: Cycles a quad read is stalled because the read latency hiding fifo is full. 1X18@PERF_quad_rd_32byte_reqs: Number of 32 Byte quad read requests 2 29>PERF_quad_rd_panic: Cycles DB is panicing for quad read data 32:vPERF_mi_quad_rd_outstanding_sum: Multiply by 16 and divide by quad_rd_32byte_reqs to get depth buffer memory latency `43;<PERF_quad_rdret_sends: Number of 32 byte quad read returns (54<>PERF_quad_rdret_busy: Cycles the quad read data is returning 5p5=*PERF_tile_wr_sends: 32 Byte HTile writes 6 6>-PERF_tile_wr_acks: 32 Byte Htile write acks 76?nPERF_mi_tile_wr_outstanding_sum: Multiply by 16 and divide by tile_wr_sends to get tile write memory latency p87@cPERF_quad_wr_sends: Cycles quad is sending write requests to the memory interface block of the DB @98AKPERF_quad_wr_busy: Cycles quad is trying to write to the memory interface :9BUPERF_quad_wr_mi_stall: Cycles quad is stalled while writing to the memory interface ;h:CwPERF_quad_wr_coherency_stall: Cycles quad write is stalled waiting for a previous write to finish on the same address ;h;D6PERF_quad_wr_acks: Number of 32 Byte quad write acks <(<ErPERF_mi_quad_wr_outstanding_sum: Multiply by 16 and divide by the quad_wr_sends to get quad memory write latency = =F,PERF_Tile_Cache_misses: Htile Cache misses 8>=G(PERF_Tile_Cache_hits: Htile Cache hits >>H.PERF_Tile_Cache_flushes: Htile Cache flushes ?8?I[PERF_Tile_Cache_surface_stall: Tile stalls waiting for an htile surface to flush and free @@JMPERF_Tile_Cache_starves: Tile stalls waiting for an htile cacheline to free A@K[PERF_Tile_Cache_mem_return_starve: Tile stalls waiting for an htile memory read to return hBALYPERF_tcp_dispatcher_reads: Number of htile cachelines fetched by the normal tile stream @CBMQPERF_tcp_prefetcher_reads: Number of htile cachelines fetched by the prefetcher DCNOPERF_tcp_preloader_reads: Number of htile cachelines fetched by the preloader D`DOXPERF_tcp_dispatcher_flushes: Number of htile flushes caused byt the normal tile stream E@EPWPERF_tcp_prefetcher_flushes: Number of htile flushes caused byt the normal prefetcher F FQUPERF_tcp_preloader_flushes: Number of htile flushes caused byt the normal preloader GGRHPERF_Depth_Tile_Cache_sends: Tiles/Events through the Depth Tile Cache pHGSbPERF_Depth_Tile_Cache_busy: Cycles the Depth Tile Cache is busy testing hit/miss on tiles/events XIHT_PERF_Depth_Tile_Cache_starves: Cycles starved waiting for a depth surface tile tag to free up HJIUgPERF_Depth_Tile_Cache_dtile_locked: Cycles stalled waiting for a forced flush or invalidate to finish KJVTPERF_Depth_Tile_Cache_alloc_stall: Cycles depth tile stalled while allocating data KhKW?PERF_Depth_Tile_Cache_misses: Depth/Stencil Cache tile misses L0LX;PERF_Depth_Tile_Cache_hits: Depth/Stencil Cache tile hits pMLYAPERF_Depth_Tile_Cache_flushes: Depth/Stencil Cache tile flushes @NMZJPERF_Depth_Tile_Cache_noop_tile: Noop tiles through the depth tile cache ON[VPERF_Depth_Tile_Cache_detailed_noop: Detail walked noops though the depth tile cache OhO\%PERF_Depth_Tile_Cache_event: Events PP]4PERF_Depth_Tile_Cache_tile_frees: Depth tile frees pQP^cPERF_Depth_Tile_Cache_data_frees: Depth tile data frees (may free data without freeing the dtile) `RQ_ePERF_Depth_Tile_Cache_mem_return_starve: Cycles depth/stencil cache is waiting for memory to return SR`/PERF_Stencil_Cache_misses: 512 bit allocation S`SaPERF_Stencil_Cache_hits: TTbpPERF_Stencil_Cache_flushes: 256 bit flushes. Two per cacheline unless it is compressed, in which case it is 1. UTcmPERF_Stencil_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate HVUdPERF_Stencil_Cache_frees: VVe"PERF_Z_Cache_separate_Z_misses: W8Wf PERF_Z_Cache_separate_Z_hits: @XWg#PERF_Z_Cache_separate_Z_flushes: 8YXhrPERF_Z_Cache_separate_Z_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate YYiPERF_Z_Cache_pmask_misses: Z(ZjPERF_Z_Cache_pmask_hits: ([ZkPERF_Z_Cache_pmask_flushes: \p[lmPERF_Z_Cache_pmask_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate \h\mPERF_Z_Cache_frees: `]]nPERF_Plane_Cache_misses: ^]oPERF_Plane_Cache_hits: ^H^pPERF_Plane_Cache_flushes: _^qkPERF_Plane_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate 0`_rPERF_Plane_Cache_frees: ax`sGPERF_flush_expanded_stencil: Tiles flushed with with expanded stencil aHatKPERF_flush_compressed_stencil: Tiles flushed with with compressed stencil bbuCPERF_flush_single_stencil: Tiles flushed with with single stencil Pcbv0PERF_flush_1plane: Tiles flushed with 1 ZPlane dcw1PERF_flush_2plane: Tiles flushed with 2 ZPlanes dPdx1PERF_flush_3plane: Tiles flushed with 3 ZPlanes xeey1PERF_flush_4plane: Tiles flushed with 4 ZPlanes 0fez1PERF_flush_5plane: Tiles flushed with 5 ZPlanes fxf{1PERF_flush_6plane: Tiles flushed with 6 ZPlanes g0g|1PERF_flush_7plane: Tiles flushed with 7 ZPlanes Xhg}1PERF_flush_8plane: Tiles flushed with 8 ZPlanes ih~1PERF_flush_9plane: Tiles flushed with 9 ZPlanes iXi3PERF_flush_10plane: Tiles flushed with 10 ZPlanes jj3PERF_flush_11plane: Tiles flushed with 11 ZPlanes 8kj3PERF_flush_12plane: Tiles flushed with 12 ZPlanes kk3PERF_flush_13plane: Tiles flushed with 13 ZPlanes l8l3PERF_flush_14plane: Tiles flushed with 14 ZPlanes `ml3PERF_flush_15plane: Tiles flushed with 15 ZPlanes nm3PERF_flush_16plane: Tiles flushed with 16 ZPlanes n`n6PERF_flush_expanded_z: Tiles flushed with expanded Z o o`PERF_earlyZ_waiting_for_postZ_done: Cycles stalled while transitioning from Late/ReZ to EarlyZ pprPERF_reZ_waiting_for_postZ_done: Cycles stalled while transitioning to ReZ from an incompatible Z mode/func/etc. qq@PERF_dk_tile_sends: Detail kill block tiles/squads/events sent 8rq2PERF_dk_tile_busy: Cycles Detail Kill block busy srZPERF_dk_tile_quad_starves: Cycles Detail Kill has tile, but no quads from the SC_DB_quad s`s?PERF_dk_tile_stalls: Cycles Detail Kill is stalled from below t(t)PERF_dk_squad_sends: Detail Kill squads Xut@PERF_dk_squad_busy: Cycles the squad Detail Kill input is busy vu=PERF_dk_squad_stalls: Cycles squads are stalled from below. whvrPERF_Op_Pipe_Busy: Cycles the quad OP pipe of the DB is busy (including memory fetches, but not initial startup) x`wkPERF_Op_Pipe_MC_Read_stall: Cycles the Op Pipe is waiting for memory to return (ignoring initial startup) xPx1PERF_qc_busy: Cycles the Quad Coherency is busy yyCPERF_qc_xfc: Number of transfers through the Quad Coherency block zyPERF_qc_conflicts: Stalls on a squad input because of a coherency check conflict (the same sample ahead of it could affect the dest data) h{zKPERF_qc_full_stall: Quad Coherency is stalled because it is out of slots. |{PERF_qc_in_preZ_tile_stalls_postZ: Cycles postZ squad inputs are stalled because the OP pipe is operating on a preZ tile, and there is no PreZ squad input available }|PERF_qc_in_postZ_tile_stalls_preZ: Cycles preZ squad inputs are stalled because the OP pipe is operating on a postZ tile, and there is no PostZ squad input available ~~rPERF_tsc_insert_summarize_stall: Cycles the op pipe is stalled by the tile summarizer inserting summarize squads x-PERF_tl_busy: Cycles Tile Lookup block busy 04PERF_tl_dtc_read_starved: Cycles Tile Lookup block xIPERF_tl_z_fetch_stall: Cycles Tile Lookup block stalled by zfetch block ؁HOPERF_tl_stencil_stall: Cycles Tile Lookup block stalled by stencil test block TPERF_tl_z_decompress_stall: Cycles Tile Lookup block stalled by z decompress block XPERF_tl_stencil_locked_stall: Cycles Tile Lookup block stalled by stencil being locked P؃;PERF_tl_events: Cycles Tile Lookup block sends out events (OPERF_tl_summarize_squads: Cycles Tile Lookup block sends out summarize squads pUPERF_tl_flush_expand_squads: Cycles Tile Lookup block sends out flush expand squads ؆PIPERF_tl_expand_squads: Cycles Tile Lookup block sends out expand squads EPERF_tl_preZ_squads: Cycles Tile Lookup block sends out preZ squads xGPERF_tl_postZ_squads: Cycles Tile Lookup block sends out postZ squads XUPERF_tl_preZ_noop_squads: Cycles Tile Lookup block sends out noops on the preZ path 8WPERF_tl_postZ_noop_squads: Cycles Tile Lookup block sends out noops on the postZ path NPERF_tl_getZ_squads: Cycles Tile Lookup block sends out z import pass squads XEPERF_tl_tile_ops: Cycles Tile Lookup block sends out tile op squads (=PERF_tl_in_xfc: Cycles Tile Lookup block receives any input nPERF_tl_in_single_stencil_expand_stall: Cycles Tile Lookup block is stalling due to expanding single stencil 荺ePERF_tl_in_constant_stencil_walk_stall: Cycles Tile Lookup block is stalling due to walking stencil `؎LPERF_tl_in_fast_z_stall: Cycles Tile Lookup block is stalling due to fastZ (CPERF_tl_out_xfc: Cycles Tile Lookup block is sending anything out pDPERF_tl_out_squads: Cycles Tile Lookup block is sending squads out 8PERF_zf_plane_multicycle: Cycles the z fetch is multicycling a squad because it needs to fetch more than 2 planes from the cache for compressed Z ؒPJPERF_PostZ_Samples_passing_Z: Samples passing Z test during a PostZ pass JPERF_PostZ_Samples_failing_Z: Samples failing Z test during a PostZ pass PPERF_PostZ_Samples_failing_S: Samples failing Stencil test during a PostZ pass PȔHPERF_PreZ_Samples_passing_Z: Samples passing Z test during a PreZ pass HPERF_PreZ_Samples_failing_Z: Samples failing Z test during a PreZ pass hNPERF_PreZ_Samples_failing_S: Samples failing Stencil test during a PreZ pass ؗ@ZPERF_ts_tc_update_stall: Cycles Tile Summarizer to Tile Cache write interface is stalled >PERF_sc_kick_start: Times the DB sent a hang panic to the SC `蘺7PERF_sc_kick_end: Times the DB completed a hang panic (>PERF_SX_DB_mem_exports: Number of memory exports from the SX pPPERF_SX_DB_mem_exports_acked: Number of memory export writes acked from the MC ؛HPPERF_SX_DB_ack_mem_exports: Number of ack requested memory exports from the SX SPERF_SX_DB_ack_mem_exports_acked: Number of memory export acks returned to the SX p5PERF_mem_export_busy: Cycles writing memory exports hsPERF_mem_export_mi_stall: Cycles mem exports are stalled waiting for other DB writes or MC write bus arbitration. PdPERF_mem_export_tag_stall: Cycles mem exports are stalled waiting for a free mem export write tag. <PERF_clock_reg_active: Cycles register part of DB is awake РX9PERF_clock_main_active: Cycles core part of DB is awake EPERF_clock_mem_export_active: Cycles mem export part of DB is awake `衺7PERF_esr_out_busy: Early Squad Router Out cycles busy ;PERF_esr_out_sc_stall: Early Squad Router Out to SC stall hZPERF_esr_out_lquad_fifo_full_stall: Early Squad Router Out to Late Quad Fifo full stalls H0PERF_etr_out_send: Early Tile Router Out sends x6PERF_etr_out_busy: Early Tile Router Out cycles busy hePERF_etr_out_ltile_probe_fifo_full_stall: Early Tile Router Out to Late Tile Probe Fifo full stalls 0APERF_etr_out_cb_tile_stall: Early Tile Router to CB tile stalls xIPERF_etr_out_esr_stall: Early Tile Router to Early Squad Router stalls. `@,,""DB0_PERFCOUNTER3_HI PERF_COUNT" ""(DB0_PERFCOUNTER2_HI PERF_COUNT"p""DB0_PERFCOUNTER1_HI PERF_COUNT" ""XDB0_PERFCOUNTER0_HI PERF_COUNT"((""DB0_PERFCOUNTER3_LOWH PERF_COUNT"@(""DB0_PERFCOUNTER2_LOW PERF_COUNT"""DB0_PERFCOUNTER1_LOWh PERF_COUNT"UH""DB0_PERFCOUNTER0_LOW PERF_COUNT"0xU$$""UDB0_PERFCOUNTER3_SELECT(VpV PERF_SEL(WV4PERF_SC_DB_tile_sends: Cycles Interface is sending WpW0PERF_SC_DB_tile_busy: Cycles Interface is busy X(X5PERF_SC_DB_tile_stalls: Cycles Interface is stalled XYX4PERF_SC_DB_tile_events: Events sent over interface ZY2PERF_SC_DB_tile_tiles: Tiles sent over interface ZXZ.PERF_SC_DB_tile_covered: Fully covered tiles [[IPERF_hiz_tc_read_starved: HiZ starved waiting for htile data from cache `\[=PERF_hiz_tc_write_stall: HiZ stalled writing to htile cache ]\5PERF_hiz_qtiles_culled: Quarter tiles culled by hiZ ]h] 5PERF_his_qtiles_culled: Quarter tiles culled by HiS ^(^ 4PERF_DB_SC_tile_sends: Cycles Interface is sending P_^ 0PERF_DB_SC_tile_busy: Cycles Interface is busy `_ ;PERF_DB_SC_tile_stalls: Cycles Interface is stalled by SC `X` QPERF_DB_SC_tile_df_stalls: Cycles Interface is stalled by detail walk tile fifo a0a2PERF_DB_SC_tile_tiles: Tiles sent over interface Xba/PERF_DB_SC_tile_culled: Tiles culled in total (cbIPERF_DB_SC_tile_hier_kill: Tiles culled due to a hierarchical fail test dpcSPERF_DB_SC_tile_fast_ops: Tiles culled because they were accerated fast tile ops. dHdIPERF_DB_SC_tile_no_ops: Tiles culled because they would not do anything eeTPERF_DB_SC_tile_pixel_rate: Tiles run at pixel rate as opposed to sample rate tile feqPERF_DB_SC_tile_ssaa_kill: Tiles culled because they were supersample tiles that are merged into a fast tile op gftPERF_DB_SC_tile_fast_z_ops: Tiles that operate on Z in 1 clock. Can be inside a slow, pixel rate, or fast tile op hgPERF_DB_SC_tile_fast_stencil_ops: Tiles that operate on stencil in 1 clock. Can be inside a slow, pixel rate, or fast tile op Xih4PERF_SC_DB_quad_sends: Cycles Interface is sending ji0PERF_SC_DB_quad_busy: Cycles Interface is busy jXj;PERF_SC_DB_quad_squads: Squads transferred over interface kk2PERF_SC_DB_quad_tiles: Tiles sent over interface Hlk:PERF_SC_DB_quad_pixels: Pixels transfered over interface ml=PERF_SC_DB_quad_killed_tiles: Number of detail killed tiles mXm4PERF_DB_SC_quad_sends: Cycles Interface is sending nn0PERF_DB_SC_quad_busy: Cycles Interface is busy @on5PERF_DB_SC_quad_stalls: Cycles Interface is stalled oo 4PERF_DB_SC_quad_squads: Squads sent over interface p@p!2PERF_DB_SC_quad_tiles: Tiles sent over interface qp"HPERF_DB_SC_quad_quads: Quads transferred over the DB_SC_quad interface xrq#nPERF_DB_CB_tile_sends: Cycles sending tiles/events to CB. Tiles not shaded or needed by the CB are not sent. sr$PERF_DB_CB_tile_busy: s`s%PERF_DB_CB_tile_stalls: ptt&4PERF_SX_DB_quad_sends: Cycles Interface is sending (ut'0PERF_SX_DB_quad_busy: Cycles Interface is busy upu(5PERF_SX_DB_quad_stalls: Cycles Interface is stalled v0v)2PERF_SX_DB_quad_quads: Quads sent over interface Xwv*4PERF_SX_DB_quad_pixels: Pixels sent over interface xw+APERF_SX_DB_quad_exports: Each MRT of a quad sent over interface yhx,bPERF_SH_quads_outstanding_sum: Multiple by 128 and divide by DB_SC_quad_quads to get PS latency. yPy-5PERF_DB_CB_lquad_sends: Cycles Interface is sending zz.1PERF_DB_CB_lquad_busy: Cycles Interface is busy @{z/6PERF_DB_CB_lquad_stalls: Cycles Interface is stalled {{03PERF_DB_CB_lquad_quads: Quads sent over interface |@|1/PERF_tile_rd_sends: HTile reads. Each is 256B }|2hPERF_mi_tile_rd_outstanding_sum: Multiply by 2 and divide by tile_rd_sends to get htile memory latency `~}3:PERF_quad_rd_sends: Quad read reqs. Each is 32B to 256B 0~4JPERF_quad_rd_busy: Cycles quad read interface is trying to send requests x5VPERF_quad_rd_mi_stall: Cycles quad read interface is stalled by the memory interface X6XPERF_quad_rd_rw_collision: Cycles a quad read is stalled waiting for a write to finish 87ePERF_quad_rd_tag_stall: Cycles a quad read is stalled because the read latency hiding fifo is full. (8@PERF_quad_rd_32byte_reqs: Number of 32 Byte quad read requests p9>PERF_quad_rd_panic: Cycles DB is panicing for quad read data p:vPERF_mi_quad_rd_outstanding_sum: Multiply by 16 and divide by quad_rd_32byte_reqs to get depth buffer memory latency 0;<PERF_quad_rdret_sends: Number of 32 byte quad read returns x<>PERF_quad_rdret_busy: Cycles the quad read data is returning @=*PERF_tile_wr_sends: 32 Byte HTile writes `>-PERF_tile_wr_acks: 32 Byte Htile write acks X?nPERF_mi_tile_wr_outstanding_sum: Multiply by 16 and divide by tile_wr_sends to get tile write memory latency @@cPERF_quad_wr_sends: Cycles quad is sending write requests to the memory interface block of the DB AKPERF_quad_wr_busy: Cycles quad is trying to write to the memory interface XBUPERF_quad_wr_mi_stall: Cycles quad is stalled while writing to the memory interface 8CwPERF_quad_wr_coherency_stall: Cycles quad write is stalled waiting for a previous write to finish on the same address 8D6PERF_quad_wr_acks: Number of 32 Byte quad write acks ErPERF_mi_quad_wr_outstanding_sum: Multiply by 16 and divide by the quad_wr_sends to get quad memory write latency XF,PERF_Tile_Cache_misses: Htile Cache misses G(PERF_Tile_Cache_hits: Htile Cache hits PH.PERF_Tile_Cache_flushes: Htile Cache flushes I[PERF_Tile_Cache_surface_stall: Tile stalls waiting for an htile surface to flush and free x萹JMPERF_Tile_Cache_starves: Tile stalls waiting for an htile cacheline to free XK[PERF_Tile_Cache_mem_return_starve: Tile stalls waiting for an htile memory read to return 8LYPERF_tcp_dispatcher_reads: Number of htile cachelines fetched by the normal tile stream MQPERF_tcp_prefetcher_reads: Number of htile cachelines fetched by the prefetcher 蔹XNOPERF_tcp_preloader_reads: Number of htile cachelines fetched by the preloader ȕ0OXPERF_tcp_dispatcher_flushes: Number of htile flushes caused byt the normal tile stream PWPERF_tcp_prefetcher_flushes: Number of htile flushes caused byt the normal prefetcher QUPERF_tcp_preloader_flushes: Number of htile flushes caused byt the normal preloader XЗRHPERF_Depth_Tile_Cache_sends: Tiles/Events through the Depth Tile Cache @SbPERF_Depth_Tile_Cache_busy: Cycles the Depth Tile Cache is busy testing hit/miss on tiles/events (T_PERF_Depth_Tile_Cache_starves: Cycles starved waiting for a depth surface tile tag to free up pUgPERF_Depth_Tile_Cache_dtile_locked: Cycles stalled waiting for a forced flush or invalidate to finish `VTPERF_Depth_Tile_Cache_alloc_stall: Cycles depth tile stalled while allocating data 8W?PERF_Depth_Tile_Cache_misses: Depth/Stencil Cache tile misses xX;PERF_Depth_Tile_Cache_hits: Depth/Stencil Cache tile hits @YAPERF_Depth_Tile_Cache_flushes: Depth/Stencil Cache tile flushes ZJPERF_Depth_Tile_Cache_noop_tile: Noop tiles through the depth tile cache X[VPERF_Depth_Tile_Cache_detailed_noop: Detail walked noops though the depth tile cache 8\%PERF_Depth_Tile_Cache_event: Events X蠹]4PERF_Depth_Tile_Cache_tile_frees: Depth tile frees @^cPERF_Depth_Tile_Cache_data_frees: Depth tile data frees (may free data without freeing the dtile) 0_ePERF_Depth_Tile_Cache_mem_return_starve: Cycles depth/stencil cache is waiting for memory to return 裹x`/PERF_Stencil_Cache_misses: 512 bit allocation 0aPERF_Stencil_Cache_hits: ФbpPERF_Stencil_Cache_flushes: 256 bit flushes. Two per cacheline unless it is compressed, in which case it is 1. xȥcmPERF_Stencil_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate dPERF_Stencil_Cache_frees: `e"PERF_Z_Cache_separate_Z_misses: hf PERF_Z_Cache_separate_Z_hits: g#PERF_Z_Cache_separate_Z_flushes: XhrPERF_Z_Cache_separate_Z_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate PiPERF_Z_Cache_pmask_misses: PjPERF_Z_Cache_pmask_hits: kPERF_Z_Cache_pmask_flushes: @lmPERF_Z_Cache_pmask_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate 8mPERF_Z_Cache_frees: 0حnPERF_Plane_Cache_misses: ЮxoPERF_Plane_Cache_hits: ppPERF_Plane_Cache_flushes: `qkPERF_Plane_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate rPERF_Plane_Cache_frees: бHsGPERF_flush_expanded_stencil: Tiles flushed with with expanded stencil tKPERF_flush_compressed_stencil: Tiles flushed with with compressed stencil h貹uCPERF_flush_single_stencil: Tiles flushed with with single stencil v0PERF_flush_1plane: Tiles flushed with 1 ZPlane شhw1PERF_flush_2plane: Tiles flushed with 2 ZPlanes x1PERF_flush_3plane: Tiles flushed with 3 ZPlanes Hصy1PERF_flush_4plane: Tiles flushed with 4 ZPlanes z1PERF_flush_5plane: Tiles flushed with 5 ZPlanes H{1PERF_flush_6plane: Tiles flushed with 6 ZPlanes p|1PERF_flush_7plane: Tiles flushed with 7 ZPlanes (}1PERF_flush_8plane: Tiles flushed with 8 ZPlanes ๹p~1PERF_flush_9plane: Tiles flushed with 9 ZPlanes (3PERF_flush_10plane: Tiles flushed with 10 ZPlanes Pູ3PERF_flush_11plane: Tiles flushed with 11 ZPlanes 3PERF_flush_12plane: Tiles flushed with 12 ZPlanes P3PERF_flush_13plane: Tiles flushed with 13 ZPlanes x3PERF_flush_14plane: Tiles flushed with 14 ZPlanes 03PERF_flush_15plane: Tiles flushed with 15 ZPlanes 边x3PERF_flush_16plane: Tiles flushed with 16 ZPlanes 06PERF_flush_expanded_z: Tiles flushed with expanded Z `PERF_earlyZ_waiting_for_postZ_done: Cycles stalled while transitioning from Late/ReZ to EarlyZ rPERF_reZ_waiting_for_postZ_done: Cycles stalled while transitioning to ReZ from an incompatible Z mode/func/etc. P¹@PERF_dk_tile_sends: Detail kill block tiles/squads/events sent ù¹2PERF_dk_tile_busy: Cycles Detail Kill block busy ùPùZPERF_dk_tile_quad_starves: Cycles Detail Kill has tile, but no quads from the SC_DB_quad Ĺ0Ĺ?PERF_dk_tile_stalls: Cycles Detail Kill is stalled from below `ŹĹ)PERF_dk_squad_sends: Detail Kill squads (ƹŹ@PERF_dk_squad_busy: Cycles the squad Detail Kill input is busy ƹpƹ=PERF_dk_squad_stalls: Cycles squads are stalled from below. ǹ8ǹrPERF_Op_Pipe_Busy: Cycles the quad OP pipe of the DB is busy (including memory fetches, but not initial startup) ȹ0ȹkPERF_Op_Pipe_MC_Read_stall: Cycles the Op Pipe is waiting for memory to return (ignoring initial startup) ɹ ɹ1PERF_qc_busy: Cycles the Quad Coherency is busy XʹɹCPERF_qc_xfc: Number of transfers through the Quad Coherency block h˹ʹPERF_qc_conflicts: Stalls on a squad input because of a coherency check conflict (the same sample ahead of it could affect the dest data) 8̹˹KPERF_qc_full_stall: Quad Coherency is stalled because it is out of slots. h͹̹PERF_qc_in_preZ_tile_stalls_postZ: Cycles postZ squad inputs are stalled because the OP pipe is operating on a preZ tile, and there is no PreZ squad input available ι͹PERF_qc_in_postZ_tile_stalls_preZ: Cycles preZ squad inputs are stalled because the OP pipe is operating on a postZ tile, and there is no PostZ squad input available ϹιrPERF_tsc_insert_summarize_stall: Cycles the op pipe is stalled by the tile summarizer inserting summarize squads HйϹ-PERF_tl_busy: Cycles Tile Lookup block busy ѹй4PERF_tl_dtc_read_starved: Cycles Tile Lookup block ѹHѹIPERF_tl_z_fetch_stall: Cycles Tile Lookup block stalled by zfetch block ҹҹOPERF_tl_stencil_stall: Cycles Tile Lookup block stalled by stencil test block ӹҹTPERF_tl_z_decompress_stall: Cycles Tile Lookup block stalled by z decompress block `ԹӹXPERF_tl_stencil_locked_stall: Cycles Tile Lookup block stalled by stencil being locked չԹ;PERF_tl_events: Cycles Tile Lookup block sends out events չhչOPERF_tl_summarize_squads: Cycles Tile Lookup block sends out summarize squads ֹ@ֹUPERF_tl_flush_expand_squads: Cycles Tile Lookup block sends out flush expand squads ׹ ׹IPERF_tl_expand_squads: Cycles Tile Lookup block sends out expand squads xع׹EPERF_tl_preZ_squads: Cycles Tile Lookup block sends out preZ squads HٹعGPERF_tl_postZ_squads: Cycles Tile Lookup block sends out postZ squads (ڹٹUPERF_tl_preZ_noop_squads: Cycles Tile Lookup block sends out noops on the preZ path ۹pڹWPERF_tl_postZ_noop_squads: Cycles Tile Lookup block sends out noops on the postZ path ۹P۹NPERF_tl_getZ_squads: Cycles Tile Lookup block sends out z import pass squads ܹ(ܹEPERF_tl_tile_ops: Cycles Tile Lookup block sends out tile op squads xݹܹ=PERF_tl_in_xfc: Cycles Tile Lookup block receives any input p޹ݹnPERF_tl_in_single_stencil_expand_stall: Cycles Tile Lookup block is stalling due to expanding single stencil `߹޹ePERF_tl_in_constant_stencil_walk_stall: Cycles Tile Lookup block is stalling due to walking stencil 0߹LPERF_tl_in_fast_z_stall: Cycles Tile Lookup block is stalling due to fastZ xCPERF_tl_out_xfc: Cycles Tile Lookup block is sending anything out @DPERF_tl_out_squads: Cycles Tile Lookup block is sending squads out PERF_zf_plane_multicycle: Cycles the z fetch is multicycling a squad because it needs to fetch more than 2 planes from the cache for compressed Z JPERF_PostZ_Samples_passing_Z: Samples passing Z test during a PostZ pass xJPERF_PostZ_Samples_failing_Z: Samples failing Z test during a PostZ pass PPPERF_PostZ_Samples_failing_S: Samples failing Stencil test during a PostZ pass HPERF_PreZ_Samples_passing_Z: Samples passing Z test during a PreZ pass hHPERF_PreZ_Samples_failing_Z: Samples failing Z test during a PreZ pass 8NPERF_PreZ_Samples_failing_S: Samples failing Stencil test during a PreZ pass ZPERF_ts_tc_update_stall: Cycles Tile Summarizer to Tile Cache write interface is stalled p>PERF_sc_kick_start: Times the DB sent a hang panic to the SC 07PERF_sc_kick_end: Times the DB completed a hang panic x>PERF_SX_DB_mem_exports: Number of memory exports from the SX @PPERF_SX_DB_mem_exports_acked: Number of memory export writes acked from the MC PPERF_SX_DB_ack_mem_exports: Number of ack requested memory exports from the SX SPERF_SX_DB_ack_mem_exports_acked: Number of memory export acks returned to the SX @5PERF_mem_export_busy: Cycles writing memory exports 8sPERF_mem_export_mi_stall: Cycles mem exports are stalled waiting for other DB writes or MC write bus arbitration. dPERF_mem_export_tag_stall: Cycles mem exports are stalled waiting for a free mem export write tag. h<PERF_clock_reg_active: Cycles register part of DB is awake (9PERF_clock_main_active: Cycles core part of DB is awake pEPERF_clock_mem_export_active: Cycles mem export part of DB is awake 07PERF_esr_out_busy: Early Squad Router Out cycles busy x;PERF_esr_out_sc_stall: Early Squad Router Out to SC stall 8ZPERF_esr_out_lquad_fifo_full_stall: Early Squad Router Out to Late Quad Fifo full stalls 0PERF_etr_out_send: Early Tile Router Out sends H6PERF_etr_out_busy: Early Tile Router Out cycles busy 8ePERF_etr_out_ltile_probe_fifo_full_stall: Early Tile Router Out to Late Tile Probe Fifo full stalls APERF_etr_out_cb_tile_stall: Early Tile Router to CB tile stalls HIPERF_etr_out_esr_stall: Early Tile Router to Early Squad Router stalls. X ""DB0_PERFCOUNTER2_SELECTX PERF_SELX貸4PERF_SC_DB_tile_sends: Cycles Interface is sending 0PERF_SC_DB_tile_busy: Cycles Interface is busy дX5PERF_SC_DB_tile_stalls: Cycles Interface is stalled 4PERF_SC_DB_tile_events: Events sent over interface @е2PERF_SC_DB_tile_tiles: Tiles sent over interface .PERF_SC_DB_tile_covered: Fully covered tiles ȷ@IPERF_hiz_tc_read_starved: HiZ starved waiting for htile data from cache =PERF_hiz_tc_write_stall: HiZ stalled writing to htile cache Pظ5PERF_hiz_qtiles_culled: Quarter tiles culled by hiZ  5PERF_his_qtiles_culled: Quarter tiles culled by HiS ȺX 4PERF_DB_SC_tile_sends: Cycles Interface is sending  0PERF_DB_SC_tile_busy: Cycles Interface is busy @Ȼ ;PERF_DB_SC_tile_stalls: Cycles Interface is stalled by SC  QPERF_DB_SC_tile_df_stalls: Cycles Interface is stalled by detail walk tile fifo н`2PERF_DB_SC_tile_tiles: Tiles sent over interface /PERF_DB_SC_tile_culled: Tiles culled in total XоIPERF_DB_SC_tile_hier_kill: Tiles culled due to a hierarchical fail test 0SPERF_DB_SC_tile_fast_ops: Tiles culled because they were accerated fast tile ops. xIPERF_DB_SC_tile_no_ops: Tiles culled because they would not do anything HTPERF_DB_SC_tile_pixel_rate: Tiles run at pixel rate as opposed to sample rate tile ¸ ¸qPERF_DB_SC_tile_ssaa_kill: Tiles culled because they were supersample tiles that are merged into a fast tile op øøtPERF_DB_SC_tile_fast_z_ops: Tiles that operate on Z in 1 clock. Can be inside a slow, pixel rate, or fast tile op ĸĸPERF_DB_SC_tile_fast_stencil_ops: Tiles that operate on stencil in 1 clock. Can be inside a slow, pixel rate, or fast tile op ŸŸ4PERF_SC_DB_quad_sends: Cycles Interface is sending @ƸŸ0PERF_SC_DB_quad_busy: Cycles Interface is busy ǸƸ;PERF_SC_DB_quad_squads: Squads transferred over interface ǸHǸ2PERF_SC_DB_quad_tiles: Tiles sent over interface xȸȸ:PERF_SC_DB_quad_pixels: Pixels transfered over interface @ɸȸ=PERF_SC_DB_quad_killed_tiles: Number of detail killed tiles ɸɸ4PERF_DB_SC_quad_sends: Cycles Interface is sending ʸ@ʸ0PERF_DB_SC_quad_busy: Cycles Interface is busy p˸ʸ5PERF_DB_SC_quad_stalls: Cycles Interface is stalled (̸˸ 4PERF_DB_SC_quad_squads: Squads sent over interface ̸p̸!2PERF_DB_SC_quad_tiles: Tiles sent over interface ͸(͸"HPERF_DB_SC_quad_quads: Quads transferred over the DB_SC_quad interface θ͸#nPERF_DB_CB_tile_sends: Cycles sending tiles/events to CB. Tiles not shaded or needed by the CB are not sent. Hϸθ$PERF_DB_CB_tile_busy: ϸϸ%PERF_DB_CB_tile_stalls: и0и&4PERF_SX_DB_quad_sends: Cycles Interface is sending XѸи'0PERF_SX_DB_quad_busy: Cycles Interface is busy ҸѸ(5PERF_SX_DB_quad_stalls: Cycles Interface is stalled Ҹ`Ҹ)2PERF_SX_DB_quad_quads: Quads sent over interface ӸӸ*4PERF_SX_DB_quad_pixels: Pixels sent over interface PԸӸ+APERF_SX_DB_quad_exports: Each MRT of a quad sent over interface 8ոԸ,bPERF_SH_quads_outstanding_sum: Multiple by 128 and divide by DB_SC_quad_quads to get PS latency. ոո-5PERF_DB_CB_lquad_sends: Cycles Interface is sending ָ@ָ.1PERF_DB_CB_lquad_busy: Cycles Interface is busy p׸ָ/6PERF_DB_CB_lquad_stalls: Cycles Interface is stalled (ظ׸03PERF_DB_CB_lquad_quads: Quads sent over interface ظpظ1/PERF_tile_rd_sends: HTile reads. Each is 256B ٸ(ٸ2hPERF_mi_tile_rd_outstanding_sum: Multiply by 2 and divide by tile_rd_sends to get htile memory latency ڸڸ3:PERF_quad_rd_sends: Quad read reqs. Each is 32B to 256B `۸ڸ4JPERF_quad_rd_busy: Cycles quad read interface is trying to send requests @ܸ۸5VPERF_quad_rd_mi_stall: Cycles quad read interface is stalled by the memory interface ݸܸ6XPERF_quad_rd_rw_collision: Cycles a quad read is stalled waiting for a write to finish ޸hݸ7ePERF_quad_rd_tag_stall: Cycles a quad read is stalled because the read latency hiding fifo is full. ޸X޸8@PERF_quad_rd_32byte_reqs: Number of 32 Byte quad read requests ߸ ߸9>PERF_quad_rd_panic: Cycles DB is panicing for quad read data ߸:vPERF_mi_quad_rd_outstanding_sum: Multiply by 16 and divide by quad_rd_32byte_reqs to get depth buffer memory latency `;<PERF_quad_rdret_sends: Number of 32 byte quad read returns (<>PERF_quad_rdret_busy: Cycles the quad read data is returning p=*PERF_tile_wr_sends: 32 Byte HTile writes >-PERF_tile_wr_acks: 32 Byte Htile write acks ?nPERF_mi_tile_wr_outstanding_sum: Multiply by 16 and divide by tile_wr_sends to get tile write memory latency p@cPERF_quad_wr_sends: Cycles quad is sending write requests to the memory interface block of the DB @AKPERF_quad_wr_busy: Cycles quad is trying to write to the memory interface BUPERF_quad_wr_mi_stall: Cycles quad is stalled while writing to the memory interface hCwPERF_quad_wr_coherency_stall: Cycles quad write is stalled waiting for a previous write to finish on the same address hD6PERF_quad_wr_acks: Number of 32 Byte quad write acks (ErPERF_mi_quad_wr_outstanding_sum: Multiply by 16 and divide by the quad_wr_sends to get quad memory write latency F,PERF_Tile_Cache_misses: Htile Cache misses 8G(PERF_Tile_Cache_hits: Htile Cache hits H.PERF_Tile_Cache_flushes: Htile Cache flushes 8I[PERF_Tile_Cache_surface_stall: Tile stalls waiting for an htile surface to flush and free JMPERF_Tile_Cache_starves: Tile stalls waiting for an htile cacheline to free K[PERF_Tile_Cache_mem_return_starve: Tile stalls waiting for an htile memory read to return hLYPERF_tcp_dispatcher_reads: Number of htile cachelines fetched by the normal tile stream @MQPERF_tcp_prefetcher_reads: Number of htile cachelines fetched by the prefetcher NOPERF_tcp_preloader_reads: Number of htile cachelines fetched by the preloader `OXPERF_tcp_dispatcher_flushes: Number of htile flushes caused byt the normal tile stream @PWPERF_tcp_prefetcher_flushes: Number of htile flushes caused byt the normal prefetcher QUPERF_tcp_preloader_flushes: Number of htile flushes caused byt the normal preloader RHPERF_Depth_Tile_Cache_sends: Tiles/Events through the Depth Tile Cache pSbPERF_Depth_Tile_Cache_busy: Cycles the Depth Tile Cache is busy testing hit/miss on tiles/events XT_PERF_Depth_Tile_Cache_starves: Cycles starved waiting for a depth surface tile tag to free up HUgPERF_Depth_Tile_Cache_dtile_locked: Cycles stalled waiting for a forced flush or invalidate to finish VTPERF_Depth_Tile_Cache_alloc_stall: Cycles depth tile stalled while allocating data hW?PERF_Depth_Tile_Cache_misses: Depth/Stencil Cache tile misses 0X;PERF_Depth_Tile_Cache_hits: Depth/Stencil Cache tile hits pYAPERF_Depth_Tile_Cache_flushes: Depth/Stencil Cache tile flushes @ZJPERF_Depth_Tile_Cache_noop_tile: Noop tiles through the depth tile cache [VPERF_Depth_Tile_Cache_detailed_noop: Detail walked noops though the depth tile cache h\%PERF_Depth_Tile_Cache_event: Events ]4PERF_Depth_Tile_Cache_tile_frees: Depth tile frees p^cPERF_Depth_Tile_Cache_data_frees: Depth tile data frees (may free data without freeing the dtile) `_ePERF_Depth_Tile_Cache_mem_return_starve: Cycles depth/stencil cache is waiting for memory to return `/PERF_Stencil_Cache_misses: 512 bit allocation `aPERF_Stencil_Cache_hits: bpPERF_Stencil_Cache_flushes: 256 bit flushes. Two per cacheline unless it is compressed, in which case it is 1. cmPERF_Stencil_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate HdPERF_Stencil_Cache_frees: e"PERF_Z_Cache_separate_Z_misses: 8f PERF_Z_Cache_separate_Z_hits: @g#PERF_Z_Cache_separate_Z_flushes: 8hrPERF_Z_Cache_separate_Z_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate iPERF_Z_Cache_pmask_misses: (jPERF_Z_Cache_pmask_hits: (kPERF_Z_Cache_pmask_flushes: plmPERF_Z_Cache_pmask_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate h mPERF_Z_Cache_frees: `  nPERF_Plane_Cache_misses: oPERF_Plane_Cache_hits: H pPERF_Plane_Cache_flushes: qkPERF_Plane_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate 0 rPERF_Plane_Cache_frees: x sGPERF_flush_expanded_stencil: Tiles flushed with with expanded stencil HtKPERF_flush_compressed_stencil: Tiles flushed with with compressed stencil uCPERF_flush_single_stencil: Tiles flushed with with single stencil Pv0PERF_flush_1plane: Tiles flushed with 1 ZPlane w1PERF_flush_2plane: Tiles flushed with 2 ZPlanes Px1PERF_flush_3plane: Tiles flushed with 3 ZPlanes xy1PERF_flush_4plane: Tiles flushed with 4 ZPlanes 0z1PERF_flush_5plane: Tiles flushed with 5 ZPlanes x{1PERF_flush_6plane: Tiles flushed with 6 ZPlanes 0|1PERF_flush_7plane: Tiles flushed with 7 ZPlanes X}1PERF_flush_8plane: Tiles flushed with 8 ZPlanes ~1PERF_flush_9plane: Tiles flushed with 9 ZPlanes X3PERF_flush_10plane: Tiles flushed with 10 ZPlanes 3PERF_flush_11plane: Tiles flushed with 11 ZPlanes 83PERF_flush_12plane: Tiles flushed with 12 ZPlanes 3PERF_flush_13plane: Tiles flushed with 13 ZPlanes 83PERF_flush_14plane: Tiles flushed with 14 ZPlanes `3PERF_flush_15plane: Tiles flushed with 15 ZPlanes 3PERF_flush_16plane: Tiles flushed with 16 ZPlanes `6PERF_flush_expanded_z: Tiles flushed with expanded Z  `PERF_earlyZ_waiting_for_postZ_done: Cycles stalled while transitioning from Late/ReZ to EarlyZ rPERF_reZ_waiting_for_postZ_done: Cycles stalled while transitioning to ReZ from an incompatible Z mode/func/etc. @PERF_dk_tile_sends: Detail kill block tiles/squads/events sent 82PERF_dk_tile_busy: Cycles Detail Kill block busy  ZPERF_dk_tile_quad_starves: Cycles Detail Kill has tile, but no quads from the SC_DB_quad ` ?PERF_dk_tile_stalls: Cycles Detail Kill is stalled from below !(!)PERF_dk_squad_sends: Detail Kill squads X"!@PERF_dk_squad_busy: Cycles the squad Detail Kill input is busy #"=PERF_dk_squad_stalls: Cycles squads are stalled from below. $h#rPERF_Op_Pipe_Busy: Cycles the quad OP pipe of the DB is busy (including memory fetches, but not initial startup) %`$kPERF_Op_Pipe_MC_Read_stall: Cycles the Op Pipe is waiting for memory to return (ignoring initial startup) %P%1PERF_qc_busy: Cycles the Quad Coherency is busy &&CPERF_qc_xfc: Number of transfers through the Quad Coherency block '&PERF_qc_conflicts: Stalls on a squad input because of a coherency check conflict (the same sample ahead of it could affect the dest data) h('KPERF_qc_full_stall: Quad Coherency is stalled because it is out of slots. )(PERF_qc_in_preZ_tile_stalls_postZ: Cycles postZ squad inputs are stalled because the OP pipe is operating on a preZ tile, and there is no PreZ squad input available *)PERF_qc_in_postZ_tile_stalls_preZ: Cycles preZ squad inputs are stalled because the OP pipe is operating on a postZ tile, and there is no PostZ squad input available ++rPERF_tsc_insert_summarize_stall: Cycles the op pipe is stalled by the tile summarizer inserting summarize squads x,,-PERF_tl_busy: Cycles Tile Lookup block busy 0-,4PERF_tl_dtc_read_starved: Cycles Tile Lookup block .x-IPERF_tl_z_fetch_stall: Cycles Tile Lookup block stalled by zfetch block .H.OPERF_tl_stencil_stall: Cycles Tile Lookup block stalled by stencil test block / /TPERF_tl_z_decompress_stall: Cycles Tile Lookup block stalled by z decompress block 0/XPERF_tl_stencil_locked_stall: Cycles Tile Lookup block stalled by stencil being locked P10;PERF_tl_events: Cycles Tile Lookup block sends out events (21OPERF_tl_summarize_squads: Cycles Tile Lookup block sends out summarize squads 3p2UPERF_tl_flush_expand_squads: Cycles Tile Lookup block sends out flush expand squads 3P3IPERF_tl_expand_squads: Cycles Tile Lookup block sends out expand squads 4 4EPERF_tl_preZ_squads: Cycles Tile Lookup block sends out preZ squads x54GPERF_tl_postZ_squads: Cycles Tile Lookup block sends out postZ squads X65UPERF_tl_preZ_noop_squads: Cycles Tile Lookup block sends out noops on the preZ path 876WPERF_tl_postZ_noop_squads: Cycles Tile Lookup block sends out noops on the postZ path 87NPERF_tl_getZ_squads: Cycles Tile Lookup block sends out z import pass squads 8X8EPERF_tl_tile_ops: Cycles Tile Lookup block sends out tile op squads 9(9=PERF_tl_in_xfc: Cycles Tile Lookup block receives any input :9nPERF_tl_in_single_stencil_expand_stall: Cycles Tile Lookup block is stalling due to expanding single stencil ;:ePERF_tl_in_constant_stencil_walk_stall: Cycles Tile Lookup block is stalling due to walking stencil `<;LPERF_tl_in_fast_z_stall: Cycles Tile Lookup block is stalling due to fastZ (=<CPERF_tl_out_xfc: Cycles Tile Lookup block is sending anything out =p=DPERF_tl_out_squads: Cycles Tile Lookup block is sending squads out ?8>PERF_zf_plane_multicycle: Cycles the z fetch is multicycling a squad because it needs to fetch more than 2 planes from the cache for compressed Z ?P?JPERF_PostZ_Samples_passing_Z: Samples passing Z test during a PostZ pass @ @JPERF_PostZ_Samples_failing_Z: Samples failing Z test during a PostZ pass A@PPERF_PostZ_Samples_failing_S: Samples failing Stencil test during a PostZ pass PBAHPERF_PreZ_Samples_passing_Z: Samples passing Z test during a PreZ pass CBHPERF_PreZ_Samples_failing_Z: Samples failing Z test during a PreZ pass ChCNPERF_PreZ_Samples_failing_S: Samples failing Stencil test during a PreZ pass D@DZPERF_ts_tc_update_stall: Cycles Tile Summarizer to Tile Cache write interface is stalled E E>PERF_sc_kick_start: Times the DB sent a hang panic to the SC `FE7PERF_sc_kick_end: Times the DB completed a hang panic (GF>PERF_SX_DB_mem_exports: Number of memory exports from the SX HpGPPERF_SX_DB_mem_exports_acked: Number of memory export writes acked from the MC HHHPPERF_SX_DB_ack_mem_exports: Number of ack requested memory exports from the SX I ISPERF_SX_DB_ack_mem_exports_acked: Number of memory export acks returned to the SX pJI5PERF_mem_export_busy: Cycles writing memory exports hKJsPERF_mem_export_mi_stall: Cycles mem exports are stalled waiting for other DB writes or MC write bus arbitration. PLKdPERF_mem_export_tag_stall: Cycles mem exports are stalled waiting for a free mem export write tag. ML<PERF_clock_reg_active: Cycles register part of DB is awake MXM9PERF_clock_main_active: Cycles core part of DB is awake NNEPERF_clock_mem_export_active: Cycles mem export part of DB is awake `ON7PERF_esr_out_busy: Early Squad Router Out cycles busy PO;PERF_esr_out_sc_stall: Early Squad Router Out to SC stall QhPZPERF_esr_out_lquad_fifo_full_stall: Early Squad Router Out to Late Quad Fifo full stalls QHQ0PERF_etr_out_send: Early Tile Router Out sends xRR6PERF_etr_out_busy: Early Tile Router Out cycles busy hSRePERF_etr_out_ltile_probe_fifo_full_stall: Early Tile Router Out to Late Tile Probe Fifo full stalls 0TSAPERF_etr_out_cb_tile_stall: Early Tile Router to CB tile stalls xTIPERF_etr_out_esr_stall: Early Tile Router to Early Squad Router stalls. i  ""(DB0_PERFCOUNTER1_SELECT PERF_SEL4PERF_SC_DB_tile_sends: Cycles Interface is sending 80PERF_SC_DB_tile_busy: Cycles Interface is busy 5PERF_SC_DB_tile_stalls: Cycles Interface is stalled @4PERF_SC_DB_tile_events: Events sent over interface h2PERF_SC_DB_tile_tiles: Tiles sent over interface .PERF_SC_DB_tile_covered: Fully covered tiles hIPERF_hiz_tc_read_starved: HiZ starved waiting for htile data from cache 8=PERF_hiz_tc_write_stall: HiZ stalled writing to htile cache x5PERF_hiz_qtiles_culled: Quarter tiles culled by hiZ 8 5PERF_his_qtiles_culled: Quarter tiles culled by HiS  4PERF_DB_SC_tile_sends: Cycles Interface is sending 8 0PERF_DB_SC_tile_busy: Cycles Interface is busy h ;PERF_DB_SC_tile_stalls: Cycles Interface is stalled by SC @ QPERF_DB_SC_tile_df_stalls: Cycles Interface is stalled by detail walk tile fifo 2PERF_DB_SC_tile_tiles: Tiles sent over interface @/PERF_DB_SC_tile_culled: Tiles culled in total IPERF_DB_SC_tile_hier_kill: Tiles culled due to a hierarchical fail test XSPERF_DB_SC_tile_fast_ops: Tiles culled because they were accerated fast tile ops. (IPERF_DB_SC_tile_no_ops: Tiles culled because they would not do anything pTPERF_DB_SC_tile_pixel_rate: Tiles run at pixel rate as opposed to sample rate tile HqPERF_DB_SC_tile_ssaa_kill: Tiles culled because they were supersample tiles that are merged into a fast tile op @tPERF_DB_SC_tile_fast_z_ops: Tiles that operate on Z in 1 clock. Can be inside a slow, pixel rate, or fast tile op 8 PERF_DB_SC_tile_fast_stencil_ops: Tiles that operate on stencil in 1 clock. Can be inside a slow, pixel rate, or fast tile op !@!4PERF_SC_DB_quad_sends: Cycles Interface is sending h"!0PERF_SC_DB_quad_busy: Cycles Interface is busy (#";PERF_SC_DB_quad_squads: Squads transferred over interface #p#2PERF_SC_DB_quad_tiles: Tiles sent over interface $($:PERF_SC_DB_quad_pixels: Pixels transfered over interface h%$=PERF_SC_DB_quad_killed_tiles: Number of detail killed tiles &%4PERF_DB_SC_quad_sends: Cycles Interface is sending &h&0PERF_DB_SC_quad_busy: Cycles Interface is busy ' '5PERF_DB_SC_quad_stalls: Cycles Interface is stalled P(' 4PERF_DB_SC_quad_squads: Squads sent over interface )(!2PERF_DB_SC_quad_tiles: Tiles sent over interface )P)"HPERF_DB_SC_quad_quads: Quads transferred over the DB_SC_quad interface * *#nPERF_DB_CB_tile_sends: Cycles sending tiles/events to CB. Tiles not shaded or needed by the CB are not sent. p++$PERF_DB_CB_tile_busy: ,+%PERF_DB_CB_tile_stalls: ,X,&4PERF_SX_DB_quad_sends: Cycles Interface is sending --'0PERF_SX_DB_quad_busy: Cycles Interface is busy @.-(5PERF_SX_DB_quad_stalls: Cycles Interface is stalled ..)2PERF_SX_DB_quad_quads: Quads sent over interface /@/*4PERF_SX_DB_quad_pixels: Pixels sent over interface x0/+APERF_SX_DB_quad_exports: Each MRT of a quad sent over interface `10,bPERF_SH_quads_outstanding_sum: Multiple by 128 and divide by DB_SC_quad_quads to get PS latency. 21-5PERF_DB_CB_lquad_sends: Cycles Interface is sending 2h2.1PERF_DB_CB_lquad_busy: Cycles Interface is busy 3 3/6PERF_DB_CB_lquad_stalls: Cycles Interface is stalled P4303PERF_DB_CB_lquad_quads: Quads sent over interface 541/PERF_tile_rd_sends: HTile reads. Each is 256B 5P52hPERF_mi_tile_rd_outstanding_sum: Multiply by 2 and divide by tile_rd_sends to get htile memory latency 6@63:PERF_quad_rd_sends: Quad read reqs. Each is 32B to 256B 774JPERF_quad_rd_busy: Cycles quad read interface is trying to send requests h875VPERF_quad_rd_mi_stall: Cycles quad read interface is stalled by the memory interface H986XPERF_quad_rd_rw_collision: Cycles a quad read is stalled waiting for a write to finish 8:97ePERF_quad_rd_tag_stall: Cycles a quad read is stalled because the read latency hiding fifo is full. ;:8@PERF_quad_rd_32byte_reqs: Number of 32 Byte quad read requests ;H;9>PERF_quad_rd_panic: Cycles DB is panicing for quad read data <<:vPERF_mi_quad_rd_outstanding_sum: Multiply by 16 and divide by quad_rd_32byte_reqs to get depth buffer memory latency ==;<PERF_quad_rdret_sends: Number of 32 byte quad read returns P>=<>PERF_quad_rdret_busy: Cycles the quad read data is returning ?>=*PERF_tile_wr_sends: 32 Byte HTile writes ?H?>-PERF_tile_wr_acks: 32 Byte Htile write acks @@?nPERF_mi_tile_wr_outstanding_sum: Multiply by 16 and divide by tile_wr_sends to get tile write memory latency AA@cPERF_quad_wr_sends: Cycles quad is sending write requests to the memory interface block of the DB pBAAKPERF_quad_wr_busy: Cycles quad is trying to write to the memory interface PCBBUPERF_quad_wr_mi_stall: Cycles quad is stalled while writing to the memory interface PDCCwPERF_quad_wr_coherency_stall: Cycles quad write is stalled waiting for a previous write to finish on the same address EDD6PERF_quad_wr_acks: Number of 32 Byte quad write acks FXEErPERF_mi_quad_wr_outstanding_sum: Multiply by 16 and divide by the quad_wr_sends to get quad memory write latency FPFF,PERF_Tile_Cache_misses: Htile Cache misses hGGG(PERF_Tile_Cache_hits: Htile Cache hits HGH.PERF_Tile_Cache_flushes: Htile Cache flushes IhHI[PERF_Tile_Cache_surface_stall: Tile stalls waiting for an htile surface to flush and free IHIJMPERF_Tile_Cache_starves: Tile stalls waiting for an htile cacheline to free J JK[PERF_Tile_Cache_mem_return_starve: Tile stalls waiting for an htile memory read to return KKLYPERF_tcp_dispatcher_reads: Number of htile cachelines fetched by the normal tile stream pLKMQPERF_tcp_prefetcher_reads: Number of htile cachelines fetched by the prefetcher HMLNOPERF_tcp_preloader_reads: Number of htile cachelines fetched by the preloader (NMOXPERF_tcp_dispatcher_flushes: Number of htile flushes caused byt the normal tile stream OpNPWPERF_tcp_prefetcher_flushes: Number of htile flushes caused byt the normal prefetcher OPOQUPERF_tcp_preloader_flushes: Number of htile flushes caused byt the normal preloader P0PRHPERF_Depth_Tile_Cache_sends: Tiles/Events through the Depth Tile Cache QQSbPERF_Depth_Tile_Cache_busy: Cycles the Depth Tile Cache is busy testing hit/miss on tiles/events RQT_PERF_Depth_Tile_Cache_starves: Cycles starved waiting for a depth surface tile tag to free up xSRUgPERF_Depth_Tile_Cache_dtile_locked: Cycles stalled waiting for a forced flush or invalidate to finish PTSVTPERF_Depth_Tile_Cache_alloc_stall: Cycles depth tile stalled while allocating data UTW?PERF_Depth_Tile_Cache_misses: Depth/Stencil Cache tile misses U`UX;PERF_Depth_Tile_Cache_hits: Depth/Stencil Cache tile hits V VYAPERF_Depth_Tile_Cache_flushes: Depth/Stencil Cache tile flushes pWVZJPERF_Depth_Tile_Cache_noop_tile: Noop tiles through the depth tile cache PXW[VPERF_Depth_Tile_Cache_detailed_noop: Detail walked noops though the depth tile cache YX\%PERF_Depth_Tile_Cache_event: Events YHY]4PERF_Depth_Tile_Cache_tile_frees: Depth tile frees ZZ^cPERF_Depth_Tile_Cache_data_frees: Depth tile data frees (may free data without freeing the dtile) [Z_ePERF_Depth_Tile_Cache_mem_return_starve: Cycles depth/stencil cache is waiting for memory to return H\[`/PERF_Stencil_Cache_misses: 512 bit allocation \\aPERF_Stencil_Cache_hits: ]0]bpPERF_Stencil_Cache_flushes: 256 bit flushes. Two per cacheline unless it is compressed, in which case it is 1. ^(^cmPERF_Stencil_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate x_ _dPERF_Stencil_Cache_frees: `_e"PERF_Z_Cache_separate_Z_misses: `h`f PERF_Z_Cache_separate_Z_hits: paag#PERF_Z_Cache_separate_Z_flushes: hbahrPERF_Z_Cache_separate_Z_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate cbiPERF_Z_Cache_pmask_misses: cXcjPERF_Z_Cache_pmask_hits: XdckPERF_Z_Cache_pmask_flushes: PedlmPERF_Z_Cache_pmask_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate eemPERF_Z_Cache_frees: f8fnPERF_Plane_Cache_misses: 0gfoPERF_Plane_Cache_hits: gxgpPERF_Plane_Cache_flushes: hhqkPERF_Plane_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate `iirPERF_Plane_Cache_frees: 0jisGPERF_flush_expanded_stencil: Tiles flushed with with expanded stencil kxjtKPERF_flush_compressed_stencil: Tiles flushed with with compressed stencil kHkuCPERF_flush_single_stencil: Tiles flushed with with single stencil llv0PERF_flush_1plane: Tiles flushed with 1 ZPlane 8mlw1PERF_flush_2plane: Tiles flushed with 2 ZPlanes mmx1PERF_flush_3plane: Tiles flushed with 3 ZPlanes n8ny1PERF_flush_4plane: Tiles flushed with 4 ZPlanes `onz1PERF_flush_5plane: Tiles flushed with 5 ZPlanes po{1PERF_flush_6plane: Tiles flushed with 6 ZPlanes p`p|1PERF_flush_7plane: Tiles flushed with 7 ZPlanes qq}1PERF_flush_8plane: Tiles flushed with 8 ZPlanes @rq~1PERF_flush_9plane: Tiles flushed with 9 ZPlanes rr3PERF_flush_10plane: Tiles flushed with 10 ZPlanes s@s3PERF_flush_11plane: Tiles flushed with 11 ZPlanes hts3PERF_flush_12plane: Tiles flushed with 12 ZPlanes ut3PERF_flush_13plane: Tiles flushed with 13 ZPlanes uhu3PERF_flush_14plane: Tiles flushed with 14 ZPlanes v v3PERF_flush_15plane: Tiles flushed with 15 ZPlanes Hwv3PERF_flush_16plane: Tiles flushed with 16 ZPlanes xw6PERF_flush_expanded_z: Tiles flushed with expanded Z xPx`PERF_earlyZ_waiting_for_postZ_done: Cycles stalled while transitioning from Late/ReZ to EarlyZ y8yrPERF_reZ_waiting_for_postZ_done: Cycles stalled while transitioning to ReZ from an incompatible Z mode/func/etc. z0z@PERF_dk_tile_sends: Detail kill block tiles/squads/events sent h{z2PERF_dk_tile_busy: Cycles Detail Kill block busy H|{ZPERF_dk_tile_quad_starves: Cycles Detail Kill has tile, but no quads from the SC_DB_quad }|?PERF_dk_tile_stalls: Cycles Detail Kill is stalled from below }X})PERF_dk_squad_sends: Detail Kill squads ~~@PERF_dk_squad_busy: Cycles the squad Detail Kill input is busy P~=PERF_dk_squad_stalls: Cycles squads are stalled from below. HrPERF_Op_Pipe_Busy: Cycles the quad OP pipe of the DB is busy (including memory fetches, but not initial startup) 8kPERF_Op_Pipe_MC_Read_stall: Cycles the Op Pipe is waiting for memory to return (ignoring initial startup) 1PERF_qc_busy: Cycles the Quad Coherency is busy 8CPERF_qc_xfc: Number of transfers through the Quad Coherency block ȃPERF_qc_conflicts: Stalls on a squad input because of a coherency check conflict (the same sample ahead of it could affect the dest data) KPERF_qc_full_stall: Quad Coherency is stalled because it is out of slots. ȅPERF_qc_in_preZ_tile_stalls_postZ: Cycles postZ squad inputs are stalled because the OP pipe is operating on a preZ tile, and there is no PreZ squad input available PERF_qc_in_postZ_tile_stalls_preZ: Cycles preZ squad inputs are stalled because the OP pipe is operating on a postZ tile, and there is no PostZ squad input available @rPERF_tsc_insert_summarize_stall: Cycles the op pipe is stalled by the tile summarizer inserting summarize squads 8-PERF_tl_busy: Cycles Tile Lookup block busy `4PERF_tl_dtc_read_starved: Cycles Tile Lookup block 0IPERF_tl_z_fetch_stall: Cycles Tile Lookup block stalled by zfetch block xOPERF_tl_stencil_stall: Cycles Tile Lookup block stalled by stencil test block PTPERF_tl_z_decompress_stall: Cycles Tile Lookup block stalled by z decompress block (XPERF_tl_stencil_locked_stall: Cycles Tile Lookup block stalled by stencil being locked ;PERF_tl_events: Cycles Tile Lookup block sends out events XȍOPERF_tl_summarize_squads: Cycles Tile Lookup block sends out summarize squads 8UPERF_tl_flush_expand_squads: Cycles Tile Lookup block sends out flush expand squads IPERF_tl_expand_squads: Cycles Tile Lookup block sends out expand squads ؐPEPERF_tl_preZ_squads: Cycles Tile Lookup block sends out preZ squads GPERF_tl_postZ_squads: Cycles Tile Lookup block sends out postZ squads UPERF_tl_preZ_noop_squads: Cycles Tile Lookup block sends out noops on the preZ path hВWPERF_tl_postZ_noop_squads: Cycles Tile Lookup block sends out noops on the postZ path @NPERF_tl_getZ_squads: Cycles Tile Lookup block sends out z import pass squads EPERF_tl_tile_ops: Cycles Tile Lookup block sends out tile op squads ؕX=PERF_tl_in_xfc: Cycles Tile Lookup block receives any input Ж nPERF_tl_in_single_stencil_expand_stall: Cycles Tile Lookup block is stalling due to expanding single stencil ePERF_tl_in_constant_stencil_walk_stall: Cycles Tile Lookup block is stalling due to walking stencil LPERF_tl_in_fast_z_stall: Cycles Tile Lookup block is stalling due to fastZ XؘCPERF_tl_out_xfc: Cycles Tile Lookup block is sending anything out DPERF_tl_out_squads: Cycles Tile Lookup block is sending squads out 8hPERF_zf_plane_multicycle: Cycles the z fetch is multicycling a squad because it needs to fetch more than 2 planes from the cache for compressed Z JPERF_PostZ_Samples_passing_Z: Samples passing Z test during a PostZ pass ؜PJPERF_PostZ_Samples_failing_Z: Samples failing Z test during a PostZ pass PPERF_PostZ_Samples_failing_S: Samples failing Stencil test during a PostZ pass HPERF_PreZ_Samples_passing_Z: Samples passing Z test during a PreZ pass PȞHPERF_PreZ_Samples_failing_Z: Samples failing Z test during a PreZ pass (NPERF_PreZ_Samples_failing_S: Samples failing Stencil test during a PreZ pass pZPERF_ts_tc_update_stall: Cycles Tile Summarizer to Tile Cache write interface is stalled СP>PERF_sc_kick_start: Times the DB sent a hang panic to the SC 7PERF_sc_kick_end: Times the DB completed a hang panic Xآ>PERF_SX_DB_mem_exports: Number of memory exports from the SX 0PPERF_SX_DB_mem_exports_acked: Number of memory export writes acked from the MC xPPERF_SX_DB_ack_mem_exports: Number of ack requested memory exports from the SX ॸPSPERF_SX_DB_ack_mem_exports_acked: Number of memory export acks returned to the SX (5PERF_mem_export_busy: Cycles writing memory exports 覸sPERF_mem_export_mi_stall: Cycles mem exports are stalled waiting for other DB writes or MC write bus arbitration. ৸dPERF_mem_export_tag_stall: Cycles mem exports are stalled waiting for a free mem export write tag. @Ȩ<PERF_clock_reg_active: Cycles register part of DB is awake 9PERF_clock_main_active: Cycles core part of DB is awake ЪHEPERF_clock_mem_export_active: Cycles mem export part of DB is awake 7PERF_esr_out_busy: Early Squad Router Out cycles busy Pث;PERF_esr_out_sc_stall: Early Squad Router Out to SC stall 0ZPERF_esr_out_lquad_fifo_full_stall: Early Squad Router Out to Late Quad Fifo full stalls 譸x0PERF_etr_out_send: Early Tile Router Out sends 06PERF_etr_out_busy: Early Tile Router Out cycles busy ePERF_etr_out_ltile_probe_fifo_full_stall: Early Tile Router Out to Late Tile Probe Fifo full stalls `௸APERF_etr_out_cb_tile_stall: Early Tile Router to CB tile stalls IPERF_etr_out_esr_stall: Early Tile Router to Early Squad Router stalls. dj""XjDB0_PERFCOUNTER0_SELECTjj PERF_SELk@k4PERF_SC_DB_tile_sends: Cycles Interface is sending hlk0PERF_SC_DB_tile_busy: Cycles Interface is busy (ml5PERF_SC_DB_tile_stalls: Cycles Interface is stalled mpm4PERF_SC_DB_tile_events: Events sent over interface n(n2PERF_SC_DB_tile_tiles: Tiles sent over interface Pon.PERF_SC_DB_tile_covered: Fully covered tiles poIPERF_hiz_tc_read_starved: HiZ starved waiting for htile data from cache php=PERF_hiz_tc_write_stall: HiZ stalled writing to htile cache q0q5PERF_hiz_qtiles_culled: Quarter tiles culled by hiZ hrq 5PERF_his_qtiles_culled: Quarter tiles culled by HiS sr 4PERF_DB_SC_tile_sends: Cycles Interface is sending shs 0PERF_DB_SC_tile_busy: Cycles Interface is busy t t ;PERF_DB_SC_tile_stalls: Cycles Interface is stalled by SC put QPERF_DB_SC_tile_df_stalls: Cycles Interface is stalled by detail walk tile fifo (vu2PERF_DB_SC_tile_tiles: Tiles sent over interface vpv/PERF_DB_SC_tile_culled: Tiles culled in total w(wIPERF_DB_SC_tile_hier_kill: Tiles culled due to a hierarchical fail test xwSPERF_DB_SC_tile_fast_ops: Tiles culled because they were accerated fast tile ops. XyxIPERF_DB_SC_tile_no_ops: Tiles culled because they would not do anything 0zyTPERF_DB_SC_tile_pixel_rate: Tiles run at pixel rate as opposed to sample rate tile ({xzqPERF_DB_SC_tile_ssaa_kill: Tiles culled because they were supersample tiles that are merged into a fast tile op |p{tPERF_DB_SC_tile_fast_z_ops: Tiles that operate on Z in 1 clock. Can be inside a slow, pixel rate, or fast tile op (}h|PERF_DB_SC_tile_fast_stencil_ops: Tiles that operate on stencil in 1 clock. Can be inside a slow, pixel rate, or fast tile op }p}4PERF_SC_DB_quad_sends: Cycles Interface is sending ~(~0PERF_SC_DB_quad_busy: Cycles Interface is busy X~;PERF_SC_DB_quad_squads: Squads transferred over interface 2PERF_SC_DB_quad_tiles: Tiles sent over interface ЀX:PERF_SC_DB_quad_pixels: Pixels transfered over interface =PERF_SC_DB_quad_killed_tiles: Number of detail killed tiles P4PERF_DB_SC_quad_sends: Cycles Interface is sending 0PERF_DB_SC_quad_busy: Cycles Interface is busy ȃP5PERF_DB_SC_quad_stalls: Cycles Interface is stalled  4PERF_DB_SC_quad_squads: Squads sent over interface 8Ȅ!2PERF_DB_SC_quad_tiles: Tiles sent over interface "HPERF_DB_SC_quad_quads: Quads transferred over the DB_SC_quad interface P#nPERF_DB_CB_tile_sends: Cycles sending tiles/events to CB. Tiles not shaded or needed by the CB are not sent. H$PERF_DB_CB_tile_busy: @臷%PERF_DB_CB_tile_stalls: &4PERF_SX_DB_quad_sends: Cycles Interface is sending @'0PERF_SX_DB_quad_busy: Cycles Interface is busy p(5PERF_SX_DB_quad_stalls: Cycles Interface is stalled ()2PERF_SX_DB_quad_quads: Quads sent over interface p*4PERF_SX_DB_quad_pixels: Pixels sent over interface (+APERF_SX_DB_quad_exports: Each MRT of a quad sent over interface ,bPERF_SH_quads_outstanding_sum: Multiple by 128 and divide by DB_SC_quad_quads to get PS latency. P؍-5PERF_DB_CB_lquad_sends: Cycles Interface is sending .1PERF_DB_CB_lquad_busy: Cycles Interface is busy ȏP/6PERF_DB_CB_lquad_stalls: Cycles Interface is stalled 03PERF_DB_CB_lquad_quads: Quads sent over interface 8Ȑ1/PERF_tile_rd_sends: HTile reads. Each is 256B (2hPERF_mi_tile_rd_outstanding_sum: Multiply by 2 and divide by tile_rd_sends to get htile memory latency 蒷p3:PERF_quad_rd_sends: Quad read reqs. Each is 32B to 256B 04JPERF_quad_rd_busy: Cycles quad read interface is trying to send requests 5VPERF_quad_rd_mi_stall: Cycles quad read interface is stalled by the memory interface x6XPERF_quad_rd_rw_collision: Cycles a quad read is stalled waiting for a write to finish h7ePERF_quad_rd_tag_stall: Cycles a quad read is stalled because the read latency hiding fifo is full. 08@PERF_quad_rd_32byte_reqs: Number of 32 Byte quad read requests x9>PERF_quad_rd_panic: Cycles DB is panicing for quad read data @:vPERF_mi_quad_rd_outstanding_sum: Multiply by 16 and divide by quad_rd_32byte_reqs to get depth buffer memory latency @;<PERF_quad_rdret_sends: Number of 32 byte quad read returns <>PERF_quad_rdret_busy: Cycles the quad read data is returning 0Ț=*PERF_tile_wr_sends: 32 Byte HTile writes 蛷x>-PERF_tile_wr_acks: 32 Byte Htile write acks 0?nPERF_mi_tile_wr_outstanding_sum: Multiply by 16 and divide by tile_wr_sends to get tile write memory latency ȝ(@cPERF_quad_wr_sends: Cycles quad is sending write requests to the memory interface block of the DB AKPERF_quad_wr_busy: Cycles quad is trying to write to the memory interface xBUPERF_quad_wr_mi_stall: Cycles quad is stalled while writing to the memory interface xCwPERF_quad_wr_coherency_stall: Cycles quad write is stalled waiting for a previous write to finish on the same address 8D6PERF_quad_wr_acks: Number of 32 Byte quad write acks 0ErPERF_mi_quad_wr_outstanding_sum: Multiply by 16 and divide by the quad_wr_sends to get quad memory write latency ࢷxF,PERF_Tile_Cache_misses: Htile Cache misses (G(PERF_Tile_Cache_hits: Htile Cache hits HأH.PERF_Tile_Cache_flushes: Htile Cache flushes (I[PERF_Tile_Cache_surface_stall: Tile stalls waiting for an htile surface to flush and free pJMPERF_Tile_Cache_starves: Tile stalls waiting for an htile cacheline to free ষHK[PERF_Tile_Cache_mem_return_starve: Tile stalls waiting for an htile memory read to return (LYPERF_tcp_dispatcher_reads: Number of htile cachelines fetched by the normal tile stream MQPERF_tcp_prefetcher_reads: Number of htile cachelines fetched by the prefetcher p਷NOPERF_tcp_preloader_reads: Number of htile cachelines fetched by the preloader POXPERF_tcp_dispatcher_flushes: Number of htile flushes caused byt the normal tile stream 0PWPERF_tcp_prefetcher_flushes: Number of htile flushes caused byt the normal prefetcher xQUPERF_tcp_preloader_flushes: Number of htile flushes caused byt the normal preloader ଷXRHPERF_Depth_Tile_Cache_sends: Tiles/Events through the Depth Tile Cache ȭ(SbPERF_Depth_Tile_Cache_busy: Cycles the Depth Tile Cache is busy testing hit/miss on tiles/events T_PERF_Depth_Tile_Cache_starves: Cycles starved waiting for a depth surface tile tag to free up UgPERF_Depth_Tile_Cache_dtile_locked: Cycles stalled waiting for a forced flush or invalidate to finish x请VTPERF_Depth_Tile_Cache_alloc_stall: Cycles depth tile stalled while allocating data @W?PERF_Depth_Tile_Cache_misses: Depth/Stencil Cache tile misses X;PERF_Depth_Tile_Cache_hits: Depth/Stencil Cache tile hits ȲHYAPERF_Depth_Tile_Cache_flushes: Depth/Stencil Cache tile flushes ZJPERF_Depth_Tile_Cache_noop_tile: Noop tiles through the depth tile cache x೷[VPERF_Depth_Tile_Cache_detailed_noop: Detail walked noops though the depth tile cache (\%PERF_Depth_Tile_Cache_event: Events ൷p]4PERF_Depth_Tile_Cache_tile_frees: Depth tile frees ȶ(^cPERF_Depth_Tile_Cache_data_frees: Depth tile data frees (may free data without freeing the dtile) _ePERF_Depth_Tile_Cache_mem_return_starve: Cycles depth/stencil cache is waiting for memory to return p`/PERF_Stencil_Cache_misses: 512 bit allocation aPERF_Stencil_Cache_hits: XbpPERF_Stencil_Cache_flushes: 256 bit flushes. Two per cacheline unless it is compressed, in which case it is 1. PcmPERF_Stencil_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate HdPERF_Stencil_Cache_frees: H軷e"PERF_Z_Cache_separate_Z_misses: f PERF_Z_Cache_separate_Z_hits: 8g#PERF_Z_Cache_separate_Z_flushes: ཷhrPERF_Z_Cache_separate_Z_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate 8ؾiPERF_Z_Cache_pmask_misses: ؿjPERF_Z_Cache_pmask_hits: kPERF_Z_Cache_pmask_flushes: xlmPERF_Z_Cache_pmask_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate ·mPERF_Z_Cache_frees: ·`·nPERF_Plane_Cache_misses: X÷÷oPERF_Plane_Cache_hits: ÷÷pPERF_Plane_Cache_flushes: ķ@ķqkPERF_Plane_Cache_starves: Cache starves when the cache wants to miss but is out of cachelines to allocate ŷ0ŷrPERF_Plane_Cache_frees: XƷŷsGPERF_flush_expanded_stencil: Tiles flushed with with expanded stencil (ǷƷtKPERF_flush_compressed_stencil: Tiles flushed with with compressed stencil ǷpǷuCPERF_flush_single_stencil: Tiles flushed with with single stencil ȷ8ȷv0PERF_flush_1plane: Tiles flushed with 1 ZPlane `ɷȷw1PERF_flush_2plane: Tiles flushed with 2 ZPlanes ʷɷx1PERF_flush_3plane: Tiles flushed with 3 ZPlanes ʷ`ʷy1PERF_flush_4plane: Tiles flushed with 4 ZPlanes ˷˷z1PERF_flush_5plane: Tiles flushed with 5 ZPlanes @̷˷{1PERF_flush_6plane: Tiles flushed with 6 ZPlanes ̷̷|1PERF_flush_7plane: Tiles flushed with 7 ZPlanes ͷ@ͷ}1PERF_flush_8plane: Tiles flushed with 8 ZPlanes hηͷ~1PERF_flush_9plane: Tiles flushed with 9 ZPlanes Ϸη3PERF_flush_10plane: Tiles flushed with 10 ZPlanes ϷhϷ3PERF_flush_11plane: Tiles flushed with 11 ZPlanes з з3PERF_flush_12plane: Tiles flushed with 12 ZPlanes Hѷз3PERF_flush_13plane: Tiles flushed with 13 ZPlanes ҷѷ3PERF_flush_14plane: Tiles flushed with 14 ZPlanes ҷHҷ3PERF_flush_15plane: Tiles flushed with 15 ZPlanes pӷӷ3PERF_flush_16plane: Tiles flushed with 16 ZPlanes 0Էӷ6PERF_flush_expanded_z: Tiles flushed with expanded Z շxԷ`PERF_earlyZ_waiting_for_postZ_done: Cycles stalled while transitioning from Late/ReZ to EarlyZ ַ`շrPERF_reZ_waiting_for_postZ_done: Cycles stalled while transitioning to ReZ from an incompatible Z mode/func/etc. ַXַ@PERF_dk_tile_sends: Detail kill block tiles/squads/events sent ׷ ׷2PERF_dk_tile_busy: Cycles Detail Kill block busy pط׷ZPERF_dk_tile_quad_starves: Cycles Detail Kill has tile, but no quads from the SC_DB_quad 8ٷط?PERF_dk_tile_stalls: Cycles Detail Kill is stalled from below ٷٷ)PERF_dk_squad_sends: Detail Kill squads ڷ0ڷ@PERF_dk_squad_busy: Cycles the squad Detail Kill input is busy x۷ڷ=PERF_dk_squad_stalls: Cycles squads are stalled from below. pܷ۷rPERF_Op_Pipe_Busy: Cycles the quad OP pipe of the DB is busy (including memory fetches, but not initial startup) `ݷܷkPERF_Op_Pipe_MC_Read_stall: Cycles the Op Pipe is waiting for memory to return (ignoring initial startup) ޷ݷ1PERF_qc_busy: Cycles the Quad Coherency is busy ޷`޷CPERF_qc_xfc: Number of transfers through the Quad Coherency block ߷(߷PERF_qc_conflicts: Stalls on a squad input because of a coherency check conflict (the same sample ahead of it could affect the dest data) 8KPERF_qc_full_stall: Quad Coherency is stalled because it is out of slots. PERF_qc_in_preZ_tile_stalls_postZ: Cycles postZ squad inputs are stalled because the OP pipe is operating on a preZ tile, and there is no PreZ squad input available 8PERF_qc_in_postZ_tile_stalls_preZ: Cycles preZ squad inputs are stalled because the OP pipe is operating on a postZ tile, and there is no PostZ squad input available hrPERF_tsc_insert_summarize_stall: Cycles the op pipe is stalled by the tile summarizer inserting summarize squads `-PERF_tl_busy: Cycles Tile Lookup block busy 4PERF_tl_dtc_read_starved: Cycles Tile Lookup block XIPERF_tl_z_fetch_stall: Cycles Tile Lookup block stalled by zfetch block 0OPERF_tl_stencil_stall: Cycles Tile Lookup block stalled by stencil test block xTPERF_tl_z_decompress_stall: Cycles Tile Lookup block stalled by z decompress block PXPERF_tl_stencil_locked_stall: Cycles Tile Lookup block stalled by stencil being locked 0;PERF_tl_events: Cycles Tile Lookup block sends out events OPERF_tl_summarize_squads: Cycles Tile Lookup block sends out summarize squads `UPERF_tl_flush_expand_squads: Cycles Tile Lookup block sends out flush expand squads 0IPERF_tl_expand_squads: Cycles Tile Lookup block sends out expand squads xEPERF_tl_preZ_squads: Cycles Tile Lookup block sends out preZ squads HGPERF_tl_postZ_squads: Cycles Tile Lookup block sends out postZ squads UPERF_tl_preZ_noop_squads: Cycles Tile Lookup block sends out noops on the preZ path WPERF_tl_postZ_noop_squads: Cycles Tile Lookup block sends out noops on the postZ path hNPERF_tl_getZ_squads: Cycles Tile Lookup block sends out z import pass squads 8EPERF_tl_tile_ops: Cycles Tile Lookup block sends out tile op squads =PERF_tl_in_xfc: Cycles Tile Lookup block receives any input HnPERF_tl_in_single_stencil_expand_stall: Cycles Tile Lookup block is stalling due to expanding single stencil @ePERF_tl_in_constant_stencil_walk_stall: Cycles Tile Lookup block is stalling due to walking stencil 0LPERF_tl_in_fast_z_stall: Cycles Tile Lookup block is stalling due to fastZ CPERF_tl_out_xfc: Cycles Tile Lookup block is sending anything out HDPERF_tl_out_squads: Cycles Tile Lookup block is sending squads out `PERF_zf_plane_multicycle: Cycles the z fetch is multicycling a squad because it needs to fetch more than 2 planes from the cache for compressed Z 0JPERF_PostZ_Samples_passing_Z: Samples passing Z test during a PostZ pass xJPERF_PostZ_Samples_failing_Z: Samples failing Z test during a PostZ pass HPPERF_PostZ_Samples_failing_S: Samples failing Stencil test during a PostZ pass HPERF_PreZ_Samples_passing_Z: Samples passing Z test during a PreZ pass xHPERF_PreZ_Samples_failing_Z: Samples failing Z test during a PreZ pass PNPERF_PreZ_Samples_failing_S: Samples failing Stencil test during a PreZ pass 0ZPERF_ts_tc_update_stall: Cycles Tile Summarizer to Tile Cache write interface is stalled x>PERF_sc_kick_start: Times the DB sent a hang panic to the SC @7PERF_sc_kick_end: Times the DB completed a hang panic >PERF_SX_DB_mem_exports: Number of memory exports from the SX XPPERF_SX_DB_mem_exports_acked: Number of memory export writes acked from the MC 0PPERF_SX_DB_ack_mem_exports: Number of ack requested memory exports from the SX xSPERF_SX_DB_ack_mem_exports_acked: Number of memory export acks returned to the SX P5PERF_mem_export_busy: Cycles writing memory exports sPERF_mem_export_mi_stall: Cycles mem exports are stalled waiting for other DB writes or MC write bus arbitration. dPERF_mem_export_tag_stall: Cycles mem exports are stalled waiting for a free mem export write tag. h<PERF_clock_reg_active: Cycles register part of DB is awake (9PERF_clock_main_active: Cycles core part of DB is awake pEPERF_clock_mem_export_active: Cycles mem export part of DB is awake @7PERF_esr_out_busy: Early Squad Router Out cycles busy x;PERF_esr_out_sc_stall: Early Squad Router Out to SC stall X ZPERF_esr_out_lquad_fifo_full_stall: Early Squad Router Out to Late Quad Fifo full stalls  0PERF_etr_out_send: Early Tile Router Out sends X 6PERF_etr_out_busy: Early Tile Router Out cycles busy  ePERF_etr_out_ltile_probe_fifo_full_stall: Early Tile Router Out to Late Tile Probe Fifo full stalls  APERF_etr_out_cb_tile_stall: Early Tile Router to CB tile stalls IPERF_etr_out_esr_stall: Early Tile Router to Early Squad Router stalls. * eDD""peDB_ALPHA_TO_MASK feALPHA_TO_MASK_ENABLE"fxfALPHA_TO_MASK_OFFSET0"g(g ALPHA_TO_MASK_OFFSET1"0hg ALPHA_TO_MASK_OFFSET2"hhALPHA_TO_MASK_OFFSET3"8i OFFSET_ROUND"@"X+""+DB_DEPTH_CONTROL P,,STENCIL_ENABLE",, Z_ENABLE"-H-Z_WRITE_ENABLE"3-8.ZFUNC..FRAG_NEVER: never pass / /$FRAG_LESS: pass if fragment < dest 00/%FRAG_EQUAL: pass if fragment = dest 0x0'FRAG_LEQUAL: pass if fragment <= dest 1(1'FRAG_GREATER: pass if fragment > dest @21)FRAG_NOTEQUAL: pass if fragment != dest 22'FRAG_GEQUAL: pass if fragment >= dest 83FRAG_ALWAYS: always pass 843BACKFACE_ENABLE":44 STENCILFUNCx5 5REF_NEVER: never pass 65 REF_LESS: pass if left < right 6h6!REF_EQUAL: pass if left = right p77#REF_LEQUAL: pass if left <= right 87#REF_GREATER: pass if left > right 8`8%REF_NOTEQUAL: pass if left != right p99#REF_GEQUAL: pass if left >= right 9REF_ALWAYS: always pass (@h: : STENCILFAIL`;:%STENCIL_KEEP: New value = Old Value <;STENCIL_ZERO: New value = 0 <P<)STENCIL_REPLACE: New value = STENCILREF h==)STENCIL_INCR_CLAMP: New value++ (clamp) >=)STENCIL_DECR_CLAMP: New value-- (clamp) >`>&STENCIL_INVERT: New value=~Old value x??'STENCIL_INCR_WRAP: New value++ (wrap) ?'STENCIL_DECR_WRAP: New value-- (wrap) HF@@ STENCILZPASSAA%STENCIL_KEEP: New value = Old Value (BASTENCIL_ZERO: New value = 0 BpB)STENCIL_REPLACE: New value = STENCILREF C C)STENCIL_INCR_CLAMP: New value++ (clamp) 8DC)STENCIL_DECR_CLAMP: New value-- (clamp) DD&STENCIL_INVERT: New value=~Old value E0E'STENCIL_INCR_WRAP: New value++ (wrap) E'STENCIL_DECR_WRAP: New value-- (wrap) hLFF STENCILZFAILG8G%STENCIL_KEEP: New value = Old Value HHGSTENCIL_ZERO: New value = 0 HH)STENCIL_REPLACE: New value = STENCILREF I@I)STENCIL_INCR_CLAMP: New value++ (clamp) XJI)STENCIL_DECR_CLAMP: New value-- (clamp) KJ&STENCIL_INVERT: New value=~Old value KPK'STENCIL_INCR_WRAP: New value++ (wrap) L'STENCIL_DECR_WRAP: New value-- (wrap) HRLMSTENCILFUNC_BFMXMREF_NEVER: never pass XNM REF_LESS: pass if left < right ON!REF_EQUAL: pass if left = right OHO#REF_LEQUAL: pass if left <= right PPO#REF_GREATER: pass if left > right QP%REF_NOTEQUAL: pass if left != right QHQ#REF_GEQUAL: pass if left >= right QREF_ALWAYS: always pass hXRRSTENCILFAIL_BFS8S%STENCIL_KEEP: New value = Old Value HTSSTENCIL_ZERO: New value = 0 TT)STENCIL_REPLACE: New value = STENCILREF U@U)STENCIL_INCR_CLAMP: New value++ (clamp) XVU)STENCIL_DECR_CLAMP: New value-- (clamp) WV&STENCIL_INVERT: New value=~Old value WPW'STENCIL_INCR_WRAP: New value++ (wrap) X'STENCIL_DECR_WRAP: New value-- (wrap) ^XYSTENCILZPASS_BFYXY%STENCIL_KEEP: New value = Old Value hZZSTENCIL_ZERO: New value = 0 [Z)STENCIL_REPLACE: New value = STENCILREF [`[)STENCIL_INCR_CLAMP: New value++ (clamp) x\\)STENCIL_DECR_CLAMP: New value-- (clamp) (]\&STENCIL_INVERT: New value=~Old value ]p]'STENCIL_INCR_WRAP: New value++ (wrap) ^'STENCIL_DECR_WRAP: New value-- (wrap) ^0_STENCILZFAIL_BF_x_%STENCIL_KEEP: New value = Old Value `(`STENCIL_ZERO: New value = 0 8a`)STENCIL_REPLACE: New value = STENCILREF aa)STENCIL_INCR_CLAMP: New value++ (clamp) b0b)STENCIL_DECR_CLAMP: New value-- (clamp) Hcb&STENCIL_INVERT: New value=~Old value cc'STENCIL_INCR_WRAP: New value++ (wrap) @d'STENCIL_DECR_WRAP: New value-- (wrap) ",,""#DB_SRESULTS_COMPARE_STATE1(h## COMPAREFUNC1X$$REF_NEVER: never pass %$ REF_LESS: pass if left < right %H%!REF_EQUAL: pass if left = right P&%#REF_LEQUAL: pass if left <= right &&#REF_GREATER: pass if left > right '@'%REF_NOTEQUAL: pass if left != right P('#REF_GEQUAL: pass if left >= right (REF_ALWAYS: always pass )H)COMPAREVALUE1"@*)  COMPAREMASK1"*ENABLE1"((""pDB_SRESULTS_COMPARE_STATE0P  COMPAREFUNC0`REF_NEVER: never pass ` REF_LESS: pass if left < right !REF_EQUAL: pass if left = right P#REF_LEQUAL: pass if left <= right X#REF_GREATER: pass if left > right %REF_NOTEQUAL: pass if left != right P#REF_GEQUAL: pass if left >= right REF_ALWAYS: always pass COMPAREVALUE0"!P!  COMPAREMASK0"!ENABLE0"(P44""DB_STENCILREFMASK_BFPSTENCILREF_BF"STENCILMASK_BF"PSTENCILWRITEMASK_BF"00""DB_STENCILREFMASKH STENCILREF"0 STENCILMASK"STENCILWRITEMASK"h(44""xDB_PREFETCH_LIMIT DEPTH_HEIGHT_TILE_MAX"x 00""0DB_PRELOAD_CONTROLSTART_X"p(START_Y"MAX_X"hMAX_Y" $$""@ DB_HTILE_SURFACE  HTILE_WIDTH" 8  HTILE_HEIGHT"( LINEAR"  FULL_CACHE"x HTILE_USES_PRELOAD_WIN" PRELOAD"pPREFETCH_WIDTH" PREFETCH_HEIGHT"""DB_HTILE_DATA_BASE0 BASE_256B" ,,""pDB_DEPTH_CLEAR DEPTH_CLEAR" ((""pDB_STENCIL_CLEARCLEAR"hMIN"hh  ""DB_SHADER_CONTROL `Z_EXPORT_ENABLE"STENCIL_REF_EXPORT_ENABLE"hZ_ORDER@LATE_ZEARLY_Z_THEN_LATE_Zh RE_ZEARLY_Z_THEN_RE_Z` KILL_ENABLE"XCOVERAGE_TO_MASK_ENABLE"MASK_EXPORT_ENABLE"X DUAL_EXPORT_ENABLE"P EXEC_ON_HIER_FAIL"  EXEC_ON_NOOP"P ALPHA_TO_MASK_DISABLE"ն""0DB_RENDER_OVERRIDE0FORCE_HIZ_ENABLEh FORCE_OFF FORCE_ENABLEHFORCE_DISABLEFORCE_RESERVED0FORCE_HIS_ENABLE0h FORCE_OFF FORCE_ENABLEHFORCE_DISABLEFORCE_RESERVED0FORCE_HIS_ENABLE1h FORCE_OFF FORCE_ENABLEHFORCE_DISABLEFORCE_RESERVEDFORCE_SHADER_Z_ORDER"8FAST_Z_DISABLE"8FAST_STENCIL_DISABLE" NOOP_CULL_DISABLE"8 FORCE_COLOR_KILL"0  FORCE_Z_READ" FORCE_STENCIL_READ"0 FORCE_FULL_Z_RANGE FORCE_OFFX FORCE_ENABLE@FORCE_DISABLEFORCE_RESERVED0FORCE_QC_SMASK_CONFLICT"8DISABLE_VIEWPORT_CLAMP"IGNORE_SC_ZRANGE"8DISABLE_FULLY_COVERED"8FORCE_Z_LIMIT_SUMMFORCE_SUMM_OFFhFORCE_SUMM_MINZFORCE_SUMM_MAXZHFORCE_SUMM_BOTH@MAX_TILES_IN_DTT"DISABLE_PIXEL_RATE_TILES"Ӷhֶ  ""ֶDB_RENDER_CONTROL `׶׶DEPTH_CLEAR_ENABLE"ض׶STENCIL_CLEAR_ENABLE"ضhض DEPTH_COPY"Xٶٶ STENCIL_COPY"ڶٶRESUMMARIZE_ENABLE"ڶXڶSTENCIL_COMPRESS_DISABLE"`۶۶DEPTH_COMPRESS_DISABLE"ܶ۶COPY_CENTROID"ܶ`ܶ COPY_SAMPLE"Xݶݶ ZPASS_INCREMENT_DISABLE"޶ݶ COLOR_DISABLE"X޶ ޶CONSERVATIVE_Z_EXPORT`߶޶+EXPORT_ANY_Z: Exported Z can be any value 8߶SEXPORT_LESS_THAN_Z: Exported Z will be assumed to be less than the source z value YEXPORT_GREATER_THAN_Z: Exported Z will be assumed to be greater than the source z value `EXPORT_RESERVED: Reserved PERFECT_ZPASS_COUNTS"Ѷ`Զ""ԶDB_DEPTH_VIEWPնն SLICE_START"ն SLICE_MAX"HҶ""ҶDB_DEPTH_SIZE@ӶҶ PITCH_TILE_MAX"Ӷ SLICE_TILE_MAX"0""`DB_DEPTH_INFO¶FORMATH9DEPTH_INVALID: Depth and stencil surface are not valid. hDEPTH_16: UNORM 16-bit depth. 0>DEPTH_X8_24: 24-bit UNORM depth and invalid stencil surface. 辶x1DEPTH_8_24: 24-bit UNORM depth and int stencil. 0RDEPTH_X8_24_FLOAT: 24-bit float depth and invalid stencil surface. (Unsupported) EDEPTH_8_24_FLOAT: 24-bit float depth and int stencil. (Unsupported) @%DEPTH_32_FLOAT: 32-bit float depth. ;DEPTH_X24_8_32_FLOAT: 32-bit float depth and int stencil. öX¶¶ READ_SIZE8ö¶READ_256_BITSöREAD_512_BITS϶(ĶpĶ ARRAY_MODE(ŶĶ.ARRAY_LINEAR_GENERAL: Unaligned linear array ŶpŶ,ARRAY_LINEAR_ALIGNED: Aligned linear array ƶ ƶ+ARRAY_1D_TILED_THIN1: Uses 1D 8x8x1 tiles 8Ƕƶ+ARRAY_1D_TILED_THICK: Uses 1D 8x8x4 tiles ǶǶ.ARRAY_2D_TILED_THIN1: Uses 8x8x1 macro-tiles ȶ8ȶ/ARRAY_2D_TILED_THIN2: Macro-tiles are 2x high `ɶȶ/ARRAY_2D_TILED_THIN4: Macro-tiles are 4x high ʶɶ.ARRAY_2D_TILED_THICK: Uses 8x8x4 macro-tiles ʶ`ʶ.ARRAY_2B_TILED_THIN1: uses row bank swapping ˶˶ .ARRAY_2B_TILED_THIN2: uses row bank swapping @̶˶ .ARRAY_2B_TILED_THIN4: uses row bank swapping ̶̶ .ARRAY_2B_TILED_THICK: uses row bank swapping Ͷ@Ͷ /ARRAY_3D_TILED_THIN1: Slices are pipe rotated hζͶ /ARRAY_3D_TILED_THICK: Slices are pipe rotated ϶ζ/ARRAY_3B_TILED_THIN1: Slices are pipe rotated h϶/ARRAY_3B_TILED_THICK: Slices are pipe rotated ж0жTILE_SURFACE_ENABLE"(Ѷж TILE_COMPACT"ѶZRANGE_PRECISION"@  ""DB_DEPTH_BASEP BASE_256B"h88"" SX_ALPHA_REF` ALPHA_REF"ଶ""8SX_ALPHA_TEST_CONTROLح ALPHA_FUNCx REF_NEVER: never pass  REF_LESS: pass if left < right ȯh!REF_EQUAL: pass if left = right p#REF_LEQUAL: pass if left <= right #REF_GREATER: pass if left > right ȱ`%REF_NOTEQUAL: pass if left != right p#REF_GEQUAL: pass if left >= right REF_ALWAYS: always pass (hALPHA_TEST_ENABLEh%DISABLE: force ALPHA_FUNC to ALWAYS 9ENABLE: discard pixels that do not pass the alpha test. еALPHA_TEST_BYPASS:DISABLE: discard pixels that do not pass the alpha test. ض%ENABLE: force ALPHA_FUNC to ALWAYS. pTT""SX_SURFACE_SYNC SURFACE_SYNC_MASK"0PP""`SX_MISC@ MULTIPASSHDo not kill all primitives 詶Kill all primitives REORDER_PIXEL_MEMORY_BUFFERS"""SX_PERFCOUNTER3_LOWP PERF_COUNT_LOW"P8""SX_PERFCOUNTER3_HIॶ PERF_COUNT_HI"ࡶȣ""SX_PERFCOUNTER2_LOWp PERF_COUNT_LOW"pX""SX_PERFCOUNTER2_HI PERF_COUNT_HI"蠶""8SX_PERFCOUNTER1_LOW PERF_COUNT_LOW"x""ȟSX_PERFCOUNTER1_HI PERF_COUNT_HI" ""XSX_PERFCOUNTER0_LOW PERF_COUNT_LOW"""蜶SX_PERFCOUNTER0_HI@ PERF_COUNT_HI"@(||""SX_PERFCOUNTER3_SELECT؛ PERF_SEL"Зxx""SX_PERFCOUNTER2_SELECTh PERF_SEL"PHtt""SX_PERFCOUNTER1_SELECT PERF_SEL"NPQpp""QSX_PERFCOUNTER0_SELECTRHR PERF_SELVSR?SX_GS_FLUSH_EVENT_IN : Number of events received for GS flush SXS?SX_ES_FLUSH_EVENT_IN : Number of events received for ES flush T T;SX_TS_EVENT_IN : Number of events received for Timestamps `UT=SX_CONTEXT_EVENT_IN : Number of events received for context (VUASX_GS_FLUSH_EVENT_OUT : Number of events submitted for GS flush VpVASX_ES_FLUSH_EVENT_OUT : Number of events submitted for ES flush W8W=SX_TS_EVENT_OUT : Number of events submitted for Timestamps XX?SX_CONTEXT_EVENT_OUT : Number of events submitted for context `YXXSX_DB0_IDLE_CYCLES : Nr of cycles where DB0 was idle waiting to accept vectors from SX PZY fSX_DB0_STALL_CYCLES : Nr of cycles where DB0 wasn't ready to accept vectors and SX was ready to send [Z 6SX_DB0_HALF_QUADS : Nr of half quads sent to the DB0 [X[ .SX_DB0_PIXELS : Nr of pixels sent to the DB0 \\ BSX_DB0_PRED_PIXELS : Nr of non predicated pixels sent to the DB0 p]\ XSX_DB1_IDLE_CYCLES : Nr of cycles where DB1 was idle waiting to accept vectors from SX `^]fSX_DB1_STALL_CYCLES : Nr of cycles where DB1 wasn't ready to accept vectors and SX was ready to send _^6SX_DB1_HALF_QUADS : Nr of half quads sent to the DB1 _h_.SX_DB1_PIXELS : Nr of pixels sent to the DB1 ` `BSX_DB1_PRED_PIXELS : Nr of non predicated pixels sent to the DB1 a`XSX_DB2_IDLE_CYCLES : Nr of cycles where DB2 was idle waiting to accept vectors from SX pbafSX_DB2_STALL_CYCLES : Nr of cycles where DB2 wasn't ready to accept vectors and SX was ready to send 0cb6SX_DB2_HALF_QUADS : Nr of half quads sent to the DB2 cxc.SX_DB2_PIXELS : Nr of pixels sent to the DB2 d0dBSX_DB2_PRED_PIXELS : Nr of non predicated pixels sent to the DB0 edXSX_DB3_IDLE_CYCLES : Nr of cycles where DB3 was idle waiting to accept vectors from SX fefSX_DB3_STALL_CYCLES : Nr of cycles where DB3 wasn't ready to accept vectors and SX was ready to send @gf6SX_DB3_HALF_QUADS : Nr of half quads sent to the DB3 gg.SX_DB3_PIXELS : Nr of pixels sent to the DB3 h@hBSX_DB3_PRED_PIXELS : Nr of non predicated pixels sent to the DB3 iiXSX_DB4_IDLE_CYCLES : Nr of cycles where DB4 was idle waiting to accept vectors from SX jifSX_DB4_STALL_CYCLES : Nr of cycles where DB4 wasn't ready to accept vectors and SX was ready to send Pkj6SX_DB4_HALF_QUADS : Nr of half quads sent to the DB4 lk.SX_DB4_PIXELS : Nr of pixels sent to the DB4 lPl BSX_DB4_PRED_PIXELS : Nr of non predicated pixels sent to the DB4 mm!XSX_DB5_IDLE_CYCLES : Nr of cycles where DB5 was idle waiting to accept vectors from SX nm"fSX_DB5_STALL_CYCLES : Nr of cycles where DB5 wasn't ready to accept vectors and SX was ready to send `on#6SX_DB5_HALF_QUADS : Nr of half quads sent to the DB5 po$.SX_DB5_PIXELS : Nr of pixels sent to the DB5 p`p%BSX_DB5_PRED_PIXELS : Nr of non predicated pixels sent to the DB5 q(q&XSX_DB6_IDLE_CYCLES : Nr of cycles where DB6 was idle waiting to accept vectors from SX rr'fSX_DB6_STALL_CYCLES : Nr of cycles where DB6 wasn't ready to accept vectors and SX was ready to send psr(6SX_DB6_HALF_QUADS : Nr of half quads sent to the DB6 (ts).SX_DB6_PIXELS : Nr of pixels sent to the DB6 tpt*BSX_DB6_PRED_PIXELS : Nr of non predicated pixels sent to the DB6 u8u+XSX_DB7_IDLE_CYCLES : Nr of cycles where DB7 was idle waiting to accept vectors from SX vv,fSX_DB7_STALL_CYCLES : Nr of cycles where DB7 wasn't ready to accept vectors and SX was ready to send ww-6SX_DB7_HALF_QUADS : Nr of half quads sent to the DB7 8xw..SX_DB7_PIXELS : Nr of pixels sent to the DB7 yx/BSX_DB7_PRED_PIXELS : Nr of non predicated pixels sent to the DB7 yHy0VSX_PA_IDLE_CYCLES : Nr of cycles where PA was idle waiting to accept vectors from SX z(z1(SX_PA_REQ : Nr of PA requests received @{z2,SX_PA_POS : Nr of positions sent to the PA {{3.SX_SPI_REQ_0 : Nr of SPI requests 0 received |@|4.SX_SPI_REQ_1 : Nr of SPI requests 1 received h}|5-SX_CLOCK_PS : Nr of clocks in the PS window ~}6-SX_CLOCK_VS : Nr of clocks in the VS window ~h~7-SX_CLOCK_GS : Nr of clocks in the GS window  8-SX_CLOCK_ES : Nr of clocks in the ES window @9'SX_CLOCK : Nr of clocks in any window :NSX_DB0_ACK_REQUEST : Number of ack requests sent to DB0 for memory transfers `;NSX_DB1_ACK_REQUEST : Number of ack requests sent to DB1 for memory transfers Ȃ8<NSX_DB2_ACK_REQUEST : Number of ack requests sent to DB2 for memory transfers =NSX_DB3_ACK_REQUEST : Number of ack requests sent to DB3 for memory transfers x胶>NSX_DB4_ACK_REQUEST : Number of ack requests sent to DB4 for memory transfers P?NSX_DB5_ACK_REQUEST : Number of ack requests sent to DB5 for memory transfers (@NSX_DB6_ACK_REQUEST : Number of ack requests sent to DB6 for memory transfers pANSX_DB7_ACK_REQUEST : Number of ack requests sent to DB7 for memory transfers HB8SX_SC_CLOCK : Nr of clocks the SC buffer was not empty CLSX_PS_ADJUSTED_CLOCK : Nr of PS clocks from first to last quad transaction X؈DDSX_DB0_ALPHA_KILLED_PIXELS : Nr of pixels killed due to alpha test EDSX_DB1_ALPHA_KILLED_PIXELS : Nr of pixels killed due to alpha test 芶hFDSX_DB2_ALPHA_KILLED_PIXELS : Nr of pixels killed due to alpha test 0GDSX_DB3_ALPHA_KILLED_PIXELS : Nr of pixels killed due to alpha test xHCSX_GATE_EN1 : Nr of clocks for the global CGTS clock group in SXM HIKSX_GATE_EN2 : Nr of clocks for the CGTS clock group of quad pipe 0 in SXM JKSX_GATE_EN3 : Nr of clocks for the CGTS clock group of quad pipe 1 in SXM 莶`KKSX_GATE_EN4 : Nr of clocks for the CGTS clock group of quad pipe 2 in SXM 0LKSX_GATE_EN5 : Nr of clocks for the CGTS clock group of quad pipe 3 in SXM MTSX_PIX_CLK_VALID : Nr of clocks the local clocks for the pixel engine is on in SXM xNUSX_SC_CLK_VALID : Nr of clocks the local clocks for the sc fifo engine is on in SXM XOZSX_PA_CLK_VALID : Nr of clocks the local clocks for the pa requester engine is on in SXM 8PWSX_REG_CLK_VALID : Nr of clocks the local clocks for the register engine is on in SXM QRSX_SMX_CLK_VALID : Nr of clocks the local clocks for the smx engine is on in SXM XReSX_ARB_QP0_COLLISION : Nr of collisions on QP0 due to multiple RBs requesting data from the same QP HSeSX_ARB_QP1_COLLISION : Nr of collisions on QP1 due to multiple RBs requesting data from the same QP 8TeSX_ARB_QP2_COLLISION : Nr of collisions on QP2 due to multiple RBs requesting data from the same QP (UeSX_ARB_QP3_COLLISION : Nr of collisions on QP3 due to multiple RBs requesting data from the same QP ?@O\\""O SX_DEBUG_28POSX_DB_QUAD_MEM_CREDIT"P DEBUG_DATA"/X@XX""@ SX_DEBUG_1 B@HASMX_EVENT_RELEASEBA=Block SMX transactions until corresponding event FIFO is OK XB:Send SMX transfers as soon as the alloc_done is received C(CSX_DB_DATA_FIFO_DEPTH"0DCSX_DB_REQUESTER_FIFO_DEPTH"DD SX_DB_QUAD_CREDIT"E0EENABLE_NEW_SMX_ADDRESS"HE8FNEW_SMX_ADDRESS_BUFFERSFFNo buffers affected G GOnly affects scratch buffer (HGOnly affects reduction buffer pH,Affects both reduction and scratch buffers I0I REORDER_VERTEX_MEMORY_BUFFERS"KI8JEVENT_PROCESS_MODEKJEOnly the last event seen on any thread type is sent (uses counters) PK(Only PS events are kept and considered (NL`LUSE_MC_CHANNEL_BITHML_Use the MC channel in the hash table, this option should be default for non-harvested designs M\Do not use the MC channel in the hash table, this option only applies to harvested designs N DEBUG_DATA"(0TT""x0SX_DEBUG_BUSY_2 10REQUESTER_0_BUSY"1x1REQUESTER_1_BUSY"p2 2REQUESTER_2_BUSY"32REQUESTER_3_BUSY"3p3REQUESTER_4_BUSY"h44REQUESTER_5_BUSY"54REQUESTER_6_BUSY"5h5REQUESTER_7_BUSY"`66DB0_WORK_REMAINING"76 DB1_WORK_REMAINING"7`7 DB2_WORK_REMAINING"X88 DB3_WORK_REMAINING"98 DB4_WORK_REMAINING"9X9 DB5_WORK_REMAINING"P::DB6_WORK_REMAINING"::DB7_WORK_REMAINING";P;WORK_DISPATCHED_FIFO_NOT_EMPTY"`<<SX_QUAD_FIFO_NOT_EMPTY"=<"EVENT_FLUSH_AND_INV_DB_DATA_TS_VS"=p="EVENT_FLUSH_AND_INV_DB_DATA_TS_PS">(>"EVENT_FLUSH_AND_INV_CB_DATA_TS_VS"@?>"EVENT_FLUSH_AND_INV_CB_DATA_TS_PS"? UNUSED"PP""PSX_DEBUG_BUSY SX_ALLOC_BUSY"PSMX_EXPORT_BUSY"HCOLOR_EXPORT_BUSY"BUFFER_ARBITERS_BUSY"PCOLOR_REQUESTERS_BUSY"PBUFFER_VALID_BUSY"POS_VALID_BUSY"PPOS_PA_REQ_INCOMPLETE"X  POS_PA_REQ_PENDING"! EVENT_ES_BUSY"!X! EVENT_GS_BUSY"P"" EVENT_VS_BUSY""" EVENT_PS_BUSY"#P# ALLOC_POS_BUSY"H$#ALLOC_SMX_BUSY"$$ALLOC_PIX_BUSY"%H% EVENT_CTX_ES"@&% EVENT_CTX_GS"&& EVENT_CTX_VS"'@' EVENT_CTX_PS"8('EVENT_BOTTOM_TS_VS"((EVENT_BOTTOM_TS_PS")8)EVENT_CACHE_INV_TS_VS"@*)EVENT_CACHE_INV_TS_PS"**EVENT_CACHE_SX_TS_VS"+H+EVENT_CACHE_SX_TS_PS"P,+EVENT_CACHE_FLUSH_TS_VS"-,EVENT_CACHE_FLUSH_TS_PS"-X-EVENT_CACHE_INV_VS"P..EVENT_CACHE_INV_PS"/.EVENT_CACHE_FLUSH_VS"X/EVENT_CACHE_FLUSH_PS" @@""`CGTT_SX_CLK_CTRL4  ON_DELAY"XOFF_HYTERESIS"H RESERVED"SOFT_OVERRIDE7"HSOFT_OVERRIDE6"@SOFT_OVERRIDE5"SOFT_OVERRIDE4"@SOFT_OVERRIDE3"8SOFT_OVERRIDE2"SOFT_OVERRIDE1"8SOFT_OVERRIDE0" <<""p CGTT_SX_CLK_CTRL3   ON_DELAY" h OFF_HYTERESIS"X  RESERVED" SOFT_OVERRIDE7" X SOFT_OVERRIDE6"PSOFT_OVERRIDE5"SOFT_OVERRIDE4"PSOFT_OVERRIDE3"HSOFT_OVERRIDE2"SOFT_OVERRIDE1"HSOFT_OVERRIDE0"088""CGTT_SX_CLK_CTRL2  ON_DELAY"xOFF_HYTERESIS"h  RESERVED"SOFT_OVERRIDE7"hSOFT_OVERRIDE6"`SOFT_OVERRIDE5"SOFT_OVERRIDE4"`SOFT_OVERRIDE3"XSOFT_OVERRIDE2" SOFT_OVERRIDE1"X SOFT_OVERRIDE0"@44""CGTT_SX_CLK_CTRL1 0 ON_DELAY"OFF_HYTERESIS"x0 RESERVED" SOFT_OVERRIDE7"xSOFT_OVERRIDE6"p SOFT_OVERRIDE5"SOFT_OVERRIDE4"pSOFT_OVERRIDE3"hSOFT_OVERRIDE2"SOFT_OVERRIDE1"hSOFT_OVERRIDE0"hP00""CGTT_SX_CLK_CTRL0 @ ON_DELAY"OFF_HYTERESIS"@ RESERVED"0SOFT_OVERRIDE7"SOFT_OVERRIDE6"0SOFT_OVERRIDE5"(SOFT_OVERRIDE4"SOFT_OVERRIDE3"x(SOFT_OVERRIDE2" SOFT_OVERRIDE1"xSOFT_OVERRIDE0"""8SX_MEMORY_EXPORT_SIZE SIZE"p""SX_MEMORY_EXPORT_BASE ADDRESS" ""XSX_EXPORT_BUFFER_SIZESCOLOR_BUFFER_SIZE"XPOSITION_BUFFER_SIZE"XSMX_BUFFER_SIZE" DEBUG_DATA"P ""pCGTS_TCC32_CTRL_REGTCC2"hTCC2_OVERRIDE"XTCC3"TCC3_OVERRIDE"P""CGTS_TCC10_CTRL_REGpTCC0"`TCC0_OVERRIDE"TCC1"XTCC1_OVERRIDE"@""CGTS_VC_CTRL_REGpVC" VC_OVERRIDE"0޵""CGTS_SX74_CTRL_REG`SX74"SX74_OVERRIDE"ڵ޵""޵CGTS_SX30_CTRL_REGߵPߵSX30"ߵSX30_OVERRIDE"صP۵""۵CGTS_TCP9_TD9_CTRL_REG@ܵܵTD9"ܵܵ TD9_OVERRIDE"ݵ@ݵTCP9"ݵTCP9_OVERRIDE"hյ@ٵ""ٵCGTS_RSP9_CTRL_REG0ڵٵRSP9"ڵRSP9_OVERRIDE"ҵյ""8ֵCGTS_SP4_97_96_CTRL_REGֵֵSP4_96"׵0׵SP4_96_OVERRIDE" ص׵SP4_97"xصSP4_97_OVERRIDE"εҵ""ҵCGTS_SP4_95_94_CTRL_REGxӵ0ӵSP4_94" ԵӵSP4_94_OVERRIDE"ԵxԵSP4_95"յSP4_95_OVERRIDE"H˵ ϵ""xϵCGTS_SP4_93_92_CTRL_REGеϵSP4_92"еpеSP4_92_OVERRIDE"`ѵѵSP4_93"ѵSP4_93_OVERRIDE"ǵ˵||""̵CGTS_SP4_91_90_CTRL_REG̵p̵SP4_90"`͵͵SP4_90_OVERRIDE"ε͵SP4_91"XεSP4_91_OVERRIDE"ĵhȵxx""ȵCGTS_TA9_SQA21_CTRL_REG`ɵɵSQA21"ʵɵSQA21_OVERRIDE"ʵ`ʵTA9"ʵ TA9_OVERRIDE"µŵtt""hŵCGTS_TCP8_TD8_CTRL_REGƵŵTD8"ƵXƵ TD8_OVERRIDE"HǵǵTCP8"ǵTCP8_OVERRIDE"(õpp""PõCGTS_RSP8_CTRL_REGõõRSP8"HĵRSP8_OVERRIDE"Ȼll""CGTS_SP4_87_86_CTRL_REGPSP4_86"@SP4_86_OVERRIDE"SP4_87"8µSP4_87_OVERRIDE"h@hh""CGTS_SP4_85_84_CTRL_REG8SP4_84"ཱུSP4_84_OVERRIDE"8SP4_85"ؾSP4_85_OVERRIDE"ีdd""8CGTS_SP4_83_82_CTRL_REGعSP4_82"0SP4_82_OVERRIDE" غSP4_83"xSP4_83_OVERRIDE"``""صCGTS_SP4_81_80_CTRL_REGx0SP4_80" жSP4_80_OVERRIDE"xSP4_81"SP4_81_OVERRIDE"X(\\""CGTS_TA8_SQA20_CTRL_REG زSQA20"ȳxSQA20_OVERRIDE"` TA8" TA8_OVERRIDE"HЮXX""(CGTS_TCP7_TD7_CTRL_REGTD7"h TD7_OVERRIDE"TCP7"`TCP7_OVERRIDE"訵TT""CGTS_RSP7_CTRL_REGhRSP7"RSP7_OVERRIDE"`PP""CGTS_SP4_77_76_CTRL_REGXSP4_76"SP4_76_OVERRIDE"XSP4_77"SP4_77_OVERRIDE"(LL""XCGTS_SP4_75_74_CTRL_REGSP4_74"PSP4_74_OVERRIDE"@SP4_75"SP4_75_OVERRIDE"ȞHH""CGTS_SP4_73_72_CTRL_REGPSP4_72"@SP4_72_OVERRIDE"वSP4_73"8SP4_73_OVERRIDE"p@DD""CGTS_SP4_71_70_CTRL_REG8SP4_70"࠵SP4_70_OVERRIDE"8SP4_71"ءSP4_71_OVERRIDE"蛵@@""@CGTS_TA7_SQA13_CTRL_REGSQA13"8SQA13_OVERRIDE" TA7"x TA7_OVERRIDE"<<""蘵CGTS_TCP6_TD6_CTRL_REG@TD6"(ؙ TD6_OVERRIDE"ȚTCP6" TCP6_OVERRIDE"88""ЖCGTS_RSP6_CTRL_REGp(RSP6"ȗRSP6_OVERRIDE"H 44""xCGTS_SP4_67_66_CTRL_REGГSP4_66"pSP4_66_OVERRIDE"`SP4_67"SP4_67_OVERRIDE"苵00""CGTS_SP4_65_64_CTRL_REGpSP4_64"`SP4_64_OVERRIDE"SP4_65"XSP4_65_OVERRIDE"`,,""CGTS_SP4_63_62_CTRL_REGXSP4_62"SP4_62_OVERRIDE"XSP4_63"SP4_63_OVERRIDE"0((""XCGTS_SP4_61_60_CTRL_REGSP4_60"PSP4_60_OVERRIDE"@SP4_61"SP4_61_OVERRIDE"؁$$""CGTS_TA6_SQA12_CTRL_REGXSQA12"HSQA12_OVERRIDE"TA6"8 TA6_OVERRIDE"P ""CGTS_TCP5_TD5_CTRL_REG@TD5"胵 TD5_OVERRIDE"@TCP5"TCP5_OVERRIDE"h|@""CGTS_RSP5_CTRL_REG0耵RSP5"RSP5_OVERRIDE"y|""8}CGTS_SP4_57_56_CTRL_REG}}SP4_56"~0~SP4_56_OVERRIDE" ~SP4_57"xSP4_57_OVERRIDE"uy""yCGTS_SP4_55_54_CTRL_REGxz0zSP4_54" {zSP4_54_OVERRIDE"{x{SP4_55"|SP4_55_OVERRIDE"Hr v""xvCGTS_SP4_53_52_CTRL_REGwvSP4_52"wpwSP4_52_OVERRIDE"`xxSP4_53"xSP4_53_OVERRIDE"nr ""sCGTS_SP4_51_50_CTRL_REGspsSP4_50"`ttSP4_50_OVERRIDE"utSP4_51"XuSP4_51_OVERRIDE"kho""oCGTS_TA5_SQA11_CTRL_REG`ppSQA11"qpSQA11_OVERRIDE"q`qTA5"q TA5_OVERRIDE"il""hlCGTS_TCP4_TD4_CTRL_REGmlTD4"mXm TD4_OVERRIDE"HnnTCP4"nTCP4_OVERRIDE"(fj""PjCGTS_RSP4_CTRL_REGjjRSP4"HkRSP4_OVERRIDE"bf""fCGTS_SP4_46_47_CTRL_REGgPgSP4_46"@hgSP4_46_OVERRIDE"hhSP4_47"8iSP4_47_OVERRIDE"h_@c""cCGTS_SP4_45_44_CTRL_REG8dcSP4_44"ddSP4_44_OVERRIDE"e8eSP4_45"eSP4_45_OVERRIDE"\_""8`CGTS_SP4_43_42_CTRL_REG``SP4_42"a0aSP4_42_OVERRIDE" baSP4_43"xbSP4_43_OVERRIDE"X\""\CGTS_SP4_41_40_CTRL_REGx]0]SP4_40" ^]SP4_40_OVERRIDE"^x^SP4_41"_SP4_41_OVERRIDE"V(Y""YCGTS_TA4_SQA10_CTRL_REG ZYSQA10"ZxZSQA10_OVERRIDE"`[ [TA4"[ TA4_OVERRIDE"PS W""pWCGTS_SQB_CTRL_REGXWSQB"`X SQB_OVERRIDE"@QS"" TCGTS_TCP3_TD3_CTRL_REGTxTTD3"`UU TD3_OVERRIDE"VUTCP3"XVTCP3_OVERRIDE"MQ""RCGTS_RSP3_CTRL_REGR`RRSP3"SRSP3_OVERRIDE"JXNܑܑ""NCGTS_SP4_37_36_CTRL_REGPOOSP4_36"OOSP4_36_OVERRIDE"PPPSP4_37"PSP4_37_OVERRIDE" GJؑؑ""PKCGTS_SP4_35_34_CTRL_REGKKSP4_34"LHLSP4_34_OVERRIDE"8MLSP4_35"MSP4_35_OVERRIDE"CGԑԑ""GCGTS_SP4_33_32_CTRL_REGHHHSP4_32"8IHSP4_32_OVERRIDE"IISP4_33"0JSP4_33_OVERRIDE"h@8DББ""DCGTS_SP4_31_30_CTRL_REG0EDSP4_30"EESP4_30_OVERRIDE"xF0FSP4_31"FSP4_31_OVERRIDE"=@̑̑""8ACGTS_TA3_SQA03_CTRL_REGAASQA03"B0BSQA03_OVERRIDE"CBTA3"pC TA3_OVERRIDE";=ȑȑ""=CGTS_TCP2_TD2_CTRL_REGx>8>TD2" ?> TD2_OVERRIDE"?x?TCP2"@TCP2_OVERRIDE"7x;đđ"";CGTS_RSP2_CTRL_REGh< <RSP2"<RSP2_OVERRIDE"@48""p8CGTS_SP4_27_26_CTRL_REG98SP4_26"9h9SP4_26_OVERRIDE"X::SP4_27":SP4_27_OVERRIDE"04""5CGTS_SP4_25_24_CTRL_REG5h5SP4_24"X66SP4_24_OVERRIDE"66SP4_25"P7SP4_25_OVERRIDE"-X1""1CGTS_SP4_23_22_CTRL_REGP22SP4_22"22SP4_22_OVERRIDE"3P3SP4_23"3SP4_23_OVERRIDE"(*-""P.CGTS_SP4_21_20_CTRL_REG..SP4_20"/H/SP4_20_OVERRIDE"80/SP4_21"0SP4_21_OVERRIDE"&*""*CGTS_TA2_SQA02_CTRL_REG+P+SQA02"@,+SQA02_OVERRIDE",,TA2"0- TA2_OVERRIDE"$H'""'CGTS_TCP1_TD1_CTRL_REG8('TD1"(( TD1_OVERRIDE")8)TCP1")TCP1_OVERRIDE"`!8%""%CGTS_RSP1_CTRL_REG(&%RSP1"&RSP1_OVERRIDE"!""0"CGTS_SP4_17_16_CTRL_REG""SP4_16"x#(#SP4_16_OVERRIDE"$#SP4_17"p$SP4_17_OVERRIDE"x""CGTS_SP4_15_14_CTRL_REGp(SP4_14" SP4_14_OVERRIDE" p SP4_15"!SP4_15_OVERRIDE"@""pCGTS_SP4_13_12_CTRL_REGSP4_12"hSP4_12_OVERRIDE"XSP4_13"SP4_13_OVERRIDE"""CGTS_SP4_11_10_CTRL_REGhSP4_10"XSP4_10_OVERRIDE"SP4_11"PSP4_11_OVERRIDE"`""CGTS_TA1_SQA01_CTRL_REGXSQA01"SQA01_OVERRIDE"XTA1" TA1_OVERRIDE"""`CGTS_TCP0_TD0_CTRL_REGTD0"P TD0_OVERRIDE"@TCP0"TCP0_OVERRIDE" ""HCGTS_RSP0_CTRL_REGRSP0"@RSP0_OVERRIDE" "" CGTS_SP4_07_06_CTRL_REG H SP4_06"8 SP4_06_OVERRIDE" SP4_07"0SP4_07_OVERRIDE"`8""CGTS_SP4_05_04_CTRL_REG0 SP4_04" SP4_04_OVERRIDE"x 0 SP4_05" SP4_05_OVERRIDE"""0CGTS_SP4_03_02_CTRL_REGSP4_02"x(SP4_02_OVERRIDE"SP4_03"pSP4_03_OVERRIDE"x||""CGTS_SP4_01_00_CTRL_REGp(SP4_00"SP4_00_OVERRIDE"pSP4_01"SP4_01_OVERRIDE"P xx""xCGTS_TA0_SQA00_CTRL_REGSQA00"pSQA00_OVERRIDE"XTA0" TA0_OVERRIDE"tt""CGTS_TCA10_CTRL_REGpTCA0"`TCA0_OVERRIDE"TCA1"XTCA1_OVERRIDE"ppp""CGTS_TCC76_CTRL_REG`TCC6"TCC6_OVERRIDE"`TCC7"TCC7_OVERRIDE"Hll""hCGTS_TCC54_CTRL_REGTCC4"`TCC4_OVERRIDE"PTCC5"TCC5_OVERRIDE"hh""CGTS_SPI76_CTRL_REGhSPIS6"XSPIS6_OVERRIDE"SPIS7"PSPIS7_OVERRIDE"hdd""CGTS_SPI54_CTRL_REGXSPIS4"SPIS4_OVERRIDE"XSPIS5"SPIS5_OVERRIDE"@``""`CGTS_SPI32_CTRL_REGSPIS2"XSPIS2_OVERRIDE"HSPIS3"SPIS3_OVERRIDE"\\""CGTS_SPI10_CTRL_REG`SPIM"PSPIM_OVERRIDE"SPIS1"HSPIS1_OVERRIDE"(XXX"" CGTS_RD_REG READ_DATA"۴TT""CGTS_RD_CTRL_REGH ROW_MUX_SEL"0 REG_MUX_SEL"FRONT_CLKGATE_ON_SEL" ڴܴPP""XܴCGTS_SM_CTRL_REG ݴܴ ON_SEQ_DELAY"ݴXݴOFF_SEQ_DELAY"H޴޴ BASE_MODE"޴޴SM_MODE"ߴ@ߴSM_MODE_ENABLE"0ߴ OVERRIDE" OVERRIDE_RSS"0ON_MONITOR_ADD_EN"ON_MONITOR_ADD"شڴLL""ڴCGTS_USER_TCC_DISABLEH۴ TCC_DISABLE"дشHH""شCGTS_TCC_DISABLEٴ8ٴ WRITE_DIS"ٴ TCC_DISABLE"Ŵ0ѴDD""ѴCGTT_SPI_CLK_CTRL ҴѴ ON_DELAY"ҴxҴOFF_HYSTERESIS"pӴ ӴSOFT_OVERRIDE7" ԴӴBACK_CLK_ON_OVERRIDE"ԴxԴFRONT_CLK_ON_OVERRIDE"xմ(մCORE3_OVERRIDE" ִմCORE2_OVERRIDE"ִxִCORE1_OVERRIDE"p״ ״CORE0_OVERRIDE"״ REG_OVERRIDE"Xƴ@@""ƴSPI_DEBUG_BUSYHǴǴPS_BUSY"ǴǴSC_DATA_IN_BUSY"ȴHȴSC_CNTL_IN_BUSY"8ɴȴES_BUSY"ɴɴGS_BUSY"xʴ0ʴVS_BUSY"˴ʴ SPI_BUSY_6"˴p˴ SPI_BUSY_7"X̴̴ SPI_BUSY_8"̴̴  SPI_BUSY_9"ʹPʹ  SPI_BUSY_10"8δʹ  SPI_BUSY_11"δδ  SPI_BUSY_12"xϴ0ϴ  SPI_BUSY_13"дϴ SPI_BUSY_14"pд SPI_BUSY_15"(<<""hSPI_CONFIG_CNTL_1ôVTX_DONE_DELAYкX;delay 14 clks (defalut, min value needed for pele config) hdelay 16 clks delay 18 clks Hdelay 20 clks 0༴delay 22 clks Ƚxdelay 24 clks `delay 26 clks delay 28 clks @delay 30 clks (ؿ delay 32 clks p delay 34 clks X delay 4 clks delay 6 clks ´8´ delay 8 clks ô´delay 10 clks hôdelay 12 clks ĴhĴINTERP_ONE_PRIM_PER_ROW0ŴĴBInterpolate two prims per clock, assuming no conflicts (default) xŴ%Only interpolate one prim per clock 88""SPI_PERFCOUNTER3_LOWP PERF_COUNT_LOW"@044""SPI_PERFCOUNTER3_HIض PERF_COUNT_HI"в00""SPI_PERFCOUNTER2_LOWh PERF_COUNT_LOW"XH,,""SPI_PERFCOUNTER2_HI PERF_COUNT_HI"说б((""(SPI_PERFCOUNTER1_LOW PERF_COUNT_LOW"p`$$""SPI_PERFCOUNTER1_HI PERF_COUNT_HI"讴 ""@SPI_PERFCOUNTER0_LOW PERF_COUNT_LOW"x""ȭSPI_PERFCOUNTER0_HI PERF_COUNT_HI" ""`SPI_PERFCOUNTER3_SELECT PERF_SEL"""SPI_PERFCOUNTER2_SELECTH PERF_SEL"G(""SPI_PERFCOUNTER1_SELECTة PERF_SEL" FH ""XHSPI_PERFCOUNTER0_SELECTHH PERF_SELgI@IdSPI_VS_WINDOW_VALID: SPI_VS_WINDOW_VALID Clock count enabled by perfcounter_start event. J(JgSPI_VS_BUSY: SPI_VS_BUSY Number of clocks with outstanding thread work (SPI or SH). KKmSPI_VS_INPUT_STARVED: SPI_VS_INPUT_STARVED Number of clocks input fifo is empty and no work to do. LLjSPI_VS_VSR_STALL: SPI_VS_VSR_STALL Number of clocks stalled due to VSR write port conflicts MMYSPI_VS_VSR_FULL: SPI_VS_VSR_FULL Number of clocks VS VSR buffers are full NM^SPI_VS_GPR_STALL: SPI_VS_GPR_STALL Number of clocks stalled due to lack of GPRs pONiSPI_VS_INPUT_STALL: SPI_VS_INPUT_STALL Number of clocks stalled waiting for GPR input cycles `POlSPI_VS_MEM_STALL: SPI_VS_MEM_STALL Number of clocks stalled due to lack of stack or tmp space PQPeSPI_VS_TB_FULL: SPI_VS_TB_FULL Number of clocks stalled due to full SQ thread buffer @RQ gSPI_VS_EV_FIFO_FULL: SPI_VS_EV_FIFO_FULL Number of clocks stalled due to full SQ event fifo 8SR oSPI_VS_THREAD_STALL: SPI_VS_THREAD_STALL Number of clocks thread is stalled due to thread_input_arb TS RSPI_VS_EVENT_VECTOR: SPI_VS_EVENT_VECTOR Number of vectors plus events TXT @SPI_VS_VECTOR: SPI_VS_VECTOR Number of vectors U U dSPI_GS_WINDOW_VALID: SPI_GS_WINDOW_VALID Clock count enabled by perfcounter_start event. VVgSPI_GS_BUSY: SPI_GS_BUSY Number of clocks with outstanding thread work (SPI or SH). WVmSPI_GS_INPUT_STARVED: SPI_GS_INPUT_STARVED Number of clocks input fifo is empty and no work to do. XWjSPI_GS_GSR_STALL: SPI_GS_GSR_STALL Number of clocks stalled due to VSR write port conflicts xYXYSPI_GS_GSR_FULL: SPI_GS_GSR_FULL Number of clocks VS VSR buffers are full `ZY^SPI_GS_GPR_STALL: SPI_GS_GPR_STALL Number of clocks stalled due to lack of GPRs P[ZiSPI_GS_INPUT_STALL: SPI_GS_INPUT_STALL Number of clocks stalled waiting for GPR input cycles @\[lSPI_GS_MEM_STALL: SPI_GS_MEM_STALL Number of clocks stalled due to lack of stack or tmp space 0]\eSPI_GS_TB_FULL: SPI_GS_TB_FULL Number of clocks stalled due to full SQ thread buffer ^x]gSPI_GS_EV_FIFO_FULL: SPI_GS_EV_FIFO_FULL Number of clocks stalled due to full SQ event fifo _h^oSPI_GS_THREAD_STALL: SPI_GS_THREAD_STALL Number of clocks thread is stalled due to thread_input_arb _`_RSPI_GS_EVENT_VECTOR: SPI_GS_EVENT_VECTOR Number of vectors plus events `8`@SPI_GS_VECTOR: SPI_GS_VECTOR Number of vectors aadSPI_ES_WINDOW_VALID: SPI_ES_WINDOW_VALID Clock count enabled by perfcounter_start event. bagSPI_ES_BUSY: SPI_ES_BUSY Number of clocks with outstanding thread work (SPI or SH). cbmSPI_ES_INPUT_STARVED: SPI_ES_INPUT_STARVED Number of clocks input fifo is empty and no work to do. xdcjSPI_ES_ESR_STALL: SPI_ES_ESR_STALL Number of clocks stalled due to VSR write port conflicts XedYSPI_ES_ESR_FULL: SPI_ES_ESR_FULL Number of clocks VS VSR buffers are full @fe^SPI_ES_GPR_STALL: SPI_ES_GPR_STALL Number of clocks stalled due to lack of GPRs 0gf iSPI_ES_INPUT_STALL: SPI_ES_INPUT_STALL Number of clocks stalled waiting for GPR input cycles hxg!lSPI_ES_MEM_STALL: SPI_ES_MEM_STALL Number of clocks stalled due to lack of stack or tmp space ihh"eSPI_ES_TB_FULL: SPI_ES_TB_FULL Number of clocks stalled due to full SQ thread buffer jXi#gSPI_ES_EV_FIFO_FULL: SPI_ES_EV_FIFO_FULL Number of clocks stalled due to full SQ event fifo jHj$oSPI_ES_THREAD_STALL: SPI_ES_THREAD_STALL Number of clocks thread is stalled due to thread_input_arb k@k%RSPI_ES_EVENT_VECTOR: SPI_ES_EVENT_VECTOR Number of vectors plus events ll&@SPI_ES_VECTOR: SPI_ES_VECTOR Number of vectors ml'kSPI_ITER_CTRL_WINDOW_VALID: SPI_ITER_CTRL_WINDOW_VALID Clock count enabled by perfcounter_start event. hnm(ZSPI_ITER_CTRL_ACTIVE: SPI_ITER_CTRL_ACTIVE Number of clks iter cmd fifo is busy Hon)XSPI_ITER_CTRL_FULL: SPI_ITER_CTRL_FULL Number of clks iter cmd fifo is full @po*rSPI_ITER_CTRL_STALL_PV: SPI_ITER_CTRL_STALL_PV Number of clks stalled due to ptr_buff storage (2 vectors) 0qp+iSPI_ITER_CTRL_STALL_EV: SPI_ITER_CTRL_STALL_EV Number of clks stalled due to ptr_buff event fifo rxq,iSPI_ITER_STARVED: SPI_ITER_STARVED Number of clocks input fifo is empty and no work to do. rhr-OSPI_ITER_ACTIVE: SPI_ITER_ACTIVE Number of clks iter is working s@s.OSPI_ITER_FULL: SPI_ITER_FULL Number of clks iter fifo is full tt/kSPI_ITER_STALL: SPI_ITER_STALL Number of clks iter is stalled due to IJ buffers or vec cnt uu0jSPI_PTR_BUFF_WINDOW_VALID: SPI_PTR_BUFF_WINDOW_VALID Clock count enabled by perfcounter_start event. vu1mSPI_PTR_BUFF_BUSY: SPI_PTR_BUFF_BUSY Number of clocks with outstanding thread work (SPI or SH). wv2cSPI_PTR_BUFF_ACTIVE: SPI_PTR_BUFF_ACTIVE Number of clks ptr_buff is processing threads. pxw3VSPI_PTR_BUFF_STALL: SPI_PTR_BUFF_STALL Number of clks ptr_buff is stalled `yx4iSPI_PTR_BUFF_GPR_STALL: SPI_PTR_BUFF_GPR_STALL Number of clks alloc machine has to wait for gprs Xzy5oSPI_PTR_BUFF_MEM_STALL: SPI_PTR_BUFF_MEM_STALL Number of clks alloc machine has to wait for stk or tmp H{z6kSPI_PTR_BUFF_IJ_STALL: SPI_PTR_BUFF_IJ_STALL Number of clks alloc machine has to wait for IJ data 8|{7lSPI_PTR_BUFF_CTL_STALL: SPI_PTR_BUFF_CTL_STALL Number of clks alloc machine has to wait for pix ctl }|8XSPI_PTR_BUFF_EVENT_VECTOR: SPI_PTR_BUFF_EVENT_VECTOR Number of vectors plus events }`}9FSPI_PTR_BUFF_VECTOR: SPI_PTR_BUFF_VECTOR Number of vectors ~0~:fSPI_PTR_BUFF_2_PASS_VEC: SPI_PTR_BUFF_2_PASS_VEC Number of threads requiring two interp passes  ;hSPI_PTR_BUFF_3_PASS_VEC: SPI_PTR_BUFF_3_PASS_VEC Number of threads requiring three interp passes <gSPI_PTR_BUFF_4_PASS_VEC: SPI_PTR_BUFF_4_PASS_VEC Number of threads requiring four interp passes =lSPI_PCTL0_INPUT_STALL: SPI_PCTL0_INPUT_STALL Number of clocks stalled waiting for GPR input cycles >lSPI_PCTL0_PI_PPB_STALL: SPI_PCTL0_PI_PPB_STALL Number of clocks pi machine is stalled for full ppb. ?hSPI_PCTL0_THREAD_STALL: SPI_PCTL0_THREAD_STALL Number of clocks stalled due to thread_input_arb xЃ@jSPI_PCTL0_PI_BUSY: SPI_PCTL0_PI_BUSY Number of clocks pi machine is busy with interpolation. hAgSPI_PCTL0_SX_VALID: SPI_PCTL0_SX_VALID Number of param cache read requests sent to the SX. XBlSPI_PCTL1_INPUT_STALL: SPI_PCTL1_INPUT_STALL Number of clocks stalled waiting for GPR input cycles HClSPI_PCTL1_PI_PPB_STALL: SPI_PCTL1_PI_PPB_STALL Number of clocks pi machine is stalled for full ppb. 8DhSPI_PCTL1_THREAD_STALL: SPI_PCTL1_THREAD_STALL Number of clocks stalled due to thread_input_arb (EjSPI_PCTL1_PI_BUSY: SPI_PCTL1_PI_BUSY Number of clocks pi machine is busy with interpolation. pFgSPI_PCTL1_SX_VALID: SPI_PCTL1_SX_VALID Number of param cache read requests sent to the SX. `GZSPI_PS_TB_FULL: SPI_PS_TB_FULL Number of clocks PS thread buffer is full. ؋@H\SPI_PS_EV_FIFO_FULL: SPI_PS_EV_FIFO_FULL Number of clocks PS event fifo is full. IdSPI_THREAD_CONFLICT: SPI_THREAD_CONFLICT Number of clocks with more than one thread req. JdSPI_VS_STK_STALL: SPI_VS_STK_STALL Number of clocks vs is stalled due to stack space. KcSPI_VS_TMP_STALL: SPI_VS_TMP_STALL Number of clocks vs is stalled due to temp space. x؎LdSPI_GS_STK_STALL: SPI_GS_STK_STALL Number of clocks gs is stalled due to stack space. `McSPI_GS_TMP_STALL: SPI_GS_TMP_STALL Number of clocks gs is stalled due to temp space. HNdSPI_ES_STK_STALL: SPI_ES_STK_STALL Number of clocks es is stalled due to stack space. 0OcSPI_ES_TMP_STALL: SPI_ES_TMP_STALL Number of clocks es is stalled due to temp space. xPdSPI_PS_STK_STALL: SPI_PS_STK_STALL Number of clocks ps is stalled due to stack space. `QcSPI_PS_TMP_STALL: SPI_PS_TMP_STALL Number of clocks ps is stalled due to temp space. HRgSPI_PS_FBUF_STALL: SPI_PS_FBUF_STALL Number of clocks ps is stalled due to fbuffer space. Е8S[SPI_PTR_BUFF_FPOS: SPI_PTR_BUFF_FPOS Number of fpos flags popped by ptr_buff. ȖTnSPI_PTR_BUFF_DEALLOC: SPI_PTR_BUFF_DEALLOC Number of param cache dealloc tokens popped by ptr buff. ȗU|SPI_PTR_BUFF_0_CONFLICT_VEC: SPI_PTR_BUFF_0_CONFLICT_VEC Number of PS vecs processed containing 0 param cache conflicts. ȘV{SPI_PTR_BUFF_1_CONFLICT_VEC: SPI_PTR_BUFF_1_CONFLICT_VEC Number of PS vecs processed containing 1 param cache conflict. șW|SPI_PTR_BUFF_2_CONFLICT_VEC: SPI_PTR_BUFF_2_CONFLICT_VEC Number of PS vecs processed containing 2 param cache conflicts. ȚX|SPI_PTR_BUFF_3_CONFLICT_VEC: SPI_PTR_BUFF_3_CONFLICT_VEC Number of PS vecs processed containing 3 param cache conflicts. țY|SPI_PTR_BUFF_4_CONFLICT_VEC: SPI_PTR_BUFF_4_CONFLICT_VEC Number of PS vecs processed containing 4 param cache conflicts. ȜZ|SPI_PTR_BUFF_5_CONFLICT_VEC: SPI_PTR_BUFF_5_CONFLICT_VEC Number of PS vecs processed containing 5 param cache conflicts. ȝ[zSPI_DYN_GPR_PS_SKIP_SIMD: SPI_DYN_GPR_PS_SKIP_SIMD Number of PS threads that alloc GPR by skipping to another SIMD. Ȟ\zSPI_DYN_GPR_VS_SKIP_SIMD: SPI_DYN_GPR_VS_SKIP_SIMD Number of VS threads that alloc GPR by skipping to another SIMD. ȟ]zSPI_DYN_GPR_GS_SKIP_SIMD: SPI_DYN_GPR_GS_SKIP_SIMD Number of GS threads that alloc GPR by skipping to another SIMD. Ƞ^zSPI_DYN_GPR_ES_SKIP_SIMD: SPI_DYN_GPR_ES_SKIP_SIMD Number of ES threads that alloc GPR by skipping to another SIMD. ȡ_zSPI_DYN_GPR_PS_WRAP_SOONER: SPI_DYN_GPR_PS_WRAP_SOONER Number of PS threads that jump back to pool base to alloc GPR. Ȣ`zSPI_DYN_GPR_VS_WRAP_SOONER: SPI_DYN_GPR_VS_WRAP_SOONER Number of VS threads that jump back to pool base to alloc GPR. ȣazSPI_DYN_GPR_GS_WRAP_SOONER: SPI_DYN_GPR_GS_WRAP_SOONER Number of GS threads that jump back to pool base to alloc GPR. ȤbzSPI_DYN_GPR_ES_WRAP_SOONER: SPI_DYN_GPR_ES_WRAP_SOONER Number of ES threads that jump back to pool base to alloc GPR. cmSPI_CLKGATE_BUSY_STALL: SPI_CLKGATE_BUSY_STALL Number of clocks with spi busy and not all_clocks_on. ئdSPI_CLKGATE_ACTIVE_STALL: SPI_CLKGATE_ACTIVE_STALL Number of clocks with spim_active (includes VGT and SQ wakeup) and not all_clocks_on. e_SPI_CLKGATE_ALL_CLOCKS_ON: SPI_CLKGATE_ALL_CLOCKS_ON Number of clocks with all_clocks_on. feSPI_CLKGATE_SPI_CLOCKS_ON: SPI_CLKGATE_SPI_CLOCKS_ON Number of clocks with spim grp0 clocks on. :F""FSPI_DEBUG_READ@GDATA"X;""; SPI_ENHANCEH<;SPI_ECO_SPARE_0"<<SPI_ECO_SPARE_1"=H=SPI_ECO_SPARE_2"@>=SPI_ECO_SPARE_3">>SPI_ECO_SPARE_4"?@?SPI_ECO_SPARE_5"8@?SPI_ECO_SPARE_6"@@SPI_ECO_SPARE_7"A8ASPI_ECO_SPARE_8"0BA SPI_ECO_SPARE_9"BB SPI_ECO_SPARE_10"C0C SPI_ECO_SPARE_11"(DC SPI_ECO_SPARE_12"DD SPI_ECO_SPARE_13"xE(ESPI_ECO_SPARE_14"ESPI_ECO_SPARE_15"` "" SPI_CONFIG_CNTL2!X!GPR_WRITE_PRIORITY"!/Priority order (high to low) = VS, GS, ES, PS "X"/Priority order = VS, GS, PS, ES ##/Priority order = VS, ES, GS, PS 8$#/Priority order = VS, ES, PS, GS $$/Priority order = VS, PS, GS, ES %8%/Priority order = VS, PS, ES, GS `&%/Priority order = GS, VS, ES, PS '&/Priority order = GS, VS, PS, ES '`'/Priority order = GS, ES, VS, PS (( /Priority order = GS, ES, PS, VS @)( /Priority order = GS, PS, VS, ES )) /Priority order = GS, PS, ES, VS *@* /Priority order = ES, VS, GS, PS h+* /Priority order = ES, VS, PS, GS ,+/Priority order = ES, GS, VS, PS ,h,/Priority order = ES, GS, PS, VS - -/Priority order = ES, PS, VS, GS H.-/Priority order = ES, PS, GS, VS /./Priority order = PS, VS, GS, ES /H//Priority order = PS, VS, ES, GS x00/Priority order = PS, GS, VS, ES 010/Priority order = PS, GS, ES, VS 1x1/Priority order = PS, ES, VS, GS 02/Priority order = PS, ES, GS, VS 42H3DISABLE_INTERP_143>Use both interpolators and both of SPI_SH_input0/1 (default) X4#Disable interp1 and SPI_SH_input1 75h5DEBUG_THREAD_TYPE_SEL55PS x686VS 76GS H7ES 087DEBUG_GROUP_SEL"8:8 8DEBUG_GRBM_OVERRIDE9 9&Use dbg_common output to mux group_0 9,Use DEBUG_GROUP_SEL setting to mux group_0 :DEBUG_SIMD_SEL"""HSPI_FOG_FUNC_BIAS VALUE"p""SPI_FOG_FUNC_SCALE8 VALUE"܆܆""8 SPI_FOG_CNTLPASS_FOG_THROUGH_PS"8PIXEL_FOG_FUNC(SPI_FOG_NONE: SPI_FOG_NONE pSPI_FOG_EXP: SPI_FOG_EXP hSPI_FOG_EXP2: SPI_FOG_EXP2  SPI_FOG_LINEAR: SPI_FOG_LINEAR hPIXEL_FOG_SRC_SELp-Use Z value for fog source (WNEAR=WFAR=1.0) Use W value for fog source hVS_FOG_CLAMP_DISABLEp)Clamp VS fog result between 0.0 and 1.0 Do not clamp VS fog result. ؆؆"" SPI_INPUT_Z PROVIDE_Z_TO_SPI"(ԆԆ""SPI_INTERP_CONTROL_0(FLAT_SHADE_ENA"PNT_SPRITE_ENA" (xPNT_SPRITE_OVRD_X04SPI_PNT_SPRITE_SEL_0: Override component with 0.0f x4SPI_PNT_SPRITE_SEL_1: Override component with 1.0f 07SPI_PNT_SPRITE_SEL_S: Override component with S value h7SPI_PNT_SPRITE_SEL_T: Override component with T value 3SPI_PNT_SPRITE_SEL_NONE: Keep interpolated result pxPNT_SPRITE_OVRD_Y4SPI_PNT_SPRITE_SEL_0: Override component with 0.0f 84SPI_PNT_SPRITE_SEL_1: Override component with 1.0f 7SPI_PNT_SPRITE_SEL_S: Override component with S value @7SPI_PNT_SPRITE_SEL_T: Override component with T value 3SPI_PNT_SPRITE_SEL_NONE: Keep interpolated result  PNT_SPRITE_OVRD_Z ` 4SPI_PNT_SPRITE_SEL_0: Override component with 0.0f  4SPI_PNT_SPRITE_SEL_1: Override component with 1.0f H 7SPI_PNT_SPRITE_SEL_S: Override component with S value  7SPI_PNT_SPRITE_SEL_T: Override component with T value P 3SPI_PNT_SPRITE_SEL_NONE: Keep interpolated result  h PNT_SPRITE_OVRD_W  4SPI_PNT_SPRITE_SEL_0: Override component with 0.0f h4SPI_PNT_SPRITE_SEL_1: Override component with 1.0f  7SPI_PNT_SPRITE_SEL_S: Override component with S value X7SPI_PNT_SPRITE_SEL_T: Override component with T value 3SPI_PNT_SPRITE_SEL_NONE: Keep interpolated result hPNT_SPRITE_TOP_1`!T is 1.0 at bottom of primitive T is 1.0 at top of primitive (ІІ""xSPI_PS_IN_CONTROL_1 GEN_INDEX_PIX"xGEN_INDEX_PIX_ADDR"p FRONT_FACE_ENA" FRONT_FACE_CHAN"`p FRONT_FACE_ALL_BITSGSign bit represents isFF (dx9, -1.0f == backFace, +1.0f == frontFace) FReplace whole 32b val with isFF (WGF, 1 == frontFace, 0 == backFace)  FRONT_FACE_ADDR"` FOG_ADDR"XFIXED_PT_POSITION_ENA"FIXED_PT_POSITION_ADDR"` POSITION_ULC"h̆̆""SPI_PS_IN_CONTROL_0 X NUM_INTERP" POSITION_ENA"X POSITION_CENTROID"P POSITION_ADDR" PARAM_GEN"HPARAM_GEN_ADDR"@BARYC_SAMPLE_CNTL CENTROIDS_ONLY: CENTROIDS_ONLY 0CENTERS_ONLY: CENTERS_ONLY @.CENTROIDS_AND_CENTERS: CENTROIDS_AND_CENTERS KUNDEF: No center or centroid, UNDEFINED unless BARYC_AT_SAMPLE_ENA is set hPERSP_GRADIENT_ENA"`LINEAR_GRADIENT_ENA"POSITION_SAMPLE"`BARYC_AT_SAMPLE_ENA"@ ȆȆ""pSPI_THREAD_GROUPING PS_GROUPING"h VS_GROUPING"P GS_GROUPING" ES_GROUPING"(ܳĆĆ""SPI_VS_OUT_CONFIG`VS_PER_COMPONENT"XVS_EXPORT_COUNT"VS_EXPORTS_FOG"X VS_OUT_FOG_VEC_ADDR"ճܳ""ܳSPI_PS_INPUT_CNTL_31ݳPݳ SEMANTIC"ݳ8޳ DEFAULT_VAL޳޳0.0f, 0.0f, 0.0f, 0.0f x߳ ߳0.0f, 0.0f, 0.0f, 1.0f ߳1.0f, 1.0f, 1.0f, 0.0f `1,0f, 1.0f, 1.0f, 1.0f X  FLAT_SHADE"  SEL_CENTROID"X  SEL_LINEAR" SEL_SAMPLE"ͳճ""ճSPI_PS_INPUT_CNTL_30ֳ8ֳ SEMANTIC"ٳֳ ׳ DEFAULT_VAL׳h׳0.0f, 0.0f, 0.0f, 0.0f `سس0.0f, 0.0f, 0.0f, 1.0f ٳس1.0f, 1.0f, 1.0f, 0.0f Hٳ1,0f, 1.0f, 1.0f, 1.0f @ڳٳ  FLAT_SHADE"ڳڳ  SEL_CENTROID"۳@۳  SEL_LINEAR"۳ SEL_SAMPLE"Ƴpγ""γSPI_PS_INPUT_CNTL_29hϳ ϳ SEMANTIC"ҳϳг DEFAULT_VALгPг0.0f, 0.0f, 0.0f, 0.0f Hѳг0.0f, 0.0f, 0.0f, 1.0f ѳѳ1.0f, 1.0f, 1.0f, 0.0f 0ҳ1,0f, 1.0f, 1.0f, 1.0f (ӳҳ  FLAT_SHADE"ӳӳ  SEL_CENTROID"pԳ(Գ  SEL_LINEAR"Գ SEL_SAMPLE"ȿXdz""dzSPI_PS_INPUT_CNTL_28Pȳȳ SEMANTIC"p˳ȳȳ DEFAULT_VALɳ8ɳ0.0f, 0.0f, 0.0f, 0.0f 0ʳɳ0.0f, 0.0f, 0.0f, 1.0f ʳxʳ1.0f, 1.0f, 1.0f, 0.0f ˳1,0f, 1.0f, 1.0f, 1.0f ̳˳  FLAT_SHADE"̳h̳  SEL_CENTROID"Xͳͳ  SEL_LINEAR"ͳ SEL_SAMPLE"@""SPI_PS_INPUT_CNTL_278 SEMANTIC"Xij DEFAULT_VALx³ ³0.0f, 0.0f, 0.0f, 0.0f ó³0.0f, 0.0f, 0.0f, 1.0f ó`ó1.0f, 1.0f, 1.0f, 0.0f ij1,0f, 1.0f, 1.0f, 1.0f ijij  FLAT_SHADE"ųPų  SEL_CENTROID"@Ƴų  SEL_LINEAR"Ƴ SEL_SAMPLE"(""SPI_PS_INPUT_CNTL_26 ع SEMANTIC"@x DEFAULT_VAL`0.0f, 0.0f, 0.0f, 0.0f 0.0f, 0.0f, 0.0f, 1.0f H1.0f, 1.0f, 1.0f, 0.0f 輳1,0f, 1.0f, 1.0f, 1.0f ཱི  FLAT_SHADE"8  SEL_CENTROID"(ླ  SEL_LINEAR" SEL_SAMPLE"""hSPI_PS_INPUT_CNTL_25 SEMANTIC"(` DEFAULT_VALH0.0f, 0.0f, 0.0f, 0.0f 贳0.0f, 0.0f, 0.0f, 1.0f 01.0f, 1.0f, 1.0f, 0.0f е1,0f, 1.0f, 1.0f, 1.0f ȶ  FLAT_SHADE"p  SEL_CENTROID"ȷ  SEL_LINEAR"h SEL_SAMPLE"h""PSPI_PS_INPUT_CNTL_24 SEMANTIC"H DEFAULT_VAL0ج0.0f, 0.0f, 0.0f, 0.0f Эx0.0f, 0.0f, 0.0f, 1.0f p1.0f, 1.0f, 1.0f, 0.0f 1,0f, 1.0f, 1.0f, 1.0f h  FLAT_SHADE"X  SEL_CENTROID"  SEL_LINEAR"P SEL_SAMPLE"Pࣳ""8SPI_PS_INPUT_CNTL_23ؤ SEMANTIC"0x DEFAULT_VAL0.0f, 0.0f, 0.0f, 0.0f `0.0f, 0.0f, 0.0f, 1.0f X1.0f, 1.0f, 1.0f, 0.0f 1,0f, 1.0f, 1.0f, 1.0f P  FLAT_SHADE"@  SEL_CENTROID"ੳ  SEL_LINEAR"8 SEL_SAMPLE"8Ȝ"" SPI_PS_INPUT_CNTL_22x SEMANTIC"࠳` DEFAULT_VAL0.0f, 0.0f, 0.0f, 0.0f H0.0f, 0.0f, 0.0f, 1.0f @蟳1.0f, 1.0f, 1.0f, 0.0f 1,0f, 1.0f, 1.0f, 1.0f 8  FLAT_SHADE"(ء  SEL_CENTROID"Ȣ  SEL_LINEAR"  SEL_SAMPLE" ""SPI_PS_INPUT_CNTL_21` SEMANTIC"șH DEFAULT_VAL藳0.0f, 0.0f, 0.0f, 0.0f 00.0f, 0.0f, 0.0f, 1.0f (И1.0f, 1.0f, 1.0f, 0.0f p1,0f, 1.0f, 1.0f, 1.0f h  FLAT_SHADE"  SEL_CENTROID"h  SEL_LINEAR" SEL_SAMPLE"""SPI_PS_INPUT_CNTL_20H SEMANTIC"菳0 DEFAULT_VALАx0.0f, 0.0f, 0.0f, 0.0f p0.0f, 0.0f, 0.0f, 1.0f 1.0f, 1.0f, 1.0f, 0.0f X1,0f, 1.0f, 1.0f, 1.0f P  FLAT_SHADE"  SEL_CENTROID"P  SEL_LINEAR" SEL_SAMPLE"`}8""SPI_PS_INPUT_CNTL_190膳 SEMANTIC"PЇ DEFAULT_VALp0.0f, 0.0f, 0.0f, 0.0f 0.0f, 0.0f, 0.0f, 1.0f X1.0f, 1.0f, 1.0f, 0.0f 1,0f, 1.0f, 1.0f, 1.0f  FLAT_SHADE"H  SEL_CENTROID"8  SEL_LINEAR"،  CYL_WRAP"0PT_SPRITE_TEX"؍ SEL_SAMPLE"u}""0~SPI_PS_INPUT_CNTL_18~~ SEMANTIC"(p DEFAULT_VAL0.0f, 0.0f, 0.0f, 0.0f X0.0f, 0.0f, 0.0f, 1.0f P1.0f, 1.0f, 1.0f, 0.0f 1,0f, 1.0f, 1.0f, 1.0f H  FLAT_SHADE"8肳  SEL_CENTROID"؃  SEL_LINEAR"x0  CYL_WRAP" ЄPT_SPRITE_TEX"x SEL_SAMPLE"lxu""uSPI_PS_INPUT_CNTL_17pv(v SEMANTIC"yvw DEFAULT_VALwXw0.0f, 0.0f, 0.0f, 0.0f Pxw0.0f, 0.0f, 0.0f, 1.0f xx1.0f, 1.0f, 1.0f, 0.0f 8y1,0f, 1.0f, 1.0f, 1.0f 0zy  FLAT_SHADE"zz  SEL_CENTROID"x{0{  SEL_LINEAR"|{  CYL_WRAP"|p|PT_SPRITE_TEX"} SEL_SAMPLE"@dm""pmSPI_PS_INPUT_CNTL_16nm SEMANTIC"0qhnn DEFAULT_VALPon0.0f, 0.0f, 0.0f, 0.0f oo0.0f, 0.0f, 0.0f, 1.0f p8p1.0f, 1.0f, 1.0f, 0.0f p1,0f, 1.0f, 1.0f, 1.0f qq  FLAT_SHADE"xr(r  SEL_CENTROID"sr  SEL_LINEAR"sps  CYL_WRAP"`ttPT_SPRITE_TEX"t SEL_SAMPLE"[d""eSPI_PS_INPUT_CNTL_15ehe SEMANTIC"hfPf DEFAULT_VALff0.0f, 0.0f, 0.0f, 0.0f g8g0.0f, 0.0f, 0.0f, 1.0f 0hg1.0f, 1.0f, 1.0f, 0.0f xh1,0f, 1.0f, 1.0f, 1.0f pi(i  FLAT_SHADE"ji  SEL_CENTROID"jpj  SEL_LINEAR"Xkk  CYL_WRAP"lkPT_SPRITE_TEX"Xl SEL_SAMPLE"SX\||""\SPI_PS_INPUT_CNTL_14P]] SEMANTIC"p`]] DEFAULT_VAL^8^0.0f, 0.0f, 0.0f, 0.0f 0_^0.0f, 0.0f, 0.0f, 1.0f _x_1.0f, 1.0f, 1.0f, 0.0f `1,0f, 1.0f, 1.0f, 1.0f a`  FLAT_SHADE"aha  SEL_CENTROID"Xbb  SEL_LINEAR"bb  CYL_WRAP"cPcPT_SPRITE_TEX"c SEL_SAMPLE" KSxx""PTSPI_PS_INPUT_CNTL_13TT SEMANTIC"XHUU DEFAULT_VAL0VU0.0f, 0.0f, 0.0f, 0.0f VxV0.0f, 0.0f, 0.0f, 1.0f pWW1.0f, 1.0f, 1.0f, 0.0f W1,0f, 1.0f, 1.0f, 1.0f XhX  FLAT_SHADE"XYY  SEL_CENTROID"YY  SEL_LINEAR"ZPZ  CYL_WRAP"@[ZPT_SPRITE_TEX"[ SEL_SAMPLE"BKtt""KSPI_PS_INPUT_CNTL_12LHL SEMANTIC"OL0M DEFAULT_VALMxM0.0f, 0.0f, 0.0f, 0.0f pNN0.0f, 0.0f, 0.0f, 1.0f ON1.0f, 1.0f, 1.0f, 0.0f XO1,0f, 1.0f, 1.0f, 1.0f PPP  FLAT_SHADE"PP  SEL_CENTROID"QPQ  SEL_LINEAR"8RQ  CYL_WRAP"RRPT_SPRITE_TEX"8S SEL_SAMPLE"`:8Cpp""CSPI_PS_INPUT_CNTL_110DC SEMANTIC"PGDD DEFAULT_VALpEE0.0f, 0.0f, 0.0f, 0.0f FE0.0f, 0.0f, 0.0f, 1.0f FXF1.0f, 1.0f, 1.0f, 0.0f F1,0f, 1.0f, 1.0f, 1.0f GG  FLAT_SHADE"HHH  SEL_CENTROID"8IH  SEL_LINEAR"II  CYL_WRAP"J0JPT_SPRITE_TEX"J SEL_SAMPLE"2:ll""0;SPI_PS_INPUT_CNTL_10;; SEMANTIC">(<p< DEFAULT_VAL=<0.0f, 0.0f, 0.0f, 0.0f =X=0.0f, 0.0f, 0.0f, 1.0f P>=1.0f, 1.0f, 1.0f, 0.0f >1,0f, 1.0f, 1.0f, 1.0f ?H?  FLAT_SHADE"8@?  SEL_CENTROID"@@  SEL_LINEAR"xA0A  CYL_WRAP" BAPT_SPRITE_TEX"xB SEL_SAMPLE")2hh""2SPI_PS_INPUT_CNTL_9p3(3 SEMANTIC"634 DEFAULT_VAL4X40.0f, 0.0f, 0.0f, 0.0f P540.0f, 0.0f, 0.0f, 1.0f 551.0f, 1.0f, 1.0f, 0.0f 861,0f, 1.0f, 1.0f, 1.0f 076  FLAT_SHADE"77  SEL_CENTROID"x808  SEL_LINEAR"98  CYL_WRAP"9p9PT_SPRITE_TEX": SEL_SAMPLE"X!(*dd""x*SPI_PS_INPUT_CNTL_8+* SEMANTIC"8.p++ DEFAULT_VALX,,0.0f, 0.0f, 0.0f, 0.0f ,,0.0f, 0.0f, 0.0f, 1.0f -@-1.0f, 1.0f, 1.0f, 0.0f -1,0f, 1.0f, 1.0f, 1.0f ..  FLAT_SHADE"/0/  SEL_CENTROID" 0/  SEL_LINEAR"0x0  CYL_WRAP"h11PT_SPRITE_TEX"1 SEL_SAMPLE"!``"" "SPI_PS_INPUT_CNTL_7"x" SEMANTIC"%#`# DEFAULT_VAL$#0.0f, 0.0f, 0.0f, 0.0f $H$0.0f, 0.0f, 0.0f, 1.0f @%$1.0f, 1.0f, 1.0f, 0.0f %1,0f, 1.0f, 1.0f, 1.0f &8&  FLAT_SHADE"('&  SEL_CENTROID"''  SEL_LINEAR"h( (  CYL_WRAP")(PT_SPRITE_TEX"h) SEL_SAMPLE"x\\""SPI_PS_INPUT_CNTL_6h  SEMANTIC" DEFAULT_VALP0.0f, 0.0f, 0.0f, 0.0f H0.0f, 0.0f, 0.0f, 1.0f 1.0f, 1.0f, 1.0f, 0.0f 01,0f, 1.0f, 1.0f, 1.0f (  FLAT_SHADE"  SEL_CENTROID"p(  SEL_LINEAR"   CYL_WRAP" h PT_SPRITE_TEX"! SEL_SAMPLE"H XX""pSPI_PS_INPUT_CNTL_5 SEMANTIC"0h DEFAULT_VALP0.0f, 0.0f, 0.0f, 0.0f 0.0f, 0.0f, 0.0f, 1.0f 81.0f, 1.0f, 1.0f, 0.0f 1,0f, 1.0f, 1.0f, 1.0f   FLAT_SHADE"x(  SEL_CENTROID"  SEL_LINEAR"p  CYL_WRAP"`PT_SPRITE_TEX" SEL_SAMPLE"TT"" SPI_PS_INPUT_CNTL_4 h  SEMANTIC"  P DEFAULT_VAL 0.0f, 0.0f, 0.0f, 0.0f 8 0.0f, 0.0f, 0.0f, 1.0f 0 1.0f, 1.0f, 1.0f, 0.0f x 1,0f, 1.0f, 1.0f, 1.0f p (  FLAT_SHADE"  SEL_CENTROID"p  SEL_LINEAR"X  CYL_WRAP"PT_SPRITE_TEX"` SEL_SAMPLE"hPP""SPI_PS_INPUT_CNTL_3X SEMANTIC"x DEFAULT_VAL@0.0f, 0.0f, 0.0f, 0.0f 80.0f, 0.0f, 0.0f, 1.0f 1.0f, 1.0f, 1.0f, 0.0f 1,0f, 1.0f, 1.0f, 1.0f   FLAT_SHADE"p  SEL_CENTROID"`  SEL_LINEAR"  CYL_WRAP"XPT_SPRITE_TEX" SEL_SAMPLE"8LL""`SPI_PS_INPUT_CNTL_2 SEMANTIC" X DEFAULT_VAL@0.0f, 0.0f, 0.0f, 0.0f 0.0f, 0.0f, 0.0f, 1.0f (1.0f, 1.0f, 1.0f, 0.0f 1,0f, 1.0f, 1.0f, 1.0f x  FLAT_SHADE"h  SEL_CENTROID"  SEL_LINEAR"`  CYL_WRAP"PPT_SPRITE_TEX" SEL_SAMPLE"HH""SPI_PS_INPUT_CNTL_1` SEMANTIC"H DEFAULT_VAL0.0f, 0.0f, 0.0f, 0.0f 00.0f, 0.0f, 0.0f, 1.0f (1.0f, 1.0f, 1.0f, 0.0f p1,0f, 1.0f, 1.0f, 1.0f h  FLAT_SHADE"  SEL_CENTROID"h  SEL_LINEAR"P  CYL_WRAP"PT_SPRITE_TEX"P SEL_SAMPLE"XDD""SPI_PS_INPUT_CNTL_0H SEMANTIC"h DEFAULT_VAL00.0f, 0.0f, 0.0f, 0.0f (0.0f, 0.0f, 0.0f, 1.0f p1.0f, 1.0f, 1.0f, 0.0f 1,0f, 1.0f, 1.0f, 1.0f   FLAT_SHADE"`  SEL_CENTROID"P  SEL_LINEAR"  CYL_WRAP"HPT_SPRITE_TEX" SEL_SAMPLE"P88""`SPI_VS_OUT_ID_9 SEMANTIC_0"X SEMANTIC_1"@ SEMANTIC_2" SEMANTIC_3"ݲ44""SPI_VS_OUT_ID_8p SEMANTIC_0"X SEMANTIC_1" SEMANTIC_2"P SEMANTIC_3"ٲݲ00""ݲSPI_VS_OUT_ID_7p޲(޲ SEMANTIC_0"߲޲ SEMANTIC_1"߲h߲ SEMANTIC_2" SEMANTIC_3"xֲ8ڲ,,""ڲSPI_VS_OUT_ID_6(۲ڲ SEMANTIC_0"۲۲ SEMANTIC_1"hܲ ܲ SEMANTIC_2"ܲ SEMANTIC_3"0Ӳֲ((""@ײSPI_VS_OUT_ID_5ײײ SEMANTIC_0"ز8ز SEMANTIC_1" ٲز SEMANTIC_2"xٲ SEMANTIC_3"ϲӲ$$""ӲSPI_VS_OUT_ID_4ԲPԲ SEMANTIC_0"8ղԲ SEMANTIC_1"ղղ SEMANTIC_2"0ֲ SEMANTIC_3"̲`в  ""вSPI_VS_OUT_ID_3PѲѲ SEMANTIC_0"ѲѲ SEMANTIC_1"ҲHҲ SEMANTIC_2"Ҳ SEMANTIC_3"XɲͲ""hͲSPI_VS_OUT_ID_2βͲ SEMANTIC_0"β`β SEMANTIC_1"Hϲϲ SEMANTIC_2"ϲ SEMANTIC_3"Ʋɲ"" ʲSPI_VS_OUT_ID_1ʲxʲ SEMANTIC_0"`˲˲ SEMANTIC_1"̲˲ SEMANTIC_2"X̲ SEMANTIC_3" IJƲ""ƲSPI_VS_OUT_ID_0xDz0Dz SEMANTIC_0"ȲDz SEMANTIC_1"ȲpȲ SEMANTIC_2"ɲ SEMANTIC_3"²IJ""IJSQ_BOOL_CONST_2@Ų BOOLEANS"P0ò""òSQ_BOOL_CONST_1ò BOOLEANS"࿲""²SQ_BOOL_CONST_0p² BOOLEANS"@X""SQ_LOOP_CONST_DX10_0 COUNT"л""SQ_LOOP_CONST_0` COUNT"H INIT"INC"hH""SQ_VTX_START_INST_LOC OFFSET"າ""0SQ_VTX_BASE_VTX_LOC OFFSET"<<""سSQ_TEX_SAMPLER_MISC_0 x0 Z_FILTER" дLOD_USES_MINOR_AXIS"еxPOINT_SAMPLING_CLAMP"x(TEX_ARRAY_OVERRIDE" жMC_COORD_TRUNCATE"зxHIGH_PRECISION_FILTER"p(FETCH_4"ȸSAMPLE_IS_PCF"p TRUNCATE_COORD" DISABLE_CUBE_WRAP"0 88""SQ_TEX_SAMPLER_FILTER_PERF_0 ذ PERF_MIP"xPERF_Z"` ANISO_BIAS" LOD_BIAS_SEC"44""$SQ_TEX_SAMPLER_DEPTH_COMPARE_FUNC_0`DATA"P800""SQ_TEX_SAMPLER_MAX_LOD_0譲 DATA"ةȫ,,"" SQ_TEX_SAMPLER_DEGAMMA_0xDATA"`P((""SQ_TEX_SAMPLER_CHROMA_TYPE_0DATA"ب$$""8SQ_TEX_SAMPLER_BORDER_COLOR_0DATA"h  ""SQ_TEX_SAMPLER_LOD_BIAS_0 DATA"""PSQ_TEX_SAMPLER_MIN_LOD_0 DATA"""लSQ_TEX_SAMPLER_MAX_ANISO_08DATA"0""pSQ_TEX_SAMPLER_MIP_FILTER_0ȣDATA"""SQ_TEX_SAMPLER_MAG_FILTER_0XDATA"P8  ""SQ_TEX_SAMPLER_MIN_FILTER_0蠲DATA"Ȟ"" SQ_TEX_SAMPLER_CLAMP_Z_0xDATA"pX""SQ_TEX_SAMPLER_CLAMP_Y_0DATA"蛲""@SQ_TEX_SAMPLER_CLAMP_X_0DATA"0X""SQ_TEX_SAMPLER_WORD2_0 X LOD_BIAS_SEC" MC_COORD_TRUNCATE"X FORCE_DEGAMMA"XHIGH_PRECISION_FILTER" PERF_MIP"PPERF_Z"8 ANISO_BIAS"ؘFETCH_4"0SAMPLE_IS_PCF"(ؙTRUNCATE_COORD"КDISABLE_CUBE_WRAP"(TYPE"Y""SQ_TEX_SAMPLER_WORD1_0X MIN_LOD"@ MAX_LOD" LOD_BIAS"UPZ""ZSQ_TEX_SAMPLER_WORD0_0`[H[CLAMP_X[[ SQ_TEX_WRAPp\ \SQ_TEX_MIRROR8]\CSQ_TEX_CLAMP_LAST_TEXEL: [0,1] normalized, [0,dimen] unnormalized ]]'SQ_TEX_MIRROR_ONCE_LAST_TEXEL: [-1,1] ^0^DSQ_TEX_CLAMP_HALF_BORDER: [0,1] normalized, [0,dimen] unnormalized `_^(SQ_TEX_MIRROR_ONCE_HALF_BORDER: [-1,1] (`_?SQ_TEX_CLAMP_BORDER: [0,1] normalized, [0,dimen] unnormalized p`#SQ_TEX_MIRROR_ONCE_BORDER: [-1,1] f(apaCLAMP_Yba SQ_TEX_WRAPbHbSQ_TEX_MIRROR`cbCSQ_TEX_CLAMP_LAST_TEXEL: [0,1] normalized, [0,dimen] unnormalized dc'SQ_TEX_MIRROR_ONCE_LAST_TEXEL: [-1,1] dXdDSQ_TEX_CLAMP_HALF_BORDER: [0,1] normalized, [0,dimen] unnormalized e e(SQ_TEX_MIRROR_ONCE_HALF_BORDER: [-1,1] Pfe?SQ_TEX_CLAMP_BORDER: [0,1] normalized, [0,dimen] unnormalized f#SQ_TEX_MIRROR_ONCE_BORDER: [-1,1] mPggCLAMP_Z(hg SQ_TEX_WRAPhphSQ_TEX_MIRRORiiCSQ_TEX_CLAMP_LAST_TEXEL: [0,1] normalized, [0,dimen] unnormalized 8ji'SQ_TEX_MIRROR_ONCE_LAST_TEXEL: [-1,1] kjDSQ_TEX_CLAMP_HALF_BORDER: [0,1] normalized, [0,dimen] unnormalized kHk(SQ_TEX_MIRROR_ONCE_HALF_BORDER: [-1,1] xlk?SQ_TEX_CLAMP_BORDER: [0,1] normalized, [0,dimen] unnormalized l#SQ_TEX_MIRROR_ONCE_BORDER: [-1,1] prxm mXY_MAG_FILTERhnnSQ_TEX_XY_FILTER_POINTonSQ_TEX_XY_FILTER_BILINEARoPoSQ_TEX_XY_FILTER_BICUBICxpoESQ_TEX_XY_FILTER_CLEARTYPE: special filter available for FMT_1 only qpSQ_TEX_XY_FILTER_ANISO_POINTqhq SQ_TEX_XY_FILTER_ANISO_BILINEARrSQ_TEX_XY_FILTER_ANISO_BICUBICwr sXY_MIN_FILTERs`sSQ_TEX_XY_FILTER_POINTXttSQ_TEX_XY_FILTER_BILINEARttSQ_TEX_XY_FILTER_BICUBICu@uESQ_TEX_XY_FILTER_CLEARTYPE: special filter available for FMT_1 only pvvSQ_TEX_XY_FILTER_ANISO_POINTwv SQ_TEX_XY_FILTER_ANISO_BILINEAR`wSQ_TEX_XY_FILTER_ANISO_BICUBIC@zx`x Z_FILTERyxSQ_TEX_Z_FILTER_NONEyHySQ_TEX_Z_FILTER_POINTySQ_TEX_Z_FILTER_LINEAR|zz MIP_FILTER{({SQ_TEX_Z_FILTER_NONE |{SQ_TEX_Z_FILTER_POINTh|SQ_TEX_Z_FILTER_LINEAR؀}h}MAX_ANISO_RATIO~}(SQ_TEX_ANISO_RATIO_1: max ratio 1 to 1 ~`~(SQ_TEX_ANISO_RATIO_2: max ratio 2 to 1 x(SQ_TEX_ANISO_RATIO_4: max ratio 4 to 1 ((SQ_TEX_ANISO_RATIO_8: max ratio 8 to 1 p*SQ_TEX_ANISO_RATIO_16: max ratio 16 to 1 0BORDER_COLOR_TYPE@ȁ7SQ_TEX_BORDER_COLOR_TRANS_BLACK: (0.0, 0.0, 0.0, 0.0) 8SQ_TEX_BORDER_COLOR_OPAQUE_BLACK: (0.0, 0.0, 0.0, 1.0) H8SQ_TEX_BORDER_COLOR_OPAQUE_WHITE: (1.0, 1.0, 1.0, 1.0) 7SQ_TEX_BORDER_COLOR_REGISTER: use BORDER_COLOR_[XYZW] 0؄POINT_SAMPLING_CLAMP"؅TEX_ARRAY_OVERRIDE"0DEPTH_COMPARE_FUNCTION8І&SQ_TEX_DEPTH_COMPARE_NEVER: always 0 ;SQ_TEX_DEPTH_COMPARE_LESS: 1 if incoming Z < fetched data @=SQ_TEX_DEPTH_COMPARE_EQUAL: 1 if incoming Z == fetched data ASQ_TEX_DEPTH_COMPARE_LESSEQUAL: 1 if incoming Z <= fetched data PЉ>SQ_TEX_DEPTH_COMPARE_GREATER: 1 if incoming Z > fetched data @SQ_TEX_DEPTH_COMPARE_NOTEQUAL: 1 if incoming Z != fetched data `DSQ_TEX_DEPTH_COMPARE_GREATEREQUAL: 1 if incoming Z >= fetched data ('SQ_TEX_DEPTH_COMPARE_ALWAYS: always 1 茲0 CHROMA_KEY荲x.SQ_TEX_CHROMA_KEY_DISABLED: no chroma keying 0PSQ_TEX_CHROMA_KEY_KILL: returns negative value if any texel matches chroma key DSQ_TEX_CHROMA_KEY_BLEND: sets matching texels to 0 before blending LOD_USES_MINOR_AXIS"S`V""VSQ_VTX_CONSTANT_WORD6_0WXWTYPEWWSQ_TEX_VTX_INVALID_TEXTUREX@XSQ_TEX_VTX_INVALID_BUFFER8YXSQ_TEX_VTX_VALID_TEXTUREYSQ_TEX_VTX_VALID_BUFFER0DHT  ""TSQ_VTX_CONSTANT_WORD3_0HUTMEM_REQUEST_SIZE"U UNCACHED"BD""ESQ_VTX_CONSTANT_WORD2_0EXEBASE_ADDRESS_HI"HFF STRIDE"XHFFCLAMP_XG0G0SQ_VTX_CLAMP_ZERO: clamp to zero (0x00000000). G.SQ_VTX_CLAMP_NAN: clamp to NaN (0xffc00000). HH DATA_FORMAT"xLPIINUM_FORMAT_ALLJIjSQ_NUM_FORMAT_NORM: repeating fraction number (0.N) with range [0, 1] if unsigned, or [-1, 1] if signed. KJpSQ_NUM_FORMAT_INT: integer number (N.0) with range [0, 2^N] if unsigned, or [-2^M, 2^M] if signed (M = N - 1). KiSQ_NUM_FORMAT_SCALED: integer number stored as a S23E8 floating-point representation (1 == 0x3f800000). `NL MFORMAT_COMP_ALLMhMSQ_FORMAT_COMP_UNSIGNED NSQ_FORMAT_COMP_SIGNED PNO SRF_MODE_ALLPPOuSQ_SRF_MODE_ZERO_CLAMP_MINUS_ONE: representation with two -1 representations (one is slightly past -1 but clamped). PPBSQ_SRF_MODE_NO_ZERO: OpenGL format lacking representation for 0. (QpQ ENDIAN_SWAP RQ+SQ_ENDIAN_NONE: no endian swap (XOR by 0) RhRMSQ_ENDIAN_8IN16: 8 bit swap in 16 bit word (XOR by 1): AABBCCDD -> BBAADDCC @SMSQ_ENDIAN_8IN32: 8 bit swap in 32 bit word (XOR by 3): AABBCCDD -> DDCCBBAA HA8C""CSQ_VTX_CONSTANT_WORD1_0C SIZE"3A""BSQ_VTX_CONSTANT_WORD0_0pB BASE_ADDRESS"-(4""4SQ_TEX_RESOURCE_WORD6_0x74 5 MPEG_CLAMP5h5SSQ_TEX_MPEG_CLAMP_OFF: no clamping (FMT_16 is plain 16b fixed/normalized number). 6@6KSQ_TEX_MPEG_9: consider FMT_16 as s9 in LSBs, clamp range to [-256, 255). 7+SQ_TEX_MPEG_10: mask bottom 6b of FMT_16. ;7 8MAX_ANISO_RATIO8h8(SQ_TEX_ANISO_RATIO_1: max ratio 1 to 1 99(SQ_TEX_ANISO_RATIO_2: max ratio 2 to 1 0:9(SQ_TEX_ANISO_RATIO_4: max ratio 4 to 1 :x:(SQ_TEX_ANISO_RATIO_8: max ratio 8 to 1 (;*SQ_TEX_ANISO_RATIO_16: max ratio 16 to 1 8<;PERF_MODULATION"<< INTERLACED"=0= ADVIS_FAULT_LOD"(>= ADVIS_CLAMP_LOD">>TYPEh??SQ_TEX_VTX_INVALID_TEXTURE@?SQ_TEX_VTX_INVALID_BUFFER@P@SQ_TEX_VTX_VALID_TEXTURE@SQ_TEX_VTX_VALID_BUFFER`H."".SQ_TEX_RESOURCE_WORD5_0@/. LAST_LEVEL"// BASE_ARRAY"080 LAST_ARRAY"0 1 YUV_CONV1h1$SQ_TEX_YUV_OFF: no YUV conversion. 22iSQ_TEX_YUV_RGB_CLAMP: YUV to RGB conversion with clamping (FMT_8_8_8_8, FMG_GB_GR, and FMT_BG_RB only). 3nSQ_TEX_YUB_RGB_NOCLAMP: YUV to RGB conversion without clamping (FMT_8_8_8_8, FMG_GB_GR, and FMT_BG_RB only). ""0SQ_TEX_RESOURCE_WORD4_0 FORMAT_COMP_Xx SQ_FORMAT_COMP_UNSIGNED  SQ_FORMAT_COMP_SIGNED `  SQ_FORMAT_COMP_UNSIGNED_BIASED P  h FORMAT_COMP_Y SQ_FORMAT_COMP_UNSIGNED P SQ_FORMAT_COMP_SIGNED  SQ_FORMAT_COMP_UNSIGNED_BIASED   FORMAT_COMP_Z @ SQ_FORMAT_COMP_UNSIGNED 8 SQ_FORMAT_COMP_SIGNED  SQ_FORMAT_COMP_UNSIGNED_BIASED p8FORMAT_COMP_W(SQ_FORMAT_COMP_UNSIGNED pSQ_FORMAT_COMP_SIGNED  SQ_FORMAT_COMP_UNSIGNED_BIASED NUM_FORMAT_ALL`jSQ_NUM_FORMAT_NORM: repeating fraction number (0.N) with range [0, 1] if unsigned, or [-1, 1] if signed. PpSQ_NUM_FORMAT_INT: integer number (N.0) with range [0, 2^N] if unsigned, or [-2^M, 2^M] if signed (M = N - 1). HiSQ_NUM_FORMAT_SCALED: integer number stored as a S23E8 floating-point representation (1 == 0x3f800000). `H  SRF_MODE_ALLuSQ_SRF_MODE_ZERO_CLAMP_MINUS_ONE: representation with two -1 representations (one is slightly past -1 but clamped). BSQ_SRF_MODE_NO_ZERO: OpenGL format lacking representation for 0.  FORCE_DEGAMMA"`  ENDIAN_SWAPX+SQ_ENDIAN_NONE: no endian swap (XOR by 0) 0MSQ_ENDIAN_8IN16: 8 bit swap in 16 bit word (XOR by 1): AABBCCDD -> BBAADDCC xMSQ_ENDIAN_8IN32: 8 bit swap in 32 bit word (XOR by 3): AABBCCDD -> DDCCBBAA ` REQUEST_SIZE" P DST_SEL_XSQ_SEL_X: use X component 8SQ_SEL_Y: use Y component 0SQ_SEL_Z: use Z component xSQ_SEL_W: use W component pSQ_SEL_0: use constant 0.0 SQ_SEL_1: use constant 1.0 p$h  DST_SEL_YP! SQ_SEL_X: use X component !!SQ_SEL_Y: use Y component "8"SQ_SEL_Z: use Z component 0#"SQ_SEL_W: use W component #x#SQ_SEL_0: use constant 0.0 $SQ_SEL_1: use constant 1.0 ($% DST_SEL_Z%X%SQ_SEL_X: use X component P&%SQ_SEL_Y: use Y component &&SQ_SEL_Z: use Z component '8'SQ_SEL_W: use W component 0('SQ_SEL_0: use constant 0.0 x(SQ_SEL_1: use constant 1.0 0-()p) DST_SEL_W*)SQ_SEL_X: use X component *X*SQ_SEL_Y: use Y component P+*SQ_SEL_Z: use Z component ++SQ_SEL_W: use W component ,8,SQ_SEL_0: use constant 0.0 ,SQ_SEL_1: use constant 1.0 - BASE_LEVEL"xh  ""SQ_TEX_RESOURCE_WORD3_0 MIP_ADDRESS"""HSQ_TEX_RESOURCE_WORD2_0 BASE_ADDRESS"@""SQ_TEX_RESOURCE_WORD1_08 TEX_HEIGHT" TEX_DEPTH"0 DATA_FORMAT"""SQ_TEX_RESOURCE_WORD0_0H@DIMSQ_TEX_DIM_1D`SQ_TEX_DIM_2DHSQ_TEX_DIM_3DSQ_TEX_DIM_CUBEMAPx(SQ_TEX_DIM_1D_ARRAYSQ_TEX_DIM_2D_ARRAYXSQ_TEX_DIM_2D_MSAASQ_TEX_DIM_2D_ARRAY_MSAA TILE_MODE"@ TILE_TYPE"( PITCH" TEX_WIDTH"X0  ""SQ_ALU_CONSTANT3_0 W""" SQ_ALU_CONSTANT2_0x Z"p""SQ_ALU_CONSTANT1_0 Y" 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DATA"ͱϱ""0бSQ_ALU_CONST_BUFFER_SIZE_VS_8б DATA"ẖXα""αSQ_ALU_CONST_BUFFER_SIZE_VS_7ϱ DATA"ʱ̱""@ͱSQ_ALU_CONST_BUFFER_SIZE_VS_6ͱ DATA"xɱh˱""˱SQ_ALU_CONST_BUFFER_SIZE_VS_5 ̱ DATA"ȱɱ""PʱSQ_ALU_CONST_BUFFER_SIZE_VS_4ʱ DATA"Ʊxȱ""ȱSQ_ALU_CONST_BUFFER_SIZE_VS_30ɱ DATA"űDZ""`DZSQ_ALU_CONST_BUFFER_SIZE_VS_2DZ DATA"ñű""űSQ_ALU_CONST_BUFFER_SIZE_VS_1@Ʊ DATA" ±ı""pıSQ_ALU_CONST_BUFFER_SIZE_VS_0ı DATA"±||""±SQ_ALU_CONST_BUFFER_SIZE_PS_15Pñ DATA"( xx""SQ_ALU_CONST_BUFFER_SIZE_PS_14 DATA"tt""SQ_ALU_CONST_BUFFER_SIZE_PS_13` DATA"8(pp""SQ_ALU_CONST_BUFFER_SIZE_PS_12ྱ DATA"ll""SQ_ALU_CONST_BUFFER_SIZE_PS_11h DATA"H8hh""SQ_ALU_CONST_BUFFER_SIZE_PS_10 DATA"зdd"" SQ_ALU_CONST_BUFFER_SIZE_PS_9x DATA"XH``""SQ_ALU_CONST_BUFFER_SIZE_PS_8 DATA"റж\\""0SQ_ALU_CONST_BUFFER_SIZE_PS_7 DATA"hXXX""SQ_ALU_CONST_BUFFER_SIZE_PS_6 DATA"ೱTT""@SQ_ALU_CONST_BUFFER_SIZE_PS_5 DATA"xhPP""ȲSQ_ALU_CONST_BUFFER_SIZE_PS_4 DATA"LL""PSQ_ALU_CONST_BUFFER_SIZE_PS_3 DATA"xHH""دSQ_ALU_CONST_BUFFER_SIZE_PS_20 DATA"DD""`SQ_ALU_CONST_BUFFER_SIZE_PS_1 DATA"@@""謱SQ_ALU_CONST_BUFFER_SIZE_PS_0@ DATA"0""pSQ_ALU_CONST_CACHE_GS_15ȫ DATA"""SQ_ALU_CONST_CACHE_GS_14X DATA"P8""SQ_ALU_CONST_CACHE_GS_13許 DATA"ऱȦ"" SQ_ALU_CONST_CACHE_GS_12x DATA"pX""SQ_ALU_CONST_CACHE_GS_11 DATA"裱""@SQ_ALU_CONST_CACHE_GS_10 DATA"x""ТSQ_ALU_CONST_CACHE_GS_9( DATA" ""`SQ_ALU_CONST_CACHE_GS_8 DATA"܉܉""SQ_ALU_CONST_CACHE_GS_7H DATA"@(؉؉""SQ_ALU_CONST_CACHE_GS_6؞ DATA"Кԉԉ""SQ_ALU_CONST_CACHE_GS_5h DATA"`HЉЉ""SQ_ALU_CONST_CACHE_GS_4 DATA"ؙ̉̉""0SQ_ALU_CONST_CACHE_GS_3 DATA"hȉȉ""SQ_ALU_CONST_CACHE_GS_2 DATA"ĉĉ""PSQ_ALU_CONST_CACHE_GS_1 DATA"""SQ_ALU_CONST_CACHE_GS_08 DATA"0""pSQ_ALU_CONST_CACHE_VS_15Ȕ DATA"""SQ_ALU_CONST_CACHE_VS_14X DATA"P8""SQ_ALU_CONST_CACHE_VS_13葱 DATA"ȏ"" SQ_ALU_CONST_CACHE_VS_12x DATA"pX""SQ_ALU_CONST_CACHE_VS_11 DATA"茱""@SQ_ALU_CONST_CACHE_VS_10 DATA"x""ЋSQ_ALU_CONST_CACHE_VS_9( DATA" ""`SQ_ALU_CONST_CACHE_VS_8 DATA"""SQ_ALU_CONST_CACHE_VS_7H DATA"@(""SQ_ALU_CONST_CACHE_VS_6؇ DATA"Ѓ""SQ_ALU_CONST_CACHE_VS_5h DATA"`H""SQ_ALU_CONST_CACHE_VS_4 DATA"؂""0SQ_ALU_CONST_CACHE_VS_3 DATA"h""SQ_ALU_CONST_CACHE_VS_2 DATA"~""PSQ_ALU_CONST_CACHE_VS_1 DATA"|~""~SQ_ALU_CONST_CACHE_VS_08 DATA"0{}||""p}SQ_ALU_CONST_CACHE_PS_15} DATA"y{xx""|SQ_ALU_CONST_CACHE_PS_14X| DATA"Px8ztt""zSQ_ALU_CONST_CACHE_PS_13z DATA"vxpp"" ySQ_ALU_CONST_CACHE_PS_12xy DATA"puXwll""wSQ_ALU_CONST_CACHE_PS_11x DATA"tuhh""@vSQ_ALU_CONST_CACHE_PS_10v DATA"rxtdd""tSQ_ALU_CONST_CACHE_PS_9(u DATA" qs``""`sSQ_ALU_CONST_CACHE_PS_8s DATA"oq\\""qSQ_ALU_CONST_CACHE_PS_7Hr DATA"@n(pXX""pSQ_ALU_CONST_CACHE_PS_6p DATA"lnTT""oSQ_ALU_CONST_CACHE_PS_5ho DATA"`kHmPP""mSQ_ALU_CONST_CACHE_PS_4m DATA"ikLL""0lSQ_ALU_CONST_CACHE_PS_3l DATA"hhjHH""jSQ_ALU_CONST_CACHE_PS_2k DATA"ghDD""PiSQ_ALU_CONST_CACHE_PS_1i DATA"@fg@@""gSQ_ALU_CONST_CACHE_PS_08h DATA"pef """SQ_ALU_DEBUG_BUS_SQA3_SIMD3de """SQ_ALU_DEBUG_BUS_SQA3_SIMD2ce """SQ_ALU_DEBUG_BUS_SQA3_SIMD1cHd """SQ_ALU_DEBUG_BUS_SQA3_SIMD00bxc """SQ_ALU_DEBUG_BUS_SQA3_CA1`ab """SQ_ALU_DEBUG_BUS_SQA3_CA0`a """SQ_ALU_DEBUG_BUS_SQA3_TOP_a """SQ_ALU_DEBUG_BUS_SQA3_BLOCK_ID^0` """SQ_ALU_DEBUG_BUS_SQA2_SIMD3^`_ """SQ_ALU_DEBUG_BUS_SQA2_SIMD2H]^ """SQ_ALU_DEBUG_BUS_SQA2_SIMD1x\] """SQ_ALU_DEBUG_BUS_SQA2_SIMD0[\ """SQ_ALU_DEBUG_BUS_SQA2_CA1Z \ """SQ_ALU_DEBUG_BUS_SQA2_CA0ZP[ """SQ_ALU_DEBUG_BUS_SQA2_TOP0YxZ """SQ_ALU_DEBUG_BUS_SQA2_BLOCK_ID`XY """SQ_ALU_DEBUG_BUS_SQA1_SIMD3WX """SQ_ALU_DEBUG_BUS_SQA1_SIMD2VX """SQ_ALU_DEBUG_BUS_SQA1_SIMD1U8W """SQ_ALU_DEBUG_BUS_SQA1_SIMD0 UhV """SQ_ALU_DEBUG_BUS_SQA1_CA1PTU """SQ_ALU_DEBUG_BUS_SQA1_CA0xST """SQ_ALU_DEBUG_BUS_SQA1_TOPRS """SQ_ALU_DEBUG_BUS_SQA1_BLOCK_IDQ S """SQ_ALU_DEBUG_BUS_SQA0_SIMD3QPR """SQ_ALU_DEBUG_BUS_SQA0_SIMD28PQ """SQ_ALU_DEBUG_BUS_SQA0_SIMD1hOP """SQ_ALU_DEBUG_BUS_SQA0_SIMD0NO """SQ_ALU_DEBUG_BUS_SQA0_CA1MO """SQ_ALU_DEBUG_BUS_SQA0_CA0L@N """SQ_ALU_DEBUG_BUS_SQA0_TOPBhM """SQ_ALU_DEBUG_BUS_SQA0_BLOCK_IDH<0C """CSQ_DEBUG_BUS_TM DCSQ_BCD"DxDVGT_BCD"`EE GRBM_REG_OP"FEGRBM_REG_SEND"F`F WR_FC_LOOP"HGG WR_FC_CONST"GGWR_FC_SAMPLER"HHH WR_FC_RSRC"0IH WR_FC_BASE"II HOLD5"pJ(J HOLD4"KJ HOLD3"KhK HOLD2"PLL HOLD1"LHOLD0";< """=SQ_DEBUG_BUS_EX =h= SMX_BUF_STS"P>> PIX_BUF_STS">> PC_BUF_STS"?H? POS_BUF_STS"8@?INST_THREAD_ID"@@ INST_SMX"xA0A INST_VLD"BA AUTO_TYPE"pB AUTO_VLD":; """SQ_DEBUG_BUS_CA_290; """SQ_DEBUG_BUS_unused(9h: """SQ_DEBUG_BUS_TV_2`89 """SQ_DEBUG_BUS_CA_178 """SQ_DEBUG_BUS_TV_168 """SQ_DEBUG_BUS_TV_06H7 """SQ_DEBUG_BUS_ALU3_1@56 """SQ_DEBUG_BUS_ALU3_0x45 """SQ_DEBUG_BUS_ALU2_134 """SQ_DEBUG_BUS_ALU2_02(4 """SQ_DEBUG_BUS_ALU1_1 2`3 """SQ_DEBUG_BUS_ALU1_0X12 """SQ_DEBUG_BUS_ALU0_101 """SQ_DEBUG_BUS_ALU0_0/1 """SQ_DEBUG_BUS_CORE_5/@0 """SQ_DEBUG_BUS_CORE_48.x/ """SQ_DEBUG_BUS_CORE_3p-. """SQ_DEBUG_BUS_CORE_2,- """SQ_DEBUG_BUS_CORE_1@+ - """SQ_DEBUG_BUS_CORE_0x+ """,SQ_DEBUG_BUS_MS_2`, ALU_BUSY2"X """@ SQ_DEBUG_BUS_MS_1 BUSY_PS"!8!BUSY_VS" "!BUSY_GS""x"BUSY_ES"`##TF_BUSY"$#VF_BUSY"$X$EX_BUSY"@%$ SMX_BUSY"%%CA_BUSY"&8& DONE_FIFO_STALL"8'& ALU_UPDATE_FIFO_STALL"'' FETCH_FIFO_STALL"(8( SX_EVENT_FIFO_FULL_PS"@)( SX_EVENT_FIFO_FULL_VS"))SX_EVENT_FIFO_FULL_GS"*H*SX_EVENT_FIFO_FULL_ES"* ALU_BUSY" """ SQ_DEBUG_BUS_MS_0 x ALU_FULL"`TF_FULL" VF_FULL"X EX_FULL"@  SMX_FULL" CA_FULL"8 POS_ALLOC_BUSY"0PARAM_ALLOC_BUSY"PIX_ALLOC_BUSY"0 ALU_FULL2" h """SQ_DEBUG_BUS_TOP_5`SH_MC_RDREQ_FREE"SH_MC_RDREQ_SEND"`MC_SH_RDRET_VLD"CA_DBG_MEM_BUS"  """h SQ_DEBUG_BUS_TOP_4  CP_SH_SYNC_CLEAN"hCP_SH_SYNC_START"p SH_SX_ALLOC_FREE_ALLOCTABLE_SMX"( SH_SX_ALLOC_FREE_ALLOCTABLE_POS" SH_SX_ALLOC_FREE_ALLOCTABLE_COL"8SH_SX_ALLOC_FREE_SMX"@SH_SX_ALLOC_FREE_POS"SH_SX_ALLOC_FREE_COL"HSH_SX_EVENT_TYPE"HSH_SX_EVENT_THREAD_TYPE"SH_SX_EVENT_SEND"(` """SQ_DEBUG_BUS_TOP_3X  SH_SX_EXPORT_TID" SH_SX_EXPORT_TYPE" X SH_SX_EXPORT_VALID"P SH_SX_ALLOC_TID" SH_SX_ALLOC_TYPE"P SH_SX_ALLOC_SEND" """SQ_DEBUG_BUS_TOP_2HSMX_SH_RDDONE_TID"@ SMX_SH_RDDONE_VALID"SH_SMX_SYNC_PHASE_1"8 """SQ_DEBUG_BUS_TOP_1 0VC_SH_RDDONE_TID"VC_SH_RDDONE_VALID"0 SH_VC_CMD_INDEX_FREE"8 SH_VC_CMD_INSTR_FREE" SH_VC_CMD_SEND"8 TD_SH_RDDONE_TID"0TD_SH_RDDONE_VALID"SH_TA_CMD_FREE"0SH_TA_CMD_SEND"SH_VC_SYNC_PHASE_1"  """pSQ_DEBUG_BUS_TOP_0SH_GRBM_STAT_BUSY"p EX_MS_BUSY"`SH_VGT_VSFETCH_DONE"SH_VGT_GSFETCH_DONE"`SH_VGT_GSCNT_OP"XSH_VGT_GSCNT_VALID"SH_SPI_DONE_THREAD_TYPE"` SH_SPI_DONE_IS_EVENT"` SH_SPI_DONE_VALID" SPI_SH_PCDEALLOC_CNT"hSPI_SH_PCDEALLOC_VALID"hSPI_SH_THREAD_TYPE"SPI_SH_THREAD_IS_EVENT"pSPI_SH_THREAD_VALID"X """SQ_DEBUG_BUS_CA_0X""SQ_DEBUG_STS_MS_PC_1HPC"TID"X""SQ_DEBUG_STS_MS_PC_0HPC"TID"@̍̍""`SQ_DYN_GPR_SIZE_SIMD_AB_7 SIMDA_RING0"X SIMDA_RING1"@ SIMDB_RING0" SIMDB_RING1"ȍȍ""SQ_DYN_GPR_SIZE_SIMD_AB_6h SIMDA_RING0"P SIMDA_RING1" SIMDB_RING0"H SIMDB_RING1"hčč""SQ_DYN_GPR_SIZE_SIMD_AB_5` SIMDA_RING0" SIMDA_RING1"X SIMDB_RING0" SIMDB_RING1"Pް""pSQ_DYN_GPR_SIZE_SIMD_AB_4 SIMDA_RING0"h SIMDA_RING1"P SIMDB_RING0" SIMDB_RING1"۰ް"" ߰SQ_DYN_GPR_SIZE_SIMD_AB_3߰x߰ SIMDA_RING0"` SIMDA_RING1" SIMDB_RING0"X SIMDB_RING1"װx۰""۰SQ_DYN_GPR_SIZE_SIMD_AB_2pܰ(ܰ SIMDA_RING0"ݰܰ SIMDA_RING1"ݰhݰ SIMDB_RING0"ް SIMDB_RING1"`԰(ذ""ذSQ_DYN_GPR_SIZE_SIMD_AB_1 ٰذ SIMDA_RING0"ٰxٰ SIMDA_RING1"`ڰڰ SIMDB_RING0"ڰ SIMDB_RING1"Ұ԰""0հSQ_DYN_GPR_SIZE_SIMD_AB_0հհ SIMDA_RING0"pְ(ְ SIMDA_RING1"װְ SIMDB_RING0"hװ SIMDB_RING1"ѰhӰ""ӰSQ_DYN_GPR_ES_SIMD_ENABLE԰ ACTIVE_SIMD"аѰ""PҰSQ_DYN_GPR_GS_SIMD_ENABLEҰ ACTIVE_SIMD"ΰа""аSQ_DYN_GPR_VS_SIMD_ENABLE8Ѱ ACTIVE_SIMD"˰ϰ""pϰSQ_DYN_GPR_PS_SIMD_ENABLEϰ ACTIVE_SIMD"ǰP̰""̰SQ_DYN_GPR_THREAD_LIMITPͰͰVS_THREAD_LIMIT"ͰͰ GS_THREAD_LIMIT"PΰES_THREAD_LIMIT"@Ȱ""ȰSQ_DYN_GPR_RING1_PRIORITY@ɰȰTHRESHOLD_ENABLE"ɰɰVS_LOW_THRESHOLD"ʰ@ʰGS_LOW_THRESHOLD"8˰ʰ ES_LOW_THRESHOLD"˰ VS_PC_LIMIT"p""ȽSQ_DYN_GPR_OPTIMIZATIONp R0_MIN_LEVEL_ENABLE"ȾR1_MIN_LEVEL_ENABLE"pPS_SKIP_SIMD_ENABLE"hVS_SKIP_SIMD_ENABLE"GS_SKIP_SIMD_ENABLE"hES_SKIP_SIMD_ENABLE"h°°PS_WRAP_SOONER_ENABLE"ð°VS_WRAP_SOONER_ENABLE"ðpðGS_WRAP_SOONER_ENABLE"xİ İ ES_WRAP_SOONER_ENABLE"(Űİ PS_DISABLE_LAST_SENT"ŰŰPS_WRAP_SOONER_MULT"xư(ưVS_WRAP_SOONER_MULT" ǰưGS_WRAP_SOONER_MULT"xǰES_WRAP_SOONER_MULT"8""XSQ_DYN_GPR_CNTL_PS_FLUSH_REQ RING0_OFFSET"X ISOLATE_ES_ENABLE"P ISOLATE_GS_ENABLE"VS_PC_LIMIT_ENABLE"||""SQ_DEBUG_TA_CREDIT3X TA12_CREDIT"@ TA13_CREDIT"ะ TA14_CREDIT"8 TA15_CREDIT"hxx""SQ_DEBUG_TA_CREDIT2X TA8_CREDIT" TA9_CREDIT"P TA10_CREDIT" TA11_CREDIT"` tt""pSQ_DEBUG_TA_CREDIT1Ȱ TA4_CREDIT"h TA5_CREDIT"P TA6_CREDIT" TA7_CREDIT"0جpp""(SQ_DEBUG_TA_CREDIT0ȭ TA0_CREDIT"h  TA1_CREDIT" TA2_CREDIT"` TA3_CREDIT"ll""SQ_DEBUG_STS_THREAD_LVLXPS"0VS"ȫGS" ES"hh""ৰSQ_DEBUG_STS38VC_INST_CREDIT"ਰVC_INDX_CREDIT"H(dd""xSQ_DEBUG_STS2 РSX_SMX_AT_FREE_CNT"ȡxSX_SMX_BUF_FREE_CNT"p SX_PC_BUF_FREE_CNT" ȢNEW_THR_PIX_FIFO_EMPTY"УxNEW_THR_POS_FIFO_EMPTY"(NEW_THR_PC_FIFO_EMPTY"(ؤMS_OFIFO_BUSY"إMS_SX_EVENT_FIFO_BUSY"x0EX_BUSY"ЦSH_BUSY"``""SQ_DEBUG_STS1hSX_PIX_AT_FREE_CNT"`SX_PIX_BUF_FREE_CNT"SX_POS_AT_FREE_CNT"`SX_POS_BUF_FREE_CNT"蒰pXX""CGTT_SQ_CLK_CTRL ` ON_DELAY"OFF_HYSTERESIS"`SOFT_OVERRIDE7"XSOFT_OVERRIDE6"SOFT_OVERRIDE5"XSOFT_OVERRIDE4"PSOFT_OVERRIDE3"SOFT_OVERRIDE2"PSOFT_OVERRIDE1"SOFT_OVERRIDE0"`TT""SQ_CURRENT_CONTEXTXCURRENT_CONTEXT" RESERVED"PP""HSQ_TEX_STREAM FLUSH_CAM"LL""SQ_PERF_CTR7_HI_DIRECT8 COUNT"0DD""pSQ_PERF_CTR6_HI_DIRECTȏ COUNT"<<""SQ_PERF_CTR5_HI_DIRECTX COUNT"P844""SQ_PERF_CTR4_HI_DIRECT茰 COUNT"Ȋ,,"" SQ_PERF_CTR3_HI_DIRECTx COUNT"pX$$""SQ_PERF_CTR2_HI_DIRECT COUNT"臰""@SQ_PERF_CTR1_HI_DIRECT COUNT"x""ІSQ_PERF_CTR0_HI_DIRECT( COUNT" HH""`SQ_PERF_CTR7_LO_DIRECT COUNT"@@""SQ_PERF_CTR6_LO_DIRECTH COUNT"@(88""SQ_PERF_CTR5_LO_DIRECT؂ COUNT"~00""SQ_PERF_CTR4_LO_DIRECTh COUNT"`}H((""SQ_PERF_CTR3_LO_DIRECT COUNT"{} ""0~SQ_PERF_CTR2_LO_DIRECT~ COUNT"zh|""|SQ_PERF_CTR1_LO_DIRECT} COUNT"sz""P{SQ_PERF_CTR0_LO_DIRECT{ COUNT"8pHt""tSQ_DEBUG_STS0 @utALU_IF_FIFO_FULL"uuCONSTANT_CACHE_OVERLAP"vHvMAX_SQ_STATES"@wv SQ_64STATE_OVFL"ww UPDATE_PS_BUSY"x@x UPDATE_ANY_BUSY"8yxMAX_PC_EXCEEDED"yyCLAUSE_START_MINI"8z DF_OVERFLOW"np""q SQ_PERF_CF_INST_CHECKPOINT_CTRLhqq THREAD_TYPE8rqPS rrVS HssGS sES E8o""o SQ_PERF_CF_INST_CHECKPOINT_ADDRoADDR"XF܌܌""FSQ_PERF_CTR7_SEL_G@GSELHGRSQ_PERF_SEL_NONE: don't count anything Deterministic. Should be select value 0. H`HWSQ_PERF_SEL_CYCLES: Clock cycles. Thread-type independent. Should be select value 1. J@ISQ_PERF_SEL_BUSY_CYCLES: Clock cycles while SQ is reporting that it is busy. Thread-type independent. Should be select value 2. KHJSQ_PERF_SEL_ANY_BUSY_PER_TYPE: Number of cycles we have a thread or an event. Thread-type dependent. Should be select value 3. LPKSQ_PERF_SEL_EVENTS_PER_TYPE: Number of events. Thread-type dependent. Caveat: Event counts are slightly unpredictable because they don't have an associated state and because we don't count events when we don't have acitve threads. Should be select value 4. MLuSQ_PERF_SEL_EVENTS_BUSY_PER_TYPE: Number cycles we have an event. Thread-type dependent. Should be select value 5. NMSQ_PERF_SEL_EVENT_LEVEL_PER_TYPE: Number of events in the pipeline per clock. Thread-type dependent. Should be select value 6. ONSQ_PERF_SEL_ITEMS_PER_TYPE: Number of valid items per thread. Thread-type dependent. Deterministic. Should be select value 7. POSQ_PERF_SEL_ITEMS_GT_48_PER_TYPE: Number of threads with a valid item in a position >= 48. Thread-type dependent. Deterministic. Should be select value 8. QQ SQ_PERF_SEL_ITEMS_GT_32_PER_TYPE: Number of threads with a valid item in a position >= 32. Thread-type dependent. Deterministic. Should be select value 9. S8R SQ_PERF_SEL_ITEMS_GT_16_PER_TYPE: Number of threads with a valid item in a position >= 16. Thread-type dependent. Deterministic. Should be select value 10. T`S nSQ_PERF_SEL_QUADS: Number of valid pixel shader quads per thread. Deterministic. Should be select value 11. UXT wSQ_PERF_SEL_THREADS_BUSY_PER_TYPE: Number cycles we have a thread. Thread-type dependent. Should be select value 12. VXU tSQ_PERF_SEL_THREADS_PER_TYPE: Number of threads. Thread-type dependent. Deterministic Should be select value 13. WPVSQ_PERF_SEL_THREAD_LEVEL_PER_TYPE: Number of threads in the pipeline per clock. Thread-type dependent. Should be select value 14. XXWSQ_PERF_SEL_THREAD_LEVEL_WAIT_CREATE_PER_TYPE: Number of threads waiting to be created. Thread-type dependent. Should be select value 15. @YhXSQ_PERF_SEL_THREAD_LEVEL_UNALLOC_PARAM_PER_TYPE: Number of threads with parameter cache unallocated. Thread-type dependent. Should be select value 16. XZYSQ_PERF_SEL_THREAD_LEVEL_UNALLOC_PIX_PER_TYPE: Number of threads with pixel buffer unallocated. Thread-type dependent. Should be select value 17. x[ZSQ_PERF_SEL_THREAD_LEVEL_UNALLOC_POS_PER_TYPE: Number of threads with position buffer unallocated. Thread-type dependent. Should be select value 18. \[SQ_PERF_SEL_THREADS_NONPS: Number of existing non-PS threads sharing the set of enabled thread-types with other selected NONPS counters. Should be select value 19. ]\SQ_PERF_SEL_THREAD_LEVEL_NONPS: Number of existing non-PS threads per cycle sharing the set of enabled thread-types with other selected NONPS counters. Should be select value 20. @_(^SQ_PERF_SEL_THREAD_LEVEL_WAIT_ALLOC_NONPS: Number of non-PS threads waiting for export space to be allocated. Must share the set of enabled thread-types with other selected NONPS counters. Should be select value 21. `_SQ_PERF_SEL_THREAD_LEVEL_WAIT_OTHER_NONPS: Number of non-PS threads waiting for instructions to be fetched or completed. Must share the set of enabled thread-types with other selected SHARED_TYPESET counters. Should be select value 22. aaSQ_PERF_SEL_THREAD_LEVEL_WAIT_ALLOC_PS: Number of PS threads waiting for pixel buffer to be allocated. Should be select value 23. bbSQ_PERF_SEL_THREAD_LEVEL_WAIT_OTHER_PS: Number of PS threads waiting for for instructions to be fetched or completed. Should be select value 24. c cSQ_PERF_SEL_CF_INST_ISSUES_PER_TYPE: Number of CF instruction issues. Thread-type dependent. Deterministic. Should be select value 25. e0dSQ_PERF_SEL_CF_INST_ISSUE_ONE: Number of times only a single instruction is issued on a cycle. Thread-type independent. Should be select value 26. fPeSQ_PERF_SEL_CF_INST_ISSUE_TWO: Number of times two instructions are issued in a single cycle. Thread-type independent. Should be select value 27. HghfSQ_PERF_SEL_CF_INST_ISSUE_IDLE_PER_TYPE: Number of cycles when threads exist but no threads are ready to issue. Thread-type dependent. Should be select value 28. hgSQ_PERF_SEL_CF_INST_ISSUE_FS_PER_TYPE: Number of instructions executed in Fetch Shader Mode. Does not include initial CALL_FS instruction. Thread-type dependent. Deterministic. Should be select value 29. ihSQ_PERF_SEL_CF_INST_ISSUE_ALU_PER_TYPE: Number of CF_ALU instructions issued. Thread-type dependent. Deterministic. Should be select value 30. jjSQ_PERF_SEL_CF_INST_ISSUE_TF_PER_TYPE: Number of CF_TF instructions issued. Thread-type dependent. Deterministic. Should be select value 31. kk SQ_PERF_SEL_CF_INST_ISSUE_VF_PER_TYPE: Number of CF_VF instructions issued. Thread-type dependent. Deterministic. Should be select value 32. m0l!SQ_PERF_SEL_CF_INST_ISSUE_EX_PER_TYPE: Number of Export instructions issued. Thread-type dependent. Deterministic. Should be select value 33. nHm"SQ_PERF_SEL_CF_INST_ISSUE_SMX_WR_PER_TYPE: Number of SMX write instructions issued. Thread-type dependent. Deterministic. Should be select value 34. @ohn#SQ_PERF_SEL_CF_INST_ISSUE_SMX_RD_PER_TYPE: Number of SMX read instructions issued. Thread-type dependent. Deterministic. Should be select value 35. Xpo$SQ_PERF_SEL_CF_INST_ISSUE_GF_PER_TYPE: Number of geometry instructions issued. Thread-type dependent. Deterministic. Should be select value 36. qp%SQ_PERF_SEL_CF_INST_ISSUE_OTHER_PER_TYPE: Number of non-ALU/TF/VF/EX/SMX/GF instructions issued. Thread-type dependent. Deterministic. Should be select value 37. rq&SQ_PERF_SEL_CF_INST_ISSUE_ALU_CF_PER_TYPE: Number of ALU CF tags processed. Thread-type dependent. Deterministic. Should be select value 38. sr'SQ_PERF_SEL_CF_INST_ISSUE_BL_PER_TYPE: Number of OTHER and ALU CF tags processed. Thread-type dependent. Deterministic. Should be select value 39. tt(SQ_PERF_SEL_CF_INST_REJECT_ALU_PER_TYPE: Number of ALU instructions scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 40. 8v8u)SQ_PERF_SEL_CF_INST_REJECT_TF_PER_TYPE: Number of times a Texture Fetch instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 41. xwv*SQ_PERF_SEL_CF_INST_REJECT_VF_PER_TYPE: Number of times a Vertex Fetch instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 42. xw+SQ_PERF_SEL_CF_INST_REJECT_EX_PER_TYPE: Number of times an Export instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 43. zy,SQ_PERF_SEL_CF_INST_REJECT_SMX_WR_PER_TYPE: Number of times a SMX write instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 44. @{Hz-SQ_PERF_SEL_CF_INST_REJECT_SMX_RD_PER_TYPE: Number of times a SMX read instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 45. h|{.SQ_PERF_SEL_CF_INST_REJECT_GF_PER_TYPE: Number of geometry instructions trivially rejected. Thread-type dependent. Deterministic. Should be select value 46. }|/SQ_PERF_SEL_CF_INST_REJECT_OTHER_PER_TYPE: Number of non-ALU/TF/VF/EX/SMX/GF instructions rejected. Thread-type dependent. Deterministic. Should be select value 47. ~}0SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_PER_TYPE: Number of instructions sent to ALU. Thread-type dependent. Deterministic. Should be select value 48. ~1SQ_PERF_SEL_CF_INST_FIFO_SEND_TF_PER_TYPE: Number of instructions sent to Texture Fetch unit. Thread-type dependent. Deterministic. Should be select value 49. 2SQ_PERF_SEL_CF_INST_FIFO_SEND_VF_PER_TYPE: Number of instructions sent to Vertex Fetch unit. Thread-type dependent. Deterministic. Should be select value 50. H3SQ_PERF_SEL_CF_INST_FIFO_SEND_EX_PER_TYPE: Number of instructions sent to Export unit. Thread-type dependent. Deterministic. Should be select value 51. Ph4SQ_PERF_SEL_CF_INST_FIFO_SEND_SMX_WR_PER_TYPE: Number of write instructions sent to SMX Export unit. Thread-type dependent. Deterministic. Should be select value 52. 5SQ_PERF_SEL_CF_INST_FIFO_SEND_SMX_RD_PER_TYPE: Number of read instructions sent to SMX Export unit. Thread-type dependent. Deterministic. Should be select value 53. Ȅ6SQ_PERF_SEL_CF_INST_FIFO_SEND_GF_PER_TYPE: Number of geometry instructions executed. Thread-type dependent. Deterministic. Should be select value 54. І腯7SQ_PERF_SEL_CF_INST_FIFO_SEND_OTHER_PER_TYPE: Number of non-ALU/TF/VF/EX/SMX/GF instructions executed. Thread-type dependent. Deterministic. Should be select value 55. 8SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_NONE_PER_TYPE: Number of instructions sent to ALU with no kcache regions locked. Thread-type dependent. Deterministic. Should be select value 56. ``9SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_ONE_PER_TYPE: Number of instructions sent to ALU with one kcache regions locked. Thread-type dependent. Deterministic. Should be select value 57. :SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_TWO_PER_TYPE: Number of instructions sent to ALU with two kcache regions locked. Thread-type dependent. Deterministic. Should be select value 58. ;SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_PER_TYPE: Number of kcache region locks in instructions sent to ALU. Thread-type dependent. Deterministic. Should be select value 59. 茯(<~SQ_PERF_SEL_CF_INST_FIFO_FULL_ALU: Number of ALU units full on a cycle. Thread-type independent. Should be select value 60. 0=SQ_PERF_SEL_CF_INST_FIFO_FULL_TF: Number of cycles the Texture Fetch unit was full. Thread-type independent. Should be select value 61. @>SQ_PERF_SEL_CF_INST_FIFO_FULL_VF: Number of cycles the Vertex Fetch unit was full. Thread-type independent. Should be select value 62. P?SQ_PERF_SEL_CF_INST_FIFO_FULL_EX: Number of cycles the Export unit was full. Thread-type independent. Should be select value 63. X@SQ_PERF_SEL_CF_INST_FIFO_FULL_SMX: Number of cycles the SMX Export unit was full. Thread-type independent. Should be select value 64. 0hASQ_PERF_SEL_CF_INST_FIFO_FULL_GF: Number of cycles the Geometry Fifo was full. Thread-type independent. Should be select value 65. xBKSQ_PERF_SEL_CF_INST_FIFO_FULL_OTHER: Reserved. Should be select value 66. HCSQ_PERF_SEL_CF_INST_FIFO_LEVEL_ALU: Number of credits available for all ALU units. Thread-type independent. Should be select value 67. XDSQ_PERF_SEL_CF_INST_FIFO_LEVEL_TF: Number of credits available for TF unit. Thread-type independent. Should be select value 68. `ESQ_PERF_SEL_CF_INST_FIFO_LEVEL_VF: Number of credits available for VF unit. Thread-type independent. Should be select value 69. (hFSQ_PERF_SEL_CF_INST_FIFO_LEVEL_EX: Number of credits available for EX unit. Thread-type independent. Should be select value 70. 0pGSQ_PERF_SEL_CF_INST_FIFO_LEVEL_SMX: Number of credits available for SMX unit. Thread-type independent. Should be select value 71. @xHSQ_PERF_SEL_CF_INST_FIFO_LEVEL_GF: Number of credits available for Geometry Fifo. Thread-type independent. Should be select value 72. ILSQ_PERF_SEL_CF_INST_FIFO_LEVEL_OTHER: Reserved. Should be select value 73. XJSQ_PERF_SEL_CF_INST_FIFO_EMPTY_ALU: Number of ALU units empty on a cycle. Thread-type independent. Should be select value 74. (`KSQ_PERF_SEL_CF_INST_FIFO_EMPTY_TF: Number of cycles the Texture Fetch unit was empty. Thread-type independent. Should be select value 75. 8pLSQ_PERF_SEL_CF_INST_FIFO_EMPTY_VF: Number of cycles the Vertex Fetch unit was empty. Thread-type independent. Should be select value 76. HMSQ_PERF_SEL_CF_INST_FIFO_EMPTY_EX: Number of cycles the Export unit was empty. Thread-type independent. Should be select value 77. PNSQ_PERF_SEL_CF_INST_FIFO_EMPTY_SMX: Number of cycles the SMX unit was empty. Thread-type independent. Should be select value 78. `OSQ_PERF_SEL_CF_INST_FIFO_EMPTY_GF: Number of cycles the Geometry fifo was empty. Thread-type independent. Should be select value 79. 0PLSQ_PERF_SEL_CF_INST_FIFO_EMPTY_OTHER: Reserved. Should be select value 80. PxQSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_ALU_PER_TYPE: Number of instructions outstanding for all ALU units. Thread-type dependent. Should be select value 81. hRSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_TF_PER_TYPE: Number of instructions outstanding for TF unit. Thread-type dependent. Should be select value 82. SSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_VF_PER_TYPE: Number of instructions outstanding for VF unit. Thread-type ependent. Should be select value 83. ȤTSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_EX_PER_TYPE: Number of instructions outstanding for EX unit. Thread-type dependent. Should be select value 84. ९USQ_PERF_SEL_CF_INST_ISSUE_LEVEL_SMX_WR_PER_TYPE: Number of write instructions outstanding for SMX unit. Thread-type dependent. Should be select value 85. اVSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_SMX_RD_PER_TYPE: Number of read instructions outstanding for SMX unit. Thread-type dependent. Should be select value 86. WSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_GF_PER_TYPE: Number of instructions outstanding for Geometry Fifo. Thread-type dependent. Should be select value 87. @XSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_OTHER_PER_TYPE: Number of instructions outstanding for non-ALU/TF/VF/EX/SMX/GF. Thread-type dependent. Should be select value 88. (hYSQ_PERF_SEL_CF_INST_CHECKPOINT: Number of times user specified CF address is executed. Deterministic. Should be select value 89. PpZSQ_PERF_SEL_CF_INST_CHECKPOINT_BEFORE: Number of CF instructions executed including and after the specified CF address. Deterministic. Should be select value 90. p[SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_VALID: Number of items valid for execution of instruction at CF address. Deterministic. Should be select value 91. \SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_VALID_NONE: Number of times no items are valid for execution of instruction at CF address. Deterministic. Should be select value 92. 讯]SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_ACTIVE: Number of items active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 93. P^SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_ACTIVE_NONE: Number of times no items are active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 94. 貯ȱ_SQ_PERF_SEL_CF_INST_CHECKPOINT_QUADS_ACTIVE: Number of pixel quads active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 95. P0`SQ_PERF_SEL_CF_INST_CHECKPOINT_QUADS_VALID: Number of pixel quads valid for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 96. `aSQ_PERF_SEL_CF_INST_CHECKPOINT_THREADS: Number of times a thread first reaches the CF address. Deterministic. Should be select value 97. pbSQ_PERF_SEL_CF_INST_CHECKPOINT_THREAD_LEVEL: Number of threads that have reached the CF address per cycle. Should be select value 98. xcSQ_PERF_SEL_CF_INST_FETCH_PER_TYPE: Number of CF fetch requests from cache. Thread-type dependent. Should be select value 99. dSQ_PERF_SEL_CF_INST_FETCH_RETURNS_PER_TYPE: Number of CF fetch return cycles from cache. Thread-type dependent. Should be select value 100. ظeSQ_PERF_SEL_CF_INST_FETCH_INSTS_PER_TYPE: Number of CF instructions requested from cache. Thread-type dependent. Should be select value 101. ȺfSQ_PERF_SEL_CF_INST_FETCH_LEVEL_PER_TYPE: Number of CF fetch requests from cache pending per cycle. Thread-type dependent. Should be select value 102. 0gSQ_PERF_SEL_CF_INST_FETCH_EXTRA_PER_TYPE: Number of times we didn't issue the second instruction in a pair. Does not include instructions after PROGRAM_END. Thread-type dependent. Deterministic. Should be select value 103. HxhSQ_PERF_SEL_CF_INST_FETCH_FIFO_SEND: Number of requests passing through the fetch fifo. Thread-type independent. Should be select value 104. PiSQ_PERF_SEL_CF_INST_FETCH_FIFO_LEVEL: Control Flow Fetch fifo entry level. Thread-type independent. Should be select value 105. pjSQ_PERF_SEL_CF_INST_FETCH_FIFO_STALL: Number of cycles when the CF fetch fifo is stalling issues. Thread-type independent. Should be select value 106. kSQ_PERF_SEL_CF_INST_CACHE_FIFO_SEND: Number of requests passing through the cache fifo. Thread-type independent. Should be select value 107. lySQ_PERF_SEL_CF_INST_CACHE_FIFO_LEVEL: Number of credits in cache. Thread-type independent. Should be select value 108. ¯mSQ_PERF_SEL_CF_INST_CACHE_FIFO_FULL: Number of cycles when we have no cache credits. Thread-type independent. Should be select value 109. ï¯nSQ_PERF_SEL_CF_INST_ISSUE_DONES: Number of issues that need to be accounted for to avoid overflowing the done fifo. Thread-type independent. Should be select value 110. ůįoSQ_PERF_SEL_CF_INST_ISSUE_DONE_LEVEL: Number of issues pending at any given time that need to be accounted for to avoid overflowing the done fifo. Thread-type independent. Should be select value 111. 0Ư`ůpSQ_PERF_SEL_CF_INST_ISSUE_DONE_STALL: Stalls triggered to avoid overflowing the done fifo. Thread-type independent. Should be select value 112. HǯxƯqSQ_PERF_SEL_CF_INST_ISSUE_DONE_FIFO_SEND: Number of items passing through the done fifo. Thread-type independent. Should be select value 113. XȯǯrSQ_PERF_SEL_CF_INST_ISSUE_DONE_FIFO_LEVEL: Control Flow Done fifo entry level. Thread-type independent. Should be select value 114. hɯȯsSQ_PERF_SEL_CF_INST_ALU_UPDATE_FIFO_SEND: Macro sequencer alu update fifo send. Thread-type independent. Should be select value 115. xʯɯtSQ_PERF_SEL_CF_INST_ALU_UPDATE_FIFO_LEVEL: Macro sequencer alu update fifo level. Thread-type independent. Should be select value 116. ˯ʯuSQ_PERF_SEL_CF_INST_ALU_UPDATE_FIFO_STALL: Number of cycles when the MS alu update fifo is stalling issues and alu returns. Thread-type independent. Should be select value 117. ̯˯vSQ_PERF_SEL_OFIFO_LEVEL_PER_TYPE: Number of threads and events in the ofifo. Thread-type dependent. Should be select value 118. ͯͯwSQ_PERF_SEL_SX_EVENT_FIFO_FULL_PER_TYPE: Number of cycles the SX event fifo is full. Thread-type dependent. Should be select value 119. ίίxSQ_PERF_SEL_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE: Number of ALU instruction groups executed. Thread-type dependent. Deterministic. Should be select value 120. Я8ϯySQ_PERF_SEL_ALU_CLAUSE_INSTRS_PER_TYPE: Number of ALU individual alu instructions executed. Thread-type dependent. Deterministic. Should be select value 121. Hѯ`ЯzSQ_PERF_SEL_ALU_KWATERFALL_PER_TYPE: Number of ALU instruction groups which use const-waterfall. Thread-type dependent. Deterministic. Should be select value 122. xүѯ{SQ_PERF_SEL_ALU_GPRWATERFALL_PER_TYPE: Number of ALU instruction groups which use gpr-waterfall. Thread-type dependent. Deterministic. Should be select value 123. ӯү|SQ_PERF_SEL_ALU_K_INSTR_PER_TYPE: Number of ALU instructions which use one or more constant (literal, kcache, or kfile). Thread-type dependent. Deterministic. Should be select value 124. ԯԯ}SQ_PERF_SEL_ALU_ICACHE_BUSY_PER_TYPE: Number of times ALU Icache read was denied - cache busy. Thread-type dependent. Should be select value 125. կ կ~SQ_PERF_SEL_ALU_KCACHE_BUSY_PER_TYPE: Number of times ALU Kcache/Kfile read was denied - cache busy. Thread-type dependent. Should be select value 126. ׯ@֯SQ_PERF_SEL_ALU_MOVA_IDLE_WAIT_PER_TYPE: Number of instruction cycles idle waiting for MOVA to complete. Thread-type dependent. Should be select value 127. `دhׯSQ_PERF_SEL_ALU_LOCK_WAIT: Number of times (1 every 4 clocks) ALU has clauses in input fifo but no clauses locked -- ALU is idle. Thread-type independent. Should be select value 128. ٯدSQ_PERF_SEL_ALU_ICACHE_READS_PER_TYPE: Number of read requests to the ALU I-cache. Thread-type dependent. Deterministic. Should be select value 129. گٯSQ_PERF_SEL_ALU_KCACHE_READS_PER_TYPE: Number of read requests to the ALU K-cache/K-file. Thread-type dependent. Deterministic. Should be select value 130. ۯگSQ_PERF_SEL_ALU_DONE_FIFO_FULL: Number of times the done-fifo is full and that caused a stall. Thread-type independent. Should be select value 131. ݯܯSQ_PERF_SEL_ALU_MOVA_WAIT_PER_TYPE: Number of times more than one SIMD tried to execute MOVA, and one was denied access. Thread-type dependent. Should be select value 132. 0ޯHݯSQ_PERF_SEL_ALU_THREADS_IN_FIFO_PER_TYPE: Number of threads waiting in the alu-seq's input fifo each cycle, of the selected thread type. Should be select value 133. ޯxޯSQ_PERF_SEL_UNUSED_006p߯߯SQ_PERF_SEL_UNUSED_007߯SQ_PERF_SEL_TV_ICACHE_WAIT_PER_TYPE: Number of cycles the Tex/Vtx Icache denied a read request (busy). Thread-type dependent. Should be select value 136. 0SQ_PERF_SEL_UNUSED_010xSQ_PERF_SEL_UNUSED_001pSQ_PERF_SEL_UNUSED_002SQ_PERF_SEL_TF_TA_STALL_PER_TYPE: Number of times the TF had data to send to TA, but the TA input fifo was full. Thread-type dependent. Should be select value 140. SQ_PERF_SEL_VF_VC_INSTR_STALL_PER_TYPE: Number of times the VF had data to send to VC, but the VC instruction input fifo was full. Thread-type dependent. Should be select value 141. (SQ_PERF_SEL_VF_VC_INDEX_STALL_PER_TYPE: Number of times the VF had data to send to VC, but the VC index input fifo was full. Thread-type dependent. Should be select value 142. `SQ_PERF_SEL_UNUSED_003XSQ_PERF_SEL_UNUSED_008SQ_PERF_SEL_UNUSED_004@SQ_PERF_SEL_UNUSED_009wSQ_PERF_SEL_EXPORT_INSTR_PER_TYPE: Number of exports (seen by export-seq). Determinstic. Should be select value 147. {SQ_PERF_SEL_EXPORT_IDLE: Number of clocks where export unit is idle. Thread-type independent. Should be select value 148. SQ_PERF_SEL_EXPORT_SMX_AL_STALL: Number of clocks SMX export stalled waiting for alloc. Thread-type independent. Should be select value 149. SQ_PERF_SEL_EXPORT_PC_AL_STALL: Number of clocks Param.cache alloc was stalled. Thread-type independent. Should be select value 150. SQ_PERF_SEL_EXPORT_POS_AL_STALL: Number of clocks Position export alloc was stalled. Thread-type independent. Should be select value 151. SQ_PERF_SEL_EXPORT_PIX_AL_STALL: Number of clocks Pixel export alloc was stalled. Thread-type independent. Should be select value 152. (SQ_PERF_SEL_EXPORT_POS_CYCLE: Number of position export cycles (4 clocks), * burst count). Thread-type independent. Determinstic. Should be select value 153. 0PSQ_PERF_SEL_EXPORT_PIX_CYCLE: Number of pixel export cycles (4 clocks), * burst count). Thread-type independent. Determinstic. Should be select value 154. XxSQ_PERF_SEL_EXPORT_PC_CYCLE: Number of param.cache export cycles (4 clocks), * burst count). Thread-type independent. Determinstic. Should be select value 155. SQ_PERF_SEL_EXPORT_SMX_CYCLE_PER_TYPE: Number of smx export cycles (4 clocks), * burst count). Thread-type dependent. Determinstic. Should be select value 156. SQ_PERF_SEL_CACHE_INVAL_ANY: Number of cache invalidation (surface synchronization) operations of any kind. Thread-type independent. Should be select value 157. SQ_PERF_SEL_CACHE_INVAL_ALL: Number of cache invalidation (surface synchronization) operations that invalidate the whole cache (due to a large invalidation region). Thread-type independent. Should be select value 158. PSQ_PERF_SEL_CACHE_INVAL_CYCLES: Number of cache invalidation (surface synchronization) cycles, not including full invalidations; indicates the size of the invalidation regions in 4K byte increments. Thread-type independent. Should be select value 159. SQ_PERF_SEL_CF_ICACHE_HITS: Number of CF instruction cache hits (it was found in the cache). Thread-type independent. Should be select value 160. SQ_PERF_SEL_TF_ICACHE_HITS: Number of TV instruction cache hits (it was found in the cache). Thread-type independent. Should be select value 161. QSQ_PERF_SEL_VF_ICACHE_HITS: DEPRECATED. Do not use. Should be select value 162. SQ_PERF_SEL_ALU_ICACHE_HITS: Number of ALU instruction cache hits (it was found in the cache). Thread-type independent. Should be select value 163. SQ_PERF_SEL_ALU_KCACHE_HITS: Number of ALU constant cache hits (it was found in the cache). Thread-type independent. Should be select value 164. SQ_PERF_SEL_CF_ICACHE_MISSES: Number of CF instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 165. ``SQ_PERF_SEL_TF_ICACHE_MISSES: Number of TV instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 166. 8SSQ_PERF_SEL_VF_ICACHE_MISSES: DEPRECATED. Do not use. Should be select value 167. SQ_PERF_SEL_ALU_ICACHE_MISSES: Number of ALU instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 168. SQ_PERF_SEL_ALU_KCACHE_MISSES: Number of ALU constant cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 169. SQ_PERF_SEL_CF_ICACHE_DUP_MISSES: Number of CF instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 170. hSQ_PERF_SEL_TF_ICACHE_DUP_MISSES: Number of TV instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 171. `WSQ_PERF_SEL_VF_ICACHE_DUP_MISSES: DEPRECATED. Do not use. Should be select value 172. SQ_PERF_SEL_ALU_ICACHE_DUP_MISSES: Number of ALU instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 173. SQ_PERF_SEL_ALU_KCACHE_DUP_MISSES: Number of ALU constant cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 174. h SQ_PERF_SEL_CF_ICACHE_ACCESSES: Number of CF instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 175. SQ_PERF_SEL_TF_ICACHE_ACCESSES: Number of TV instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 176. H USQ_PERF_SEL_VF_ICACHE_ACCESSES: DEPRECATED. Do not use. Should be select value 177. P( SQ_PERF_SEL_ALU_ICACHE_ACCESSES: Number of ALU instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 178. SQ_PERF_SEL_ALU_KCACHE_ACCESSES: Number of ALU constant cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 179. SQ_PERF_SEL_CF_ICACHE_INPUT_FIFO_ENTRIES: Count of CF instruction cache requests stored in the input FIFO. Thread-type independent. Should be select value 180. 0SQ_PERF_SEL_TF_ICACHE_INPUT_FIFO_ENTRIES: Count of TV instruction cache requests stored in the input FIFO. Thread-type independent. Should be select value 181. X_SQ_PERF_SEL_VF_ICACHE_INPUT_FIFO_ENTRIES: DEPRECATED. Do not use. Should be select value 182. @SQ_PERF_SEL_ALU_ICACHE_INPUT_FIFO_ENTRIES: Count of ALU instruction cache requests stored in the input FIFO. Thread-type independent. Should be select value 183. HhSQ_PERF_SEL_ALU_KCACHE_INPUT_FIFO_ENTRIES: Count of ALU constant cache requests stored in the input FIFO. Thread-type independent. Should be select value 184. SQ_PERF_SEL_CF_ICACHE_MISS_MEM_STALL: Number of CF instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 185. SQ_PERF_SEL_TF_ICACHE_MISS_MEM_STALL: Number of TV instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 186. P[SQ_PERF_SEL_VF_ICACHE_MISS_MEM_STALL: DEPRECATED. Do not use. Should be select value 187. P0SQ_PERF_SEL_ALU_ICACHE_MISS_MEM_STALL: Number of ALU instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 188. SQ_PERF_SEL_ALU_KCACHE_MISS_MEM_STALL: Number of ALU constant cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 189. (SQ_PERF_SEL_CF_ICACHE_MISS_FIFO_STALL: Number of CF instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 190. pSQ_PERF_SEL_TF_ICACHE_MISS_FIFO_STALL: Number of TV instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 191. \SQ_PERF_SEL_VF_ICACHE_MISS_FIFO_STALL: DEPRECATED. Do not use. Should be select value 192. SQ_PERF_SEL_ALU_ICACHE_MISS_FIFO_STALL: Number of ALU instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 193. p"@!SQ_PERF_SEL_ALU_KCACHE_MISS_FIFO_STALL: Number of ALU constant cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 194. #"SQ_PERF_SEL_CF_ICACHE_HIT_STALL: Number of CF instruction cache cycles that are a cache hit but are stalled due to processing previous misses. Thread-type independent. Should be select value 195. (%$SQ_PERF_SEL_CF_ICACHE_MISS_LOCKED_STALL: Number of CF instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 196. &p%SQ_PERF_SEL_TF_ICACHE_MISS_LOCKED_STALL: Number of TV instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 197. x'&^SQ_PERF_SEL_VF_ICACHE_MISS_LOCKED_STALL: DEPRECATED. Do not use. Should be select value 198. ('SQ_PERF_SEL_ALU_ICACHE_MISS_LOCKED_STALL: Number of ALU instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 199. H*()SQ_PERF_SEL_ALU_KCACHE_MISS_LOCKED_STALL: Number of ALU constant cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 200. +*SQ_PERF_SEL_CF_ICACHE_LOCKED_TAGS: Count of CF instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 201. ,+SQ_PERF_SEL_TF_ICACHE_LOCKED_TAGS: Count of TV instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 202. -@-XSQ_PERF_SEL_VF_ICACHE_LOCKED_TAGS: DEPRECATED. Do not use. Should be select value 203. 0/ .SQ_PERF_SEL_ALU_ICACHE_LOCKED_TAGS: Count of ALU instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 204. 0x/SQ_PERF_SEL_ALU_KCACHE_LOCKED_TAGS: Count of ALU constant cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 205. 10SQ_PERF_SEL_CF_ICACHE_MISS_LOCKED_TAGS: Count of CF instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 206. 32SQ_PERF_SEL_TF_ICACHE_MISS_LOCKED_TAGS: Count of TV instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 207. 3P3]SQ_PERF_SEL_VF_ICACHE_MISS_LOCKED_TAGS: DEPRECATED. Do not use. Should be select value 208. 0584SQ_PERF_SEL_ALU_ICACHE_MISS_LOCKED_TAGS: Count of ALU instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 209. p6x5SQ_PERF_SEL_ALU_KCACHE_MISS_LOCKED_TAGS: Count of ALU constant cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 210. 76SQ_PERF_SEL_CACHE_MEM_REQUESTS: Number of cache to memory controller requests of any type. Thread-type independent. Should be select value 211. 87SQ_PERF_SEL_CF_ICACHE_MEM_REQUESTS: Number of CF instruction cache to memory controller requests. Thread-type independent. Should be select value 212. 98SQ_PERF_SEL_TV_ICACHE_MEM_REQUESTS: Number of TV instruction cache to memory controller requests. Thread-type independent. Should be select value 213. ::SQ_PERF_SEL_ALU_ICACHE_MEM_REQUESTS: Number of ALU instruction cache to memory controller requests. Thread-type independent. Should be select value 214. <0;SQ_PERF_SEL_ALU_KCACHE_MEM_REQUESTS: Number of ALU constant cache to memory controller requests. Thread-type independent. Should be select value 215. H=P<SQ_PERF_SEL_CF_ICACHE_RD_WR_COLLISION: Number of times a read to the CF icache memory was blocked by a write from a memory return. Thread-type independent. Should be select value 216. >=SQ_PERF_SEL_CF_ICACHE_MISS_HIT_RD_COLLISION: Number of times processing a hit is stalled by processing a now-resident miss. Thread-type independent. Should be select value 217. ?>SQ_PERF_SEL_CF_ICACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding CF instruction cache to memory controller requests of any type. Thread-type independent. Should be select value 218. A@SQ_PERF_SEL_TV_ICACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding TV instruction cache to memory controller requests of any type. Thread-type independent. Should be select value 219. pBhASQ_PERF_SEL_ALU_ICACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding ALU instruction cache to memory controller requests of any type. Thread-type independent. Should be select value 220. CBSQ_PERF_SEL_ALU_KCACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding ALU constant cache to memory controller requests of any type. Thread-type independent. Should be select value 221. DDSQ_PERF_SEL_CF_ICACHE_MISS_FIFO_MISSES: Count of the number of CF instruction cache misses waiting in the miss FIFO. Thread-type independent. Should be select value 222. F8ESQ_PERF_SEL_TF_ICACHE_MISS_FIFO_MISSES: Count of the number of TV instruction cache misses waiting in the miss FIFO. Thread-type independent. Should be select value 223. GhF]SQ_PERF_SEL_VF_ICACHE_MISS_FIFO_MISSES: DEPRECATED. Do not use. Should be select value 224. HHPGSQ_PERF_SEL_ALU_ICACHE_MISS_FIFO_MISSES: Count of the number of ALU instruction cache misses waiting in the miss FIFO. Divided by 2. Thread-type independent. Should be select value 225. IHSQ_PERF_SEL_ALU_KCACHE_MISS_FIFO_MISSES: Count of the number of ALU constant cache misses waiting in the miss FIFO. Divided by 2. Thread-type independent. Should be select value 226. JISQ_PERF_SEL_CACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding cache to memory controller requests of any type. Divided by 2. Thread-type independent. Should be select value 227. KKSQ_PERF_SEL_CACHE_MEM_STALL: Number of cache to memory controller cycles that are stalled. Thread-type independent. Should be select value 228. L0LqSQ_PERF_SEL_TM_TS64_STALL: Clock cycles GRBM stalled due to Timestamp-64 FIFO full. Should be select value 229. M(MSQ_PERF_SEL_TM_ALU_CONST_STALL: Clock cycles GRBM stalled due to ALU constant overflow buffer full. Should be select value 230. N0NSQ_PERF_SEL_TM_LOOP_CONST_STALL: Clock cycles GRBM stalled due to Loop constant overflow buffer full. Should be select value 231. P8OSQ_PERF_SEL_TM_TEX_BASE_CONST_STALL: Clock cycles GRBM stalled due to VertexBase/InstantStart constant overflow buffer full. Should be select value 232. (QXPSQ_PERF_SEL_TM_TEX_SAMPLER_STALL: Clock cycles GRBM stalled due to Texture Sampler constant overflow buffer full. Should be select value 233. @RpQSQ_PERF_SEL_TM_TEX_RESOURCE_STALL: Clock cycles GRBM stalled due to Texture Resource constant overflow buffer full. Should be select value 234. RRSQ_PERF_SEL_UNUSED_0050T(SSQ_PERF_SEL_TA_TEX_INSTRS_PER_TYPE: Number of texture-fetch instructions executed by the Texture cache, including killed fetches. Thread-type dependent. Determinstic. Should be select value 236. xUxTSQ_PERF_SEL_TA_VTX_INSTRS_PER_TYPE: Number of vertex-fetch instructions executed by the Texture cache, including killed fetches. Thread-type dependent. Determinstic. Should be select value 237. VUSQ_PERF_SEL_VC_INSTRS_PER_TYPE: Number of instructions executed by the Vertex cache, including killed fetches. Thread-type dependent. Determinstic. Should be select value 238. WVSQ_PERF_SEL_TV_LOCK_WAIT: Number of cycles the TF input FIFO had clauses, none were locked. Thread-type independent, non-deterministic. Should be select value 239. X(XSQ_PERF_SEL_TA_SRC_C: Number of times an TA fetch (16 pix or verts) was executed as a src-c export. Non-deterministic. Should be select value 240. Z@YSQ_PERF_SEL_VC_SRC_C: Number of times a VC fetch (16 pix or verts) was executed as a src-c export. Non-deterministic. Should be select value 241. 8[XZSQ_PERF_SEL_TV_KILLED_FETCH_PER_TYPE: Number of fetch instructions killed (vertex semantic failed or gpr out of range). Deterministic. Should be select value 242. p\[SQ_PERF_SEL_TV_NULL_FETCH_PER_TYPE: Number of null fetchs issued (null = issue empty fetch at end of clause due to killed fetches). Deterministic. Should be select value 243. ]\SQ_PERF_SEL_TV_THREADS_IN_FIFO_PER_TYPE: Number of threads waiting in the fetch-seq's input fifo each cycle, of the selected thread type. Should be select value 244. ^]SQ_PERF_SEL_EXPORT_SPQ_LEVEL: Internal export per-quadpipe queue level average. Non-deterministic. Should be select value 245. ^ySQ_PERF_SEL_EXPORT_SPQ_STALL: Internal export per-quadpipe stall cycles. Non-deterministic. Should be select value 246. a`P`PS_ENa`8Exclude pixel shader threads from performance counters Xa6Include pixel shader threads in performance counters c(b pbVS_EN0cb9Exclude vertex shader threads from performance counters xc7Include vertex shader threads in performance counters fHd dGS_ENPed;Exclude geometry shader threads from performance counters e9Include geometry shader threads in performance counters 0hhf fES_ENpgf9Exclude export shader threads from performance counters g7Include export shader threads in performance counters pjh hMAXiiBAccumulate performance events (if both TEST_MODE and LIVE are 0) iXRetain maximum single-cycle performance event value (if both TEST_MODE and LIVE are 0) lj k TEST_MODEkXk:Update performance counters based on MAX and LIVE fields l7Shift in 1's rather than counting, For Debugging only l0mLIVEmxm4Update performance counters based on the MAX field 0nMRetain the current single-cycle performance event value (if TEST_MODE is 0) p،،""SQ_PERF_CTR6_SEL6XSEL0RSQ_PERF_SEL_NONE: don't count anything Deterministic. Should be select value 0.  xWSQ_PERF_SEL_CYCLES: Clock cycles. Thread-type independent. Should be select value 1. !X SQ_PERF_SEL_BUSY_CYCLES: Clock cycles while SQ is reporting that it is busy. Thread-type independent. Should be select value 2. "`!SQ_PERF_SEL_ANY_BUSY_PER_TYPE: Number of cycles we have a thread or an event. Thread-type dependent. Should be select value 3. #h"SQ_PERF_SEL_EVENTS_PER_TYPE: Number of events. Thread-type dependent. Caveat: Event counts are slightly unpredictable because they don't have an associated state and because we don't count events when we don't have acitve threads. Should be select value 4. $#uSQ_PERF_SEL_EVENTS_BUSY_PER_TYPE: Number cycles we have an event. Thread-type dependent. Should be select value 5. %$SQ_PERF_SEL_EVENT_LEVEL_PER_TYPE: Number of events in the pipeline per clock. Thread-type dependent. Should be select value 6. &%SQ_PERF_SEL_ITEMS_PER_TYPE: Number of valid items per thread. Thread-type dependent. Deterministic. Should be select value 7. ''SQ_PERF_SEL_ITEMS_GT_48_PER_TYPE: Number of threads with a valid item in a position >= 48. Thread-type dependent. Deterministic. Should be select value 8. )(( SQ_PERF_SEL_ITEMS_GT_32_PER_TYPE: Number of threads with a valid item in a position >= 32. Thread-type dependent. Deterministic. Should be select value 9. 0*P) SQ_PERF_SEL_ITEMS_GT_16_PER_TYPE: Number of threads with a valid item in a position >= 16. Thread-type dependent. Deterministic. Should be select value 10. (+x* nSQ_PERF_SEL_QUADS: Number of valid pixel shader quads per thread. Deterministic. Should be select value 11. (,p+ wSQ_PERF_SEL_THREADS_BUSY_PER_TYPE: Number cycles we have a thread. Thread-type dependent. Should be select value 12. -p, tSQ_PERF_SEL_THREADS_PER_TYPE: Number of threads. Thread-type dependent. Deterministic Should be select value 13. (.h-SQ_PERF_SEL_THREAD_LEVEL_PER_TYPE: Number of threads in the pipeline per clock. Thread-type dependent. Should be select value 14. 8/p.SQ_PERF_SEL_THREAD_LEVEL_WAIT_CREATE_PER_TYPE: Number of threads waiting to be created. Thread-type dependent. Should be select value 15. X0/SQ_PERF_SEL_THREAD_LEVEL_UNALLOC_PARAM_PER_TYPE: Number of threads with parameter cache unallocated. Thread-type dependent. Should be select value 16. p10SQ_PERF_SEL_THREAD_LEVEL_UNALLOC_PIX_PER_TYPE: Number of threads with pixel buffer unallocated. Thread-type dependent. Should be select value 17. 21SQ_PERF_SEL_THREAD_LEVEL_UNALLOC_POS_PER_TYPE: Number of threads with position buffer unallocated. Thread-type dependent. Should be select value 18. 32SQ_PERF_SEL_THREADS_NONPS: Number of existing non-PS threads sharing the set of enabled thread-types with other selected NONPS counters. Should be select value 19. 44SQ_PERF_SEL_THREAD_LEVEL_NONPS: Number of existing non-PS threads per cycle sharing the set of enabled thread-types with other selected NONPS counters. Should be select value 20. X6@5SQ_PERF_SEL_THREAD_LEVEL_WAIT_ALLOC_NONPS: Number of non-PS threads waiting for export space to be allocated. Must share the set of enabled thread-types with other selected NONPS counters. Should be select value 21. 76SQ_PERF_SEL_THREAD_LEVEL_WAIT_OTHER_NONPS: Number of non-PS threads waiting for instructions to be fetched or completed. Must share the set of enabled thread-types with other selected SHARED_TYPESET counters. Should be select value 22. 88SQ_PERF_SEL_THREAD_LEVEL_WAIT_ALLOC_PS: Number of PS threads waiting for pixel buffer to be allocated. Should be select value 23. 9 9SQ_PERF_SEL_THREAD_LEVEL_WAIT_OTHER_PS: Number of PS threads waiting for for instructions to be fetched or completed. Should be select value 24. ;8:SQ_PERF_SEL_CF_INST_ISSUES_PER_TYPE: Number of CF instruction issues. Thread-type dependent. Deterministic. Should be select value 25. <H;SQ_PERF_SEL_CF_INST_ISSUE_ONE: Number of times only a single instruction is issued on a cycle. Thread-type independent. Should be select value 26. 8=h<SQ_PERF_SEL_CF_INST_ISSUE_TWO: Number of times two instructions are issued in a single cycle. Thread-type independent. Should be select value 27. `>=SQ_PERF_SEL_CF_INST_ISSUE_IDLE_PER_TYPE: Number of cycles when threads exist but no threads are ready to issue. Thread-type dependent. Should be select value 28. ?>SQ_PERF_SEL_CF_INST_ISSUE_FS_PER_TYPE: Number of instructions executed in Fetch Shader Mode. Does not include initial CALL_FS instruction. Thread-type dependent. Deterministic. Should be select value 29. @@SQ_PERF_SEL_CF_INST_ISSUE_ALU_PER_TYPE: Number of CF_ALU instructions issued. Thread-type dependent. Deterministic. Should be select value 30. A ASQ_PERF_SEL_CF_INST_ISSUE_TF_PER_TYPE: Number of CF_TF instructions issued. Thread-type dependent. Deterministic. Should be select value 31. C8B SQ_PERF_SEL_CF_INST_ISSUE_VF_PER_TYPE: Number of CF_VF instructions issued. Thread-type dependent. Deterministic. Should be select value 32. DPC!SQ_PERF_SEL_CF_INST_ISSUE_EX_PER_TYPE: Number of Export instructions issued. Thread-type dependent. Deterministic. Should be select value 33. @EhD"SQ_PERF_SEL_CF_INST_ISSUE_SMX_WR_PER_TYPE: Number of SMX write instructions issued. Thread-type dependent. Deterministic. Should be select value 34. `FE#SQ_PERF_SEL_CF_INST_ISSUE_SMX_RD_PER_TYPE: Number of SMX read instructions issued. Thread-type dependent. Deterministic. Should be select value 35. xGF$SQ_PERF_SEL_CF_INST_ISSUE_GF_PER_TYPE: Number of geometry instructions issued. Thread-type dependent. Deterministic. Should be select value 36. HG%SQ_PERF_SEL_CF_INST_ISSUE_OTHER_PER_TYPE: Number of non-ALU/TF/VF/EX/SMX/GF instructions issued. Thread-type dependent. Deterministic. Should be select value 37. IH&SQ_PERF_SEL_CF_INST_ISSUE_ALU_CF_PER_TYPE: Number of ALU CF tags processed. Thread-type dependent. Deterministic. Should be select value 38. JJ'SQ_PERF_SEL_CF_INST_ISSUE_BL_PER_TYPE: Number of OTHER and ALU CF tags processed. Thread-type dependent. Deterministic. Should be select value 39. L(K(SQ_PERF_SEL_CF_INST_REJECT_ALU_PER_TYPE: Number of ALU instructions scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 40. XMXL)SQ_PERF_SEL_CF_INST_REJECT_TF_PER_TYPE: Number of times a Texture Fetch instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 41. NM*SQ_PERF_SEL_CF_INST_REJECT_VF_PER_TYPE: Number of times a Vertex Fetch instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 42. ON+SQ_PERF_SEL_CF_INST_REJECT_EX_PER_TYPE: Number of times an Export instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 43. Q P,SQ_PERF_SEL_CF_INST_REJECT_SMX_WR_PER_TYPE: Number of times a SMX write instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 44. `RhQ-SQ_PERF_SEL_CF_INST_REJECT_SMX_RD_PER_TYPE: Number of times a SMX read instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 45. SR.SQ_PERF_SEL_CF_INST_REJECT_GF_PER_TYPE: Number of geometry instructions trivially rejected. Thread-type dependent. Deterministic. Should be select value 46. TS/SQ_PERF_SEL_CF_INST_REJECT_OTHER_PER_TYPE: Number of non-ALU/TF/VF/EX/SMX/GF instructions rejected. Thread-type dependent. Deterministic. Should be select value 47. UU0SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_PER_TYPE: Number of instructions sent to ALU. Thread-type dependent. Deterministic. Should be select value 48. VV1SQ_PERF_SEL_CF_INST_FIFO_SEND_TF_PER_TYPE: Number of instructions sent to Texture Fetch unit. Thread-type dependent. Deterministic. Should be select value 49. X@W2SQ_PERF_SEL_CF_INST_FIFO_SEND_VF_PER_TYPE: Number of instructions sent to Vertex Fetch unit. Thread-type dependent. Deterministic. Should be select value 50. @YhX3SQ_PERF_SEL_CF_INST_FIFO_SEND_EX_PER_TYPE: Number of instructions sent to Export unit. Thread-type dependent. Deterministic. Should be select value 51. pZY4SQ_PERF_SEL_CF_INST_FIFO_SEND_SMX_WR_PER_TYPE: Number of write instructions sent to SMX Export unit. Thread-type dependent. Deterministic. Should be select value 52. [Z5SQ_PERF_SEL_CF_INST_FIFO_SEND_SMX_RD_PER_TYPE: Number of read instructions sent to SMX Export unit. Thread-type dependent. Deterministic. Should be select value 53. \[6SQ_PERF_SEL_CF_INST_FIFO_SEND_GF_PER_TYPE: Number of geometry instructions executed. Thread-type dependent. Deterministic. Should be select value 54. ]]7SQ_PERF_SEL_CF_INST_FIFO_SEND_OTHER_PER_TYPE: Number of non-ALU/TF/VF/EX/SMX/GF instructions executed. Thread-type dependent. Deterministic. Should be select value 55. 8_8^8SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_NONE_PER_TYPE: Number of instructions sent to ALU with no kcache regions locked. Thread-type dependent. Deterministic. Should be select value 56. `_9SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_ONE_PER_TYPE: Number of instructions sent to ALU with one kcache regions locked. Thread-type dependent. Deterministic. Should be select value 57. a`:SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_TWO_PER_TYPE: Number of instructions sent to ALU with two kcache regions locked. Thread-type dependent. Deterministic. Should be select value 58. cb;SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_PER_TYPE: Number of kcache region locks in instructions sent to ALU. Thread-type dependent. Deterministic. Should be select value 59. dHc<~SQ_PERF_SEL_CF_INST_FIFO_FULL_ALU: Number of ALU units full on a cycle. Thread-type independent. Should be select value 60. ePd=SQ_PERF_SEL_CF_INST_FIFO_FULL_TF: Number of cycles the Texture Fetch unit was full. Thread-type independent. Should be select value 61. (f`e>SQ_PERF_SEL_CF_INST_FIFO_FULL_VF: Number of cycles the Vertex Fetch unit was full. Thread-type independent. Should be select value 62. 0gpf?SQ_PERF_SEL_CF_INST_FIFO_FULL_EX: Number of cycles the Export unit was full. Thread-type independent. Should be select value 63. @hxg@SQ_PERF_SEL_CF_INST_FIFO_FULL_SMX: Number of cycles the SMX Export unit was full. Thread-type independent. Should be select value 64. PihASQ_PERF_SEL_CF_INST_FIFO_FULL_GF: Number of cycles the Geometry Fifo was full. Thread-type independent. Should be select value 65. jiBKSQ_PERF_SEL_CF_INST_FIFO_FULL_OTHER: Reserved. Should be select value 66. 0khjCSQ_PERF_SEL_CF_INST_FIFO_LEVEL_ALU: Number of credits available for all ALU units. Thread-type independent. Should be select value 67. 8lxkDSQ_PERF_SEL_CF_INST_FIFO_LEVEL_TF: Number of credits available for TF unit. Thread-type independent. Should be select value 68. @mlESQ_PERF_SEL_CF_INST_FIFO_LEVEL_VF: Number of credits available for VF unit. Thread-type independent. Should be select value 69. HnmFSQ_PERF_SEL_CF_INST_FIFO_LEVEL_EX: Number of credits available for EX unit. Thread-type independent. Should be select value 70. PonGSQ_PERF_SEL_CF_INST_FIFO_LEVEL_SMX: Number of credits available for SMX unit. Thread-type independent. Should be select value 71. `poHSQ_PERF_SEL_CF_INST_FIFO_LEVEL_GF: Number of credits available for Geometry Fifo. Thread-type independent. Should be select value 72. 0qpILSQ_PERF_SEL_CF_INST_FIFO_LEVEL_OTHER: Reserved. Should be select value 73. 8rxqJSQ_PERF_SEL_CF_INST_FIFO_EMPTY_ALU: Number of ALU units empty on a cycle. Thread-type independent. Should be select value 74. HsrKSQ_PERF_SEL_CF_INST_FIFO_EMPTY_TF: Number of cycles the Texture Fetch unit was empty. Thread-type independent. Should be select value 75. XtsLSQ_PERF_SEL_CF_INST_FIFO_EMPTY_VF: Number of cycles the Vertex Fetch unit was empty. Thread-type independent. Should be select value 76. hutMSQ_PERF_SEL_CF_INST_FIFO_EMPTY_EX: Number of cycles the Export unit was empty. Thread-type independent. Should be select value 77. pvuNSQ_PERF_SEL_CF_INST_FIFO_EMPTY_SMX: Number of cycles the SMX unit was empty. Thread-type independent. Should be select value 78. wvOSQ_PERF_SEL_CF_INST_FIFO_EMPTY_GF: Number of cycles the Geometry fifo was empty. Thread-type independent. Should be select value 79. PxwPLSQ_PERF_SEL_CF_INST_FIFO_EMPTY_OTHER: Reserved. Should be select value 80. pyxQSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_ALU_PER_TYPE: Number of instructions outstanding for all ALU units. Thread-type dependent. Should be select value 81. zyRSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_TF_PER_TYPE: Number of instructions outstanding for TF unit. Thread-type dependent. Should be select value 82. {zSSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_VF_PER_TYPE: Number of instructions outstanding for VF unit. Thread-type ependent. Should be select value 83. |{TSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_EX_PER_TYPE: Number of instructions outstanding for EX unit. Thread-type dependent. Should be select value 84. }}USQ_PERF_SEL_CF_INST_ISSUE_LEVEL_SMX_WR_PER_TYPE: Number of write instructions outstanding for SMX unit. Thread-type dependent. Should be select value 85. ~ ~VSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_SMX_RD_PER_TYPE: Number of read instructions outstanding for SMX unit. Thread-type dependent. Should be select value 86. @WSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_GF_PER_TYPE: Number of instructions outstanding for Geometry Fifo. Thread-type dependent. Should be select value 87. @`XSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_OTHER_PER_TYPE: Number of instructions outstanding for non-ALU/TF/VF/EX/SMX/GF. Thread-type dependent. Should be select value 88. HYSQ_PERF_SEL_CF_INST_CHECKPOINT: Number of times user specified CF address is executed. Deterministic. Should be select value 89. pZSQ_PERF_SEL_CF_INST_CHECKPOINT_BEFORE: Number of CF instructions executed including and after the specified CF address. Deterministic. Should be select value 90. [SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_VALID: Number of items valid for execution of instruction at CF address. Deterministic. Should be select value 91. ؄\SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_VALID_NONE: Number of times no items are valid for execution of instruction at CF address. Deterministic. Should be select value 92. ]SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_ACTIVE: Number of items active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 93. h^SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_ACTIVE_NONE: Number of times no items are active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 94. _SQ_PERF_SEL_CF_INST_CHECKPOINT_QUADS_ACTIVE: Number of pixel quads active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 95. hH`SQ_PERF_SEL_CF_INST_CHECKPOINT_QUADS_VALID: Number of pixel quads valid for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 96. xaSQ_PERF_SEL_CF_INST_CHECKPOINT_THREADS: Number of times a thread first reaches the CF address. Deterministic. Should be select value 97. bSQ_PERF_SEL_CF_INST_CHECKPOINT_THREAD_LEVEL: Number of threads that have reached the CF address per cycle. Should be select value 98. ЍcSQ_PERF_SEL_CF_INST_FETCH_PER_TYPE: Number of CF fetch requests from cache. Thread-type dependent. Should be select value 99. ؎dSQ_PERF_SEL_CF_INST_FETCH_RETURNS_PER_TYPE: Number of CF fetch return cycles from cache. Thread-type dependent. Should be select value 100. eSQ_PERF_SEL_CF_INST_FETCH_INSTS_PER_TYPE: Number of CF instructions requested from cache. Thread-type dependent. Should be select value 101. fSQ_PERF_SEL_CF_INST_FETCH_LEVEL_PER_TYPE: Number of CF fetch requests from cache pending per cycle. Thread-type dependent. Should be select value 102. H(gSQ_PERF_SEL_CF_INST_FETCH_EXTRA_PER_TYPE: Number of times we didn't issue the second instruction in a pair. Does not include instructions after PROGRAM_END. Thread-type dependent. Deterministic. Should be select value 103. `hSQ_PERF_SEL_CF_INST_FETCH_FIFO_SEND: Number of requests passing through the fetch fifo. Thread-type independent. Should be select value 104. hiSQ_PERF_SEL_CF_INST_FETCH_FIFO_LEVEL: Control Flow Fetch fifo entry level. Thread-type independent. Should be select value 105. jSQ_PERF_SEL_CF_INST_FETCH_FIFO_STALL: Number of cycles when the CF fetch fifo is stalling issues. Thread-type independent. Should be select value 106. ЖkSQ_PERF_SEL_CF_INST_CACHE_FIFO_SEND: Number of requests passing through the cache fifo. Thread-type independent. Should be select value 107. 藮lySQ_PERF_SEL_CF_INST_CACHE_FIFO_LEVEL: Number of credits in cache. Thread-type independent. Should be select value 108. 蘮mSQ_PERF_SEL_CF_INST_CACHE_FIFO_FULL: Number of cycles when we have no cache credits. Thread-type independent. Should be select value 109. nSQ_PERF_SEL_CF_INST_ISSUE_DONES: Number of issues that need to be accounted for to avoid overflowing the done fifo. Thread-type independent. Should be select value 110. 0(oSQ_PERF_SEL_CF_INST_ISSUE_DONE_LEVEL: Number of issues pending at any given time that need to be accounted for to avoid overflowing the done fifo. Thread-type independent. Should be select value 111. HxpSQ_PERF_SEL_CF_INST_ISSUE_DONE_STALL: Stalls triggered to avoid overflowing the done fifo. Thread-type independent. Should be select value 112. `qSQ_PERF_SEL_CF_INST_ISSUE_DONE_FIFO_SEND: Number of items passing through the done fifo. Thread-type independent. Should be select value 113. prSQ_PERF_SEL_CF_INST_ISSUE_DONE_FIFO_LEVEL: Control Flow Done fifo entry level. Thread-type independent. Should be select value 114. sSQ_PERF_SEL_CF_INST_ALU_UPDATE_FIFO_SEND: Macro sequencer alu update fifo send. Thread-type independent. Should be select value 115. ȠtSQ_PERF_SEL_CF_INST_ALU_UPDATE_FIFO_LEVEL: Macro sequencer alu update fifo level. Thread-type independent. Should be select value 116. ȢءuSQ_PERF_SEL_CF_INST_ALU_UPDATE_FIFO_STALL: Number of cycles when the MS alu update fifo is stalling issues and alu returns. Thread-type independent. Should be select value 117. УvSQ_PERF_SEL_OFIFO_LEVEL_PER_TYPE: Number of threads and events in the ofifo. Thread-type dependent. Should be select value 118. मwSQ_PERF_SEL_SX_EVENT_FIFO_FULL_PER_TYPE: Number of cycles the SX event fifo is full. Thread-type dependent. Should be select value 119. (xSQ_PERF_SEL_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE: Number of ALU instruction groups executed. Thread-type dependent. Deterministic. Should be select value 120. 0PySQ_PERF_SEL_ALU_CLAUSE_INSTRS_PER_TYPE: Number of ALU individual alu instructions executed. Thread-type dependent. Deterministic. Should be select value 121. `xzSQ_PERF_SEL_ALU_KWATERFALL_PER_TYPE: Number of ALU instruction groups which use const-waterfall. Thread-type dependent. Deterministic. Should be select value 122. {SQ_PERF_SEL_ALU_GPRWATERFALL_PER_TYPE: Number of ALU instruction groups which use gpr-waterfall. Thread-type dependent. Deterministic. Should be select value 123. تة|SQ_PERF_SEL_ALU_K_INSTR_PER_TYPE: Number of ALU instructions which use one or more constant (literal, kcache, or kfile). Thread-type dependent. Deterministic. Should be select value 124. }SQ_PERF_SEL_ALU_ICACHE_BUSY_PER_TYPE: Number of times ALU Icache read was denied - cache busy. Thread-type dependent. Should be select value 125. 8~SQ_PERF_SEL_ALU_KCACHE_BUSY_PER_TYPE: Number of times ALU Kcache/Kfile read was denied - cache busy. Thread-type dependent. Should be select value 126. 8XSQ_PERF_SEL_ALU_MOVA_IDLE_WAIT_PER_TYPE: Number of instruction cycles idle waiting for MOVA to complete. Thread-type dependent. Should be select value 127. xSQ_PERF_SEL_ALU_LOCK_WAIT: Number of times (1 every 4 clocks) ALU has clauses in input fifo but no clauses locked -- ALU is idle. Thread-type independent. Should be select value 128. SQ_PERF_SEL_ALU_ICACHE_READS_PER_TYPE: Number of read requests to the ALU I-cache. Thread-type dependent. Deterministic. Should be select value 129. మSQ_PERF_SEL_ALU_KCACHE_READS_PER_TYPE: Number of read requests to the ALU K-cache/K-file. Thread-type dependent. Deterministic. Should be select value 130. ಮSQ_PERF_SEL_ALU_DONE_FIFO_FULL: Number of times the done-fifo is full and that caused a stall. Thread-type independent. Should be select value 131. (SQ_PERF_SEL_ALU_MOVA_WAIT_PER_TYPE: Number of times more than one SIMD tried to execute MOVA, and one was denied access. Thread-type dependent. Should be select value 132. H`SQ_PERF_SEL_ALU_THREADS_IN_FIFO_PER_TYPE: Number of threads waiting in the alu-seq's input fifo each cycle, of the selected thread type. Should be select value 133. 赮SQ_PERF_SEL_UNUSED_0060SQ_PERF_SEL_UNUSED_007жSQ_PERF_SEL_TV_ICACHE_WAIT_PER_TYPE: Number of cycles the Tex/Vtx Icache denied a read request (busy). Thread-type dependent. Should be select value 136. HSQ_PERF_SEL_UNUSED_010踮SQ_PERF_SEL_UNUSED_0010SQ_PERF_SEL_UNUSED_002йSQ_PERF_SEL_TF_TA_STALL_PER_TYPE: Number of times the TF had data to send to TA, but the TA input fifo was full. Thread-type dependent. Should be select value 140. SQ_PERF_SEL_VF_VC_INSTR_STALL_PER_TYPE: Number of times the VF had data to send to VC, but the VC instruction input fifo was full. Thread-type dependent. Should be select value 141. 0@SQ_PERF_SEL_VF_VC_INDEX_STALL_PER_TYPE: Number of times the VF had data to send to VC, but the VC index input fifo was full. Thread-type dependent. Should be select value 142. нxSQ_PERF_SEL_UNUSED_003pSQ_PERF_SEL_UNUSED_008SQ_PERF_SEL_UNUSED_004XSQ_PERF_SEL_UNUSED_009wSQ_PERF_SEL_EXPORT_INSTR_PER_TYPE: Number of exports (seen by export-seq). Determinstic. Should be select value 147. {SQ_PERF_SEL_EXPORT_IDLE: Number of clocks where export unit is idle. Thread-type independent. Should be select value 148. ®SQ_PERF_SEL_EXPORT_SMX_AL_STALL: Number of clocks SMX export stalled waiting for alloc. Thread-type independent. Should be select value 149. îîSQ_PERF_SEL_EXPORT_PC_AL_STALL: Number of clocks Param.cache alloc was stalled. Thread-type independent. Should be select value 150. Į ĮSQ_PERF_SEL_EXPORT_POS_AL_STALL: Number of clocks Position export alloc was stalled. Thread-type independent. Should be select value 151. Ů0ŮSQ_PERF_SEL_EXPORT_PIX_AL_STALL: Number of clocks Pixel export alloc was stalled. Thread-type independent. Should be select value 152. Ǯ@ƮSQ_PERF_SEL_EXPORT_POS_CYCLE: Number of position export cycles (4 clocks), * burst count). Thread-type independent. Determinstic. Should be select value 153. HȮhǮSQ_PERF_SEL_EXPORT_PIX_CYCLE: Number of pixel export cycles (4 clocks), * burst count). Thread-type independent. Determinstic. Should be select value 154. pɮȮSQ_PERF_SEL_EXPORT_PC_CYCLE: Number of param.cache export cycles (4 clocks), * burst count). Thread-type independent. Determinstic. Should be select value 155. ʮɮSQ_PERF_SEL_EXPORT_SMX_CYCLE_PER_TYPE: Number of smx export cycles (4 clocks), * burst count). Thread-type dependent. Determinstic. Should be select value 156. ˮʮSQ_PERF_SEL_CACHE_INVAL_ANY: Number of cache invalidation (surface synchronization) operations of any kind. Thread-type independent. Should be select value 157. ̮ͮSQ_PERF_SEL_CACHE_INVAL_ALL: Number of cache invalidation (surface synchronization) operations that invalidate the whole cache (due to a large invalidation region). Thread-type independent. Should be select value 158. ήhͮSQ_PERF_SEL_CACHE_INVAL_CYCLES: Number of cache invalidation (surface synchronization) cycles, not including full invalidations; indicates the size of the invalidation regions in 4K byte increments. Thread-type independent. Should be select value 159. ϮήSQ_PERF_SEL_CF_ICACHE_HITS: Number of CF instruction cache hits (it was found in the cache). Thread-type independent. Should be select value 160. ЮЮSQ_PERF_SEL_TF_ICACHE_HITS: Number of TV instruction cache hits (it was found in the cache). Thread-type independent. Should be select value 161. Ѯ ѮQSQ_PERF_SEL_VF_ICACHE_HITS: DEPRECATED. Do not use. Should be select value 162. ҮѮSQ_PERF_SEL_ALU_ICACHE_HITS: Number of ALU instruction cache hits (it was found in the cache). Thread-type independent. Should be select value 163. ӮӮSQ_PERF_SEL_ALU_KCACHE_HITS: Number of ALU constant cache hits (it was found in the cache). Thread-type independent. Should be select value 164. 0ծ0ԮSQ_PERF_SEL_CF_ICACHE_MISSES: Number of CF instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 165. x֮xծSQ_PERF_SEL_TF_ICACHE_MISSES: Number of TV instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 166. P׮֮SSQ_PERF_SEL_VF_ICACHE_MISSES: DEPRECATED. Do not use. Should be select value 167. خ׮SQ_PERF_SEL_ALU_ICACHE_MISSES: Number of ALU instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 168. ٮخSQ_PERF_SEL_ALU_KCACHE_MISSES: Number of ALU constant cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 169. 8ۮ ڮSQ_PERF_SEL_CF_ICACHE_DUP_MISSES: Number of CF instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 170. ܮۮSQ_PERF_SEL_TF_ICACHE_DUP_MISSES: Number of TV instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 171. xݮܮWSQ_PERF_SEL_VF_ICACHE_DUP_MISSES: DEPRECATED. Do not use. Should be select value 172. ޮݮSQ_PERF_SEL_ALU_ICACHE_DUP_MISSES: Number of ALU instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 173. 8 ߮SQ_PERF_SEL_ALU_KCACHE_DUP_MISSES: Number of ALU constant cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 174. SQ_PERF_SEL_CF_ICACHE_ACCESSES: Number of CF instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 175. SQ_PERF_SEL_TF_ICACHE_ACCESSES: Number of TV instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 176. `USQ_PERF_SEL_VF_ICACHE_ACCESSES: DEPRECATED. Do not use. Should be select value 177. h@SQ_PERF_SEL_ALU_ICACHE_ACCESSES: Number of ALU instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 178. SQ_PERF_SEL_ALU_KCACHE_ACCESSES: Number of ALU constant cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 179. SQ_PERF_SEL_CF_ICACHE_INPUT_FIFO_ENTRIES: Count of CF instruction cache requests stored in the input FIFO. Thread-type independent. Should be select value 180. (HSQ_PERF_SEL_TF_ICACHE_INPUT_FIFO_ENTRIES: Count of TV instruction cache requests stored in the input FIFO. Thread-type independent. Should be select value 181. p_SQ_PERF_SEL_VF_ICACHE_INPUT_FIFO_ENTRIES: DEPRECATED. Do not use. Should be select value 182. 8XSQ_PERF_SEL_ALU_ICACHE_INPUT_FIFO_ENTRIES: Count of ALU instruction cache requests stored in the input FIFO. Thread-type independent. Should be select value 183. `SQ_PERF_SEL_ALU_KCACHE_INPUT_FIFO_ENTRIES: Count of ALU constant cache requests stored in the input FIFO. Thread-type independent. Should be select value 184. SQ_PERF_SEL_CF_ICACHE_MISS_MEM_STALL: Number of CF instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 185. SQ_PERF_SEL_TF_ICACHE_MISS_MEM_STALL: Number of TV instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 186. h[SQ_PERF_SEL_VF_ICACHE_MISS_MEM_STALL: DEPRECATED. Do not use. Should be select value 187. pPSQ_PERF_SEL_ALU_ICACHE_MISS_MEM_STALL: Number of ALU instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 188. SQ_PERF_SEL_ALU_KCACHE_MISS_MEM_STALL: Number of ALU constant cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 189. HSQ_PERF_SEL_CF_ICACHE_MISS_FIFO_STALL: Number of CF instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 190. SQ_PERF_SEL_TF_ICACHE_MISS_FIFO_STALL: Number of TV instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 191. \SQ_PERF_SEL_VF_ICACHE_MISS_FIFO_STALL: DEPRECATED. Do not use. Should be select value 192. SQ_PERF_SEL_ALU_ICACHE_MISS_FIFO_STALL: Number of ALU instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 193. `SQ_PERF_SEL_ALU_KCACHE_MISS_FIFO_STALL: Number of ALU constant cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 194. SQ_PERF_SEL_CF_ICACHE_HIT_STALL: Number of CF instruction cache cycles that are a cache hit but are stalled due to processing previous misses. Thread-type independent. Should be select value 195. H(SQ_PERF_SEL_CF_ICACHE_MISS_LOCKED_STALL: Number of CF instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 196. SQ_PERF_SEL_TF_ICACHE_MISS_LOCKED_STALL: Number of TV instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 197. ^SQ_PERF_SEL_VF_ICACHE_MISS_LOCKED_STALL: DEPRECATED. Do not use. Should be select value 198. SQ_PERF_SEL_ALU_ICACHE_MISS_LOCKED_STALL: Number of ALU instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 199. pPSQ_PERF_SEL_ALU_KCACHE_MISS_LOCKED_STALL: Number of ALU constant cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 200. SQ_PERF_SEL_CF_ICACHE_LOCKED_TAGS: Count of CF instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 201. SQ_PERF_SEL_TF_ICACHE_LOCKED_TAGS: Count of TV instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 202. hXSQ_PERF_SEL_VF_ICACHE_LOCKED_TAGS: DEPRECATED. Do not use. Should be select value 203. XHSQ_PERF_SEL_ALU_ICACHE_LOCKED_TAGS: Count of ALU instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 204. SQ_PERF_SEL_ALU_KCACHE_LOCKED_TAGS: Count of ALU constant cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 205. SQ_PERF_SEL_CF_ICACHE_MISS_LOCKED_TAGS: Count of CF instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 206. 0 8 SQ_PERF_SEL_TF_ICACHE_MISS_LOCKED_TAGS: Count of TV instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 207.  x ]SQ_PERF_SEL_VF_ICACHE_MISS_LOCKED_TAGS: DEPRECATED. Do not use. Should be select value 208. X ` SQ_PERF_SEL_ALU_ICACHE_MISS_LOCKED_TAGS: Count of ALU instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 209. SQ_PERF_SEL_ALU_KCACHE_MISS_LOCKED_TAGS: Count of ALU constant cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 210.  SQ_PERF_SEL_CACHE_MEM_REQUESTS: Number of cache to memory controller requests of any type. Thread-type independent. Should be select value 211. SQ_PERF_SEL_CF_ICACHE_MEM_REQUESTS: Number of CF instruction cache to memory controller requests. Thread-type independent. Should be select value 212. SQ_PERF_SEL_TV_ICACHE_MEM_REQUESTS: Number of TV instruction cache to memory controller requests. Thread-type independent. Should be select value 213. 8SQ_PERF_SEL_ALU_ICACHE_MEM_REQUESTS: Number of ALU instruction cache to memory controller requests. Thread-type independent. Should be select value 214. 0XSQ_PERF_SEL_ALU_KCACHE_MEM_REQUESTS: Number of ALU constant cache to memory controller requests. Thread-type independent. Should be select value 215. pxSQ_PERF_SEL_CF_ICACHE_RD_WR_COLLISION: Number of times a read to the CF icache memory was blocked by a write from a memory return. Thread-type independent. Should be select value 216. SQ_PERF_SEL_CF_ICACHE_MISS_HIT_RD_COLLISION: Number of times processing a hit is stalled by processing a now-resident miss. Thread-type independent. Should be select value 217. SQ_PERF_SEL_CF_ICACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding CF instruction cache to memory controller requests of any type. Thread-type independent. Should be select value 218. H@SQ_PERF_SEL_TV_ICACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding TV instruction cache to memory controller requests of any type. Thread-type independent. Should be select value 219. SQ_PERF_SEL_ALU_ICACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding ALU instruction cache to memory controller requests of any type. Thread-type independent. Should be select value 220. SQ_PERF_SEL_ALU_KCACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding ALU constant cache to memory controller requests of any type. Thread-type independent. Should be select value 221. 0SQ_PERF_SEL_CF_ICACHE_MISS_FIFO_MISSES: Count of the number of CF instruction cache misses waiting in the miss FIFO. Thread-type independent. Should be select value 222. H`SQ_PERF_SEL_TF_ICACHE_MISS_FIFO_MISSES: Count of the number of TV instruction cache misses waiting in the miss FIFO. Thread-type independent. Should be select value 223. 0]SQ_PERF_SEL_VF_ICACHE_MISS_FIFO_MISSES: DEPRECATED. Do not use. Should be select value 224. pxSQ_PERF_SEL_ALU_ICACHE_MISS_FIFO_MISSES: Count of the number of ALU instruction cache misses waiting in the miss FIFO. Divided by 2. Thread-type independent. Should be select value 225. SQ_PERF_SEL_ALU_KCACHE_MISS_FIFO_MISSES: Count of the number of ALU constant cache misses waiting in the miss FIFO. Divided by 2. Thread-type independent. Should be select value 226. ! SQ_PERF_SEL_CACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding cache to memory controller requests of any type. Divided by 2. Thread-type independent. Should be select value 227. #@"SQ_PERF_SEL_CACHE_MEM_STALL: Number of cache to memory controller cycles that are stalled. Thread-type independent. Should be select value 228. $X#qSQ_PERF_SEL_TM_TS64_STALL: Clock cycles GRBM stalled due to Timestamp-64 FIFO full. Should be select value 229. %P$SQ_PERF_SEL_TM_ALU_CONST_STALL: Clock cycles GRBM stalled due to ALU constant overflow buffer full. Should be select value 230. &X%SQ_PERF_SEL_TM_LOOP_CONST_STALL: Clock cycles GRBM stalled due to Loop constant overflow buffer full. Should be select value 231. 8'`&SQ_PERF_SEL_TM_TEX_BASE_CONST_STALL: Clock cycles GRBM stalled due to VertexBase/InstantStart constant overflow buffer full. Should be select value 232. P('SQ_PERF_SEL_TM_TEX_SAMPLER_STALL: Clock cycles GRBM stalled due to Texture Sampler constant overflow buffer full. Should be select value 233. h)(SQ_PERF_SEL_TM_TEX_RESOURCE_STALL: Clock cycles GRBM stalled due to Texture Resource constant overflow buffer full. Should be select value 234. *)SQ_PERF_SEL_UNUSED_005X+P*SQ_PERF_SEL_TA_TEX_INSTRS_PER_TYPE: Number of texture-fetch instructions executed by the Texture cache, including killed fetches. Thread-type dependent. Determinstic. Should be select value 236. ,+SQ_PERF_SEL_TA_VTX_INSTRS_PER_TYPE: Number of vertex-fetch instructions executed by the Texture cache, including killed fetches. Thread-type dependent. Determinstic. Should be select value 237. -,SQ_PERF_SEL_VC_INSTRS_PER_TYPE: Number of instructions executed by the Vertex cache, including killed fetches. Thread-type dependent. Determinstic. Should be select value 238. / .SQ_PERF_SEL_TV_LOCK_WAIT: Number of cycles the TF input FIFO had clauses, none were locked. Thread-type independent, non-deterministic. Should be select value 239. 0P/SQ_PERF_SEL_TA_SRC_C: Number of times an TA fetch (16 pix or verts) was executed as a src-c export. Non-deterministic. Should be select value 240. 81h0SQ_PERF_SEL_VC_SRC_C: Number of times a VC fetch (16 pix or verts) was executed as a src-c export. Non-deterministic. Should be select value 241. `21SQ_PERF_SEL_TV_KILLED_FETCH_PER_TYPE: Number of fetch instructions killed (vertex semantic failed or gpr out of range). Deterministic. Should be select value 242. 32SQ_PERF_SEL_TV_NULL_FETCH_PER_TYPE: Number of null fetchs issued (null = issue empty fetch at end of clause due to killed fetches). Deterministic. Should be select value 243. 43SQ_PERF_SEL_TV_THREADS_IN_FIFO_PER_TYPE: Number of threads waiting in the fetch-seq's input fifo each cycle, of the selected thread type. Should be select value 244. 55SQ_PERF_SEL_EXPORT_SPQ_LEVEL: Internal export per-quadpipe queue level average. Non-deterministic. Should be select value 245. 6ySQ_PERF_SEL_EXPORT_SPQ_STALL: Internal export per-quadpipe stall cycles. Non-deterministic. Should be select value 246. 8(7p7PS_EN0878Exclude pixel shader threads from performance counters x86Include pixel shader threads in performance counters ;H9 9VS_ENP:99Exclude vertex shader threads from performance counters :7Include vertex shader threads in performance counters 0=h; ;GS_ENp<;;Exclude geometry shader threads from performance counters <9Include geometry shader threads in performance counters P?= =ES_EN>>9Exclude export shader threads from performance counters >7Include export shader threads in performance counters A? ?MAX@0@BAccumulate performance events (if both TEST_MODE and LIVE are 0) @XRetain maximum single-cycle performance event value (if both TEST_MODE and LIVE are 0) CA 0B TEST_MODEBxB:Update performance counters based on MAX and LIVE fields 8C7Shift in 1's rather than counting, For Debugging only DPDLIVEED4Update performance counters based on the MAX field PEMRetain the current single-cycle performance event value (if TEST_MODE is 0) @˫ԌԌ""SQ_PERF_CTR5_SEL 8xSELPRSQ_PERF_SEL_NONE: don't count anything Deterministic. Should be select value 0. 0WSQ_PERF_SEL_CYCLES: Clock cycles. Thread-type independent. Should be select value 1. 8xSQ_PERF_SEL_BUSY_CYCLES: Clock cycles while SQ is reporting that it is busy. Thread-type independent. Should be select value 2. @SQ_PERF_SEL_ANY_BUSY_PER_TYPE: Number of cycles we have a thread or an event. Thread-type dependent. Should be select value 3. SQ_PERF_SEL_EVENTS_PER_TYPE: Number of events. Thread-type dependent. Caveat: Event counts are slightly unpredictable because they don't have an associated state and because we don't count events when we don't have acitve threads. Should be select value 4. uSQ_PERF_SEL_EVENTS_BUSY_PER_TYPE: Number cycles we have an event. Thread-type dependent. Should be select value 5. SQ_PERF_SEL_EVENT_LEVEL_PER_TYPE: Number of events in the pipeline per clock. Thread-type dependent. Should be select value 6. SQ_PERF_SEL_ITEMS_PER_TYPE: Number of valid items per thread. Thread-type dependent. Deterministic. Should be select value 7. SQ_PERF_SEL_ITEMS_GT_48_PER_TYPE: Number of threads with a valid item in a position >= 48. Thread-type dependent. Deterministic. Should be select value 8. (H SQ_PERF_SEL_ITEMS_GT_32_PER_TYPE: Number of threads with a valid item in a position >= 32. Thread-type dependent. Deterministic. Should be select value 9. Pp SQ_PERF_SEL_ITEMS_GT_16_PER_TYPE: Number of threads with a valid item in a position >= 16. Thread-type dependent. Deterministic. Should be select value 10. H nSQ_PERF_SEL_QUADS: Number of valid pixel shader quads per thread. Deterministic. Should be select value 11. H wSQ_PERF_SEL_THREADS_BUSY_PER_TYPE: Number cycles we have a thread. Thread-type dependent. Should be select value 12. @ tSQ_PERF_SEL_THREADS_PER_TYPE: Number of threads. Thread-type dependent. Deterministic Should be select value 13. HSQ_PERF_SEL_THREAD_LEVEL_PER_TYPE: Number of threads in the pipeline per clock. Thread-type dependent. Should be select value 14. XSQ_PERF_SEL_THREAD_LEVEL_WAIT_CREATE_PER_TYPE: Number of threads waiting to be created. Thread-type dependent. Should be select value 15. xSQ_PERF_SEL_THREAD_LEVEL_UNALLOC_PARAM_PER_TYPE: Number of threads with parameter cache unallocated. Thread-type dependent. Should be select value 16. SQ_PERF_SEL_THREAD_LEVEL_UNALLOC_PIX_PER_TYPE: Number of threads with pixel buffer unallocated. Thread-type dependent. Should be select value 17. SQ_PERF_SEL_THREAD_LEVEL_UNALLOC_POS_PER_TYPE: Number of threads with position buffer unallocated. Thread-type dependent. Should be select value 18. SQ_PERF_SEL_THREADS_NONPS: Number of existing non-PS threads sharing the set of enabled thread-types with other selected NONPS counters. Should be select value 19.  ( SQ_PERF_SEL_THREAD_LEVEL_NONPS: Number of existing non-PS threads per cycle sharing the set of enabled thread-types with other selected NONPS counters. Should be select value 20. x ` SQ_PERF_SEL_THREAD_LEVEL_WAIT_ALLOC_NONPS: Number of non-PS threads waiting for export space to be allocated. Must share the set of enabled thread-types with other selected NONPS counters. Should be select value 21.  SQ_PERF_SEL_THREAD_LEVEL_WAIT_OTHER_NONPS: Number of non-PS threads waiting for instructions to be fetched or completed. Must share the set of enabled thread-types with other selected SHARED_TYPESET counters. Should be select value 22. 8SQ_PERF_SEL_THREAD_LEVEL_WAIT_ALLOC_PS: Number of PS threads waiting for pixel buffer to be allocated. Should be select value 23. @SQ_PERF_SEL_THREAD_LEVEL_WAIT_OTHER_PS: Number of PS threads waiting for for instructions to be fetched or completed. Should be select value 24. XSQ_PERF_SEL_CF_INST_ISSUES_PER_TYPE: Number of CF instruction issues. Thread-type dependent. Deterministic. Should be select value 25. @hSQ_PERF_SEL_CF_INST_ISSUE_ONE: Number of times only a single instruction is issued on a cycle. Thread-type independent. Should be select value 26. XSQ_PERF_SEL_CF_INST_ISSUE_TWO: Number of times two instructions are issued in a single cycle. Thread-type independent. Should be select value 27. SQ_PERF_SEL_CF_INST_ISSUE_IDLE_PER_TYPE: Number of cycles when threads exist but no threads are ready to issue. Thread-type dependent. Should be select value 28. SQ_PERF_SEL_CF_INST_ISSUE_FS_PER_TYPE: Number of instructions executed in Fetch Shader Mode. Does not include initial CALL_FS instruction. Thread-type dependent. Deterministic. Should be select value 29.  SQ_PERF_SEL_CF_INST_ISSUE_ALU_PER_TYPE: Number of CF_ALU instructions issued. Thread-type dependent. Deterministic. Should be select value 30. 8SQ_PERF_SEL_CF_INST_ISSUE_TF_PER_TYPE: Number of CF_TF instructions issued. Thread-type dependent. Deterministic. Should be select value 31. P SQ_PERF_SEL_CF_INST_ISSUE_VF_PER_TYPE: Number of CF_VF instructions issued. Thread-type dependent. Deterministic. Should be select value 32. 8h!SQ_PERF_SEL_CF_INST_ISSUE_EX_PER_TYPE: Number of Export instructions issued. Thread-type dependent. Deterministic. Should be select value 33. X"SQ_PERF_SEL_CF_INST_ISSUE_SMX_WR_PER_TYPE: Number of SMX write instructions issued. Thread-type dependent. Deterministic. Should be select value 34. x#SQ_PERF_SEL_CF_INST_ISSUE_SMX_RD_PER_TYPE: Number of SMX read instructions issued. Thread-type dependent. Deterministic. Should be select value 35. $SQ_PERF_SEL_CF_INST_ISSUE_GF_PER_TYPE: Number of geometry instructions issued. Thread-type dependent. Deterministic. Should be select value 36. %SQ_PERF_SEL_CF_INST_ISSUE_OTHER_PER_TYPE: Number of non-ALU/TF/VF/EX/SMX/GF instructions issued. Thread-type dependent. Deterministic. Should be select value 37.  &SQ_PERF_SEL_CF_INST_ISSUE_ALU_CF_PER_TYPE: Number of ALU CF tags processed. Thread-type dependent. Deterministic. Should be select value 38. ! !'SQ_PERF_SEL_CF_INST_ISSUE_BL_PER_TYPE: Number of OTHER and ALU CF tags processed. Thread-type dependent. Deterministic. Should be select value 39. (#@"(SQ_PERF_SEL_CF_INST_REJECT_ALU_PER_TYPE: Number of ALU instructions scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 40. p$p#)SQ_PERF_SEL_CF_INST_REJECT_TF_PER_TYPE: Number of times a Texture Fetch instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 41. %$*SQ_PERF_SEL_CF_INST_REJECT_VF_PER_TYPE: Number of times a Vertex Fetch instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 42. &%+SQ_PERF_SEL_CF_INST_REJECT_EX_PER_TYPE: Number of times an Export instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 43. 8(8',SQ_PERF_SEL_CF_INST_REJECT_SMX_WR_PER_TYPE: Number of times a SMX write instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 44. x)(-SQ_PERF_SEL_CF_INST_REJECT_SMX_RD_PER_TYPE: Number of times a SMX read instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 45. *).SQ_PERF_SEL_CF_INST_REJECT_GF_PER_TYPE: Number of geometry instructions trivially rejected. Thread-type dependent. Deterministic. Should be select value 46. +*/SQ_PERF_SEL_CF_INST_REJECT_OTHER_PER_TYPE: Number of non-ALU/TF/VF/EX/SMX/GF instructions rejected. Thread-type dependent. Deterministic. Should be select value 47. ,,0SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_PER_TYPE: Number of instructions sent to ALU. Thread-type dependent. Deterministic. Should be select value 48. .0-1SQ_PERF_SEL_CF_INST_FIFO_SEND_TF_PER_TYPE: Number of instructions sent to Texture Fetch unit. Thread-type dependent. Deterministic. Should be select value 49. 8/X.2SQ_PERF_SEL_CF_INST_FIFO_SEND_VF_PER_TYPE: Number of instructions sent to Vertex Fetch unit. Thread-type dependent. Deterministic. Should be select value 50. X0/3SQ_PERF_SEL_CF_INST_FIFO_SEND_EX_PER_TYPE: Number of instructions sent to Export unit. Thread-type dependent. Deterministic. Should be select value 51. 104SQ_PERF_SEL_CF_INST_FIFO_SEND_SMX_WR_PER_TYPE: Number of write instructions sent to SMX Export unit. Thread-type dependent. Deterministic. Should be select value 52. 215SQ_PERF_SEL_CF_INST_FIFO_SEND_SMX_RD_PER_TYPE: Number of read instructions sent to SMX Export unit. Thread-type dependent. Deterministic. Should be select value 53. 336SQ_PERF_SEL_CF_INST_FIFO_SEND_GF_PER_TYPE: Number of geometry instructions executed. Thread-type dependent. Deterministic. Should be select value 54. 5 47SQ_PERF_SEL_CF_INST_FIFO_SEND_OTHER_PER_TYPE: Number of non-ALU/TF/VF/EX/SMX/GF instructions executed. Thread-type dependent. Deterministic. Should be select value 55. P6P58SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_NONE_PER_TYPE: Number of instructions sent to ALU with no kcache regions locked. Thread-type dependent. Deterministic. Should be select value 56. 769SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_ONE_PER_TYPE: Number of instructions sent to ALU with one kcache regions locked. Thread-type dependent. Deterministic. Should be select value 57. 87:SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_TWO_PER_TYPE: Number of instructions sent to ALU with two kcache regions locked. Thread-type dependent. Deterministic. Should be select value 58. :(9;SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_PER_TYPE: Number of kcache region locks in instructions sent to ALU. Thread-type dependent. Deterministic. Should be select value 59. ;`:<~SQ_PERF_SEL_CF_INST_FIFO_FULL_ALU: Number of ALU units full on a cycle. Thread-type independent. Should be select value 60. 0<h;=SQ_PERF_SEL_CF_INST_FIFO_FULL_TF: Number of cycles the Texture Fetch unit was full. Thread-type independent. Should be select value 61. @=x<>SQ_PERF_SEL_CF_INST_FIFO_FULL_VF: Number of cycles the Vertex Fetch unit was full. Thread-type independent. Should be select value 62. H>=?SQ_PERF_SEL_CF_INST_FIFO_FULL_EX: Number of cycles the Export unit was full. Thread-type independent. Should be select value 63. X?>@SQ_PERF_SEL_CF_INST_FIFO_FULL_SMX: Number of cycles the SMX Export unit was full. Thread-type independent. Should be select value 64. h@?ASQ_PERF_SEL_CF_INST_FIFO_FULL_GF: Number of cycles the Geometry Fifo was full. Thread-type independent. Should be select value 65. 8A@BKSQ_PERF_SEL_CF_INST_FIFO_FULL_OTHER: Reserved. Should be select value 66. HBACSQ_PERF_SEL_CF_INST_FIFO_LEVEL_ALU: Number of credits available for all ALU units. Thread-type independent. Should be select value 67. PCBDSQ_PERF_SEL_CF_INST_FIFO_LEVEL_TF: Number of credits available for TF unit. Thread-type independent. Should be select value 68. XDCESQ_PERF_SEL_CF_INST_FIFO_LEVEL_VF: Number of credits available for VF unit. Thread-type independent. Should be select value 69. `EDFSQ_PERF_SEL_CF_INST_FIFO_LEVEL_EX: Number of credits available for EX unit. Thread-type independent. Should be select value 70. hFEGSQ_PERF_SEL_CF_INST_FIFO_LEVEL_SMX: Number of credits available for SMX unit. Thread-type independent. Should be select value 71. xGFHSQ_PERF_SEL_CF_INST_FIFO_LEVEL_GF: Number of credits available for Geometry Fifo. Thread-type independent. Should be select value 72. HHGILSQ_PERF_SEL_CF_INST_FIFO_LEVEL_OTHER: Reserved. Should be select value 73. PIHJSQ_PERF_SEL_CF_INST_FIFO_EMPTY_ALU: Number of ALU units empty on a cycle. Thread-type independent. Should be select value 74. `JIKSQ_PERF_SEL_CF_INST_FIFO_EMPTY_TF: Number of cycles the Texture Fetch unit was empty. Thread-type independent. Should be select value 75. pKJLSQ_PERF_SEL_CF_INST_FIFO_EMPTY_VF: Number of cycles the Vertex Fetch unit was empty. Thread-type independent. Should be select value 76. LKMSQ_PERF_SEL_CF_INST_FIFO_EMPTY_EX: Number of cycles the Export unit was empty. Thread-type independent. Should be select value 77. MLNSQ_PERF_SEL_CF_INST_FIFO_EMPTY_SMX: Number of cycles the SMX unit was empty. Thread-type independent. Should be select value 78. NMOSQ_PERF_SEL_CF_INST_FIFO_EMPTY_GF: Number of cycles the Geometry fifo was empty. Thread-type independent. Should be select value 79. hONPLSQ_PERF_SEL_CF_INST_FIFO_EMPTY_OTHER: Reserved. Should be select value 80. POQSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_ALU_PER_TYPE: Number of instructions outstanding for all ALU units. Thread-type dependent. Should be select value 81. QPRSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_TF_PER_TYPE: Number of instructions outstanding for TF unit. Thread-type dependent. Should be select value 82. RQSSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_VF_PER_TYPE: Number of instructions outstanding for VF unit. Thread-type ependent. Should be select value 83. SSTSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_EX_PER_TYPE: Number of instructions outstanding for EX unit. Thread-type dependent. Should be select value 84. TTUSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_SMX_WR_PER_TYPE: Number of write instructions outstanding for SMX unit. Thread-type dependent. Should be select value 85. V8UVSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_SMX_RD_PER_TYPE: Number of read instructions outstanding for SMX unit. Thread-type dependent. Should be select value 86. 0WXVWSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_GF_PER_TYPE: Number of instructions outstanding for Geometry Fifo. Thread-type dependent. Should be select value 87. XXxWXSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_OTHER_PER_TYPE: Number of instructions outstanding for non-ALU/TF/VF/EX/SMX/GF. Thread-type dependent. Should be select value 88. `YXYSQ_PERF_SEL_CF_INST_CHECKPOINT: Number of times user specified CF address is executed. Deterministic. Should be select value 89. ZYZSQ_PERF_SEL_CF_INST_CHECKPOINT_BEFORE: Number of CF instructions executed including and after the specified CF address. Deterministic. Should be select value 90. [Z[SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_VALID: Number of items valid for execution of instruction at CF address. Deterministic. Should be select value 91. \[\SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_VALID_NONE: Number of times no items are valid for execution of instruction at CF address. Deterministic. Should be select value 92. 8^ ]]SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_ACTIVE: Number of items active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 93. _^^SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_ACTIVE_NONE: Number of times no items are active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 94. a__SQ_PERF_SEL_CF_INST_CHECKPOINT_QUADS_ACTIVE: Number of pixel quads active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 95. b`a`SQ_PERF_SEL_CF_INST_CHECKPOINT_QUADS_VALID: Number of pixel quads valid for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 96. cbaSQ_PERF_SEL_CF_INST_CHECKPOINT_THREADS: Number of times a thread first reaches the CF address. Deterministic. Should be select value 97. dcbSQ_PERF_SEL_CF_INST_CHECKPOINT_THREAD_LEVEL: Number of threads that have reached the CF address per cycle. Should be select value 98. edcSQ_PERF_SEL_CF_INST_FETCH_PER_TYPE: Number of CF fetch requests from cache. Thread-type dependent. Should be select value 99. fedSQ_PERF_SEL_CF_INST_FETCH_RETURNS_PER_TYPE: Number of CF fetch return cycles from cache. Thread-type dependent. Should be select value 100. ggeSQ_PERF_SEL_CF_INST_FETCH_INSTS_PER_TYPE: Number of CF instructions requested from cache. Thread-type dependent. Should be select value 101. h hfSQ_PERF_SEL_CF_INST_FETCH_LEVEL_PER_TYPE: Number of CF fetch requests from cache pending per cycle. Thread-type dependent. Should be select value 102. `j@igSQ_PERF_SEL_CF_INST_FETCH_EXTRA_PER_TYPE: Number of times we didn't issue the second instruction in a pair. Does not include instructions after PROGRAM_END. Thread-type dependent. Deterministic. Should be select value 103. xkjhSQ_PERF_SEL_CF_INST_FETCH_FIFO_SEND: Number of requests passing through the fetch fifo. Thread-type independent. Should be select value 104. lkiSQ_PERF_SEL_CF_INST_FETCH_FIFO_LEVEL: Control Flow Fetch fifo entry level. Thread-type independent. Should be select value 105. mljSQ_PERF_SEL_CF_INST_FETCH_FIFO_STALL: Number of cycles when the CF fetch fifo is stalling issues. Thread-type independent. Should be select value 106. nmkSQ_PERF_SEL_CF_INST_CACHE_FIFO_SEND: Number of requests passing through the cache fifo. Thread-type independent. Should be select value 107. oolySQ_PERF_SEL_CF_INST_CACHE_FIFO_LEVEL: Number of credits in cache. Thread-type independent. Should be select value 108. ppmSQ_PERF_SEL_CF_INST_CACHE_FIFO_FULL: Number of cycles when we have no cache credits. Thread-type independent. Should be select value 109. rqnSQ_PERF_SEL_CF_INST_ISSUE_DONES: Number of issues that need to be accounted for to avoid overflowing the done fifo. Thread-type independent. Should be select value 110. PsHroSQ_PERF_SEL_CF_INST_ISSUE_DONE_LEVEL: Number of issues pending at any given time that need to be accounted for to avoid overflowing the done fifo. Thread-type independent. Should be select value 111. htspSQ_PERF_SEL_CF_INST_ISSUE_DONE_STALL: Stalls triggered to avoid overflowing the done fifo. Thread-type independent. Should be select value 112. utqSQ_PERF_SEL_CF_INST_ISSUE_DONE_FIFO_SEND: Number of items passing through the done fifo. Thread-type independent. Should be select value 113. vurSQ_PERF_SEL_CF_INST_ISSUE_DONE_FIFO_LEVEL: Control Flow Done fifo entry level. Thread-type independent. Should be select value 114. wvsSQ_PERF_SEL_CF_INST_ALU_UPDATE_FIFO_SEND: Macro sequencer alu update fifo send. Thread-type independent. Should be select value 115. xwtSQ_PERF_SEL_CF_INST_ALU_UPDATE_FIFO_LEVEL: Macro sequencer alu update fifo level. Thread-type independent. Should be select value 116. yxuSQ_PERF_SEL_CF_INST_ALU_UPDATE_FIFO_STALL: Number of cycles when the MS alu update fifo is stalling issues and alu returns. Thread-type independent. Should be select value 117. z0zvSQ_PERF_SEL_OFIFO_LEVEL_PER_TYPE: Number of threads and events in the ofifo. Thread-type dependent. Should be select value 118. |8{wSQ_PERF_SEL_SX_EVENT_FIFO_FULL_PER_TYPE: Number of cycles the SX event fifo is full. Thread-type dependent. Should be select value 119. (}H|xSQ_PERF_SEL_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE: Number of ALU instruction groups executed. Thread-type dependent. Deterministic. Should be select value 120. P~p}ySQ_PERF_SEL_ALU_CLAUSE_INSTRS_PER_TYPE: Number of ALU individual alu instructions executed. Thread-type dependent. Deterministic. Should be select value 121. ~zSQ_PERF_SEL_ALU_KWATERFALL_PER_TYPE: Number of ALU instruction groups which use const-waterfall. Thread-type dependent. Deterministic. Should be select value 122. {SQ_PERF_SEL_ALU_GPRWATERFALL_PER_TYPE: Number of ALU instruction groups which use gpr-waterfall. Thread-type dependent. Deterministic. Should be select value 123. |SQ_PERF_SEL_ALU_K_INSTR_PER_TYPE: Number of ALU instructions which use one or more constant (literal, kcache, or kfile). Thread-type dependent. Deterministic. Should be select value 124. @}SQ_PERF_SEL_ALU_ICACHE_BUSY_PER_TYPE: Number of times ALU Icache read was denied - cache busy. Thread-type dependent. Should be select value 125. 0X~SQ_PERF_SEL_ALU_KCACHE_BUSY_PER_TYPE: Number of times ALU Kcache/Kfile read was denied - cache busy. Thread-type dependent. Should be select value 126. XxSQ_PERF_SEL_ALU_MOVA_IDLE_WAIT_PER_TYPE: Number of instruction cycles idle waiting for MOVA to complete. Thread-type dependent. Should be select value 127. SQ_PERF_SEL_ALU_LOCK_WAIT: Number of times (1 every 4 clocks) ALU has clauses in input fifo but no clauses locked -- ALU is idle. Thread-type independent. Should be select value 128. SQ_PERF_SEL_ALU_ICACHE_READS_PER_TYPE: Number of read requests to the ALU I-cache. Thread-type dependent. Deterministic. Should be select value 129. SQ_PERF_SEL_ALU_KCACHE_READS_PER_TYPE: Number of read requests to the ALU K-cache/K-file. Thread-type dependent. Deterministic. Should be select value 130. (SQ_PERF_SEL_ALU_DONE_FIFO_FULL: Number of times the done-fifo is full and that caused a stall. Thread-type independent. Should be select value 131. 8HSQ_PERF_SEL_ALU_MOVA_WAIT_PER_TYPE: Number of times more than one SIMD tried to execute MOVA, and one was denied access. Thread-type dependent. Should be select value 132. hSQ_PERF_SEL_ALU_THREADS_IN_FIFO_PER_TYPE: Number of threads waiting in the alu-seq's input fifo each cycle, of the selected thread type. Should be select value 133. SQ_PERF_SEL_UNUSED_006PSQ_PERF_SEL_UNUSED_007ȎSQ_PERF_SEL_TV_ICACHE_WAIT_PER_TYPE: Number of cycles the Tex/Vtx Icache denied a read request (busy). Thread-type dependent. Should be select value 136. hSQ_PERF_SEL_UNUSED_010SQ_PERF_SEL_UNUSED_001PSQ_PERF_SEL_UNUSED_002ؑSQ_PERF_SEL_TF_TA_STALL_PER_TYPE: Number of times the TF had data to send to TA, but the TA input fifo was full. Thread-type dependent. Should be select value 140.  SQ_PERF_SEL_VF_VC_INSTR_STALL_PER_TYPE: Number of times the VF had data to send to VC, but the VC instruction input fifo was full. Thread-type dependent. Should be select value 141. P`SQ_PERF_SEL_VF_VC_INDEX_STALL_PER_TYPE: Number of times the VF had data to send to VC, but the VC index input fifo was full. Thread-type dependent. Should be select value 142. SQ_PERF_SEL_UNUSED_0038SQ_PERF_SEL_UNUSED_0080ؕSQ_PERF_SEL_UNUSED_004ЖxSQ_PERF_SEL_UNUSED_009ЗwSQ_PERF_SEL_EXPORT_INSTR_PER_TYPE: Number of exports (seen by export-seq). Determinstic. Should be select value 147. И{SQ_PERF_SEL_EXPORT_IDLE: Number of clocks where export unit is idle. Thread-type independent. Should be select value 148. 虭SQ_PERF_SEL_EXPORT_SMX_AL_STALL: Number of clocks SMX export stalled waiting for alloc. Thread-type independent. Should be select value 149. 0SQ_PERF_SEL_EXPORT_PC_AL_STALL: Number of clocks Param.cache alloc was stalled. Thread-type independent. Should be select value 150. @SQ_PERF_SEL_EXPORT_POS_AL_STALL: Number of clocks Position export alloc was stalled. Thread-type independent. Should be select value 151. PSQ_PERF_SEL_EXPORT_PIX_AL_STALL: Number of clocks Pixel export alloc was stalled. Thread-type independent. Should be select value 152. @`SQ_PERF_SEL_EXPORT_POS_CYCLE: Number of position export cycles (4 clocks), * burst count). Thread-type independent. Determinstic. Should be select value 153. hSQ_PERF_SEL_EXPORT_PIX_CYCLE: Number of pixel export cycles (4 clocks), * burst count). Thread-type independent. Determinstic. Should be select value 154. SQ_PERF_SEL_EXPORT_PC_CYCLE: Number of param.cache export cycles (4 clocks), * burst count). Thread-type independent. Determinstic. Should be select value 155. ؠSQ_PERF_SEL_EXPORT_SMX_CYCLE_PER_TYPE: Number of smx export cycles (4 clocks), * burst count). Thread-type dependent. Determinstic. Should be select value 156. ࢭSQ_PERF_SEL_CACHE_INVAL_ANY: Number of cache invalidation (surface synchronization) operations of any kind. Thread-type independent. Should be select value 157. @(SQ_PERF_SEL_CACHE_INVAL_ALL: Number of cache invalidation (surface synchronization) operations that invalidate the whole cache (due to a large invalidation region). Thread-type independent. Should be select value 158. ȥSQ_PERF_SEL_CACHE_INVAL_CYCLES: Number of cache invalidation (surface synchronization) cycles, not including full invalidations; indicates the size of the invalidation regions in 4K byte increments. Thread-type independent. Should be select value 159. ভSQ_PERF_SEL_CF_ICACHE_HITS: Number of CF instruction cache hits (it was found in the cache). Thread-type independent. Should be select value 160. (SQ_PERF_SEL_TF_ICACHE_HITS: Number of TV instruction cache hits (it was found in the cache). Thread-type independent. Should be select value 161. Ш@QSQ_PERF_SEL_VF_ICACHE_HITS: DEPRECATED. Do not use. Should be select value 162. SQ_PERF_SEL_ALU_ICACHE_HITS: Number of ALU instruction cache hits (it was found in the cache). Thread-type independent. Should be select value 163. 8SQ_PERF_SEL_ALU_KCACHE_HITS: Number of ALU constant cache hits (it was found in the cache). Thread-type independent. Should be select value 164. PPSQ_PERF_SEL_CF_ICACHE_MISSES: Number of CF instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 165. SQ_PERF_SEL_TF_ICACHE_MISSES: Number of TV instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 166. p୭SSQ_PERF_SEL_VF_ICACHE_MISSES: DEPRECATED. Do not use. Should be select value 167. SQ_PERF_SEL_ALU_ICACHE_MISSES: Number of ALU instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 168. SQ_PERF_SEL_ALU_KCACHE_MISSES: Number of ALU constant cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 169. `HSQ_PERF_SEL_CF_ICACHE_DUP_MISSES: Number of CF instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 170. SQ_PERF_SEL_TF_ICACHE_DUP_MISSES: Number of TV instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 171. WSQ_PERF_SEL_VF_ICACHE_DUP_MISSES: DEPRECATED. Do not use. Should be select value 172. 购SQ_PERF_SEL_ALU_ICACHE_DUP_MISSES: Number of ALU instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 173. `HSQ_PERF_SEL_ALU_KCACHE_DUP_MISSES: Number of ALU constant cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 174. иSQ_PERF_SEL_CF_ICACHE_ACCESSES: Number of CF instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 175. @SQ_PERF_SEL_TF_ICACHE_ACCESSES: Number of TV instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 176. USQ_PERF_SEL_VF_ICACHE_ACCESSES: DEPRECATED. Do not use. Should be select value 177. hSQ_PERF_SEL_ALU_ICACHE_ACCESSES: Number of ALU instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 178. ؼSQ_PERF_SEL_ALU_KCACHE_ACCESSES: Number of ALU constant cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 179. (HSQ_PERF_SEL_CF_ICACHE_INPUT_FIFO_ENTRIES: Count of CF instruction cache requests stored in the input FIFO. Thread-type independent. Should be select value 180. PpSQ_PERF_SEL_TF_ICACHE_INPUT_FIFO_ENTRIES: Count of TV instruction cache requests stored in the input FIFO. Thread-type independent. Should be select value 181. 8_SQ_PERF_SEL_VF_ICACHE_INPUT_FIFO_ENTRIES: DEPRECATED. Do not use. Should be select value 182. `­SQ_PERF_SEL_ALU_ICACHE_INPUT_FIFO_ENTRIES: Count of ALU instruction cache requests stored in the input FIFO. Thread-type independent. Should be select value 183. í­SQ_PERF_SEL_ALU_KCACHE_INPUT_FIFO_ENTRIES: Count of ALU constant cache requests stored in the input FIFO. Thread-type independent. Should be select value 184. ĭíSQ_PERF_SEL_CF_ICACHE_MISS_MEM_STALL: Number of CF instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 185. Hƭ0ŭSQ_PERF_SEL_TF_ICACHE_MISS_MEM_STALL: Number of TV instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 186. (ǭƭ[SQ_PERF_SEL_VF_ICACHE_MISS_MEM_STALL: DEPRECATED. Do not use. Should be select value 187. ȭpǭSQ_PERF_SEL_ALU_ICACHE_MISS_MEM_STALL: Number of ALU instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 188. ɭȭSQ_PERF_SEL_ALU_KCACHE_MISS_MEM_STALL: Number of ALU constant cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 189. h˭8ʭSQ_PERF_SEL_CF_ICACHE_MISS_FIFO_STALL: Number of CF instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 190. ̭˭SQ_PERF_SEL_TF_ICACHE_MISS_FIFO_STALL: Number of TV instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 191. ͭ(ͭ\SQ_PERF_SEL_VF_ICACHE_MISS_FIFO_STALL: DEPRECATED. Do not use. Should be select value 192. 8ϭέSQ_PERF_SEL_ALU_ICACHE_MISS_FIFO_STALL: Number of ALU instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 193. ЭϭSQ_PERF_SEL_ALU_KCACHE_MISS_FIFO_STALL: Number of ALU constant cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 194. ҭЭSQ_PERF_SEL_CF_ICACHE_HIT_STALL: Number of CF instruction cache cycles that are a cache hit but are stalled due to processing previous misses. Thread-type independent. Should be select value 195. hӭHҭSQ_PERF_SEL_CF_ICACHE_MISS_LOCKED_STALL: Number of CF instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 196. ԭӭSQ_PERF_SEL_TF_ICACHE_MISS_LOCKED_STALL: Number of TV instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 197. խխ^SQ_PERF_SEL_VF_ICACHE_MISS_LOCKED_STALL: DEPRECATED. Do not use. Should be select value 198. ׭֭SQ_PERF_SEL_ALU_ICACHE_MISS_LOCKED_STALL: Number of ALU instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 199. حh׭SQ_PERF_SEL_ALU_KCACHE_MISS_LOCKED_STALL: Number of ALU constant cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 200. ٭حSQ_PERF_SEL_CF_ICACHE_LOCKED_TAGS: Count of CF instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 201. 8ۭ(ڭSQ_PERF_SEL_TF_ICACHE_LOCKED_TAGS: Count of TV instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 202. ܭۭXSQ_PERF_SEL_VF_ICACHE_LOCKED_TAGS: DEPRECATED. Do not use. Should be select value 203. pݭ`ܭSQ_PERF_SEL_ALU_ICACHE_LOCKED_TAGS: Count of ALU instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 204. ޭݭSQ_PERF_SEL_ALU_KCACHE_LOCKED_TAGS: Count of ALU constant cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 205. ߭SQ_PERF_SEL_CF_ICACHE_MISS_LOCKED_TAGS: Count of CF instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 206. HPSQ_PERF_SEL_TF_ICACHE_MISS_LOCKED_TAGS: Count of TV instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 207. 0]SQ_PERF_SEL_VF_ICACHE_MISS_LOCKED_TAGS: DEPRECATED. Do not use. Should be select value 208. pxSQ_PERF_SEL_ALU_ICACHE_MISS_LOCKED_TAGS: Count of ALU instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 209. SQ_PERF_SEL_ALU_KCACHE_MISS_LOCKED_TAGS: Count of ALU constant cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 210. SQ_PERF_SEL_CACHE_MEM_REQUESTS: Number of cache to memory controller requests of any type. Thread-type independent. Should be select value 211. SQ_PERF_SEL_CF_ICACHE_MEM_REQUESTS: Number of CF instruction cache to memory controller requests. Thread-type independent. Should be select value 212. 0SQ_PERF_SEL_TV_ICACHE_MEM_REQUESTS: Number of TV instruction cache to memory controller requests. Thread-type independent. Should be select value 213. (PSQ_PERF_SEL_ALU_ICACHE_MEM_REQUESTS: Number of ALU instruction cache to memory controller requests. Thread-type independent. Should be select value 214. HpSQ_PERF_SEL_ALU_KCACHE_MEM_REQUESTS: Number of ALU constant cache to memory controller requests. Thread-type independent. Should be select value 215. SQ_PERF_SEL_CF_ICACHE_RD_WR_COLLISION: Number of times a read to the CF icache memory was blocked by a write from a memory return. Thread-type independent. Should be select value 216. SQ_PERF_SEL_CF_ICACHE_MISS_HIT_RD_COLLISION: Number of times processing a hit is stalled by processing a now-resident miss. Thread-type independent. Should be select value 217. SQ_PERF_SEL_CF_ICACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding CF instruction cache to memory controller requests of any type. Thread-type independent. Should be select value 218. `XSQ_PERF_SEL_TV_ICACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding TV instruction cache to memory controller requests of any type. Thread-type independent. Should be select value 219. SQ_PERF_SEL_ALU_ICACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding ALU instruction cache to memory controller requests of any type. Thread-type independent. Should be select value 220. SQ_PERF_SEL_ALU_KCACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding ALU constant cache to memory controller requests of any type. Thread-type independent. Should be select value 221. 0HSQ_PERF_SEL_CF_ICACHE_MISS_FIFO_MISSES: Count of the number of CF instruction cache misses waiting in the miss FIFO. Thread-type independent. Should be select value 222. `xSQ_PERF_SEL_TF_ICACHE_MISS_FIFO_MISSES: Count of the number of TV instruction cache misses waiting in the miss FIFO. Thread-type independent. Should be select value 223. H]SQ_PERF_SEL_VF_ICACHE_MISS_FIFO_MISSES: DEPRECATED. Do not use. Should be select value 224. SQ_PERF_SEL_ALU_ICACHE_MISS_FIFO_MISSES: Count of the number of ALU instruction cache misses waiting in the miss FIFO. Divided by 2. Thread-type independent. Should be select value 225. SQ_PERF_SEL_ALU_KCACHE_MISS_FIFO_MISSES: Count of the number of ALU constant cache misses waiting in the miss FIFO. Divided by 2. Thread-type independent. Should be select value 226. SQ_PERF_SEL_CACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding cache to memory controller requests of any type. Divided by 2. Thread-type independent. Should be select value 227. (XSQ_PERF_SEL_CACHE_MEM_STALL: Number of cache to memory controller cycles that are stalled. Thread-type independent. Should be select value 228. pqSQ_PERF_SEL_TM_TS64_STALL: Clock cycles GRBM stalled due to Timestamp-64 FIFO full. Should be select value 229. (hSQ_PERF_SEL_TM_ALU_CONST_STALL: Clock cycles GRBM stalled due to ALU constant overflow buffer full. Should be select value 230. 0pSQ_PERF_SEL_TM_LOOP_CONST_STALL: Clock cycles GRBM stalled due to Loop constant overflow buffer full. Should be select value 231. PxSQ_PERF_SEL_TM_TEX_BASE_CONST_STALL: Clock cycles GRBM stalled due to VertexBase/InstantStart constant overflow buffer full. Should be select value 232. hSQ_PERF_SEL_TM_TEX_SAMPLER_STALL: Clock cycles GRBM stalled due to Texture Sampler constant overflow buffer full. Should be select value 233. SQ_PERF_SEL_TM_TEX_RESOURCE_STALL: Clock cycles GRBM stalled due to Texture Resource constant overflow buffer full. Should be select value 234. SQ_PERF_SEL_UNUSED_005phSQ_PERF_SEL_TA_TEX_INSTRS_PER_TYPE: Number of texture-fetch instructions executed by the Texture cache, including killed fetches. Thread-type dependent. Determinstic. Should be select value 236. SQ_PERF_SEL_TA_VTX_INSTRS_PER_TYPE: Number of vertex-fetch instructions executed by the Texture cache, including killed fetches. Thread-type dependent. Determinstic. Should be select value 237. SQ_PERF_SEL_VC_INSTRS_PER_TYPE: Number of instructions executed by the Vertex cache, including killed fetches. Thread-type dependent. Determinstic. Should be select value 238. 8SQ_PERF_SEL_TV_LOCK_WAIT: Number of cycles the TF input FIFO had clauses, none were locked. Thread-type independent, non-deterministic. Should be select value 239. 8hSQ_PERF_SEL_TA_SRC_C: Number of times an TA fetch (16 pix or verts) was executed as a src-c export. Non-deterministic. Should be select value 240. PSQ_PERF_SEL_VC_SRC_C: Number of times a VC fetch (16 pix or verts) was executed as a src-c export. Non-deterministic. Should be select value 241. x SQ_PERF_SEL_TV_KILLED_FETCH_PER_TYPE: Number of fetch instructions killed (vertex semantic failed or gpr out of range). Deterministic. Should be select value 242. SQ_PERF_SEL_TV_NULL_FETCH_PER_TYPE: Number of null fetchs issued (null = issue empty fetch at end of clause due to killed fetches). Deterministic. Should be select value 243. SQ_PERF_SEL_TV_THREADS_IN_FIFO_PER_TYPE: Number of threads waiting in the fetch-seq's input fifo each cycle, of the selected thread type. Should be select value 244. ( SQ_PERF_SEL_EXPORT_SPQ_LEVEL: Internal export per-quadpipe queue level average. Non-deterministic. Should be select value 245. 0 ySQ_PERF_SEL_EXPORT_SPQ_STALL: Internal export per-quadpipe stall cycles. Non-deterministic. Should be select value 246. @PS_ENH8Exclude pixel shader threads from performance counters 6Include pixel shader threads in performance counters (` VS_ENh9Exclude vertex shader threads from performance counters 7Include vertex shader threads in performance counters H GS_EN;Exclude geometry shader threads from performance counters 9Include geometry shader threads in performance counters h ES_EN09Exclude export shader threads from performance counters 7Include export shader threads in performance counters  MAXHBAccumulate performance events (if both TEST_MODE and LIVE are 0) XRetain maximum single-cycle performance event value (if both TEST_MODE and LIVE are 0)  H TEST_MODE:Update performance counters based on MAX and LIVE fields P7Shift in 1's rather than counting, For Debugging only hLIVE 4Update performance counters based on the MAX field hMRetain the current single-cycle performance event value (if TEST_MODE is 0) p˫ЌЌ""̫SQ_PERF_CTR4_SEL`̫̫SELx̫ͫRSQ_PERF_SEL_NONE: don't count anything Deterministic. Should be select value 0. XΫͫWSQ_PERF_SEL_CYCLES: Clock cycles. Thread-type independent. Should be select value 1. `ϫΫSQ_PERF_SEL_BUSY_CYCLES: Clock cycles while SQ is reporting that it is busy. Thread-type independent. Should be select value 2. hЫϫSQ_PERF_SEL_ANY_BUSY_PER_TYPE: Number of cycles we have a thread or an event. Thread-type dependent. Should be select value 3. ѫЫSQ_PERF_SEL_EVENTS_PER_TYPE: Number of events. Thread-type dependent. Caveat: Event counts are slightly unpredictable because they don't have an associated state and because we don't count events when we don't have acitve threads. Should be select value 4. ҫ8ҫuSQ_PERF_SEL_EVENTS_BUSY_PER_TYPE: Number cycles we have an event. Thread-type dependent. Should be select value 5. ӫ8ӫSQ_PERF_SEL_EVENT_LEVEL_PER_TYPE: Number of events in the pipeline per clock. Thread-type dependent. Should be select value 6. ի@ԫSQ_PERF_SEL_ITEMS_PER_TYPE: Number of valid items per thread. Thread-type dependent. Deterministic. Should be select value 7. (֫HիSQ_PERF_SEL_ITEMS_GT_48_PER_TYPE: Number of threads with a valid item in a position >= 48. Thread-type dependent. Deterministic. Should be select value 8. P׫p֫ SQ_PERF_SEL_ITEMS_GT_32_PER_TYPE: Number of threads with a valid item in a position >= 32. Thread-type dependent. Deterministic. Should be select value 9. xث׫ SQ_PERF_SEL_ITEMS_GT_16_PER_TYPE: Number of threads with a valid item in a position >= 16. Thread-type dependent. Deterministic. Should be select value 10. p٫ث nSQ_PERF_SEL_QUADS: Number of valid pixel shader quads per thread. Deterministic. Should be select value 11. pګ٫ wSQ_PERF_SEL_THREADS_BUSY_PER_TYPE: Number cycles we have a thread. Thread-type dependent. Should be select value 12. h۫ګ tSQ_PERF_SEL_THREADS_PER_TYPE: Number of threads. Thread-type dependent. Deterministic Should be select value 13. pܫ۫SQ_PERF_SEL_THREAD_LEVEL_PER_TYPE: Number of threads in the pipeline per clock. Thread-type dependent. Should be select value 14. ݫܫSQ_PERF_SEL_THREAD_LEVEL_WAIT_CREATE_PER_TYPE: Number of threads waiting to be created. Thread-type dependent. Should be select value 15. ޫݫSQ_PERF_SEL_THREAD_LEVEL_UNALLOC_PARAM_PER_TYPE: Number of threads with parameter cache unallocated. Thread-type dependent. Should be select value 16. ߫ޫSQ_PERF_SEL_THREAD_LEVEL_UNALLOC_PIX_PER_TYPE: Number of threads with pixel buffer unallocated. Thread-type dependent. Should be select value 17. SQ_PERF_SEL_THREAD_LEVEL_UNALLOC_POS_PER_TYPE: Number of threads with position buffer unallocated. Thread-type dependent. Should be select value 18. (SQ_PERF_SEL_THREADS_NONPS: Number of existing non-PS threads sharing the set of enabled thread-types with other selected NONPS counters. Should be select value 19. HXSQ_PERF_SEL_THREAD_LEVEL_NONPS: Number of existing non-PS threads per cycle sharing the set of enabled thread-types with other selected NONPS counters. Should be select value 20. SQ_PERF_SEL_THREAD_LEVEL_WAIT_ALLOC_NONPS: Number of non-PS threads waiting for export space to be allocated. Must share the set of enabled thread-types with other selected NONPS counters. Should be select value 21. SQ_PERF_SEL_THREAD_LEVEL_WAIT_OTHER_NONPS: Number of non-PS threads waiting for instructions to be fetched or completed. Must share the set of enabled thread-types with other selected SHARED_TYPESET counters. Should be select value 22. (hSQ_PERF_SEL_THREAD_LEVEL_WAIT_ALLOC_PS: Number of PS threads waiting for pixel buffer to be allocated. Should be select value 23. @pSQ_PERF_SEL_THREAD_LEVEL_WAIT_OTHER_PS: Number of PS threads waiting for for instructions to be fetched or completed. Should be select value 24. PSQ_PERF_SEL_CF_INST_ISSUES_PER_TYPE: Number of CF instruction issues. Thread-type dependent. Deterministic. Should be select value 25. pSQ_PERF_SEL_CF_INST_ISSUE_ONE: Number of times only a single instruction is issued on a cycle. Thread-type independent. Should be select value 26. SQ_PERF_SEL_CF_INST_ISSUE_TWO: Number of times two instructions are issued in a single cycle. Thread-type independent. Should be select value 27. SQ_PERF_SEL_CF_INST_ISSUE_IDLE_PER_TYPE: Number of cycles when threads exist but no threads are ready to issue. Thread-type dependent. Should be select value 28. SQ_PERF_SEL_CF_INST_ISSUE_FS_PER_TYPE: Number of instructions executed in Fetch Shader Mode. Does not include initial CALL_FS instruction. Thread-type dependent. Deterministic. Should be select value 29. PSQ_PERF_SEL_CF_INST_ISSUE_ALU_PER_TYPE: Number of CF_ALU instructions issued. Thread-type dependent. Deterministic. Should be select value 30. 8hSQ_PERF_SEL_CF_INST_ISSUE_TF_PER_TYPE: Number of CF_TF instructions issued. Thread-type dependent. Deterministic. Should be select value 31. P SQ_PERF_SEL_CF_INST_ISSUE_VF_PER_TYPE: Number of CF_VF instructions issued. Thread-type dependent. Deterministic. Should be select value 32. h!SQ_PERF_SEL_CF_INST_ISSUE_EX_PER_TYPE: Number of Export instructions issued. Thread-type dependent. Deterministic. Should be select value 33. "SQ_PERF_SEL_CF_INST_ISSUE_SMX_WR_PER_TYPE: Number of SMX write instructions issued. Thread-type dependent. Deterministic. Should be select value 34. #SQ_PERF_SEL_CF_INST_ISSUE_SMX_RD_PER_TYPE: Number of SMX read instructions issued. Thread-type dependent. Deterministic. Should be select value 35. $SQ_PERF_SEL_CF_INST_ISSUE_GF_PER_TYPE: Number of geometry instructions issued. Thread-type dependent. Deterministic. Should be select value 36. %SQ_PERF_SEL_CF_INST_ISSUE_OTHER_PER_TYPE: Number of non-ALU/TF/VF/EX/SMX/GF instructions issued. Thread-type dependent. Deterministic. Should be select value 37. 8&SQ_PERF_SEL_CF_INST_ISSUE_ALU_CF_PER_TYPE: Number of ALU CF tags processed. Thread-type dependent. Deterministic. Should be select value 38. (P'SQ_PERF_SEL_CF_INST_ISSUE_BL_PER_TYPE: Number of OTHER and ALU CF tags processed. Thread-type dependent. Deterministic. Should be select value 39. Xp(SQ_PERF_SEL_CF_INST_REJECT_ALU_PER_TYPE: Number of ALU instructions scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 40. )SQ_PERF_SEL_CF_INST_REJECT_TF_PER_TYPE: Number of times a Texture Fetch instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 41. *SQ_PERF_SEL_CF_INST_REJECT_VF_PER_TYPE: Number of times a Vertex Fetch instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 42. (+SQ_PERF_SEL_CF_INST_REJECT_EX_PER_TYPE: Number of times an Export instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 43. hh,SQ_PERF_SEL_CF_INST_REJECT_SMX_WR_PER_TYPE: Number of times a SMX write instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 44. -SQ_PERF_SEL_CF_INST_REJECT_SMX_RD_PER_TYPE: Number of times a SMX read instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 45. .SQ_PERF_SEL_CF_INST_REJECT_GF_PER_TYPE: Number of geometry instructions trivially rejected. Thread-type dependent. Deterministic. Should be select value 46. /SQ_PERF_SEL_CF_INST_REJECT_OTHER_PER_TYPE: Number of non-ALU/TF/VF/EX/SMX/GF instructions rejected. Thread-type dependent. Deterministic. Should be select value 47. H0SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_PER_TYPE: Number of instructions sent to ALU. Thread-type dependent. Deterministic. Should be select value 48. @`1SQ_PERF_SEL_CF_INST_FIFO_SEND_TF_PER_TYPE: Number of instructions sent to Texture Fetch unit. Thread-type dependent. Deterministic. Should be select value 49. h2SQ_PERF_SEL_CF_INST_FIFO_SEND_VF_PER_TYPE: Number of instructions sent to Vertex Fetch unit. Thread-type dependent. Deterministic. Should be select value 50. 3SQ_PERF_SEL_CF_INST_FIFO_SEND_EX_PER_TYPE: Number of instructions sent to Export unit. Thread-type dependent. Deterministic. Should be select value 51. 4SQ_PERF_SEL_CF_INST_FIFO_SEND_SMX_WR_PER_TYPE: Number of write instructions sent to SMX Export unit. Thread-type dependent. Deterministic. Should be select value 52. 5SQ_PERF_SEL_CF_INST_FIFO_SEND_SMX_RD_PER_TYPE: Number of read instructions sent to SMX Export unit. Thread-type dependent. Deterministic. Should be select value 53.  0 6SQ_PERF_SEL_CF_INST_FIFO_SEND_GF_PER_TYPE: Number of geometry instructions executed. Thread-type dependent. Deterministic. Should be select value 54. 8 P 7SQ_PERF_SEL_CF_INST_FIFO_SEND_OTHER_PER_TYPE: Number of non-ALU/TF/VF/EX/SMX/GF instructions executed. Thread-type dependent. Deterministic. Should be select value 55. 8SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_NONE_PER_TYPE: Number of instructions sent to ALU with no kcache regions locked. Thread-type dependent. Deterministic. Should be select value 56.  9SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_ONE_PER_TYPE: Number of instructions sent to ALU with one kcache regions locked. Thread-type dependent. Deterministic. Should be select value 57. :SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_TWO_PER_TYPE: Number of instructions sent to ALU with two kcache regions locked. Thread-type dependent. Deterministic. Should be select value 58. HX;SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_PER_TYPE: Number of kcache region locks in instructions sent to ALU. Thread-type dependent. Deterministic. Should be select value 59. P<~SQ_PERF_SEL_CF_INST_FIFO_FULL_ALU: Number of ALU units full on a cycle. Thread-type independent. Should be select value 60. `=SQ_PERF_SEL_CF_INST_FIFO_FULL_TF: Number of cycles the Texture Fetch unit was full. Thread-type independent. Should be select value 61. p>SQ_PERF_SEL_CF_INST_FIFO_FULL_VF: Number of cycles the Vertex Fetch unit was full. Thread-type independent. Should be select value 62. x?SQ_PERF_SEL_CF_INST_FIFO_FULL_EX: Number of cycles the Export unit was full. Thread-type independent. Should be select value 63. @SQ_PERF_SEL_CF_INST_FIFO_FULL_SMX: Number of cycles the SMX Export unit was full. Thread-type independent. Should be select value 64. ASQ_PERF_SEL_CF_INST_FIFO_FULL_GF: Number of cycles the Geometry Fifo was full. Thread-type independent. Should be select value 65. hBKSQ_PERF_SEL_CF_INST_FIFO_FULL_OTHER: Reserved. Should be select value 66. xCSQ_PERF_SEL_CF_INST_FIFO_LEVEL_ALU: Number of credits available for all ALU units. Thread-type independent. Should be select value 67. DSQ_PERF_SEL_CF_INST_FIFO_LEVEL_TF: Number of credits available for TF unit. Thread-type independent. Should be select value 68. ESQ_PERF_SEL_CF_INST_FIFO_LEVEL_VF: Number of credits available for VF unit. Thread-type independent. Should be select value 69. FSQ_PERF_SEL_CF_INST_FIFO_LEVEL_EX: Number of credits available for EX unit. Thread-type independent. Should be select value 70. GSQ_PERF_SEL_CF_INST_FIFO_LEVEL_SMX: Number of credits available for SMX unit. Thread-type independent. Should be select value 71. HSQ_PERF_SEL_CF_INST_FIFO_LEVEL_GF: Number of credits available for Geometry Fifo. Thread-type independent. Should be select value 72. xILSQ_PERF_SEL_CF_INST_FIFO_LEVEL_OTHER: Reserved. Should be select value 73. JSQ_PERF_SEL_CF_INST_FIFO_EMPTY_ALU: Number of ALU units empty on a cycle. Thread-type independent. Should be select value 74. ! KSQ_PERF_SEL_CF_INST_FIFO_EMPTY_TF: Number of cycles the Texture Fetch unit was empty. Thread-type independent. Should be select value 75. "!LSQ_PERF_SEL_CF_INST_FIFO_EMPTY_VF: Number of cycles the Vertex Fetch unit was empty. Thread-type independent. Should be select value 76. #"MSQ_PERF_SEL_CF_INST_FIFO_EMPTY_EX: Number of cycles the Export unit was empty. Thread-type independent. Should be select value 77. $#NSQ_PERF_SEL_CF_INST_FIFO_EMPTY_SMX: Number of cycles the SMX unit was empty. Thread-type independent. Should be select value 78. %%OSQ_PERF_SEL_CF_INST_FIFO_EMPTY_GF: Number of cycles the Geometry fifo was empty. Thread-type independent. Should be select value 79. &&PLSQ_PERF_SEL_CF_INST_FIFO_EMPTY_OTHER: Reserved. Should be select value 80. '&QSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_ALU_PER_TYPE: Number of instructions outstanding for all ALU units. Thread-type dependent. Should be select value 81. ((RSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_TF_PER_TYPE: Number of instructions outstanding for TF unit. Thread-type dependent. Should be select value 82. ))SSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_VF_PER_TYPE: Number of instructions outstanding for VF unit. Thread-type ependent. Should be select value 83. +0*TSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_EX_PER_TYPE: Number of instructions outstanding for EX unit. Thread-type dependent. Should be select value 84. ,H+USQ_PERF_SEL_CF_INST_ISSUE_LEVEL_SMX_WR_PER_TYPE: Number of write instructions outstanding for SMX unit. Thread-type dependent. Should be select value 85. @-h,VSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_SMX_RD_PER_TYPE: Number of read instructions outstanding for SMX unit. Thread-type dependent. Should be select value 86. `.-WSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_GF_PER_TYPE: Number of instructions outstanding for Geometry Fifo. Thread-type dependent. Should be select value 87. /.XSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_OTHER_PER_TYPE: Number of instructions outstanding for non-ALU/TF/VF/EX/SMX/GF. Thread-type dependent. Should be select value 88. 0/YSQ_PERF_SEL_CF_INST_CHECKPOINT: Number of times user specified CF address is executed. Deterministic. Should be select value 89. 10ZSQ_PERF_SEL_CF_INST_CHECKPOINT_BEFORE: Number of CF instructions executed including and after the specified CF address. Deterministic. Should be select value 90. 22[SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_VALID: Number of items valid for execution of instruction at CF address. Deterministic. Should be select value 91. 4 3\SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_VALID_NONE: Number of times no items are valid for execution of instruction at CF address. Deterministic. Should be select value 92. h5P4]SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_ACTIVE: Number of items active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 93. 65^SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_ACTIVE_NONE: Number of times no items are active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 94. H8(7_SQ_PERF_SEL_CF_INST_CHECKPOINT_QUADS_ACTIVE: Number of pixel quads active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 95. 98`SQ_PERF_SEL_CF_INST_CHECKPOINT_QUADS_VALID: Number of pixel quads valid for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 96. :9aSQ_PERF_SEL_CF_INST_CHECKPOINT_THREADS: Number of times a thread first reaches the CF address. Deterministic. Should be select value 97. ;;bSQ_PERF_SEL_CF_INST_CHECKPOINT_THREAD_LEVEL: Number of threads that have reached the CF address per cycle. Should be select value 98. <<cSQ_PERF_SEL_CF_INST_FETCH_PER_TYPE: Number of CF fetch requests from cache. Thread-type dependent. Should be select value 99. = =dSQ_PERF_SEL_CF_INST_FETCH_RETURNS_PER_TYPE: Number of CF fetch return cycles from cache. Thread-type dependent. Should be select value 100. ?8>eSQ_PERF_SEL_CF_INST_FETCH_INSTS_PER_TYPE: Number of CF instructions requested from cache. Thread-type dependent. Should be select value 101. (@P?fSQ_PERF_SEL_CF_INST_FETCH_LEVEL_PER_TYPE: Number of CF fetch requests from cache pending per cycle. Thread-type dependent. Should be select value 102. Ap@gSQ_PERF_SEL_CF_INST_FETCH_EXTRA_PER_TYPE: Number of times we didn't issue the second instruction in a pair. Does not include instructions after PROGRAM_END. Thread-type dependent. Deterministic. Should be select value 103. BAhSQ_PERF_SEL_CF_INST_FETCH_FIFO_SEND: Number of requests passing through the fetch fifo. Thread-type independent. Should be select value 104. CBiSQ_PERF_SEL_CF_INST_FETCH_FIFO_LEVEL: Control Flow Fetch fifo entry level. Thread-type independent. Should be select value 105. DCjSQ_PERF_SEL_CF_INST_FETCH_FIFO_STALL: Number of cycles when the CF fetch fifo is stalling issues. Thread-type independent. Should be select value 106. EEkSQ_PERF_SEL_CF_INST_CACHE_FIFO_SEND: Number of requests passing through the cache fifo. Thread-type independent. Should be select value 107. F0FlySQ_PERF_SEL_CF_INST_CACHE_FIFO_LEVEL: Number of credits in cache. Thread-type independent. Should be select value 108. G0GmSQ_PERF_SEL_CF_INST_CACHE_FIFO_FULL: Number of cycles when we have no cache credits. Thread-type independent. Should be select value 109. (I@HnSQ_PERF_SEL_CF_INST_ISSUE_DONES: Number of issues that need to be accounted for to avoid overflowing the done fifo. Thread-type independent. Should be select value 110. xJpIoSQ_PERF_SEL_CF_INST_ISSUE_DONE_LEVEL: Number of issues pending at any given time that need to be accounted for to avoid overflowing the done fifo. Thread-type independent. Should be select value 111. KJpSQ_PERF_SEL_CF_INST_ISSUE_DONE_STALL: Stalls triggered to avoid overflowing the done fifo. Thread-type independent. Should be select value 112. LKqSQ_PERF_SEL_CF_INST_ISSUE_DONE_FIFO_SEND: Number of items passing through the done fifo. Thread-type independent. Should be select value 113. MLrSQ_PERF_SEL_CF_INST_ISSUE_DONE_FIFO_LEVEL: Control Flow Done fifo entry level. Thread-type independent. Should be select value 114. NNsSQ_PERF_SEL_CF_INST_ALU_UPDATE_FIFO_SEND: Macro sequencer alu update fifo send. Thread-type independent. Should be select value 115. OOtSQ_PERF_SEL_CF_INST_ALU_UPDATE_FIFO_LEVEL: Macro sequencer alu update fifo level. Thread-type independent. Should be select value 116. Q PuSQ_PERF_SEL_CF_INST_ALU_UPDATE_FIFO_STALL: Number of cycles when the MS alu update fifo is stalling issues and alu returns. Thread-type independent. Should be select value 117. RXQvSQ_PERF_SEL_OFIFO_LEVEL_PER_TYPE: Number of threads and events in the ofifo. Thread-type dependent. Should be select value 118. (S`RwSQ_PERF_SEL_SX_EVENT_FIFO_FULL_PER_TYPE: Number of cycles the SX event fifo is full. Thread-type dependent. Should be select value 119. PTpSxSQ_PERF_SEL_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE: Number of ALU instruction groups executed. Thread-type dependent. Deterministic. Should be select value 120. xUTySQ_PERF_SEL_ALU_CLAUSE_INSTRS_PER_TYPE: Number of ALU individual alu instructions executed. Thread-type dependent. Deterministic. Should be select value 121. VUzSQ_PERF_SEL_ALU_KWATERFALL_PER_TYPE: Number of ALU instruction groups which use const-waterfall. Thread-type dependent. Deterministic. Should be select value 122. WV{SQ_PERF_SEL_ALU_GPRWATERFALL_PER_TYPE: Number of ALU instruction groups which use gpr-waterfall. Thread-type dependent. Deterministic. Should be select value 123. Y X|SQ_PERF_SEL_ALU_K_INSTR_PER_TYPE: Number of ALU instructions which use one or more constant (literal, kcache, or kfile). Thread-type dependent. Deterministic. Should be select value 124. 8ZhY}SQ_PERF_SEL_ALU_ICACHE_BUSY_PER_TYPE: Number of times ALU Icache read was denied - cache busy. Thread-type dependent. Should be select value 125. X[Z~SQ_PERF_SEL_ALU_KCACHE_BUSY_PER_TYPE: Number of times ALU Kcache/Kfile read was denied - cache busy. Thread-type dependent. Should be select value 126. \[SQ_PERF_SEL_ALU_MOVA_IDLE_WAIT_PER_TYPE: Number of instruction cycles idle waiting for MOVA to complete. Thread-type dependent. Should be select value 127. ]\SQ_PERF_SEL_ALU_LOCK_WAIT: Number of times (1 every 4 clocks) ALU has clauses in input fifo but no clauses locked -- ALU is idle. Thread-type independent. Should be select value 128. ^^SQ_PERF_SEL_ALU_ICACHE_READS_PER_TYPE: Number of read requests to the ALU I-cache. Thread-type dependent. Deterministic. Should be select value 129. `(_SQ_PERF_SEL_ALU_KCACHE_READS_PER_TYPE: Number of read requests to the ALU K-cache/K-file. Thread-type dependent. Deterministic. Should be select value 130. (aP`SQ_PERF_SEL_ALU_DONE_FIFO_FULL: Number of times the done-fifo is full and that caused a stall. Thread-type independent. Should be select value 131. `bpaSQ_PERF_SEL_ALU_MOVA_WAIT_PER_TYPE: Number of times more than one SIMD tried to execute MOVA, and one was denied access. Thread-type dependent. Should be select value 132. cbSQ_PERF_SEL_ALU_THREADS_IN_FIFO_PER_TYPE: Number of threads waiting in the alu-seq's input fifo each cycle, of the selected thread type. Should be select value 133. 0dcSQ_PERF_SEL_UNUSED_006dxdSQ_PERF_SEL_UNUSED_007eeSQ_PERF_SEL_TV_ICACHE_WAIT_PER_TYPE: Number of cycles the Tex/Vtx Icache denied a read request (busy). Thread-type dependent. Should be select value 136. f8fSQ_PERF_SEL_UNUSED_0100gfSQ_PERF_SEL_UNUSED_001gxgSQ_PERF_SEL_UNUSED_002ihSQ_PERF_SEL_TF_TA_STALL_PER_TYPE: Number of times the TF had data to send to TA, but the TA input fifo was full. Thread-type dependent. Should be select value 140. @jHiSQ_PERF_SEL_VF_VC_INSTR_STALL_PER_TYPE: Number of times the VF had data to send to VC, but the VC instruction input fifo was full. Thread-type dependent. Should be select value 141. xkjSQ_PERF_SEL_VF_VC_INDEX_STALL_PER_TYPE: Number of times the VF had data to send to VC, but the VC index input fifo was full. Thread-type dependent. Should be select value 142. lkSQ_PERF_SEL_UNUSED_003l`lSQ_PERF_SEL_UNUSED_008XmmSQ_PERF_SEL_UNUSED_004mmSQ_PERF_SEL_UNUSED_009n@nwSQ_PERF_SEL_EXPORT_INSTR_PER_TYPE: Number of exports (seen by export-seq). Determinstic. Should be select value 147. o@o{SQ_PERF_SEL_EXPORT_IDLE: Number of clocks where export unit is idle. Thread-type independent. Should be select value 148. q@pSQ_PERF_SEL_EXPORT_SMX_AL_STALL: Number of clocks SMX export stalled waiting for alloc. Thread-type independent. Should be select value 149. rXqSQ_PERF_SEL_EXPORT_PC_AL_STALL: Number of clocks Param.cache alloc was stalled. Thread-type independent. Should be select value 150. 0shrSQ_PERF_SEL_EXPORT_POS_AL_STALL: Number of clocks Position export alloc was stalled. Thread-type independent. Should be select value 151. @txsSQ_PERF_SEL_EXPORT_PIX_AL_STALL: Number of clocks Pixel export alloc was stalled. Thread-type independent. Should be select value 152. hutSQ_PERF_SEL_EXPORT_POS_CYCLE: Number of position export cycles (4 clocks), * burst count). Thread-type independent. Determinstic. Should be select value 153. vuSQ_PERF_SEL_EXPORT_PIX_CYCLE: Number of pixel export cycles (4 clocks), * burst count). Thread-type independent. Determinstic. Should be select value 154. wvSQ_PERF_SEL_EXPORT_PC_CYCLE: Number of param.cache export cycles (4 clocks), * burst count). Thread-type independent. Determinstic. Should be select value 155. xxSQ_PERF_SEL_EXPORT_SMX_CYCLE_PER_TYPE: Number of smx export cycles (4 clocks), * burst count). Thread-type dependent. Determinstic. Should be select value 156. z(ySQ_PERF_SEL_CACHE_INVAL_ANY: Number of cache invalidation (surface synchronization) operations of any kind. Thread-type independent. Should be select value 157. h{PzSQ_PERF_SEL_CACHE_INVAL_ALL: Number of cache invalidation (surface synchronization) operations that invalidate the whole cache (due to a large invalidation region). Thread-type independent. Should be select value 158. |{SQ_PERF_SEL_CACHE_INVAL_CYCLES: Number of cache invalidation (surface synchronization) cycles, not including full invalidations; indicates the size of the invalidation regions in 4K byte increments. Thread-type independent. Should be select value 159. ~8}SQ_PERF_SEL_CF_ICACHE_HITS: Number of CF instruction cache hits (it was found in the cache). Thread-type independent. Should be select value 160. P~SQ_PERF_SEL_TF_ICACHE_HITS: Number of TV instruction cache hits (it was found in the cache). Thread-type independent. Should be select value 161. hQSQ_PERF_SEL_VF_ICACHE_HITS: DEPRECATED. Do not use. Should be select value 162. @SQ_PERF_SEL_ALU_ICACHE_HITS: Number of ALU instruction cache hits (it was found in the cache). Thread-type independent. Should be select value 163. 0`SQ_PERF_SEL_ALU_KCACHE_HITS: Number of ALU constant cache hits (it was found in the cache). Thread-type independent. Should be select value 164. xxSQ_PERF_SEL_CF_ICACHE_MISSES: Number of CF instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 165. SQ_PERF_SEL_TF_ICACHE_MISSES: Number of TV instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 166. SSQ_PERF_SEL_VF_ICACHE_MISSES: DEPRECATED. Do not use. Should be select value 167. SQ_PERF_SEL_ALU_ICACHE_MISSES: Number of ALU instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 168. (SQ_PERF_SEL_ALU_KCACHE_MISSES: Number of ALU constant cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 169. hSQ_PERF_SEL_CF_ICACHE_DUP_MISSES: Number of CF instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 170. ȉSQ_PERF_SEL_TF_ICACHE_DUP_MISSES: Number of TV instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 171. (WSQ_PERF_SEL_VF_ICACHE_DUP_MISSES: DEPRECATED. Do not use. Should be select value 172. SQ_PERF_SEL_ALU_ICACHE_DUP_MISSES: Number of ALU instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 173. hSQ_PERF_SEL_ALU_KCACHE_DUP_MISSES: Number of ALU constant cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 174. ȎSQ_PERF_SEL_CF_ICACHE_ACCESSES: Number of CF instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 175. `8SQ_PERF_SEL_TF_ICACHE_ACCESSES: Number of TV instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 176. @USQ_PERF_SEL_VF_ICACHE_ACCESSES: DEPRECATED. Do not use. Should be select value 177. SQ_PERF_SEL_ALU_ICACHE_ACCESSES: Number of ALU instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 178. SQ_PERF_SEL_ALU_KCACHE_ACCESSES: Number of ALU constant cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 179. HhSQ_PERF_SEL_CF_ICACHE_INPUT_FIFO_ENTRIES: Count of CF instruction cache requests stored in the input FIFO. Thread-type independent. Should be select value 180. pSQ_PERF_SEL_TF_ICACHE_INPUT_FIFO_ENTRIES: Count of TV instruction cache requests stored in the input FIFO. Thread-type independent. Should be select value 181. X_SQ_PERF_SEL_VF_ICACHE_INPUT_FIFO_ENTRIES: DEPRECATED. Do not use. Should be select value 182. SQ_PERF_SEL_ALU_ICACHE_INPUT_FIFO_ENTRIES: Count of ALU instruction cache requests stored in the input FIFO. Thread-type independent. Should be select value 183. șSQ_PERF_SEL_ALU_KCACHE_INPUT_FIFO_ENTRIES: Count of ALU constant cache requests stored in the input FIFO. Thread-type independent. Should be select value 184. SQ_PERF_SEL_CF_ICACHE_MISS_MEM_STALL: Number of CF instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 185. hPSQ_PERF_SEL_TF_ICACHE_MISS_MEM_STALL: Number of TV instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 186. H[SQ_PERF_SEL_VF_ICACHE_MISS_MEM_STALL: DEPRECATED. Do not use. Should be select value 187. SQ_PERF_SEL_ALU_ICACHE_MISS_MEM_STALL: Number of ALU instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 188. SQ_PERF_SEL_ALU_KCACHE_MISS_MEM_STALL: Number of ALU constant cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 189. XSQ_PERF_SEL_CF_ICACHE_MISS_FIFO_STALL: Number of CF instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 190. ТSQ_PERF_SEL_TF_ICACHE_MISS_FIFO_STALL: Number of TV instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 191. बH\SQ_PERF_SEL_VF_ICACHE_MISS_FIFO_STALL: DEPRECATED. Do not use. Should be select value 192. X(SQ_PERF_SEL_ALU_ICACHE_MISS_FIFO_STALL: Number of ALU instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 193. ЧSQ_PERF_SEL_ALU_KCACHE_MISS_FIFO_STALL: Number of ALU constant cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 194. SQ_PERF_SEL_CF_ICACHE_HIT_STALL: Number of CF instruction cache cycles that are a cache hit but are stalled due to processing previous misses. Thread-type independent. Should be select value 195. hSQ_PERF_SEL_CF_ICACHE_MISS_LOCKED_STALL: Number of CF instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 196. ЪSQ_PERF_SEL_TF_ICACHE_MISS_LOCKED_STALL: Number of TV instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 197. ج8^SQ_PERF_SEL_VF_ICACHE_MISS_LOCKED_STALL: DEPRECATED. Do not use. Should be select value 198. @ SQ_PERF_SEL_ALU_ICACHE_MISS_LOCKED_STALL: Number of ALU instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 199. SQ_PERF_SEL_ALU_KCACHE_MISS_LOCKED_STALL: Number of ALU constant cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 200. SQ_PERF_SEL_CF_ICACHE_LOCKED_TAGS: Count of CF instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 201. XHSQ_PERF_SEL_TF_ICACHE_LOCKED_TAGS: Count of TV instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 202. 8XSQ_PERF_SEL_VF_ICACHE_LOCKED_TAGS: DEPRECATED. Do not use. Should be select value 203. SQ_PERF_SEL_ALU_ICACHE_LOCKED_TAGS: Count of ALU instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 204. 赬شSQ_PERF_SEL_ALU_KCACHE_LOCKED_TAGS: Count of ALU constant cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 205. (0SQ_PERF_SEL_CF_ICACHE_MISS_LOCKED_TAGS: Count of CF instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 206. hpSQ_PERF_SEL_TF_ICACHE_MISS_LOCKED_TAGS: Count of TV instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 207. P]SQ_PERF_SEL_VF_ICACHE_MISS_LOCKED_TAGS: DEPRECATED. Do not use. Should be select value 208. SQ_PERF_SEL_ALU_ICACHE_MISS_LOCKED_TAGS: Count of ALU instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 209. лغSQ_PERF_SEL_ALU_KCACHE_MISS_LOCKED_TAGS: Count of ALU constant cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 210. 輬SQ_PERF_SEL_CACHE_MEM_REQUESTS: Number of cache to memory controller requests of any type. Thread-type independent. Should be select value 211. 0SQ_PERF_SEL_CF_ICACHE_MEM_REQUESTS: Number of CF instruction cache to memory controller requests. Thread-type independent. Should be select value 212. (PSQ_PERF_SEL_TV_ICACHE_MEM_REQUESTS: Number of TV instruction cache to memory controller requests. Thread-type independent. Should be select value 213. HpSQ_PERF_SEL_ALU_ICACHE_MEM_REQUESTS: Number of ALU instruction cache to memory controller requests. Thread-type independent. Should be select value 214. hSQ_PERF_SEL_ALU_KCACHE_MEM_REQUESTS: Number of ALU constant cache to memory controller requests. Thread-type independent. Should be select value 215. ¬SQ_PERF_SEL_CF_ICACHE_RD_WR_COLLISION: Number of times a read to the CF icache memory was blocked by a write from a memory return. Thread-type independent. Should be select value 216. ì¬SQ_PERF_SEL_CF_ICACHE_MISS_HIT_RD_COLLISION: Number of times processing a hit is stalled by processing a now-resident miss. Thread-type independent. Should be select value 217. 0Ŭ(ĬSQ_PERF_SEL_CF_ICACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding CF instruction cache to memory controller requests of any type. Thread-type independent. Should be select value 218. ƬxŬSQ_PERF_SEL_TV_ICACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding TV instruction cache to memory controller requests of any type. Thread-type independent. Should be select value 219. ǬƬSQ_PERF_SEL_ALU_ICACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding ALU instruction cache to memory controller requests of any type. Thread-type independent. Should be select value 220. ɬȬSQ_PERF_SEL_ALU_KCACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding ALU constant cache to memory controller requests of any type. Thread-type independent. Should be select value 221. PʬhɬSQ_PERF_SEL_CF_ICACHE_MISS_FIFO_MISSES: Count of the number of CF instruction cache misses waiting in the miss FIFO. Thread-type independent. Should be select value 222. ˬʬSQ_PERF_SEL_TF_ICACHE_MISS_FIFO_MISSES: Count of the number of TV instruction cache misses waiting in the miss FIFO. Thread-type independent. Should be select value 223. h̬ˬ]SQ_PERF_SEL_VF_ICACHE_MISS_FIFO_MISSES: DEPRECATED. Do not use. Should be select value 224. ̬ͬSQ_PERF_SEL_ALU_ICACHE_MISS_FIFO_MISSES: Count of the number of ALU instruction cache misses waiting in the miss FIFO. Divided by 2. Thread-type independent. Should be select value 225. άͬSQ_PERF_SEL_ALU_KCACHE_MISS_FIFO_MISSES: Count of the number of ALU constant cache misses waiting in the miss FIFO. Divided by 2. Thread-type independent. Should be select value 226. 0Ь0ϬSQ_PERF_SEL_CACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding cache to memory controller requests of any type. Divided by 2. Thread-type independent. Should be select value 227. HѬxЬSQ_PERF_SEL_CACHE_MEM_STALL: Number of cache to memory controller cycles that are stalled. Thread-type independent. Should be select value 228. @ҬѬqSQ_PERF_SEL_TM_TS64_STALL: Clock cycles GRBM stalled due to Timestamp-64 FIFO full. Should be select value 229. HӬҬSQ_PERF_SEL_TM_ALU_CONST_STALL: Clock cycles GRBM stalled due to ALU constant overflow buffer full. Should be select value 230. PԬӬSQ_PERF_SEL_TM_LOOP_CONST_STALL: Clock cycles GRBM stalled due to Loop constant overflow buffer full. Should be select value 231. pլԬSQ_PERF_SEL_TM_TEX_BASE_CONST_STALL: Clock cycles GRBM stalled due to VertexBase/InstantStart constant overflow buffer full. Should be select value 232. ֬լSQ_PERF_SEL_TM_TEX_SAMPLER_STALL: Clock cycles GRBM stalled due to Texture Sampler constant overflow buffer full. Should be select value 233. ׬֬SQ_PERF_SEL_TM_TEX_RESOURCE_STALL: Clock cycles GRBM stalled due to Texture Resource constant overflow buffer full. Should be select value 234. @ج׬SQ_PERF_SEL_UNUSED_005٬جSQ_PERF_SEL_TA_TEX_INSTRS_PER_TYPE: Number of texture-fetch instructions executed by the Texture cache, including killed fetches. Thread-type dependent. Determinstic. Should be select value 236. ڬ٬SQ_PERF_SEL_TA_VTX_INSTRS_PER_TYPE: Number of vertex-fetch instructions executed by the Texture cache, including killed fetches. Thread-type dependent. Determinstic. Should be select value 237. ܬ ۬SQ_PERF_SEL_VC_INSTRS_PER_TYPE: Number of instructions executed by the Vertex cache, including killed fetches. Thread-type dependent. Determinstic. Should be select value 238. @ݬXܬSQ_PERF_SEL_TV_LOCK_WAIT: Number of cycles the TF input FIFO had clauses, none were locked. Thread-type independent, non-deterministic. Should be select value 239. XެݬSQ_PERF_SEL_TA_SRC_C: Number of times an TA fetch (16 pix or verts) was executed as a src-c export. Non-deterministic. Should be select value 240. p߬ެSQ_PERF_SEL_VC_SRC_C: Number of times a VC fetch (16 pix or verts) was executed as a src-c export. Non-deterministic. Should be select value 241. ߬SQ_PERF_SEL_TV_KILLED_FETCH_PER_TYPE: Number of fetch instructions killed (vertex semantic failed or gpr out of range). Deterministic. Should be select value 242. SQ_PERF_SEL_TV_NULL_FETCH_PER_TYPE: Number of null fetchs issued (null = issue empty fetch at end of clause due to killed fetches). Deterministic. Should be select value 243. SQ_PERF_SEL_TV_THREADS_IN_FIFO_PER_TYPE: Number of threads waiting in the fetch-seq's input fifo each cycle, of the selected thread type. Should be select value 244. HSQ_PERF_SEL_EXPORT_SPQ_LEVEL: Internal export per-quadpipe queue level average. Non-deterministic. Should be select value 245. PySQ_PERF_SEL_EXPORT_SPQ_STALL: Internal export per-quadpipe stall cycles. Non-deterministic. Should be select value 246. (`PS_ENh8Exclude pixel shader threads from performance counters 6Include pixel shader threads in performance counters H VS_EN9Exclude vertex shader threads from performance counters 7Include vertex shader threads in performance counters h GS_EN0;Exclude geometry shader threads from performance counters 9Include geometry shader threads in performance counters ES_ENP9Exclude export shader threads from performance counters 7Include export shader threads in performance counters  MAXhBAccumulate performance events (if both TEST_MODE and LIVE are 0) 0XRetain maximum single-cycle performance event value (if both TEST_MODE and LIVE are 0) h TEST_MODE(:Update performance counters based on MAX and LIVE fields p7Shift in 1's rather than counting, For Debugging only @LIVE@4Update performance counters based on the MAX field MRetain the current single-cycle performance event value (if TEST_MODE is 0) y袪̌̌""8SQ_PERF_CTR3_SEL0УSELRSQ_PERF_SEL_NONE: don't count anything Deterministic. Should be select value 0. WSQ_PERF_SEL_CYCLES: Clock cycles. Thread-type independent. Should be select value 1. ХSQ_PERF_SEL_BUSY_CYCLES: Clock cycles while SQ is reporting that it is busy. Thread-type independent. Should be select value 2. ئSQ_PERF_SEL_ANY_BUSY_PER_TYPE: Number of cycles we have a thread or an event. Thread-type dependent. Should be select value 3. ৪SQ_PERF_SEL_EVENTS_PER_TYPE: Number of events. Thread-type dependent. Caveat: Event counts are slightly unpredictable because they don't have an associated state and because we don't count events when we don't have acitve threads. Should be select value 4. huSQ_PERF_SEL_EVENTS_BUSY_PER_TYPE: Number cycles we have an event. Thread-type dependent. Should be select value 5. (hSQ_PERF_SEL_EVENT_LEVEL_PER_TYPE: Number of events in the pipeline per clock. Thread-type dependent. Should be select value 6. 0pSQ_PERF_SEL_ITEMS_PER_TYPE: Number of valid items per thread. Thread-type dependent. Deterministic. Should be select value 7. XxSQ_PERF_SEL_ITEMS_GT_48_PER_TYPE: Number of threads with a valid item in a position >= 48. Thread-type dependent. Deterministic. Should be select value 8. SQ_PERF_SEL_ITEMS_GT_32_PER_TYPE: Number of threads with a valid item in a position >= 32. Thread-type dependent. Deterministic. Should be select value 9. Ȯ SQ_PERF_SEL_ITEMS_GT_16_PER_TYPE: Number of threads with a valid item in a position >= 16. Thread-type dependent. Deterministic. Should be select value 10. nSQ_PERF_SEL_QUADS: Number of valid pixel shader quads per thread. Deterministic. Should be select value 11. 谪 wSQ_PERF_SEL_THREADS_BUSY_PER_TYPE: Number cycles we have a thread. Thread-type dependent. Should be select value 12. 豪 tSQ_PERF_SEL_THREADS_PER_TYPE: Number of threads. Thread-type dependent. Deterministic Should be select value 13. ಪSQ_PERF_SEL_THREAD_LEVEL_PER_TYPE: Number of threads in the pipeline per clock. Thread-type dependent. Should be select value 14. 質SQ_PERF_SEL_THREAD_LEVEL_WAIT_CREATE_PER_TYPE: Number of threads waiting to be created. Thread-type dependent. Should be select value 15. еSQ_PERF_SEL_THREAD_LEVEL_UNALLOC_PARAM_PER_TYPE: Number of threads with parameter cache unallocated. Thread-type dependent. Should be select value 16. 趪SQ_PERF_SEL_THREAD_LEVEL_UNALLOC_PIX_PER_TYPE: Number of threads with pixel buffer unallocated. Thread-type dependent. Should be select value 17. 0SQ_PERF_SEL_THREAD_LEVEL_UNALLOC_POS_PER_TYPE: Number of threads with position buffer unallocated. Thread-type dependent. Should be select value 18. 8PSQ_PERF_SEL_THREADS_NONPS: Number of existing non-PS threads sharing the set of enabled thread-types with other selected NONPS counters. Should be select value 19. pSQ_PERF_SEL_THREAD_LEVEL_NONPS: Number of existing non-PS threads per cycle sharing the set of enabled thread-types with other selected NONPS counters. Should be select value 20. лSQ_PERF_SEL_THREAD_LEVEL_WAIT_ALLOC_NONPS: Number of non-PS threads waiting for export space to be allocated. Must share the set of enabled thread-types with other selected NONPS counters. Should be select value 21. HSQ_PERF_SEL_THREAD_LEVEL_WAIT_OTHER_NONPS: Number of non-PS threads waiting for instructions to be fetched or completed. Must share the set of enabled thread-types with other selected SHARED_TYPESET counters. Should be select value 22. PSQ_PERF_SEL_THREAD_LEVEL_WAIT_ALLOC_PS: Number of PS threads waiting for pixel buffer to be allocated. Should be select value 23. hSQ_PERF_SEL_THREAD_LEVEL_WAIT_OTHER_PS: Number of PS threads waiting for for instructions to be fetched or completed. Should be select value 24. xSQ_PERF_SEL_CF_INST_ISSUES_PER_TYPE: Number of CF instruction issues. Thread-type dependent. Deterministic. Should be select value 25. SQ_PERF_SEL_CF_INST_ISSUE_ONE: Number of times only a single instruction is issued on a cycle. Thread-type independent. Should be select value 26. ªSQ_PERF_SEL_CF_INST_ISSUE_TWO: Number of times two instructions are issued in a single cycle. Thread-type independent. Should be select value 27. êªSQ_PERF_SEL_CF_INST_ISSUE_IDLE_PER_TYPE: Number of cycles when threads exist but no threads are ready to issue. Thread-type dependent. Should be select value 28. 0Ū ĪSQ_PERF_SEL_CF_INST_ISSUE_FS_PER_TYPE: Number of instructions executed in Fetch Shader Mode. Does not include initial CALL_FS instruction. Thread-type dependent. Deterministic. Should be select value 29. HƪxŪSQ_PERF_SEL_CF_INST_ISSUE_ALU_PER_TYPE: Number of CF_ALU instructions issued. Thread-type dependent. Deterministic. Should be select value 30. `ǪƪSQ_PERF_SEL_CF_INST_ISSUE_TF_PER_TYPE: Number of CF_TF instructions issued. Thread-type dependent. Deterministic. Should be select value 31. xȪǪ SQ_PERF_SEL_CF_INST_ISSUE_VF_PER_TYPE: Number of CF_VF instructions issued. Thread-type dependent. Deterministic. Should be select value 32. ɪȪ!SQ_PERF_SEL_CF_INST_ISSUE_EX_PER_TYPE: Number of Export instructions issued. Thread-type dependent. Deterministic. Should be select value 33. ʪɪ"SQ_PERF_SEL_CF_INST_ISSUE_SMX_WR_PER_TYPE: Number of SMX write instructions issued. Thread-type dependent. Deterministic. Should be select value 34. ˪ʪ#SQ_PERF_SEL_CF_INST_ISSUE_SMX_RD_PER_TYPE: Number of SMX read instructions issued. Thread-type dependent. Deterministic. Should be select value 35. ̪̪$SQ_PERF_SEL_CF_INST_ISSUE_GF_PER_TYPE: Number of geometry instructions issued. Thread-type dependent. Deterministic. Should be select value 36. Ϊ0ͪ%SQ_PERF_SEL_CF_INST_ISSUE_OTHER_PER_TYPE: Number of non-ALU/TF/VF/EX/SMX/GF instructions issued. Thread-type dependent. Deterministic. Should be select value 37. 0Ϫ`Ϊ&SQ_PERF_SEL_CF_INST_ISSUE_ALU_CF_PER_TYPE: Number of ALU CF tags processed. Thread-type dependent. Deterministic. Should be select value 38. PЪxϪ'SQ_PERF_SEL_CF_INST_ISSUE_BL_PER_TYPE: Number of OTHER and ALU CF tags processed. Thread-type dependent. Deterministic. Should be select value 39. ѪЪ(SQ_PERF_SEL_CF_INST_REJECT_ALU_PER_TYPE: Number of ALU instructions scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 40. ҪѪ)SQ_PERF_SEL_CF_INST_REJECT_TF_PER_TYPE: Number of times a Texture Fetch instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 41. ԪӪ*SQ_PERF_SEL_CF_INST_REJECT_VF_PER_TYPE: Number of times a Vertex Fetch instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 42. HժPԪ+SQ_PERF_SEL_CF_INST_REJECT_EX_PER_TYPE: Number of times an Export instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 43. ֪ժ,SQ_PERF_SEL_CF_INST_REJECT_SMX_WR_PER_TYPE: Number of times a SMX write instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 44. ת֪-SQ_PERF_SEL_CF_INST_REJECT_SMX_RD_PER_TYPE: Number of times a SMX read instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 45. تت.SQ_PERF_SEL_CF_INST_REJECT_GF_PER_TYPE: Number of geometry instructions trivially rejected. Thread-type dependent. Deterministic. Should be select value 46. (ڪ@٪/SQ_PERF_SEL_CF_INST_REJECT_OTHER_PER_TYPE: Number of non-ALU/TF/VF/EX/SMX/GF instructions rejected. Thread-type dependent. Deterministic. Should be select value 47. @۪pڪ0SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_PER_TYPE: Number of instructions sent to ALU. Thread-type dependent. Deterministic. Should be select value 48. hܪ۪1SQ_PERF_SEL_CF_INST_FIFO_SEND_TF_PER_TYPE: Number of instructions sent to Texture Fetch unit. Thread-type dependent. Deterministic. Should be select value 49. ݪܪ2SQ_PERF_SEL_CF_INST_FIFO_SEND_VF_PER_TYPE: Number of instructions sent to Vertex Fetch unit. Thread-type dependent. Deterministic. Should be select value 50. ުݪ3SQ_PERF_SEL_CF_INST_FIFO_SEND_EX_PER_TYPE: Number of instructions sent to Export unit. Thread-type dependent. Deterministic. Should be select value 51. ߪު4SQ_PERF_SEL_CF_INST_FIFO_SEND_SMX_WR_PER_TYPE: Number of write instructions sent to SMX Export unit. Thread-type dependent. Deterministic. Should be select value 52. (5SQ_PERF_SEL_CF_INST_FIFO_SEND_SMX_RD_PER_TYPE: Number of read instructions sent to SMX Export unit. Thread-type dependent. Deterministic. Should be select value 53. 0X6SQ_PERF_SEL_CF_INST_FIFO_SEND_GF_PER_TYPE: Number of geometry instructions executed. Thread-type dependent. Deterministic. Should be select value 54. `x7SQ_PERF_SEL_CF_INST_FIFO_SEND_OTHER_PER_TYPE: Number of non-ALU/TF/VF/EX/SMX/GF instructions executed. Thread-type dependent. Deterministic. Should be select value 55. 8SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_NONE_PER_TYPE: Number of instructions sent to ALU with no kcache regions locked. Thread-type dependent. Deterministic. Should be select value 56. 9SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_ONE_PER_TYPE: Number of instructions sent to ALU with one kcache regions locked. Thread-type dependent. Deterministic. Should be select value 57. 88:SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_TWO_PER_TYPE: Number of instructions sent to ALU with two kcache regions locked. Thread-type dependent. Deterministic. Should be select value 58. p;SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_PER_TYPE: Number of kcache region locks in instructions sent to ALU. Thread-type dependent. Deterministic. Should be select value 59. x<~SQ_PERF_SEL_CF_INST_FIFO_FULL_ALU: Number of ALU units full on a cycle. Thread-type independent. Should be select value 60. =SQ_PERF_SEL_CF_INST_FIFO_FULL_TF: Number of cycles the Texture Fetch unit was full. Thread-type independent. Should be select value 61. >SQ_PERF_SEL_CF_INST_FIFO_FULL_VF: Number of cycles the Vertex Fetch unit was full. Thread-type independent. Should be select value 62. ?SQ_PERF_SEL_CF_INST_FIFO_FULL_EX: Number of cycles the Export unit was full. Thread-type independent. Should be select value 63. @SQ_PERF_SEL_CF_INST_FIFO_FULL_SMX: Number of cycles the SMX Export unit was full. Thread-type independent. Should be select value 64. ASQ_PERF_SEL_CF_INST_FIFO_FULL_GF: Number of cycles the Geometry Fifo was full. Thread-type independent. Should be select value 65. BKSQ_PERF_SEL_CF_INST_FIFO_FULL_OTHER: Reserved. Should be select value 66. CSQ_PERF_SEL_CF_INST_FIFO_LEVEL_ALU: Number of credits available for all ALU units. Thread-type independent. Should be select value 67. DSQ_PERF_SEL_CF_INST_FIFO_LEVEL_TF: Number of credits available for TF unit. Thread-type independent. Should be select value 68. ESQ_PERF_SEL_CF_INST_FIFO_LEVEL_VF: Number of credits available for VF unit. Thread-type independent. Should be select value 69. FSQ_PERF_SEL_CF_INST_FIFO_LEVEL_EX: Number of credits available for EX unit. Thread-type independent. Should be select value 70. GSQ_PERF_SEL_CF_INST_FIFO_LEVEL_SMX: Number of credits available for SMX unit. Thread-type independent. Should be select value 71. HSQ_PERF_SEL_CF_INST_FIFO_LEVEL_GF: Number of credits available for Geometry Fifo. Thread-type independent. Should be select value 72. ILSQ_PERF_SEL_CF_INST_FIFO_LEVEL_OTHER: Reserved. Should be select value 73. JSQ_PERF_SEL_CF_INST_FIFO_EMPTY_ALU: Number of ALU units empty on a cycle. Thread-type independent. Should be select value 74. KSQ_PERF_SEL_CF_INST_FIFO_EMPTY_TF: Number of cycles the Texture Fetch unit was empty. Thread-type independent. Should be select value 75. LSQ_PERF_SEL_CF_INST_FIFO_EMPTY_VF: Number of cycles the Vertex Fetch unit was empty. Thread-type independent. Should be select value 76. MSQ_PERF_SEL_CF_INST_FIFO_EMPTY_EX: Number of cycles the Export unit was empty. Thread-type independent. Should be select value 77. NSQ_PERF_SEL_CF_INST_FIFO_EMPTY_SMX: Number of cycles the SMX unit was empty. Thread-type independent. Should be select value 78. (OSQ_PERF_SEL_CF_INST_FIFO_EMPTY_GF: Number of cycles the Geometry fifo was empty. Thread-type independent. Should be select value 79. 8PLSQ_PERF_SEL_CF_INST_FIFO_EMPTY_OTHER: Reserved. Should be select value 80. QSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_ALU_PER_TYPE: Number of instructions outstanding for all ALU units. Thread-type dependent. Should be select value 81. (RSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_TF_PER_TYPE: Number of instructions outstanding for TF unit. Thread-type dependent. Should be select value 82. @SSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_VF_PER_TYPE: Number of instructions outstanding for VF unit. Thread-type ependent. Should be select value 83. (XTSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_EX_PER_TYPE: Number of instructions outstanding for EX unit. Thread-type dependent. Should be select value 84. HpUSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_SMX_WR_PER_TYPE: Number of write instructions outstanding for SMX unit. Thread-type dependent. Should be select value 85. hVSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_SMX_RD_PER_TYPE: Number of read instructions outstanding for SMX unit. Thread-type dependent. Should be select value 86. WSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_GF_PER_TYPE: Number of instructions outstanding for Geometry Fifo. Thread-type dependent. Should be select value 87. XSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_OTHER_PER_TYPE: Number of instructions outstanding for non-ALU/TF/VF/EX/SMX/GF. Thread-type dependent. Should be select value 88. YSQ_PERF_SEL_CF_INST_CHECKPOINT: Number of times user specified CF address is executed. Deterministic. Should be select value 89. ZSQ_PERF_SEL_CF_INST_CHECKPOINT_BEFORE: Number of CF instructions executed including and after the specified CF address. Deterministic. Should be select value 90. ( [SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_VALID: Number of items valid for execution of instruction at CF address. Deterministic. Should be select value 91. 0 H \SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_VALID_NONE: Number of times no items are valid for execution of instruction at CF address. Deterministic. Should be select value 92. x ]SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_ACTIVE: Number of items active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 93.  ^SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_ACTIVE_NONE: Number of times no items are active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 94. pP_SQ_PERF_SEL_CF_INST_CHECKPOINT_QUADS_ACTIVE: Number of pixel quads active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 95. `SQ_PERF_SEL_CF_INST_CHECKPOINT_QUADS_VALID: Number of pixel quads valid for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 96.  aSQ_PERF_SEL_CF_INST_CHECKPOINT_THREADS: Number of times a thread first reaches the CF address. Deterministic. Should be select value 97. 0bSQ_PERF_SEL_CF_INST_CHECKPOINT_THREAD_LEVEL: Number of threads that have reached the CF address per cycle. Should be select value 98. @cSQ_PERF_SEL_CF_INST_FETCH_PER_TYPE: Number of CF fetch requests from cache. Thread-type dependent. Should be select value 99. HdSQ_PERF_SEL_CF_INST_FETCH_RETURNS_PER_TYPE: Number of CF fetch return cycles from cache. Thread-type dependent. Should be select value 100. 0`eSQ_PERF_SEL_CF_INST_FETCH_INSTS_PER_TYPE: Number of CF instructions requested from cache. Thread-type dependent. Should be select value 101. PxfSQ_PERF_SEL_CF_INST_FETCH_LEVEL_PER_TYPE: Number of CF fetch requests from cache pending per cycle. Thread-type dependent. Should be select value 102. gSQ_PERF_SEL_CF_INST_FETCH_EXTRA_PER_TYPE: Number of times we didn't issue the second instruction in a pair. Does not include instructions after PROGRAM_END. Thread-type dependent. Deterministic. Should be select value 103. hSQ_PERF_SEL_CF_INST_FETCH_FIFO_SEND: Number of requests passing through the fetch fifo. Thread-type independent. Should be select value 104. iSQ_PERF_SEL_CF_INST_FETCH_FIFO_LEVEL: Control Flow Fetch fifo entry level. Thread-type independent. Should be select value 105.  jSQ_PERF_SEL_CF_INST_FETCH_FIFO_STALL: Number of cycles when the CF fetch fifo is stalling issues. Thread-type independent. Should be select value 106. @kSQ_PERF_SEL_CF_INST_CACHE_FIFO_SEND: Number of requests passing through the cache fifo. Thread-type independent. Should be select value 107. XlySQ_PERF_SEL_CF_INST_CACHE_FIFO_LEVEL: Number of credits in cache. Thread-type independent. Should be select value 108. XmSQ_PERF_SEL_CF_INST_CACHE_FIFO_FULL: Number of cycles when we have no cache credits. Thread-type independent. Should be select value 109. P hnSQ_PERF_SEL_CF_INST_ISSUE_DONES: Number of issues that need to be accounted for to avoid overflowing the done fifo. Thread-type independent. Should be select value 110. ! oSQ_PERF_SEL_CF_INST_ISSUE_DONE_LEVEL: Number of issues pending at any given time that need to be accounted for to avoid overflowing the done fifo. Thread-type independent. Should be select value 111. "!pSQ_PERF_SEL_CF_INST_ISSUE_DONE_STALL: Stalls triggered to avoid overflowing the done fifo. Thread-type independent. Should be select value 112. ##qSQ_PERF_SEL_CF_INST_ISSUE_DONE_FIFO_SEND: Number of items passing through the done fifo. Thread-type independent. Should be select value 113. $$rSQ_PERF_SEL_CF_INST_ISSUE_DONE_FIFO_LEVEL: Control Flow Done fifo entry level. Thread-type independent. Should be select value 114. %(%sSQ_PERF_SEL_CF_INST_ALU_UPDATE_FIFO_SEND: Macro sequencer alu update fifo send. Thread-type independent. Should be select value 115. '8&tSQ_PERF_SEL_CF_INST_ALU_UPDATE_FIFO_LEVEL: Macro sequencer alu update fifo level. Thread-type independent. Should be select value 116. 8(H'uSQ_PERF_SEL_CF_INST_ALU_UPDATE_FIFO_STALL: Number of cycles when the MS alu update fifo is stalling issues and alu returns. Thread-type independent. Should be select value 117. @)(vSQ_PERF_SEL_OFIFO_LEVEL_PER_TYPE: Number of threads and events in the ofifo. Thread-type dependent. Should be select value 118. P*)wSQ_PERF_SEL_SX_EVENT_FIFO_FULL_PER_TYPE: Number of cycles the SX event fifo is full. Thread-type dependent. Should be select value 119. x+*xSQ_PERF_SEL_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE: Number of ALU instruction groups executed. Thread-type dependent. Deterministic. Should be select value 120. ,+ySQ_PERF_SEL_ALU_CLAUSE_INSTRS_PER_TYPE: Number of ALU individual alu instructions executed. Thread-type dependent. Deterministic. Should be select value 121. -,zSQ_PERF_SEL_ALU_KWATERFALL_PER_TYPE: Number of ALU instruction groups which use const-waterfall. Thread-type dependent. Deterministic. Should be select value 122. /.{SQ_PERF_SEL_ALU_GPRWATERFALL_PER_TYPE: Number of ALU instruction groups which use gpr-waterfall. Thread-type dependent. Deterministic. Should be select value 123. H0H/|SQ_PERF_SEL_ALU_K_INSTR_PER_TYPE: Number of ALU instructions which use one or more constant (literal, kcache, or kfile). Thread-type dependent. Deterministic. Should be select value 124. `10}SQ_PERF_SEL_ALU_ICACHE_BUSY_PER_TYPE: Number of times ALU Icache read was denied - cache busy. Thread-type dependent. Should be select value 125. 21~SQ_PERF_SEL_ALU_KCACHE_BUSY_PER_TYPE: Number of times ALU Kcache/Kfile read was denied - cache busy. Thread-type dependent. Should be select value 126. 32SQ_PERF_SEL_ALU_MOVA_IDLE_WAIT_PER_TYPE: Number of instruction cycles idle waiting for MOVA to complete. Thread-type dependent. Should be select value 127. 43SQ_PERF_SEL_ALU_LOCK_WAIT: Number of times (1 every 4 clocks) ALU has clauses in input fifo but no clauses locked -- ALU is idle. Thread-type independent. Should be select value 128. 605SQ_PERF_SEL_ALU_ICACHE_READS_PER_TYPE: Number of read requests to the ALU I-cache. Thread-type dependent. Deterministic. Should be select value 129. 07P6SQ_PERF_SEL_ALU_KCACHE_READS_PER_TYPE: Number of read requests to the ALU K-cache/K-file. Thread-type dependent. Deterministic. Should be select value 130. P8x7SQ_PERF_SEL_ALU_DONE_FIFO_FULL: Number of times the done-fifo is full and that caused a stall. Thread-type independent. Should be select value 131. 98SQ_PERF_SEL_ALU_MOVA_WAIT_PER_TYPE: Number of times more than one SIMD tried to execute MOVA, and one was denied access. Thread-type dependent. Should be select value 132. :9SQ_PERF_SEL_ALU_THREADS_IN_FIFO_PER_TYPE: Number of threads waiting in the alu-seq's input fifo each cycle, of the selected thread type. Should be select value 133. X;;SQ_PERF_SEL_UNUSED_006;;SQ_PERF_SEL_UNUSED_007=@<SQ_PERF_SEL_TV_ICACHE_WAIT_PER_TYPE: Number of cycles the Tex/Vtx Icache denied a read request (busy). Thread-type dependent. Should be select value 136. =`=SQ_PERF_SEL_UNUSED_010X>>SQ_PERF_SEL_UNUSED_001>>SQ_PERF_SEL_UNUSED_002(@@?SQ_PERF_SEL_TF_TA_STALL_PER_TYPE: Number of times the TF had data to send to TA, but the TA input fifo was full. Thread-type dependent. Should be select value 140. hAp@SQ_PERF_SEL_VF_VC_INSTR_STALL_PER_TYPE: Number of times the VF had data to send to VC, but the VC instruction input fifo was full. Thread-type dependent. Should be select value 141. BASQ_PERF_SEL_VF_VC_INDEX_STALL_PER_TYPE: Number of times the VF had data to send to VC, but the VC index input fifo was full. Thread-type dependent. Should be select value 142. @CBSQ_PERF_SEL_UNUSED_003CCSQ_PERF_SEL_UNUSED_008D(DSQ_PERF_SEL_UNUSED_004 EDSQ_PERF_SEL_UNUSED_009 FhEwSQ_PERF_SEL_EXPORT_INSTR_PER_TYPE: Number of exports (seen by export-seq). Determinstic. Should be select value 147. GhF{SQ_PERF_SEL_EXPORT_IDLE: Number of clocks where export unit is idle. Thread-type independent. Should be select value 148. 8HhGSQ_PERF_SEL_EXPORT_SMX_AL_STALL: Number of clocks SMX export stalled waiting for alloc. Thread-type independent. Should be select value 149. HIHSQ_PERF_SEL_EXPORT_PC_AL_STALL: Number of clocks Param.cache alloc was stalled. Thread-type independent. Should be select value 150. XJISQ_PERF_SEL_EXPORT_POS_AL_STALL: Number of clocks Position export alloc was stalled. Thread-type independent. Should be select value 151. hKJSQ_PERF_SEL_EXPORT_PIX_AL_STALL: Number of clocks Pixel export alloc was stalled. Thread-type independent. Should be select value 152. LKSQ_PERF_SEL_EXPORT_POS_CYCLE: Number of position export cycles (4 clocks), * burst count). Thread-type independent. Determinstic. Should be select value 153. MLSQ_PERF_SEL_EXPORT_PIX_CYCLE: Number of pixel export cycles (4 clocks), * burst count). Thread-type independent. Determinstic. Should be select value 154. NNSQ_PERF_SEL_EXPORT_PC_CYCLE: Number of param.cache export cycles (4 clocks), * burst count). Thread-type independent. Determinstic. Should be select value 155. P(OSQ_PERF_SEL_EXPORT_SMX_CYCLE_PER_TYPE: Number of smx export cycles (4 clocks), * burst count). Thread-type dependent. Determinstic. Should be select value 156. 0QPPSQ_PERF_SEL_CACHE_INVAL_ANY: Number of cache invalidation (surface synchronization) operations of any kind. Thread-type independent. Should be select value 157. RxQSQ_PERF_SEL_CACHE_INVAL_ALL: Number of cache invalidation (surface synchronization) operations that invalidate the whole cache (due to a large invalidation region). Thread-type independent. Should be select value 158. TRSQ_PERF_SEL_CACHE_INVAL_CYCLES: Number of cache invalidation (surface synchronization) cycles, not including full invalidations; indicates the size of the invalidation regions in 4K byte increments. Thread-type independent. Should be select value 159. 0U`TSQ_PERF_SEL_CF_ICACHE_HITS: Number of CF instruction cache hits (it was found in the cache). Thread-type independent. Should be select value 160. HVxUSQ_PERF_SEL_TF_ICACHE_HITS: Number of TV instruction cache hits (it was found in the cache). Thread-type independent. Should be select value 161. WVQSQ_PERF_SEL_VF_ICACHE_HITS: DEPRECATED. Do not use. Should be select value 162. @XhWSQ_PERF_SEL_ALU_ICACHE_HITS: Number of ALU instruction cache hits (it was found in the cache). Thread-type independent. Should be select value 163. XYXSQ_PERF_SEL_ALU_KCACHE_HITS: Number of ALU constant cache hits (it was found in the cache). Thread-type independent. Should be select value 164. ZYSQ_PERF_SEL_CF_ICACHE_MISSES: Number of CF instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 165. [ZSQ_PERF_SEL_TF_ICACHE_MISSES: Number of TV instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 166. \0\SSQ_PERF_SEL_VF_ICACHE_MISSES: DEPRECATED. Do not use. Should be select value 167. ^]SQ_PERF_SEL_ALU_ICACHE_MISSES: Number of ALU instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 168. H_P^SQ_PERF_SEL_ALU_KCACHE_MISSES: Number of ALU constant cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 169. `_SQ_PERF_SEL_CF_ICACHE_DUP_MISSES: Number of CF instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 170. b`SQ_PERF_SEL_TF_ICACHE_DUP_MISSES: Number of TV instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 171. bPbWSQ_PERF_SEL_VF_ICACHE_DUP_MISSES: DEPRECATED. Do not use. Should be select value 172. Hd0cSQ_PERF_SEL_ALU_ICACHE_DUP_MISSES: Number of ALU instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 173. edSQ_PERF_SEL_ALU_KCACHE_DUP_MISSES: Number of ALU constant cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 174. geSQ_PERF_SEL_CF_ICACHE_ACCESSES: Number of CF instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 175. h`gSQ_PERF_SEL_TF_ICACHE_ACCESSES: Number of TV instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 176. hihUSQ_PERF_SEL_VF_ICACHE_ACCESSES: DEPRECATED. Do not use. Should be select value 177. jiSQ_PERF_SEL_ALU_ICACHE_ACCESSES: Number of ALU instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 178. Hl kSQ_PERF_SEL_ALU_KCACHE_ACCESSES: Number of ALU constant cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 179. pmlSQ_PERF_SEL_CF_ICACHE_INPUT_FIFO_ENTRIES: Count of CF instruction cache requests stored in the input FIFO. Thread-type independent. Should be select value 180. nmSQ_PERF_SEL_TF_ICACHE_INPUT_FIFO_ENTRIES: Count of TV instruction cache requests stored in the input FIFO. Thread-type independent. Should be select value 181. on_SQ_PERF_SEL_VF_ICACHE_INPUT_FIFO_ENTRIES: DEPRECATED. Do not use. Should be select value 182. poSQ_PERF_SEL_ALU_ICACHE_INPUT_FIFO_ENTRIES: Count of ALU instruction cache requests stored in the input FIFO. Thread-type independent. Should be select value 183. qpSQ_PERF_SEL_ALU_KCACHE_INPUT_FIFO_ENTRIES: Count of ALU constant cache requests stored in the input FIFO. Thread-type independent. Should be select value 184. 0srSQ_PERF_SEL_CF_ICACHE_MISS_MEM_STALL: Number of CF instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 185. txsSQ_PERF_SEL_TF_ICACHE_MISS_MEM_STALL: Number of TV instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 186. put[SQ_PERF_SEL_VF_ICACHE_MISS_MEM_STALL: DEPRECATED. Do not use. Should be select value 187. vuSQ_PERF_SEL_ALU_ICACHE_MISS_MEM_STALL: Number of ALU instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 188. 8x wSQ_PERF_SEL_ALU_KCACHE_MISS_MEM_STALL: Number of ALU constant cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 189. yxSQ_PERF_SEL_CF_ICACHE_MISS_FIFO_STALL: Number of CF instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 190. ({ySQ_PERF_SEL_TF_ICACHE_MISS_FIFO_STALL: Number of TV instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 191. |p{\SQ_PERF_SEL_VF_ICACHE_MISS_FIFO_STALL: DEPRECATED. Do not use. Should be select value 192. }P|SQ_PERF_SEL_ALU_ICACHE_MISS_FIFO_STALL: Number of ALU instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 193. ~}SQ_PERF_SEL_ALU_KCACHE_MISS_FIFO_STALL: Number of ALU constant cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 194. H@SQ_PERF_SEL_CF_ICACHE_HIT_STALL: Number of CF instruction cache cycles that are a cache hit but are stalled due to processing previous misses. Thread-type independent. Should be select value 195. SQ_PERF_SEL_CF_ICACHE_MISS_LOCKED_STALL: Number of CF instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 196. SQ_PERF_SEL_TF_ICACHE_MISS_LOCKED_STALL: Number of TV instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 197. `^SQ_PERF_SEL_VF_ICACHE_MISS_LOCKED_STALL: DEPRECATED. Do not use. Should be select value 198. hHSQ_PERF_SEL_ALU_ICACHE_MISS_LOCKED_STALL: Number of ALU instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 199. ІSQ_PERF_SEL_ALU_KCACHE_MISS_LOCKED_STALL: Number of ALU constant cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 200. (SQ_PERF_SEL_CF_ICACHE_LOCKED_TAGS: Count of CF instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 201. pSQ_PERF_SEL_TF_ICACHE_LOCKED_TAGS: Count of TV instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 202. `ȉXSQ_PERF_SEL_VF_ICACHE_LOCKED_TAGS: DEPRECATED. Do not use. Should be select value 203. SQ_PERF_SEL_ALU_ICACHE_LOCKED_TAGS: Count of ALU instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 204. SQ_PERF_SEL_ALU_KCACHE_LOCKED_TAGS: Count of ALU constant cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 205. PXSQ_PERF_SEL_CF_ICACHE_MISS_LOCKED_TAGS: Count of CF instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 206. SQ_PERF_SEL_TF_ICACHE_MISS_LOCKED_TAGS: Count of TV instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 207. x؏]SQ_PERF_SEL_VF_ICACHE_MISS_LOCKED_TAGS: DEPRECATED. Do not use. Should be select value 208. SQ_PERF_SEL_ALU_ICACHE_MISS_LOCKED_TAGS: Count of ALU instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 209. SQ_PERF_SEL_ALU_KCACHE_MISS_LOCKED_TAGS: Count of ALU constant cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 210. @SQ_PERF_SEL_CACHE_MEM_REQUESTS: Number of cache to memory controller requests of any type. Thread-type independent. Should be select value 211. 0XSQ_PERF_SEL_CF_ICACHE_MEM_REQUESTS: Number of CF instruction cache to memory controller requests. Thread-type independent. Should be select value 212. PxSQ_PERF_SEL_TV_ICACHE_MEM_REQUESTS: Number of TV instruction cache to memory controller requests. Thread-type independent. Should be select value 213. pSQ_PERF_SEL_ALU_ICACHE_MEM_REQUESTS: Number of ALU instruction cache to memory controller requests. Thread-type independent. Should be select value 214. SQ_PERF_SEL_ALU_KCACHE_MEM_REQUESTS: Number of ALU constant cache to memory controller requests. Thread-type independent. Should be select value 215. ЙؘSQ_PERF_SEL_CF_ICACHE_RD_WR_COLLISION: Number of times a read to the CF icache memory was blocked by a write from a memory return. Thread-type independent. Should be select value 216. SQ_PERF_SEL_CF_ICACHE_MISS_HIT_RD_COLLISION: Number of times processing a hit is stalled by processing a now-resident miss. Thread-type independent. Should be select value 217. XPSQ_PERF_SEL_CF_ICACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding CF instruction cache to memory controller requests of any type. Thread-type independent. Should be select value 218. SQ_PERF_SEL_TV_ICACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding TV instruction cache to memory controller requests of any type. Thread-type independent. Should be select value 219. SQ_PERF_SEL_ALU_ICACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding ALU instruction cache to memory controller requests of any type. Thread-type independent. Should be select value 220. H@SQ_PERF_SEL_ALU_KCACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding ALU constant cache to memory controller requests of any type. Thread-type independent. Should be select value 221. xSQ_PERF_SEL_CF_ICACHE_MISS_FIFO_MISSES: Count of the number of CF instruction cache misses waiting in the miss FIFO. Thread-type independent. Should be select value 222. SQ_PERF_SEL_TF_ICACHE_MISS_FIFO_MISSES: Count of the number of TV instruction cache misses waiting in the miss FIFO. Thread-type independent. Should be select value 223. ]SQ_PERF_SEL_VF_ICACHE_MISS_FIFO_MISSES: DEPRECATED. Do not use. Should be select value 224. ФأSQ_PERF_SEL_ALU_ICACHE_MISS_FIFO_MISSES: Count of the number of ALU instruction cache misses waiting in the miss FIFO. Divided by 2. Thread-type independent. Should be select value 225. SQ_PERF_SEL_ALU_KCACHE_MISS_FIFO_MISSES: Count of the number of ALU constant cache misses waiting in the miss FIFO. Divided by 2. Thread-type independent. Should be select value 226. XXSQ_PERF_SEL_CACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding cache to memory controller requests of any type. Divided by 2. Thread-type independent. Should be select value 227. pSQ_PERF_SEL_CACHE_MEM_STALL: Number of cache to memory controller cycles that are stalled. Thread-type independent. Should be select value 228. hqSQ_PERF_SEL_TM_TS64_STALL: Clock cycles GRBM stalled due to Timestamp-64 FIFO full. Should be select value 229. pSQ_PERF_SEL_TM_ALU_CONST_STALL: Clock cycles GRBM stalled due to ALU constant overflow buffer full. Should be select value 230. xSQ_PERF_SEL_TM_LOOP_CONST_STALL: Clock cycles GRBM stalled due to Loop constant overflow buffer full. Should be select value 231. SQ_PERF_SEL_TM_TEX_BASE_CONST_STALL: Clock cycles GRBM stalled due to VertexBase/InstantStart constant overflow buffer full. Should be select value 232. ଫSQ_PERF_SEL_TM_TEX_SAMPLER_STALL: Clock cycles GRBM stalled due to Texture Sampler constant overflow buffer full. Should be select value 233. ȮSQ_PERF_SEL_TM_TEX_RESOURCE_STALL: Clock cycles GRBM stalled due to Texture Resource constant overflow buffer full. Should be select value 234. hSQ_PERF_SEL_UNUSED_005SQ_PERF_SEL_TA_TEX_INSTRS_PER_TYPE: Number of texture-fetch instructions executed by the Texture cache, including killed fetches. Thread-type dependent. Determinstic. Should be select value 236. SQ_PERF_SEL_TA_VTX_INSTRS_PER_TYPE: Number of vertex-fetch instructions executed by the Texture cache, including killed fetches. Thread-type dependent. Determinstic. Should be select value 237. 8HSQ_PERF_SEL_VC_INSTRS_PER_TYPE: Number of instructions executed by the Vertex cache, including killed fetches. Thread-type dependent. Determinstic. Should be select value 238. hSQ_PERF_SEL_TV_LOCK_WAIT: Number of cycles the TF input FIFO had clauses, none were locked. Thread-type independent, non-deterministic. Should be select value 239. SQ_PERF_SEL_TA_SRC_C: Number of times an TA fetch (16 pix or verts) was executed as a src-c export. Non-deterministic. Should be select value 240. ȵSQ_PERF_SEL_VC_SRC_C: Number of times a VC fetch (16 pix or verts) was executed as a src-c export. Non-deterministic. Should be select value 241. ණSQ_PERF_SEL_TV_KILLED_FETCH_PER_TYPE: Number of fetch instructions killed (vertex semantic failed or gpr out of range). Deterministic. Should be select value 242. SQ_PERF_SEL_TV_NULL_FETCH_PER_TYPE: Number of null fetchs issued (null = issue empty fetch at end of clause due to killed fetches). Deterministic. Should be select value 243. (@SQ_PERF_SEL_TV_THREADS_IN_FIFO_PER_TYPE: Number of threads waiting in the fetch-seq's input fifo each cycle, of the selected thread type. Should be select value 244. 0pSQ_PERF_SEL_EXPORT_SPQ_LEVEL: Internal export per-quadpipe queue level average. Non-deterministic. Should be select value 245. xySQ_PERF_SEL_EXPORT_SPQ_STALL: Internal export per-quadpipe stall cycles. Non-deterministic. Should be select value 246. PмPS_EN8Exclude pixel shader threads from performance counters ؽ6Include pixel shader threads in performance counters p VS_EN89Exclude vertex shader threads from performance counters 7Include vertex shader threads in performance counters « GS_ENX;Exclude geometry shader threads from performance counters «9Include geometry shader threads in performance counters ī« 0ëES_ENëxë9Exclude export shader threads from performance counters 8ī7Include export shader threads in performance counters ƫū HūMAXƫūBAccumulate performance events (if both TEST_MODE and LIVE are 0) XƫXRetain maximum single-cycle performance event value (if both TEST_MODE and LIVE are 0) ɫHǫ ǫ TEST_MODEPȫǫ:Update performance counters based on MAX and LIVE fields ȫ7Shift in 1's rather than counting, For Debugging only hɫɫLIVEhʫɫ4Update performance counters based on the MAX field ʫMRetain the current single-cycle performance event value (if TEST_MODE is 0) PzȌȌ""`zSQ_PERF_CTR2_SEL`zzSEL{@{RSQ_PERF_SEL_NONE: don't count anything Deterministic. Should be select value 0. ||WSQ_PERF_SEL_CYCLES: Clock cycles. Thread-type independent. Should be select value 1. }|SQ_PERF_SEL_BUSY_CYCLES: Clock cycles while SQ is reporting that it is busy. Thread-type independent. Should be select value 2. ~~SQ_PERF_SEL_ANY_BUSY_PER_TYPE: Number of cycles we have a thread or an event. Thread-type dependent. Should be select value 3. HSQ_PERF_SEL_EVENTS_PER_TYPE: Number of events. Thread-type dependent. Caveat: Event counts are slightly unpredictable because they don't have an associated state and because we don't count events when we don't have acitve threads. Should be select value 4. HuSQ_PERF_SEL_EVENTS_BUSY_PER_TYPE: Number cycles we have an event. Thread-type dependent. Should be select value 5. PSQ_PERF_SEL_EVENT_LEVEL_PER_TYPE: Number of events in the pipeline per clock. Thread-type dependent. Should be select value 6. XSQ_PERF_SEL_ITEMS_PER_TYPE: Number of valid items per thread. Thread-type dependent. Deterministic. Should be select value 7. SQ_PERF_SEL_ITEMS_GT_48_PER_TYPE: Number of threads with a valid item in a position >= 48. Thread-type dependent. Deterministic. Should be select value 8. Ȅ SQ_PERF_SEL_ITEMS_GT_32_PER_TYPE: Number of threads with a valid item in a position >= 32. Thread-type dependent. Deterministic. Should be select value 9. І SQ_PERF_SEL_ITEMS_GT_16_PER_TYPE: Number of threads with a valid item in a position >= 16. Thread-type dependent. Deterministic. Should be select value 10. ȇ nSQ_PERF_SEL_QUADS: Number of valid pixel shader quads per thread. Deterministic. Should be select value 11. Ȉ wSQ_PERF_SEL_THREADS_BUSY_PER_TYPE: Number cycles we have a thread. Thread-type dependent. Should be select value 12.  tSQ_PERF_SEL_THREADS_PER_TYPE: Number of threads. Thread-type dependent. Deterministic Should be select value 13. ȊSQ_PERF_SEL_THREAD_LEVEL_PER_TYPE: Number of threads in the pipeline per clock. Thread-type dependent. Should be select value 14. ؋SQ_PERF_SEL_THREAD_LEVEL_WAIT_CREATE_PER_TYPE: Number of threads waiting to be created. Thread-type dependent. Should be select value 15. SQ_PERF_SEL_THREAD_LEVEL_UNALLOC_PARAM_PER_TYPE: Number of threads with parameter cache unallocated. Thread-type dependent. Should be select value 16. @SQ_PERF_SEL_THREAD_LEVEL_UNALLOC_PIX_PER_TYPE: Number of threads with pixel buffer unallocated. Thread-type dependent. Should be select value 17. 0XSQ_PERF_SEL_THREAD_LEVEL_UNALLOC_POS_PER_TYPE: Number of threads with position buffer unallocated. Thread-type dependent. Should be select value 18. `xSQ_PERF_SEL_THREADS_NONPS: Number of existing non-PS threads sharing the set of enabled thread-types with other selected NONPS counters. Should be select value 19. SQ_PERF_SEL_THREAD_LEVEL_NONPS: Number of existing non-PS threads per cycle sharing the set of enabled thread-types with other selected NONPS counters. Should be select value 20. SQ_PERF_SEL_THREAD_LEVEL_WAIT_ALLOC_NONPS: Number of non-PS threads waiting for export space to be allocated. Must share the set of enabled thread-types with other selected NONPS counters. Should be select value 21. p@SQ_PERF_SEL_THREAD_LEVEL_WAIT_OTHER_NONPS: Number of non-PS threads waiting for instructions to be fetched or completed. Must share the set of enabled thread-types with other selected SHARED_TYPESET counters. Should be select value 22. xSQ_PERF_SEL_THREAD_LEVEL_WAIT_ALLOC_PS: Number of PS threads waiting for pixel buffer to be allocated. Should be select value 23. SQ_PERF_SEL_THREAD_LEVEL_WAIT_OTHER_PS: Number of PS threads waiting for for instructions to be fetched or completed. Should be select value 24. ؖSQ_PERF_SEL_CF_INST_ISSUES_PER_TYPE: Number of CF instruction issues. Thread-type dependent. Deterministic. Should be select value 25. 藩SQ_PERF_SEL_CF_INST_ISSUE_ONE: Number of times only a single instruction is issued on a cycle. Thread-type independent. Should be select value 26. ؙSQ_PERF_SEL_CF_INST_ISSUE_TWO: Number of times two instructions are issued in a single cycle. Thread-type independent. Should be select value 27. SQ_PERF_SEL_CF_INST_ISSUE_IDLE_PER_TYPE: Number of cycles when threads exist but no threads are ready to issue. Thread-type dependent. Should be select value 28. XHSQ_PERF_SEL_CF_INST_ISSUE_FS_PER_TYPE: Number of instructions executed in Fetch Shader Mode. Does not include initial CALL_FS instruction. Thread-type dependent. Deterministic. Should be select value 29. pSQ_PERF_SEL_CF_INST_ISSUE_ALU_PER_TYPE: Number of CF_ALU instructions issued. Thread-type dependent. Deterministic. Should be select value 30. SQ_PERF_SEL_CF_INST_ISSUE_TF_PER_TYPE: Number of CF_TF instructions issued. Thread-type dependent. Deterministic. Should be select value 31. О SQ_PERF_SEL_CF_INST_ISSUE_VF_PER_TYPE: Number of CF_VF instructions issued. Thread-type dependent. Deterministic. Should be select value 32. 蟩!SQ_PERF_SEL_CF_INST_ISSUE_EX_PER_TYPE: Number of Export instructions issued. Thread-type dependent. Deterministic. Should be select value 33. ء"SQ_PERF_SEL_CF_INST_ISSUE_SMX_WR_PER_TYPE: Number of SMX write instructions issued. Thread-type dependent. Deterministic. Should be select value 34. #SQ_PERF_SEL_CF_INST_ISSUE_SMX_RD_PER_TYPE: Number of SMX read instructions issued. Thread-type dependent. Deterministic. Should be select value 35. @$SQ_PERF_SEL_CF_INST_ISSUE_GF_PER_TYPE: Number of geometry instructions issued. Thread-type dependent. Deterministic. Should be select value 36. @X%SQ_PERF_SEL_CF_INST_ISSUE_OTHER_PER_TYPE: Number of non-ALU/TF/VF/EX/SMX/GF instructions issued. Thread-type dependent. Deterministic. Should be select value 37. X&SQ_PERF_SEL_CF_INST_ISSUE_ALU_CF_PER_TYPE: Number of ALU CF tags processed. Thread-type dependent. Deterministic. Should be select value 38. x'SQ_PERF_SEL_CF_INST_ISSUE_BL_PER_TYPE: Number of OTHER and ALU CF tags processed. Thread-type dependent. Deterministic. Should be select value 39. (SQ_PERF_SEL_CF_INST_REJECT_ALU_PER_TYPE: Number of ALU instructions scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 40. )SQ_PERF_SEL_CF_INST_REJECT_TF_PER_TYPE: Number of times a Texture Fetch instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 41. 08*SQ_PERF_SEL_CF_INST_REJECT_VF_PER_TYPE: Number of times a Vertex Fetch instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 42. px+SQ_PERF_SEL_CF_INST_REJECT_EX_PER_TYPE: Number of times an Export instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 43. ,SQ_PERF_SEL_CF_INST_REJECT_SMX_WR_PER_TYPE: Number of times a SMX write instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 44. -SQ_PERF_SEL_CF_INST_REJECT_SMX_RD_PER_TYPE: Number of times a SMX read instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 45. @.SQ_PERF_SEL_CF_INST_REJECT_GF_PER_TYPE: Number of geometry instructions trivially rejected. Thread-type dependent. Deterministic. Should be select value 46. Ph/SQ_PERF_SEL_CF_INST_REJECT_OTHER_PER_TYPE: Number of non-ALU/TF/VF/EX/SMX/GF instructions rejected. Thread-type dependent. Deterministic. Should be select value 47. h0SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_PER_TYPE: Number of instructions sent to ALU. Thread-type dependent. Deterministic. Should be select value 48. 1SQ_PERF_SEL_CF_INST_FIFO_SEND_TF_PER_TYPE: Number of instructions sent to Texture Fetch unit. Thread-type dependent. Deterministic. Should be select value 49. س2SQ_PERF_SEL_CF_INST_FIFO_SEND_VF_PER_TYPE: Number of instructions sent to Vertex Fetch unit. Thread-type dependent. Deterministic. Should be select value 50. ص3SQ_PERF_SEL_CF_INST_FIFO_SEND_EX_PER_TYPE: Number of instructions sent to Export unit. Thread-type dependent. Deterministic. Should be select value 51.  4SQ_PERF_SEL_CF_INST_FIFO_SEND_SMX_WR_PER_TYPE: Number of write instructions sent to SMX Export unit. Thread-type dependent. Deterministic. Should be select value 52. 8P5SQ_PERF_SEL_CF_INST_FIFO_SEND_SMX_RD_PER_TYPE: Number of read instructions sent to SMX Export unit. Thread-type dependent. Deterministic. Should be select value 53. X6SQ_PERF_SEL_CF_INST_FIFO_SEND_GF_PER_TYPE: Number of geometry instructions executed. Thread-type dependent. Deterministic. Should be select value 54. 7SQ_PERF_SEL_CF_INST_FIFO_SEND_OTHER_PER_TYPE: Number of non-ALU/TF/VF/EX/SMX/GF instructions executed. Thread-type dependent. Deterministic. Should be select value 55. лк8SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_NONE_PER_TYPE: Number of instructions sent to ALU with no kcache regions locked. Thread-type dependent. Deterministic. Should be select value 56. 9SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_ONE_PER_TYPE: Number of instructions sent to ALU with one kcache regions locked. Thread-type dependent. Deterministic. Should be select value 57. ``:SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_TWO_PER_TYPE: Number of instructions sent to ALU with two kcache regions locked. Thread-type dependent. Deterministic. Should be select value 58. ;SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_PER_TYPE: Number of kcache region locks in instructions sent to ALU. Thread-type dependent. Deterministic. Should be select value 59. ࿩<~SQ_PERF_SEL_CF_INST_FIFO_FULL_ALU: Number of ALU units full on a cycle. Thread-type independent. Should be select value 60. =SQ_PERF_SEL_CF_INST_FIFO_FULL_TF: Number of cycles the Texture Fetch unit was full. Thread-type independent. Should be select value 61. ©>SQ_PERF_SEL_CF_INST_FIFO_FULL_VF: Number of cycles the Vertex Fetch unit was full. Thread-type independent. Should be select value 62. éé?SQ_PERF_SEL_CF_INST_FIFO_FULL_EX: Number of cycles the Export unit was full. Thread-type independent. Should be select value 63. ĩĩ@SQ_PERF_SEL_CF_INST_FIFO_FULL_SMX: Number of cycles the SMX Export unit was full. Thread-type independent. Should be select value 64. ũ ũASQ_PERF_SEL_CF_INST_FIFO_FULL_GF: Number of cycles the Geometry Fifo was full. Thread-type independent. Should be select value 65. Ʃ0ƩBKSQ_PERF_SEL_CF_INST_FIFO_FULL_OTHER: Reserved. Should be select value 66. ǩǩCSQ_PERF_SEL_CF_INST_FIFO_LEVEL_ALU: Number of credits available for all ALU units. Thread-type independent. Should be select value 67. ȩȩDSQ_PERF_SEL_CF_INST_FIFO_LEVEL_TF: Number of credits available for TF unit. Thread-type independent. Should be select value 68. ɩɩESQ_PERF_SEL_CF_INST_FIFO_LEVEL_VF: Number of credits available for VF unit. Thread-type independent. Should be select value 69. ʩ ʩFSQ_PERF_SEL_CF_INST_FIFO_LEVEL_EX: Number of credits available for EX unit. Thread-type independent. Should be select value 70. ˩(˩GSQ_PERF_SEL_CF_INST_FIFO_LEVEL_SMX: Number of credits available for SMX unit. Thread-type independent. Should be select value 71. ̩0̩HSQ_PERF_SEL_CF_INST_FIFO_LEVEL_GF: Number of credits available for Geometry Fifo. Thread-type independent. Should be select value 72. ͩ@ͩILSQ_PERF_SEL_CF_INST_FIFO_LEVEL_OTHER: Reserved. Should be select value 73. ΩΩJSQ_PERF_SEL_CF_INST_FIFO_EMPTY_ALU: Number of ALU units empty on a cycle. Thread-type independent. Should be select value 74. ϩϩKSQ_PERF_SEL_CF_INST_FIFO_EMPTY_TF: Number of cycles the Texture Fetch unit was empty. Thread-type independent. Should be select value 75. Щ(ЩLSQ_PERF_SEL_CF_INST_FIFO_EMPTY_VF: Number of cycles the Vertex Fetch unit was empty. Thread-type independent. Should be select value 76. ҩ8ѩMSQ_PERF_SEL_CF_INST_FIFO_EMPTY_EX: Number of cycles the Export unit was empty. Thread-type independent. Should be select value 77. өHҩNSQ_PERF_SEL_CF_INST_FIFO_EMPTY_SMX: Number of cycles the SMX unit was empty. Thread-type independent. Should be select value 78. ԩPөOSQ_PERF_SEL_CF_INST_FIFO_EMPTY_GF: Number of cycles the Geometry fifo was empty. Thread-type independent. Should be select value 79. ԩ`ԩPLSQ_PERF_SEL_CF_INST_FIFO_EMPTY_OTHER: Reserved. Should be select value 80. ֩0թQSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_ALU_PER_TYPE: Number of instructions outstanding for all ALU units. Thread-type dependent. Should be select value 81. שP֩RSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_TF_PER_TYPE: Number of instructions outstanding for TF unit. Thread-type dependent. Should be select value 82. 8ةhשSSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_VF_PER_TYPE: Number of instructions outstanding for VF unit. Thread-type ependent. Should be select value 83. P٩ةTSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_EX_PER_TYPE: Number of instructions outstanding for EX unit. Thread-type dependent. Should be select value 84. pک٩USQ_PERF_SEL_CF_INST_ISSUE_LEVEL_SMX_WR_PER_TYPE: Number of write instructions outstanding for SMX unit. Thread-type dependent. Should be select value 85. ۩کVSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_SMX_RD_PER_TYPE: Number of read instructions outstanding for SMX unit. Thread-type dependent. Should be select value 86. ܩ۩WSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_GF_PER_TYPE: Number of instructions outstanding for Geometry Fifo. Thread-type dependent. Should be select value 87. ݩܩXSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_OTHER_PER_TYPE: Number of instructions outstanding for non-ALU/TF/VF/EX/SMX/GF. Thread-type dependent. Should be select value 88. ީ ީYSQ_PERF_SEL_CF_INST_CHECKPOINT: Number of times user specified CF address is executed. Deterministic. Should be select value 89. (ߩZSQ_PERF_SEL_CF_INST_CHECKPOINT_BEFORE: Number of CF instructions executed including and after the specified CF address. Deterministic. Should be select value 90. (P[SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_VALID: Number of items valid for execution of instruction at CF address. Deterministic. Should be select value 91. Xp\SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_VALID_NONE: Number of times no items are valid for execution of instruction at CF address. Deterministic. Should be select value 92. ]SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_ACTIVE: Number of items active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 93. 0^SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_ACTIVE_NONE: Number of times no items are active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 94. x_SQ_PERF_SEL_CF_INST_CHECKPOINT_QUADS_ACTIVE: Number of pixel quads active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 95. `SQ_PERF_SEL_CF_INST_CHECKPOINT_QUADS_VALID: Number of pixel quads valid for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 96. HaSQ_PERF_SEL_CF_INST_CHECKPOINT_THREADS: Number of times a thread first reaches the CF address. Deterministic. Should be select value 97. XbSQ_PERF_SEL_CF_INST_CHECKPOINT_THREAD_LEVEL: Number of threads that have reached the CF address per cycle. Should be select value 98. (hcSQ_PERF_SEL_CF_INST_FETCH_PER_TYPE: Number of CF fetch requests from cache. Thread-type dependent. Should be select value 99. @pdSQ_PERF_SEL_CF_INST_FETCH_RETURNS_PER_TYPE: Number of CF fetch return cycles from cache. Thread-type dependent. Should be select value 100. XeSQ_PERF_SEL_CF_INST_FETCH_INSTS_PER_TYPE: Number of CF instructions requested from cache. Thread-type dependent. Should be select value 101. xfSQ_PERF_SEL_CF_INST_FETCH_LEVEL_PER_TYPE: Number of CF fetch requests from cache pending per cycle. Thread-type dependent. Should be select value 102. gSQ_PERF_SEL_CF_INST_FETCH_EXTRA_PER_TYPE: Number of times we didn't issue the second instruction in a pair. Does not include instructions after PROGRAM_END. Thread-type dependent. Deterministic. Should be select value 103. (hSQ_PERF_SEL_CF_INST_FETCH_FIFO_SEND: Number of requests passing through the fetch fifo. Thread-type independent. Should be select value 104. @iSQ_PERF_SEL_CF_INST_FETCH_FIFO_LEVEL: Control Flow Fetch fifo entry level. Thread-type independent. Should be select value 105. HjSQ_PERF_SEL_CF_INST_FETCH_FIFO_STALL: Number of cycles when the CF fetch fifo is stalling issues. Thread-type independent. Should be select value 106. 8hkSQ_PERF_SEL_CF_INST_CACHE_FIFO_SEND: Number of requests passing through the cache fifo. Thread-type independent. Should be select value 107. 8lySQ_PERF_SEL_CF_INST_CACHE_FIFO_LEVEL: Number of credits in cache. Thread-type independent. Should be select value 108. HmSQ_PERF_SEL_CF_INST_CACHE_FIFO_FULL: Number of cycles when we have no cache credits. Thread-type independent. Should be select value 109. xnSQ_PERF_SEL_CF_INST_ISSUE_DONES: Number of issues that need to be accounted for to avoid overflowing the done fifo. Thread-type independent. Should be select value 110. oSQ_PERF_SEL_CF_INST_ISSUE_DONE_LEVEL: Number of issues pending at any given time that need to be accounted for to avoid overflowing the done fifo. Thread-type independent. Should be select value 111. pSQ_PERF_SEL_CF_INST_ISSUE_DONE_STALL: Stalls triggered to avoid overflowing the done fifo. Thread-type independent. Should be select value 112. (qSQ_PERF_SEL_CF_INST_ISSUE_DONE_FIFO_SEND: Number of items passing through the done fifo. Thread-type independent. Should be select value 113. @rSQ_PERF_SEL_CF_INST_ISSUE_DONE_FIFO_LEVEL: Control Flow Done fifo entry level. Thread-type independent. Should be select value 114. PsSQ_PERF_SEL_CF_INST_ALU_UPDATE_FIFO_SEND: Macro sequencer alu update fifo send. Thread-type independent. Should be select value 115. (`tSQ_PERF_SEL_CF_INST_ALU_UPDATE_FIFO_LEVEL: Macro sequencer alu update fifo level. Thread-type independent. Should be select value 116. `puSQ_PERF_SEL_CF_INST_ALU_UPDATE_FIFO_STALL: Number of cycles when the MS alu update fifo is stalling issues and alu returns. Thread-type independent. Should be select value 117. hvSQ_PERF_SEL_OFIFO_LEVEL_PER_TYPE: Number of threads and events in the ofifo. Thread-type dependent. Should be select value 118. xwSQ_PERF_SEL_SX_EVENT_FIFO_FULL_PER_TYPE: Number of cycles the SX event fifo is full. Thread-type dependent. Should be select value 119. xSQ_PERF_SEL_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE: Number of ALU instruction groups executed. Thread-type dependent. Deterministic. Should be select value 120. ySQ_PERF_SEL_ALU_CLAUSE_INSTRS_PER_TYPE: Number of ALU individual alu instructions executed. Thread-type dependent. Deterministic. Should be select value 121. zSQ_PERF_SEL_ALU_KWATERFALL_PER_TYPE: Number of ALU instruction groups which use const-waterfall. Thread-type dependent. Deterministic. Should be select value 122. (@{SQ_PERF_SEL_ALU_GPRWATERFALL_PER_TYPE: Number of ALU instruction groups which use gpr-waterfall. Thread-type dependent. Deterministic. Should be select value 123. pp|SQ_PERF_SEL_ALU_K_INSTR_PER_TYPE: Number of ALU instructions which use one or more constant (literal, kcache, or kfile). Thread-type dependent. Deterministic. Should be select value 124. }SQ_PERF_SEL_ALU_ICACHE_BUSY_PER_TYPE: Number of times ALU Icache read was denied - cache busy. Thread-type dependent. Should be select value 125. ~SQ_PERF_SEL_ALU_KCACHE_BUSY_PER_TYPE: Number of times ALU Kcache/Kfile read was denied - cache busy. Thread-type dependent. Should be select value 126. SQ_PERF_SEL_ALU_MOVA_IDLE_WAIT_PER_TYPE: Number of instruction cycles idle waiting for MOVA to complete. Thread-type dependent. Should be select value 127.   SQ_PERF_SEL_ALU_LOCK_WAIT: Number of times (1 every 4 clocks) ALU has clauses in input fifo but no clauses locked -- ALU is idle. Thread-type independent. Should be select value 128. 0 X SQ_PERF_SEL_ALU_ICACHE_READS_PER_TYPE: Number of read requests to the ALU I-cache. Thread-type dependent. Deterministic. Should be select value 129. Xx SQ_PERF_SEL_ALU_KCACHE_READS_PER_TYPE: Number of read requests to the ALU K-cache/K-file. Thread-type dependent. Deterministic. Should be select value 130. xSQ_PERF_SEL_ALU_DONE_FIFO_FULL: Number of times the done-fifo is full and that caused a stall. Thread-type independent. Should be select value 131. SQ_PERF_SEL_ALU_MOVA_WAIT_PER_TYPE: Number of times more than one SIMD tried to execute MOVA, and one was denied access. Thread-type dependent. Should be select value 132. SQ_PERF_SEL_ALU_THREADS_IN_FIFO_PER_TYPE: Number of threads waiting in the alu-seq's input fifo each cycle, of the selected thread type. Should be select value 133. (SQ_PERF_SEL_UNUSED_006 SQ_PERF_SEL_UNUSED_007@hSQ_PERF_SEL_TV_ICACHE_WAIT_PER_TYPE: Number of cycles the Tex/Vtx Icache denied a read request (busy). Thread-type dependent. Should be select value 136. SQ_PERF_SEL_UNUSED_010(SQ_PERF_SEL_UNUSED_001 SQ_PERF_SEL_UNUSED_002PhSQ_PERF_SEL_TF_TA_STALL_PER_TYPE: Number of times the TF had data to send to TA, but the TA input fifo was full. Thread-type dependent. Should be select value 140. SQ_PERF_SEL_VF_VC_INSTR_STALL_PER_TYPE: Number of times the VF had data to send to VC, but the VC instruction input fifo was full. Thread-type dependent. Should be select value 141. SQ_PERF_SEL_VF_VC_INDEX_STALL_PER_TYPE: Number of times the VF had data to send to VC, but the VC index input fifo was full. Thread-type dependent. Should be select value 142. hSQ_PERF_SEL_UNUSED_003SQ_PERF_SEL_UNUSED_008PSQ_PERF_SEL_UNUSED_004HSQ_PERF_SEL_UNUSED_009HwSQ_PERF_SEL_EXPORT_INSTR_PER_TYPE: Number of exports (seen by export-seq). Determinstic. Should be select value 147. H{SQ_PERF_SEL_EXPORT_IDLE: Number of clocks where export unit is idle. Thread-type independent. Should be select value 148. `SQ_PERF_SEL_EXPORT_SMX_AL_STALL: Number of clocks SMX export stalled waiting for alloc. Thread-type independent. Should be select value 149. p SQ_PERF_SEL_EXPORT_PC_AL_STALL: Number of clocks Param.cache alloc was stalled. Thread-type independent. Should be select value 150. ! SQ_PERF_SEL_EXPORT_POS_AL_STALL: Number of clocks Position export alloc was stalled. Thread-type independent. Should be select value 151. "!SQ_PERF_SEL_EXPORT_PIX_AL_STALL: Number of clocks Pixel export alloc was stalled. Thread-type independent. Should be select value 152. #"SQ_PERF_SEL_EXPORT_POS_CYCLE: Number of position export cycles (4 clocks), * burst count). Thread-type independent. Determinstic. Should be select value 153. $$SQ_PERF_SEL_EXPORT_PIX_CYCLE: Number of pixel export cycles (4 clocks), * burst count). Thread-type independent. Determinstic. Should be select value 154. &(%SQ_PERF_SEL_EXPORT_PC_CYCLE: Number of param.cache export cycles (4 clocks), * burst count). Thread-type independent. Determinstic. Should be select value 155. 0'P&SQ_PERF_SEL_EXPORT_SMX_CYCLE_PER_TYPE: Number of smx export cycles (4 clocks), * burst count). Thread-type dependent. Determinstic. Should be select value 156. X(x'SQ_PERF_SEL_CACHE_INVAL_ANY: Number of cache invalidation (surface synchronization) operations of any kind. Thread-type independent. Should be select value 157. )(SQ_PERF_SEL_CACHE_INVAL_ALL: Number of cache invalidation (surface synchronization) operations that invalidate the whole cache (due to a large invalidation region). Thread-type independent. Should be select value 158. @+*SQ_PERF_SEL_CACHE_INVAL_CYCLES: Number of cache invalidation (surface synchronization) cycles, not including full invalidations; indicates the size of the invalidation regions in 4K byte increments. Thread-type independent. Should be select value 159. X,+SQ_PERF_SEL_CF_ICACHE_HITS: Number of CF instruction cache hits (it was found in the cache). Thread-type independent. Should be select value 160. p-,SQ_PERF_SEL_TF_ICACHE_HITS: Number of TV instruction cache hits (it was found in the cache). Thread-type independent. Should be select value 161. H.-QSQ_PERF_SEL_VF_ICACHE_HITS: DEPRECATED. Do not use. Should be select value 162. h/.SQ_PERF_SEL_ALU_ICACHE_HITS: Number of ALU instruction cache hits (it was found in the cache). Thread-type independent. Should be select value 163. 0/SQ_PERF_SEL_ALU_KCACHE_HITS: Number of ALU constant cache hits (it was found in the cache). Thread-type independent. Should be select value 164. 10SQ_PERF_SEL_CF_ICACHE_MISSES: Number of CF instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 165. 32SQ_PERF_SEL_TF_ICACHE_MISSES: Number of TV instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 166. 3X3SSQ_PERF_SEL_VF_ICACHE_MISSES: DEPRECATED. Do not use. Should be select value 167. 0504SQ_PERF_SEL_ALU_ICACHE_MISSES: Number of ALU instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 168. p6x5SQ_PERF_SEL_ALU_KCACHE_MISSES: Number of ALU constant cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 169. 76SQ_PERF_SEL_CF_ICACHE_DUP_MISSES: Number of CF instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 170. 098SQ_PERF_SEL_TF_ICACHE_DUP_MISSES: Number of TV instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 171. :x9WSQ_PERF_SEL_VF_ICACHE_DUP_MISSES: DEPRECATED. Do not use. Should be select value 172. p;X:SQ_PERF_SEL_ALU_ICACHE_DUP_MISSES: Number of ALU instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 173. <;SQ_PERF_SEL_ALU_KCACHE_DUP_MISSES: Number of ALU constant cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 174. @>=SQ_PERF_SEL_CF_ICACHE_ACCESSES: Number of CF instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 175. ?>SQ_PERF_SEL_TF_ICACHE_ACCESSES: Number of TV instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 176. @?USQ_PERF_SEL_VF_ICACHE_ACCESSES: DEPRECATED. Do not use. Should be select value 177. B@SQ_PERF_SEL_ALU_ICACHE_ACCESSES: Number of ALU instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 178. pCHBSQ_PERF_SEL_ALU_KCACHE_ACCESSES: Number of ALU constant cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 179. DCSQ_PERF_SEL_CF_ICACHE_INPUT_FIFO_ENTRIES: Count of CF instruction cache requests stored in the input FIFO. Thread-type independent. Should be select value 180. EDSQ_PERF_SEL_TF_ICACHE_INPUT_FIFO_ENTRIES: Count of TV instruction cache requests stored in the input FIFO. Thread-type independent. Should be select value 181. FF_SQ_PERF_SEL_VF_ICACHE_INPUT_FIFO_ENTRIES: DEPRECATED. Do not use. Should be select value 182. GFSQ_PERF_SEL_ALU_ICACHE_INPUT_FIFO_ENTRIES: Count of ALU instruction cache requests stored in the input FIFO. Thread-type independent. Should be select value 183. HHSQ_PERF_SEL_ALU_KCACHE_INPUT_FIFO_ENTRIES: Count of ALU constant cache requests stored in the input FIFO. Thread-type independent. Should be select value 184. XJ@ISQ_PERF_SEL_CF_ICACHE_MISS_MEM_STALL: Number of CF instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 185. KJSQ_PERF_SEL_TF_ICACHE_MISS_MEM_STALL: Number of TV instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 186. LL[SQ_PERF_SEL_VF_ICACHE_MISS_MEM_STALL: DEPRECATED. Do not use. Should be select value 187. NLSQ_PERF_SEL_ALU_ICACHE_MISS_MEM_STALL: Number of ALU instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 188. `OHNSQ_PERF_SEL_ALU_KCACHE_MISS_MEM_STALL: Number of ALU constant cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 189. POSQ_PERF_SEL_CF_ICACHE_MISS_FIFO_STALL: Number of CF instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 190. PR QSQ_PERF_SEL_TF_ICACHE_MISS_FIFO_STALL: Number of TV instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 191. 0SR\SQ_PERF_SEL_VF_ICACHE_MISS_FIFO_STALL: DEPRECATED. Do not use. Should be select value 192. TxSSQ_PERF_SEL_ALU_ICACHE_MISS_FIFO_STALL: Number of ALU instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 193. VTSQ_PERF_SEL_ALU_KCACHE_MISS_FIFO_STALL: Number of ALU constant cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 194. pWhVSQ_PERF_SEL_CF_ICACHE_HIT_STALL: Number of CF instruction cache cycles that are a cache hit but are stalled due to processing previous misses. Thread-type independent. Should be select value 195. XWSQ_PERF_SEL_CF_ICACHE_MISS_LOCKED_STALL: Number of CF instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 196. @Z YSQ_PERF_SEL_TF_ICACHE_MISS_LOCKED_STALL: Number of TV instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 197. ([Z^SQ_PERF_SEL_VF_ICACHE_MISS_LOCKED_STALL: DEPRECATED. Do not use. Should be select value 198. \p[SQ_PERF_SEL_ALU_ICACHE_MISS_LOCKED_STALL: Number of ALU instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 199. ]\SQ_PERF_SEL_ALU_KCACHE_MISS_LOCKED_STALL: Number of ALU constant cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 200. P_@^SQ_PERF_SEL_CF_ICACHE_LOCKED_TAGS: Count of CF instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 201. `_SQ_PERF_SEL_TF_ICACHE_LOCKED_TAGS: Count of TV instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 202. a`XSQ_PERF_SEL_VF_ICACHE_LOCKED_TAGS: DEPRECATED. Do not use. Should be select value 203. baSQ_PERF_SEL_ALU_ICACHE_LOCKED_TAGS: Count of ALU instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 204. 8d(cSQ_PERF_SEL_ALU_KCACHE_LOCKED_TAGS: Count of ALU constant cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 205. xedSQ_PERF_SEL_CF_ICACHE_MISS_LOCKED_TAGS: Count of CF instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 206. feSQ_PERF_SEL_TF_ICACHE_MISS_LOCKED_TAGS: Count of TV instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 207. gg]SQ_PERF_SEL_VF_ICACHE_MISS_LOCKED_TAGS: DEPRECATED. Do not use. Should be select value 208. hgSQ_PERF_SEL_ALU_ICACHE_MISS_LOCKED_TAGS: Count of ALU instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 209. j(iSQ_PERF_SEL_ALU_KCACHE_MISS_LOCKED_TAGS: Count of ALU constant cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 210. 8khjSQ_PERF_SEL_CACHE_MEM_REQUESTS: Number of cache to memory controller requests of any type. Thread-type independent. Should be select value 211. XlkSQ_PERF_SEL_CF_ICACHE_MEM_REQUESTS: Number of CF instruction cache to memory controller requests. Thread-type independent. Should be select value 212. xmlSQ_PERF_SEL_TV_ICACHE_MEM_REQUESTS: Number of TV instruction cache to memory controller requests. Thread-type independent. Should be select value 213. nmSQ_PERF_SEL_ALU_ICACHE_MEM_REQUESTS: Number of ALU instruction cache to memory controller requests. Thread-type independent. Should be select value 214. onSQ_PERF_SEL_ALU_KCACHE_MEM_REQUESTS: Number of ALU constant cache to memory controller requests. Thread-type independent. Should be select value 215. qpSQ_PERF_SEL_CF_ICACHE_RD_WR_COLLISION: Number of times a read to the CF icache memory was blocked by a write from a memory return. Thread-type independent. Should be select value 216. 8rHqSQ_PERF_SEL_CF_ICACHE_MISS_HIT_RD_COLLISION: Number of times processing a hit is stalled by processing a now-resident miss. Thread-type independent. Should be select value 217. srSQ_PERF_SEL_CF_ICACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding CF instruction cache to memory controller requests of any type. Thread-type independent. Should be select value 218. tsSQ_PERF_SEL_TV_ICACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding TV instruction cache to memory controller requests of any type. Thread-type independent. Should be select value 219. (v uSQ_PERF_SEL_ALU_ICACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding ALU instruction cache to memory controller requests of any type. Thread-type independent. Should be select value 220. xwpvSQ_PERF_SEL_ALU_KCACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding ALU constant cache to memory controller requests of any type. Thread-type independent. Should be select value 221. xwSQ_PERF_SEL_CF_ICACHE_MISS_FIFO_MISSES: Count of the number of CF instruction cache misses waiting in the miss FIFO. Thread-type independent. Should be select value 222. yxSQ_PERF_SEL_TF_ICACHE_MISS_FIFO_MISSES: Count of the number of TV instruction cache misses waiting in the miss FIFO. Thread-type independent. Should be select value 223. z z]SQ_PERF_SEL_VF_ICACHE_MISS_FIFO_MISSES: DEPRECATED. Do not use. Should be select value 224. |{SQ_PERF_SEL_ALU_ICACHE_MISS_FIFO_MISSES: Count of the number of ALU instruction cache misses waiting in the miss FIFO. Divided by 2. Thread-type independent. Should be select value 225. @}H|SQ_PERF_SEL_ALU_KCACHE_MISS_FIFO_MISSES: Count of the number of ALU constant cache misses waiting in the miss FIFO. Divided by 2. Thread-type independent. Should be select value 226. ~}SQ_PERF_SEL_CACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding cache to memory controller requests of any type. Divided by 2. Thread-type independent. Should be select value 227. ~SQ_PERF_SEL_CACHE_MEM_STALL: Number of cache to memory controller cycles that are stalled. Thread-type independent. Should be select value 228. qSQ_PERF_SEL_TM_TS64_STALL: Clock cycles GRBM stalled due to Timestamp-64 FIFO full. Should be select value 229. SQ_PERF_SEL_TM_ALU_CONST_STALL: Clock cycles GRBM stalled due to ALU constant overflow buffer full. Should be select value 230. 聪SQ_PERF_SEL_TM_LOOP_CONST_STALL: Clock cycles GRBM stalled due to Loop constant overflow buffer full. Should be select value 231. ȃSQ_PERF_SEL_TM_TEX_BASE_CONST_STALL: Clock cycles GRBM stalled due to VertexBase/InstantStart constant overflow buffer full. Should be select value 232. SQ_PERF_SEL_TM_TEX_SAMPLER_STALL: Clock cycles GRBM stalled due to Texture Sampler constant overflow buffer full. Should be select value 233. (SQ_PERF_SEL_TM_TEX_RESOURCE_STALL: Clock cycles GRBM stalled due to Texture Resource constant overflow buffer full. Should be select value 234. @SQ_PERF_SEL_UNUSED_005自SQ_PERF_SEL_TA_TEX_INSTRS_PER_TYPE: Number of texture-fetch instructions executed by the Texture cache, including killed fetches. Thread-type dependent. Determinstic. Should be select value 236. 00SQ_PERF_SEL_TA_VTX_INSTRS_PER_TYPE: Number of vertex-fetch instructions executed by the Texture cache, including killed fetches. Thread-type dependent. Determinstic. Should be select value 237. hxSQ_PERF_SEL_VC_INSTRS_PER_TYPE: Number of instructions executed by the Vertex cache, including killed fetches. Thread-type dependent. Determinstic. Should be select value 238. SQ_PERF_SEL_TV_LOCK_WAIT: Number of cycles the TF input FIFO had clauses, none were locked. Thread-type independent, non-deterministic. Should be select value 239. SQ_PERF_SEL_TA_SRC_C: Number of times an TA fetch (16 pix or verts) was executed as a src-c export. Non-deterministic. Should be select value 240. ȍSQ_PERF_SEL_VC_SRC_C: Number of times a VC fetch (16 pix or verts) was executed as a src-c export. Non-deterministic. Should be select value 241. SQ_PERF_SEL_TV_KILLED_FETCH_PER_TYPE: Number of fetch instructions killed (vertex semantic failed or gpr out of range). Deterministic. Should be select value 242. (8SQ_PERF_SEL_TV_NULL_FETCH_PER_TYPE: Number of null fetchs issued (null = issue empty fetch at end of clause due to killed fetches). Deterministic. Should be select value 243. XpSQ_PERF_SEL_TV_THREADS_IN_FIFO_PER_TYPE: Number of threads waiting in the fetch-seq's input fifo each cycle, of the selected thread type. Should be select value 244. `SQ_PERF_SEL_EXPORT_SPQ_LEVEL: Internal export per-quadpipe queue level average. Non-deterministic. Should be select value 245. ySQ_PERF_SEL_EXPORT_SPQ_STALL: Internal export per-quadpipe stall cycles. Non-deterministic. Should be select value 246. PS_ENH8Exclude pixel shader threads from performance counters 6Include pixel shader threads in performance counters ؕ  VS_ENh9Exclude vertex shader threads from performance counters (7Include vertex shader threads in performance counters @GS_EN;Exclude geometry shader threads from performance counters H9Include geometry shader threads in performance counters  `ES_EN 9Exclude export shader threads from performance counters h7Include export shader threads in performance counters 8 xMAX@BAccumulate performance events (if both TEST_MODE and LIVE are 0) XRetain maximum single-cycle performance event value (if both TEST_MODE and LIVE are 0) @x  TEST_MODE:Update performance counters based on MAX and LIVE fields ȟ7Shift in 1's rather than counting, For Debugging only ࠪLIVE(4Update performance counters based on the MAX field ࡪMRetain the current single-cycle performance event value (if TEST_MODE is 0) '8QČČ""QSQ_PERF_CTR1_SELjQ RSELRhRRSQ_PERF_SEL_NONE: don't count anything Deterministic. Should be select value 0. S@SWSQ_PERF_SEL_CYCLES: Clock cycles. Thread-type independent. Should be select value 1. T TSQ_PERF_SEL_BUSY_CYCLES: Clock cycles while SQ is reporting that it is busy. Thread-type independent. Should be select value 2. U(USQ_PERF_SEL_ANY_BUSY_PER_TYPE: Number of cycles we have a thread or an event. Thread-type dependent. Should be select value 3. pW0VSQ_PERF_SEL_EVENTS_PER_TYPE: Number of events. Thread-type dependent. Caveat: Event counts are slightly unpredictable because they don't have an associated state and because we don't count events when we don't have acitve threads. Should be select value 4. pXWuSQ_PERF_SEL_EVENTS_BUSY_PER_TYPE: Number cycles we have an event. Thread-type dependent. Should be select value 5. xYXSQ_PERF_SEL_EVENT_LEVEL_PER_TYPE: Number of events in the pipeline per clock. Thread-type dependent. Should be select value 6. ZYSQ_PERF_SEL_ITEMS_PER_TYPE: Number of valid items per thread. Thread-type dependent. Deterministic. Should be select value 7. [ZSQ_PERF_SEL_ITEMS_GT_48_PER_TYPE: Number of threads with a valid item in a position >= 48. Thread-type dependent. Deterministic. Should be select value 8. \[ SQ_PERF_SEL_ITEMS_GT_32_PER_TYPE: Number of threads with a valid item in a position >= 32. Thread-type dependent. Deterministic. Should be select value 9. ]] SQ_PERF_SEL_ITEMS_GT_16_PER_TYPE: Number of threads with a valid item in a position >= 16. Thread-type dependent. Deterministic. Should be select value 10. ^@^ nSQ_PERF_SEL_QUADS: Number of valid pixel shader quads per thread. Deterministic. Should be select value 11. _8_ wSQ_PERF_SEL_THREADS_BUSY_PER_TYPE: Number cycles we have a thread. Thread-type dependent. Should be select value 12. `8` tSQ_PERF_SEL_THREADS_PER_TYPE: Number of threads. Thread-type dependent. Deterministic Should be select value 13. a0aSQ_PERF_SEL_THREAD_LEVEL_PER_TYPE: Number of threads in the pipeline per clock. Thread-type dependent. Should be select value 14. c8bSQ_PERF_SEL_THREAD_LEVEL_WAIT_CREATE_PER_TYPE: Number of threads waiting to be created. Thread-type dependent. Should be select value 15. dHcSQ_PERF_SEL_THREAD_LEVEL_UNALLOC_PARAM_PER_TYPE: Number of threads with parameter cache unallocated. Thread-type dependent. Should be select value 16. 8ehdSQ_PERF_SEL_THREAD_LEVEL_UNALLOC_PIX_PER_TYPE: Number of threads with pixel buffer unallocated. Thread-type dependent. Should be select value 17. XfeSQ_PERF_SEL_THREAD_LEVEL_UNALLOC_POS_PER_TYPE: Number of threads with position buffer unallocated. Thread-type dependent. Should be select value 18. gfSQ_PERF_SEL_THREADS_NONPS: Number of existing non-PS threads sharing the set of enabled thread-types with other selected NONPS counters. Should be select value 19. hgSQ_PERF_SEL_THREAD_LEVEL_NONPS: Number of existing non-PS threads per cycle sharing the set of enabled thread-types with other selected NONPS counters. Should be select value 20. jiSQ_PERF_SEL_THREAD_LEVEL_WAIT_ALLOC_NONPS: Number of non-PS threads waiting for export space to be allocated. Must share the set of enabled thread-types with other selected NONPS counters. Should be select value 21. khjSQ_PERF_SEL_THREAD_LEVEL_WAIT_OTHER_NONPS: Number of non-PS threads waiting for instructions to be fetched or completed. Must share the set of enabled thread-types with other selected SHARED_TYPESET counters. Should be select value 22. lkSQ_PERF_SEL_THREAD_LEVEL_WAIT_ALLOC_PS: Number of PS threads waiting for pixel buffer to be allocated. Should be select value 23. mlSQ_PERF_SEL_THREAD_LEVEL_WAIT_OTHER_PS: Number of PS threads waiting for for instructions to be fetched or completed. Should be select value 24. nnSQ_PERF_SEL_CF_INST_ISSUES_PER_TYPE: Number of CF instruction issues. Thread-type dependent. Deterministic. Should be select value 25. ooSQ_PERF_SEL_CF_INST_ISSUE_ONE: Number of times only a single instruction is issued on a cycle. Thread-type independent. Should be select value 26. q0pSQ_PERF_SEL_CF_INST_ISSUE_TWO: Number of times two instructions are issued in a single cycle. Thread-type independent. Should be select value 27. (rHqSQ_PERF_SEL_CF_INST_ISSUE_IDLE_PER_TYPE: Number of cycles when threads exist but no threads are ready to issue. Thread-type dependent. Should be select value 28. sprSQ_PERF_SEL_CF_INST_ISSUE_FS_PER_TYPE: Number of instructions executed in Fetch Shader Mode. Does not include initial CALL_FS instruction. Thread-type dependent. Deterministic. Should be select value 29. tsSQ_PERF_SEL_CF_INST_ISSUE_ALU_PER_TYPE: Number of CF_ALU instructions issued. Thread-type dependent. Deterministic. Should be select value 30. utSQ_PERF_SEL_CF_INST_ISSUE_TF_PER_TYPE: Number of CF_TF instructions issued. Thread-type dependent. Deterministic. Should be select value 31. vu SQ_PERF_SEL_CF_INST_ISSUE_VF_PER_TYPE: Number of CF_VF instructions issued. Thread-type dependent. Deterministic. Should be select value 32. ww!SQ_PERF_SEL_CF_INST_ISSUE_EX_PER_TYPE: Number of Export instructions issued. Thread-type dependent. Deterministic. Should be select value 33. y(x"SQ_PERF_SEL_CF_INST_ISSUE_SMX_WR_PER_TYPE: Number of SMX write instructions issued. Thread-type dependent. Deterministic. Should be select value 34. zHy#SQ_PERF_SEL_CF_INST_ISSUE_SMX_RD_PER_TYPE: Number of SMX read instructions issued. Thread-type dependent. Deterministic. Should be select value 35. 8{hz$SQ_PERF_SEL_CF_INST_ISSUE_GF_PER_TYPE: Number of geometry instructions issued. Thread-type dependent. Deterministic. Should be select value 36. h|{%SQ_PERF_SEL_CF_INST_ISSUE_OTHER_PER_TYPE: Number of non-ALU/TF/VF/EX/SMX/GF instructions issued. Thread-type dependent. Deterministic. Should be select value 37. }|&SQ_PERF_SEL_CF_INST_ISSUE_ALU_CF_PER_TYPE: Number of ALU CF tags processed. Thread-type dependent. Deterministic. Should be select value 38. ~}'SQ_PERF_SEL_CF_INST_ISSUE_BL_PER_TYPE: Number of OTHER and ALU CF tags processed. Thread-type dependent. Deterministic. Should be select value 39. ~(SQ_PERF_SEL_CF_INST_REJECT_ALU_PER_TYPE: Number of ALU instructions scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 40. )SQ_PERF_SEL_CF_INST_REJECT_TF_PER_TYPE: Number of times a Texture Fetch instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 41. X`*SQ_PERF_SEL_CF_INST_REJECT_VF_PER_TYPE: Number of times a Vertex Fetch instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 42. +SQ_PERF_SEL_CF_INST_REJECT_EX_PER_TYPE: Number of times an Export instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 43. ,SQ_PERF_SEL_CF_INST_REJECT_SMX_WR_PER_TYPE: Number of times a SMX write instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 44. (-SQ_PERF_SEL_CF_INST_REJECT_SMX_RD_PER_TYPE: Number of times a SMX read instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 45. Hh.SQ_PERF_SEL_CF_INST_REJECT_GF_PER_TYPE: Number of geometry instructions trivially rejected. Thread-type dependent. Deterministic. Should be select value 46. x/SQ_PERF_SEL_CF_INST_REJECT_OTHER_PER_TYPE: Number of non-ALU/TF/VF/EX/SMX/GF instructions rejected. Thread-type dependent. Deterministic. Should be select value 47. 0SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_PER_TYPE: Number of instructions sent to ALU. Thread-type dependent. Deterministic. Should be select value 48. ؉1SQ_PERF_SEL_CF_INST_FIFO_SEND_TF_PER_TYPE: Number of instructions sent to Texture Fetch unit. Thread-type dependent. Deterministic. Should be select value 49. 2SQ_PERF_SEL_CF_INST_FIFO_SEND_VF_PER_TYPE: Number of instructions sent to Vertex Fetch unit. Thread-type dependent. Deterministic. Should be select value 50. (3SQ_PERF_SEL_CF_INST_FIFO_SEND_EX_PER_TYPE: Number of instructions sent to Export unit. Thread-type dependent. Deterministic. Should be select value 51. 0H4SQ_PERF_SEL_CF_INST_FIFO_SEND_SMX_WR_PER_TYPE: Number of write instructions sent to SMX Export unit. Thread-type dependent. Deterministic. Should be select value 52. `x5SQ_PERF_SEL_CF_INST_FIFO_SEND_SMX_RD_PER_TYPE: Number of read instructions sent to SMX Export unit. Thread-type dependent. Deterministic. Should be select value 53. 6SQ_PERF_SEL_CF_INST_FIFO_SEND_GF_PER_TYPE: Number of geometry instructions executed. Thread-type dependent. Deterministic. Should be select value 54. Ȑ7SQ_PERF_SEL_CF_INST_FIFO_SEND_OTHER_PER_TYPE: Number of non-ALU/TF/VF/EX/SMX/GF instructions executed. Thread-type dependent. Deterministic. Should be select value 55. 8SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_NONE_PER_TYPE: Number of instructions sent to ALU with no kcache regions locked. Thread-type dependent. Deterministic. Should be select value 56. @@9SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_ONE_PER_TYPE: Number of instructions sent to ALU with one kcache regions locked. Thread-type dependent. Deterministic. Should be select value 57. :SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_TWO_PER_TYPE: Number of instructions sent to ALU with two kcache regions locked. Thread-type dependent. Deterministic. Should be select value 58. Е;SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_PER_TYPE: Number of kcache region locks in instructions sent to ALU. Thread-type dependent. Deterministic. Should be select value 59. ȗ<~SQ_PERF_SEL_CF_INST_FIFO_FULL_ALU: Number of ALU units full on a cycle. Thread-type independent. Should be select value 60. ؘ=SQ_PERF_SEL_CF_INST_FIFO_FULL_TF: Number of cycles the Texture Fetch unit was full. Thread-type independent. Should be select value 61. 虨 >SQ_PERF_SEL_CF_INST_FIFO_FULL_VF: Number of cycles the Vertex Fetch unit was full. Thread-type independent. Should be select value 62. 0?SQ_PERF_SEL_CF_INST_FIFO_FULL_EX: Number of cycles the Export unit was full. Thread-type independent. Should be select value 63. 8@SQ_PERF_SEL_CF_INST_FIFO_FULL_SMX: Number of cycles the SMX Export unit was full. Thread-type independent. Should be select value 64. HASQ_PERF_SEL_CF_INST_FIFO_FULL_GF: Number of cycles the Geometry Fifo was full. Thread-type independent. Should be select value 65. XBKSQ_PERF_SEL_CF_INST_FIFO_FULL_OTHER: Reserved. Should be select value 66. (CSQ_PERF_SEL_CF_INST_FIFO_LEVEL_ALU: Number of credits available for all ALU units. Thread-type independent. Should be select value 67. 8DSQ_PERF_SEL_CF_INST_FIFO_LEVEL_TF: Number of credits available for TF unit. Thread-type independent. Should be select value 68. @ESQ_PERF_SEL_CF_INST_FIFO_LEVEL_VF: Number of credits available for VF unit. Thread-type independent. Should be select value 69. HFSQ_PERF_SEL_CF_INST_FIFO_LEVEL_EX: Number of credits available for EX unit. Thread-type independent. Should be select value 70. PGSQ_PERF_SEL_CF_INST_FIFO_LEVEL_SMX: Number of credits available for SMX unit. Thread-type independent. Should be select value 71. XHSQ_PERF_SEL_CF_INST_FIFO_LEVEL_GF: Number of credits available for Geometry Fifo. Thread-type independent. Should be select value 72. hILSQ_PERF_SEL_CF_INST_FIFO_LEVEL_OTHER: Reserved. Should be select value 73. 8JSQ_PERF_SEL_CF_INST_FIFO_EMPTY_ALU: Number of ALU units empty on a cycle. Thread-type independent. Should be select value 74. @KSQ_PERF_SEL_CF_INST_FIFO_EMPTY_TF: Number of cycles the Texture Fetch unit was empty. Thread-type independent. Should be select value 75. PLSQ_PERF_SEL_CF_INST_FIFO_EMPTY_VF: Number of cycles the Vertex Fetch unit was empty. Thread-type independent. Should be select value 76. (`MSQ_PERF_SEL_CF_INST_FIFO_EMPTY_EX: Number of cycles the Export unit was empty. Thread-type independent. Should be select value 77. 0pNSQ_PERF_SEL_CF_INST_FIFO_EMPTY_SMX: Number of cycles the SMX unit was empty. Thread-type independent. Should be select value 78. @xOSQ_PERF_SEL_CF_INST_FIFO_EMPTY_GF: Number of cycles the Geometry fifo was empty. Thread-type independent. Should be select value 79. PLSQ_PERF_SEL_CF_INST_FIFO_EMPTY_OTHER: Reserved. Should be select value 80. 0XQSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_ALU_PER_TYPE: Number of instructions outstanding for all ALU units. Thread-type dependent. Should be select value 81. HxRSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_TF_PER_TYPE: Number of instructions outstanding for TF unit. Thread-type dependent. Should be select value 82. `SSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_VF_PER_TYPE: Number of instructions outstanding for VF unit. Thread-type ependent. Should be select value 83. xTSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_EX_PER_TYPE: Number of instructions outstanding for EX unit. Thread-type dependent. Should be select value 84. USQ_PERF_SEL_CF_INST_ISSUE_LEVEL_SMX_WR_PER_TYPE: Number of write instructions outstanding for SMX unit. Thread-type dependent. Should be select value 85. ౨VSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_SMX_RD_PER_TYPE: Number of read instructions outstanding for SMX unit. Thread-type dependent. Should be select value 86. سWSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_GF_PER_TYPE: Number of instructions outstanding for Geometry Fifo. Thread-type dependent. Should be select value 87. XSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_OTHER_PER_TYPE: Number of instructions outstanding for non-ALU/TF/VF/EX/SMX/GF. Thread-type dependent. Should be select value 88. HYSQ_PERF_SEL_CF_INST_CHECKPOINT: Number of times user specified CF address is executed. Deterministic. Should be select value 89. 0PZSQ_PERF_SEL_CF_INST_CHECKPOINT_BEFORE: Number of CF instructions executed including and after the specified CF address. Deterministic. Should be select value 90. Px[SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_VALID: Number of items valid for execution of instruction at CF address. Deterministic. Should be select value 91. \SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_VALID_NONE: Number of times no items are valid for execution of instruction at CF address. Deterministic. Should be select value 92. ຨȹ]SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_ACTIVE: Number of items active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 93. X(^SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_ACTIVE_NONE: Number of times no items are active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 94. _SQ_PERF_SEL_CF_INST_CHECKPOINT_QUADS_ACTIVE: Number of pixel quads active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 95. (`SQ_PERF_SEL_CF_INST_CHECKPOINT_QUADS_VALID: Number of pixel quads valid for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 96. 8paSQ_PERF_SEL_CF_INST_CHECKPOINT_THREADS: Number of times a thread first reaches the CF address. Deterministic. Should be select value 97. HbSQ_PERF_SEL_CF_INST_CHECKPOINT_THREAD_LEVEL: Number of threads that have reached the CF address per cycle. Should be select value 98. P¨cSQ_PERF_SEL_CF_INST_FETCH_PER_TYPE: Number of CF fetch requests from cache. Thread-type dependent. Should be select value 99. hè¨dSQ_PERF_SEL_CF_INST_FETCH_RETURNS_PER_TYPE: Number of CF fetch return cycles from cache. Thread-type dependent. Should be select value 100. ĨèeSQ_PERF_SEL_CF_INST_FETCH_INSTS_PER_TYPE: Number of CF instructions requested from cache. Thread-type dependent. Should be select value 101. ŨĨfSQ_PERF_SEL_CF_INST_FETCH_LEVEL_PER_TYPE: Number of CF fetch requests from cache pending per cycle. Thread-type dependent. Should be select value 102. ǨŨgSQ_PERF_SEL_CF_INST_FETCH_EXTRA_PER_TYPE: Number of times we didn't issue the second instruction in a pair. Does not include instructions after PROGRAM_END. Thread-type dependent. Deterministic. Should be select value 103. ȨPǨhSQ_PERF_SEL_CF_INST_FETCH_FIFO_SEND: Number of requests passing through the fetch fifo. Thread-type independent. Should be select value 104. (ɨhȨiSQ_PERF_SEL_CF_INST_FETCH_FIFO_LEVEL: Control Flow Fetch fifo entry level. Thread-type independent. Should be select value 105. HʨpɨjSQ_PERF_SEL_CF_INST_FETCH_FIFO_STALL: Number of cycles when the CF fetch fifo is stalling issues. Thread-type independent. Should be select value 106. `˨ʨkSQ_PERF_SEL_CF_INST_CACHE_FIFO_SEND: Number of requests passing through the cache fifo. Thread-type independent. Should be select value 107. `̨˨lySQ_PERF_SEL_CF_INST_CACHE_FIFO_LEVEL: Number of credits in cache. Thread-type independent. Should be select value 108. p̨ͨmSQ_PERF_SEL_CF_INST_CACHE_FIFO_FULL: Number of cycles when we have no cache credits. Thread-type independent. Should be select value 109. ΨͨnSQ_PERF_SEL_CF_INST_ISSUE_DONES: Number of issues that need to be accounted for to avoid overflowing the done fifo. Thread-type independent. Should be select value 110. ϨΨoSQ_PERF_SEL_CF_INST_ISSUE_DONE_LEVEL: Number of issues pending at any given time that need to be accounted for to avoid overflowing the done fifo. Thread-type independent. Should be select value 111. Ѩ8ШpSQ_PERF_SEL_CF_INST_ISSUE_DONE_STALL: Stalls triggered to avoid overflowing the done fifo. Thread-type independent. Should be select value 112. ҨPѨqSQ_PERF_SEL_CF_INST_ISSUE_DONE_FIFO_SEND: Number of items passing through the done fifo. Thread-type independent. Should be select value 113. 0ӨhҨrSQ_PERF_SEL_CF_INST_ISSUE_DONE_FIFO_LEVEL: Control Flow Done fifo entry level. Thread-type independent. Should be select value 114. @ԨxӨsSQ_PERF_SEL_CF_INST_ALU_UPDATE_FIFO_SEND: Macro sequencer alu update fifo send. Thread-type independent. Should be select value 115. PըԨtSQ_PERF_SEL_CF_INST_ALU_UPDATE_FIFO_LEVEL: Macro sequencer alu update fifo level. Thread-type independent. Should be select value 116. ֨ըuSQ_PERF_SEL_CF_INST_ALU_UPDATE_FIFO_STALL: Number of cycles when the MS alu update fifo is stalling issues and alu returns. Thread-type independent. Should be select value 117. ר֨vSQ_PERF_SEL_OFIFO_LEVEL_PER_TYPE: Number of threads and events in the ofifo. Thread-type dependent. Should be select value 118. بרwSQ_PERF_SEL_SX_EVENT_FIFO_FULL_PER_TYPE: Number of cycles the SX event fifo is full. Thread-type dependent. Should be select value 119. ٨بxSQ_PERF_SEL_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE: Number of ALU instruction groups executed. Thread-type dependent. Deterministic. Should be select value 120. ڨڨySQ_PERF_SEL_ALU_CLAUSE_INSTRS_PER_TYPE: Number of ALU individual alu instructions executed. Thread-type dependent. Deterministic. Should be select value 121. ܨ8ۨzSQ_PERF_SEL_ALU_KWATERFALL_PER_TYPE: Number of ALU instruction groups which use const-waterfall. Thread-type dependent. Deterministic. Should be select value 122. Pݨhܨ{SQ_PERF_SEL_ALU_GPRWATERFALL_PER_TYPE: Number of ALU instruction groups which use gpr-waterfall. Thread-type dependent. Deterministic. Should be select value 123. ިݨ|SQ_PERF_SEL_ALU_K_INSTR_PER_TYPE: Number of ALU instructions which use one or more constant (literal, kcache, or kfile). Thread-type dependent. Deterministic. Should be select value 124. ߨި}SQ_PERF_SEL_ALU_ICACHE_BUSY_PER_TYPE: Number of times ALU Icache read was denied - cache busy. Thread-type dependent. Should be select value 125. ߨ~SQ_PERF_SEL_ALU_KCACHE_BUSY_PER_TYPE: Number of times ALU Kcache/Kfile read was denied - cache busy. Thread-type dependent. Should be select value 126. SQ_PERF_SEL_ALU_MOVA_IDLE_WAIT_PER_TYPE: Number of instruction cycles idle waiting for MOVA to complete. Thread-type dependent. Should be select value 127. 8@SQ_PERF_SEL_ALU_LOCK_WAIT: Number of times (1 every 4 clocks) ALU has clauses in input fifo but no clauses locked -- ALU is idle. Thread-type independent. Should be select value 128. XSQ_PERF_SEL_ALU_ICACHE_READS_PER_TYPE: Number of read requests to the ALU I-cache. Thread-type dependent. Deterministic. Should be select value 129. SQ_PERF_SEL_ALU_KCACHE_READS_PER_TYPE: Number of read requests to the ALU K-cache/K-file. Thread-type dependent. Deterministic. Should be select value 130. SQ_PERF_SEL_ALU_DONE_FIFO_FULL: Number of times the done-fifo is full and that caused a stall. Thread-type independent. Should be select value 131. SQ_PERF_SEL_ALU_MOVA_WAIT_PER_TYPE: Number of times more than one SIMD tried to execute MOVA, and one was denied access. Thread-type dependent. Should be select value 132.  SQ_PERF_SEL_ALU_THREADS_IN_FIFO_PER_TYPE: Number of threads waiting in the alu-seq's input fifo each cycle, of the selected thread type. Should be select value 133. PSQ_PERF_SEL_UNUSED_006HSQ_PERF_SEL_UNUSED_007hSQ_PERF_SEL_TV_ICACHE_WAIT_PER_TYPE: Number of cycles the Tex/Vtx Icache denied a read request (busy). Thread-type dependent. Should be select value 136. SQ_PERF_SEL_UNUSED_010PSQ_PERF_SEL_UNUSED_001HSQ_PERF_SEL_UNUSED_002xSQ_PERF_SEL_TF_TA_STALL_PER_TYPE: Number of times the TF had data to send to TA, but the TA input fifo was full. Thread-type dependent. Should be select value 140. SQ_PERF_SEL_VF_VC_INSTR_STALL_PER_TYPE: Number of times the VF had data to send to VC, but the VC instruction input fifo was full. Thread-type dependent. Should be select value 141. SQ_PERF_SEL_VF_VC_INDEX_STALL_PER_TYPE: Number of times the VF had data to send to VC, but the VC index input fifo was full. Thread-type dependent. Should be select value 142. @SQ_PERF_SEL_UNUSED_0038SQ_PERF_SEL_UNUSED_008SQ_PERF_SEL_UNUSED_004x SQ_PERF_SEL_UNUSED_009xwSQ_PERF_SEL_EXPORT_INSTR_PER_TYPE: Number of exports (seen by export-seq). Determinstic. Should be select value 147. x{SQ_PERF_SEL_EXPORT_IDLE: Number of clocks where export unit is idle. Thread-type independent. Should be select value 148. SQ_PERF_SEL_EXPORT_SMX_AL_STALL: Number of clocks SMX export stalled waiting for alloc. Thread-type independent. Should be select value 149. SQ_PERF_SEL_EXPORT_PC_AL_STALL: Number of clocks Param.cache alloc was stalled. Thread-type independent. Should be select value 150. SQ_PERF_SEL_EXPORT_POS_AL_STALL: Number of clocks Position export alloc was stalled. Thread-type independent. Should be select value 151. SQ_PERF_SEL_EXPORT_PIX_AL_STALL: Number of clocks Pixel export alloc was stalled. Thread-type independent. Should be select value 152. SQ_PERF_SEL_EXPORT_POS_CYCLE: Number of position export cycles (4 clocks), * burst count). Thread-type independent. Determinstic. Should be select value 153. 0SQ_PERF_SEL_EXPORT_PIX_CYCLE: Number of pixel export cycles (4 clocks), * burst count). Thread-type independent. Determinstic. Should be select value 154. 8XSQ_PERF_SEL_EXPORT_PC_CYCLE: Number of param.cache export cycles (4 clocks), * burst count). Thread-type independent. Determinstic. Should be select value 155. `SQ_PERF_SEL_EXPORT_SMX_CYCLE_PER_TYPE: Number of smx export cycles (4 clocks), * burst count). Thread-type dependent. Determinstic. Should be select value 156. SQ_PERF_SEL_CACHE_INVAL_ANY: Number of cache invalidation (surface synchronization) operations of any kind. Thread-type independent. Should be select value 157. SQ_PERF_SEL_CACHE_INVAL_ALL: Number of cache invalidation (surface synchronization) operations that invalidate the whole cache (due to a large invalidation region). Thread-type independent. Should be select value 158. p0SQ_PERF_SEL_CACHE_INVAL_CYCLES: Number of cache invalidation (surface synchronization) cycles, not including full invalidations; indicates the size of the invalidation regions in 4K byte increments. Thread-type independent. Should be select value 159. SQ_PERF_SEL_CF_ICACHE_HITS: Number of CF instruction cache hits (it was found in the cache). Thread-type independent. Should be select value 160. SQ_PERF_SEL_TF_ICACHE_HITS: Number of TV instruction cache hits (it was found in the cache). Thread-type independent. Should be select value 161. xQSQ_PERF_SEL_VF_ICACHE_HITS: DEPRECATED. Do not use. Should be select value 162. SQ_PERF_SEL_ALU_ICACHE_HITS: Number of ALU instruction cache hits (it was found in the cache). Thread-type independent. Should be select value 163. SQ_PERF_SEL_ALU_KCACHE_HITS: Number of ALU constant cache hits (it was found in the cache). Thread-type independent. Should be select value 164. SQ_PERF_SEL_CF_ICACHE_MISSES: Number of CF instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 165. @ @ SQ_PERF_SEL_TF_ICACHE_MISSES: Number of TV instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 166.  SSQ_PERF_SEL_VF_ICACHE_MISSES: DEPRECATED. Do not use. Should be select value 167. ` ` SQ_PERF_SEL_ALU_ICACHE_MISSES: Number of ALU instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 168. SQ_PERF_SEL_ALU_KCACHE_MISSES: Number of ALU constant cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 169.  SQ_PERF_SEL_CF_ICACHE_DUP_MISSES: Number of CF instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 170. `HSQ_PERF_SEL_TF_ICACHE_DUP_MISSES: Number of TV instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 171. @WSQ_PERF_SEL_VF_ICACHE_DUP_MISSES: DEPRECATED. Do not use. Should be select value 172. SQ_PERF_SEL_ALU_ICACHE_DUP_MISSES: Number of ALU instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 173. SQ_PERF_SEL_ALU_KCACHE_DUP_MISSES: Number of ALU constant cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 174. pHSQ_PERF_SEL_CF_ICACHE_ACCESSES: Number of CF instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 175. SQ_PERF_SEL_TF_ICACHE_ACCESSES: Number of TV instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 176. (USQ_PERF_SEL_VF_ICACHE_ACCESSES: DEPRECATED. Do not use. Should be select value 177. 0SQ_PERF_SEL_ALU_ICACHE_ACCESSES: Number of ALU instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 178. xSQ_PERF_SEL_ALU_KCACHE_ACCESSES: Number of ALU constant cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 179. SQ_PERF_SEL_CF_ICACHE_INPUT_FIFO_ENTRIES: Count of CF instruction cache requests stored in the input FIFO. Thread-type independent. Should be select value 180. SQ_PERF_SEL_TF_ICACHE_INPUT_FIFO_ENTRIES: Count of TV instruction cache requests stored in the input FIFO. Thread-type independent. Should be select value 181. 8_SQ_PERF_SEL_VF_ICACHE_INPUT_FIFO_ENTRIES: DEPRECATED. Do not use. Should be select value 182.  SQ_PERF_SEL_ALU_ICACHE_INPUT_FIFO_ENTRIES: Count of ALU instruction cache requests stored in the input FIFO. Thread-type independent. Should be select value 183. ( HSQ_PERF_SEL_ALU_KCACHE_INPUT_FIFO_ENTRIES: Count of ALU constant cache requests stored in the input FIFO. Thread-type independent. Should be select value 184. !p SQ_PERF_SEL_CF_ICACHE_MISS_MEM_STALL: Number of CF instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 185. "!SQ_PERF_SEL_TF_ICACHE_MISS_MEM_STALL: Number of TV instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 186. #0#[SQ_PERF_SEL_VF_ICACHE_MISS_MEM_STALL: DEPRECATED. Do not use. Should be select value 187. 0%$SQ_PERF_SEL_ALU_ICACHE_MISS_MEM_STALL: Number of ALU instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 188. &x%SQ_PERF_SEL_ALU_KCACHE_MISS_MEM_STALL: Number of ALU constant cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 189. (&SQ_PERF_SEL_CF_ICACHE_MISS_FIFO_STALL: Number of CF instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 190. )P(SQ_PERF_SEL_TF_ICACHE_MISS_FIFO_STALL: Number of TV instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 191. `*)\SQ_PERF_SEL_VF_ICACHE_MISS_FIFO_STALL: DEPRECATED. Do not use. Should be select value 192. +*SQ_PERF_SEL_ALU_ICACHE_MISS_FIFO_STALL: Number of ALU instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 193. P- ,SQ_PERF_SEL_ALU_KCACHE_MISS_FIFO_STALL: Number of ALU constant cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 194. .-SQ_PERF_SEL_CF_ICACHE_HIT_STALL: Number of CF instruction cache cycles that are a cache hit but are stalled due to processing previous misses. Thread-type independent. Should be select value 195. 0.SQ_PERF_SEL_CF_ICACHE_MISS_LOCKED_STALL: Number of CF instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 196. p1P0SQ_PERF_SEL_TF_ICACHE_MISS_LOCKED_STALL: Number of TV instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 197. X21^SQ_PERF_SEL_VF_ICACHE_MISS_LOCKED_STALL: DEPRECATED. Do not use. Should be select value 198. 32SQ_PERF_SEL_ALU_ICACHE_MISS_LOCKED_STALL: Number of ALU instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 199. (54SQ_PERF_SEL_ALU_KCACHE_MISS_LOCKED_STALL: Number of ALU constant cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 200. 6p5SQ_PERF_SEL_CF_ICACHE_LOCKED_TAGS: Count of CF instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 201. 76SQ_PERF_SEL_TF_ICACHE_LOCKED_TAGS: Count of TV instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 202. 8 8XSQ_PERF_SEL_VF_ICACHE_LOCKED_TAGS: DEPRECATED. Do not use. Should be select value 203. :9SQ_PERF_SEL_ALU_ICACHE_LOCKED_TAGS: Count of ALU instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 204. h;X:SQ_PERF_SEL_ALU_KCACHE_LOCKED_TAGS: Count of ALU constant cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 205. <;SQ_PERF_SEL_CF_ICACHE_MISS_LOCKED_TAGS: Count of CF instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 206. =<SQ_PERF_SEL_TF_ICACHE_MISS_LOCKED_TAGS: Count of TV instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 207. >0>]SQ_PERF_SEL_VF_ICACHE_MISS_LOCKED_TAGS: DEPRECATED. Do not use. Should be select value 208. @?SQ_PERF_SEL_ALU_ICACHE_MISS_LOCKED_TAGS: Count of ALU instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 209. PAX@SQ_PERF_SEL_ALU_KCACHE_MISS_LOCKED_TAGS: Count of ALU constant cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 210. hBASQ_PERF_SEL_CACHE_MEM_REQUESTS: Number of cache to memory controller requests of any type. Thread-type independent. Should be select value 211. CBSQ_PERF_SEL_CF_ICACHE_MEM_REQUESTS: Number of CF instruction cache to memory controller requests. Thread-type independent. Should be select value 212. DCSQ_PERF_SEL_TV_ICACHE_MEM_REQUESTS: Number of TV instruction cache to memory controller requests. Thread-type independent. Should be select value 213. EDSQ_PERF_SEL_ALU_ICACHE_MEM_REQUESTS: Number of ALU instruction cache to memory controller requests. Thread-type independent. Should be select value 214. FFSQ_PERF_SEL_ALU_KCACHE_MEM_REQUESTS: Number of ALU constant cache to memory controller requests. Thread-type independent. Should be select value 215. (H0GSQ_PERF_SEL_CF_ICACHE_RD_WR_COLLISION: Number of times a read to the CF icache memory was blocked by a write from a memory return. Thread-type independent. Should be select value 216. `IpHSQ_PERF_SEL_CF_ICACHE_MISS_HIT_RD_COLLISION: Number of times processing a hit is stalled by processing a now-resident miss. Thread-type independent. Should be select value 217. JISQ_PERF_SEL_CF_ICACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding CF instruction cache to memory controller requests of any type. Thread-type independent. Should be select value 218. LJSQ_PERF_SEL_TV_ICACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding TV instruction cache to memory controller requests of any type. Thread-type independent. Should be select value 219. PMHLSQ_PERF_SEL_ALU_ICACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding ALU instruction cache to memory controller requests of any type. Thread-type independent. Should be select value 220. NMSQ_PERF_SEL_ALU_KCACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding ALU constant cache to memory controller requests of any type. Thread-type independent. Should be select value 221. ONSQ_PERF_SEL_CF_ICACHE_MISS_FIFO_MISSES: Count of the number of CF instruction cache misses waiting in the miss FIFO. Thread-type independent. Should be select value 222. QPSQ_PERF_SEL_TF_ICACHE_MISS_FIFO_MISSES: Count of the number of TV instruction cache misses waiting in the miss FIFO. Thread-type independent. Should be select value 223. QHQ]SQ_PERF_SEL_VF_ICACHE_MISS_FIFO_MISSES: DEPRECATED. Do not use. Should be select value 224. (S0RSQ_PERF_SEL_ALU_ICACHE_MISS_FIFO_MISSES: Count of the number of ALU instruction cache misses waiting in the miss FIFO. Divided by 2. Thread-type independent. Should be select value 225. hTpSSQ_PERF_SEL_ALU_KCACHE_MISS_FIFO_MISSES: Count of the number of ALU constant cache misses waiting in the miss FIFO. Divided by 2. Thread-type independent. Should be select value 226. UTSQ_PERF_SEL_CACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding cache to memory controller requests of any type. Divided by 2. Thread-type independent. Should be select value 227. VUSQ_PERF_SEL_CACHE_MEM_STALL: Number of cache to memory controller cycles that are stalled. Thread-type independent. Should be select value 228. WWqSQ_PERF_SEL_TM_TS64_STALL: Clock cycles GRBM stalled due to Timestamp-64 FIFO full. Should be select value 229. XXSQ_PERF_SEL_TM_ALU_CONST_STALL: Clock cycles GRBM stalled due to ALU constant overflow buffer full. Should be select value 230. YYSQ_PERF_SEL_TM_LOOP_CONST_STALL: Clock cycles GRBM stalled due to Loop constant overflow buffer full. Should be select value 231. ZZSQ_PERF_SEL_TM_TEX_BASE_CONST_STALL: Clock cycles GRBM stalled due to VertexBase/InstantStart constant overflow buffer full. Should be select value 232. \8[SQ_PERF_SEL_TM_TEX_SAMPLER_STALL: Clock cycles GRBM stalled due to Texture Sampler constant overflow buffer full. Should be select value 233. ]P\SQ_PERF_SEL_TM_TEX_RESOURCE_STALL: Clock cycles GRBM stalled due to Texture Resource constant overflow buffer full. Should be select value 234. ]h]SQ_PERF_SEL_UNUSED_005_^SQ_PERF_SEL_TA_TEX_INSTRS_PER_TYPE: Number of texture-fetch instructions executed by the Texture cache, including killed fetches. Thread-type dependent. Determinstic. Should be select value 236. X`X_SQ_PERF_SEL_TA_VTX_INSTRS_PER_TYPE: Number of vertex-fetch instructions executed by the Texture cache, including killed fetches. Thread-type dependent. Determinstic. Should be select value 237. a`SQ_PERF_SEL_VC_INSTRS_PER_TYPE: Number of instructions executed by the Vertex cache, including killed fetches. Thread-type dependent. Determinstic. Should be select value 238. baSQ_PERF_SEL_TV_LOCK_WAIT: Number of cycles the TF input FIFO had clauses, none were locked. Thread-type independent, non-deterministic. Should be select value 239. ccSQ_PERF_SEL_TA_SRC_C: Number of times an TA fetch (16 pix or verts) was executed as a src-c export. Non-deterministic. Should be select value 240. d dSQ_PERF_SEL_VC_SRC_C: Number of times a VC fetch (16 pix or verts) was executed as a src-c export. Non-deterministic. Should be select value 241. f8eSQ_PERF_SEL_TV_KILLED_FETCH_PER_TYPE: Number of fetch instructions killed (vertex semantic failed or gpr out of range). Deterministic. Should be select value 242. Pg`fSQ_PERF_SEL_TV_NULL_FETCH_PER_TYPE: Number of null fetchs issued (null = issue empty fetch at end of clause due to killed fetches). Deterministic. Should be select value 243. hgSQ_PERF_SEL_TV_THREADS_IN_FIFO_PER_TYPE: Number of threads waiting in the fetch-seq's input fifo each cycle, of the selected thread type. Should be select value 244. ihSQ_PERF_SEL_EXPORT_SPQ_LEVEL: Internal export per-quadpipe queue level average. Non-deterministic. Should be select value 245. iySQ_PERF_SEL_EXPORT_SPQ_STALL: Internal export per-quadpipe stall cycles. Non-deterministic. Should be select value 246. lj(kPS_ENkpk8Exclude pixel shader threads from performance counters 0l6Include pixel shader threads in performance counters nm HmVS_ENnm9Exclude vertex shader threads from performance counters Pn7Include vertex shader threads in performance counters p o hoGS_EN(po;Exclude geometry shader threads from performance counters pp9Include geometry shader threads in performance counters s@q qES_ENHrq9Exclude export shader threads from performance counters r7Include export shader threads in performance counters Hu`s sMAXhtsBAccumulate performance events (if both TEST_MODE and LIVE are 0) tXRetain maximum single-cycle performance event value (if both TEST_MODE and LIVE are 0) hwu u TEST_MODEv0v:Update performance counters based on MAX and LIVE fields v7Shift in 1's rather than counting, For Debugging only wxLIVExPx4Update performance counters based on the MAX field yMRetain the current single-cycle performance event value (if TEST_MODE is 0) &h(""(SQ_PERF_CTR0_SELA)P)SEL(*)RSQ_PERF_SEL_NONE: don't count anything Deterministic. Should be select value 0. +p*WSQ_PERF_SEL_CYCLES: Clock cycles. Thread-type independent. Should be select value 1. ,P+SQ_PERF_SEL_BUSY_CYCLES: Clock cycles while SQ is reporting that it is busy. Thread-type independent. Should be select value 2. -X,SQ_PERF_SEL_ANY_BUSY_PER_TYPE: Number of cycles we have a thread or an event. Thread-type dependent. Should be select value 3. .`-SQ_PERF_SEL_EVENTS_PER_TYPE: Number of events. Thread-type dependent. Caveat: Event counts are slightly unpredictable because they don't have an associated state and because we don't count events when we don't have acitve threads. Should be select value 4. /.uSQ_PERF_SEL_EVENTS_BUSY_PER_TYPE: Number cycles we have an event. Thread-type dependent. Should be select value 5. 0/SQ_PERF_SEL_EVENT_LEVEL_PER_TYPE: Number of events in the pipeline per clock. Thread-type dependent. Should be select value 6. 10SQ_PERF_SEL_ITEMS_PER_TYPE: Number of valid items per thread. Thread-type dependent. Deterministic. Should be select value 7. 21SQ_PERF_SEL_ITEMS_GT_48_PER_TYPE: Number of threads with a valid item in a position >= 48. Thread-type dependent. Deterministic. Should be select value 8. 4 3 SQ_PERF_SEL_ITEMS_GT_32_PER_TYPE: Number of threads with a valid item in a position >= 32. Thread-type dependent. Deterministic. Should be select value 9. (5H4 SQ_PERF_SEL_ITEMS_GT_16_PER_TYPE: Number of threads with a valid item in a position >= 16. Thread-type dependent. Deterministic. Should be select value 10. 6p5 nSQ_PERF_SEL_QUADS: Number of valid pixel shader quads per thread. Deterministic. Should be select value 11. 7h6 wSQ_PERF_SEL_THREADS_BUSY_PER_TYPE: Number cycles we have a thread. Thread-type dependent. Should be select value 12. 8h7 tSQ_PERF_SEL_THREADS_PER_TYPE: Number of threads. Thread-type dependent. Deterministic Should be select value 13. 9`8SQ_PERF_SEL_THREAD_LEVEL_PER_TYPE: Number of threads in the pipeline per clock. Thread-type dependent. Should be select value 14. 0:h9SQ_PERF_SEL_THREAD_LEVEL_WAIT_CREATE_PER_TYPE: Number of threads waiting to be created. Thread-type dependent. Should be select value 15. P;x:SQ_PERF_SEL_THREAD_LEVEL_UNALLOC_PARAM_PER_TYPE: Number of threads with parameter cache unallocated. Thread-type dependent. Should be select value 16. h<;SQ_PERF_SEL_THREAD_LEVEL_UNALLOC_PIX_PER_TYPE: Number of threads with pixel buffer unallocated. Thread-type dependent. Should be select value 17. =<SQ_PERF_SEL_THREAD_LEVEL_UNALLOC_POS_PER_TYPE: Number of threads with position buffer unallocated. Thread-type dependent. Should be select value 18. >=SQ_PERF_SEL_THREADS_NONPS: Number of existing non-PS threads sharing the set of enabled thread-types with other selected NONPS counters. Should be select value 19. ??SQ_PERF_SEL_THREAD_LEVEL_NONPS: Number of existing non-PS threads per cycle sharing the set of enabled thread-types with other selected NONPS counters. Should be select value 20. PA8@SQ_PERF_SEL_THREAD_LEVEL_WAIT_ALLOC_NONPS: Number of non-PS threads waiting for export space to be allocated. Must share the set of enabled thread-types with other selected NONPS counters. Should be select value 21. BASQ_PERF_SEL_THREAD_LEVEL_WAIT_OTHER_NONPS: Number of non-PS threads waiting for instructions to be fetched or completed. Must share the set of enabled thread-types with other selected SHARED_TYPESET counters. Should be select value 22. CCSQ_PERF_SEL_THREAD_LEVEL_WAIT_ALLOC_PS: Number of PS threads waiting for pixel buffer to be allocated. Should be select value 23. DDSQ_PERF_SEL_THREAD_LEVEL_WAIT_OTHER_PS: Number of PS threads waiting for for instructions to be fetched or completed. Should be select value 24. E0ESQ_PERF_SEL_CF_INST_ISSUES_PER_TYPE: Number of CF instruction issues. Thread-type dependent. Deterministic. Should be select value 25. G@FSQ_PERF_SEL_CF_INST_ISSUE_ONE: Number of times only a single instruction is issued on a cycle. Thread-type independent. Should be select value 26. 0H`GSQ_PERF_SEL_CF_INST_ISSUE_TWO: Number of times two instructions are issued in a single cycle. Thread-type independent. Should be select value 27. XIxHSQ_PERF_SEL_CF_INST_ISSUE_IDLE_PER_TYPE: Number of cycles when threads exist but no threads are ready to issue. Thread-type dependent. Should be select value 28. JISQ_PERF_SEL_CF_INST_ISSUE_FS_PER_TYPE: Number of instructions executed in Fetch Shader Mode. Does not include initial CALL_FS instruction. Thread-type dependent. Deterministic. Should be select value 29. KJSQ_PERF_SEL_CF_INST_ISSUE_ALU_PER_TYPE: Number of CF_ALU instructions issued. Thread-type dependent. Deterministic. Should be select value 30. LLSQ_PERF_SEL_CF_INST_ISSUE_TF_PER_TYPE: Number of CF_TF instructions issued. Thread-type dependent. Deterministic. Should be select value 31. M(M SQ_PERF_SEL_CF_INST_ISSUE_VF_PER_TYPE: Number of CF_VF instructions issued. Thread-type dependent. Deterministic. Should be select value 32. O@N!SQ_PERF_SEL_CF_INST_ISSUE_EX_PER_TYPE: Number of Export instructions issued. Thread-type dependent. Deterministic. Should be select value 33. 0PXO"SQ_PERF_SEL_CF_INST_ISSUE_SMX_WR_PER_TYPE: Number of SMX write instructions issued. Thread-type dependent. Deterministic. Should be select value 34. PQxP#SQ_PERF_SEL_CF_INST_ISSUE_SMX_RD_PER_TYPE: Number of SMX read instructions issued. Thread-type dependent. Deterministic. Should be select value 35. hRQ$SQ_PERF_SEL_CF_INST_ISSUE_GF_PER_TYPE: Number of geometry instructions issued. Thread-type dependent. Deterministic. Should be select value 36. SR%SQ_PERF_SEL_CF_INST_ISSUE_OTHER_PER_TYPE: Number of non-ALU/TF/VF/EX/SMX/GF instructions issued. Thread-type dependent. Deterministic. Should be select value 37. TS&SQ_PERF_SEL_CF_INST_ISSUE_ALU_CF_PER_TYPE: Number of ALU CF tags processed. Thread-type dependent. Deterministic. Should be select value 38. UT'SQ_PERF_SEL_CF_INST_ISSUE_BL_PER_TYPE: Number of OTHER and ALU CF tags processed. Thread-type dependent. Deterministic. Should be select value 39. WV(SQ_PERF_SEL_CF_INST_REJECT_ALU_PER_TYPE: Number of ALU instructions scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 40. HXHW)SQ_PERF_SEL_CF_INST_REJECT_TF_PER_TYPE: Number of times a Texture Fetch instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 41. YX*SQ_PERF_SEL_CF_INST_REJECT_VF_PER_TYPE: Number of times a Vertex Fetch instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 42. ZY+SQ_PERF_SEL_CF_INST_REJECT_EX_PER_TYPE: Number of times an Export instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 43. \[,SQ_PERF_SEL_CF_INST_REJECT_SMX_WR_PER_TYPE: Number of times a SMX write instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 44. P]X\-SQ_PERF_SEL_CF_INST_REJECT_SMX_RD_PER_TYPE: Number of times a SMX read instruction is scheduled and trivially rejected. Thread-type dependent. Deterministic. Should be select value 45. x^].SQ_PERF_SEL_CF_INST_REJECT_GF_PER_TYPE: Number of geometry instructions trivially rejected. Thread-type dependent. Deterministic. Should be select value 46. _^/SQ_PERF_SEL_CF_INST_REJECT_OTHER_PER_TYPE: Number of non-ALU/TF/VF/EX/SMX/GF instructions rejected. Thread-type dependent. Deterministic. Should be select value 47. `_0SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_PER_TYPE: Number of instructions sent to ALU. Thread-type dependent. Deterministic. Should be select value 48. aa1SQ_PERF_SEL_CF_INST_FIFO_SEND_TF_PER_TYPE: Number of instructions sent to Texture Fetch unit. Thread-type dependent. Deterministic. Should be select value 49. c0b2SQ_PERF_SEL_CF_INST_FIFO_SEND_VF_PER_TYPE: Number of instructions sent to Vertex Fetch unit. Thread-type dependent. Deterministic. Should be select value 50. 0dXc3SQ_PERF_SEL_CF_INST_FIFO_SEND_EX_PER_TYPE: Number of instructions sent to Export unit. Thread-type dependent. Deterministic. Should be select value 51. `exd4SQ_PERF_SEL_CF_INST_FIFO_SEND_SMX_WR_PER_TYPE: Number of write instructions sent to SMX Export unit. Thread-type dependent. Deterministic. Should be select value 52. fe5SQ_PERF_SEL_CF_INST_FIFO_SEND_SMX_RD_PER_TYPE: Number of read instructions sent to SMX Export unit. Thread-type dependent. Deterministic. Should be select value 53. gf6SQ_PERF_SEL_CF_INST_FIFO_SEND_GF_PER_TYPE: Number of geometry instructions executed. Thread-type dependent. Deterministic. Should be select value 54. hg7SQ_PERF_SEL_CF_INST_FIFO_SEND_OTHER_PER_TYPE: Number of non-ALU/TF/VF/EX/SMX/GF instructions executed. Thread-type dependent. Deterministic. Should be select value 55. (j(i8SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_NONE_PER_TYPE: Number of instructions sent to ALU with no kcache regions locked. Thread-type dependent. Deterministic. Should be select value 56. pkpj9SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_ONE_PER_TYPE: Number of instructions sent to ALU with one kcache regions locked. Thread-type dependent. Deterministic. Should be select value 57. lk:SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_TWO_PER_TYPE: Number of instructions sent to ALU with two kcache regions locked. Thread-type dependent. Deterministic. Should be select value 58. mm;SQ_PERF_SEL_CF_INST_FIFO_SEND_ALU_KCACHE_PER_TYPE: Number of kcache region locks in instructions sent to ALU. Thread-type dependent. Deterministic. Should be select value 59. n8n<~SQ_PERF_SEL_CF_INST_FIFO_FULL_ALU: Number of ALU units full on a cycle. Thread-type independent. Should be select value 60. p@o=SQ_PERF_SEL_CF_INST_FIFO_FULL_TF: Number of cycles the Texture Fetch unit was full. Thread-type independent. Should be select value 61. qPp>SQ_PERF_SEL_CF_INST_FIFO_FULL_VF: Number of cycles the Vertex Fetch unit was full. Thread-type independent. Should be select value 62. r`q?SQ_PERF_SEL_CF_INST_FIFO_FULL_EX: Number of cycles the Export unit was full. Thread-type independent. Should be select value 63. 0shr@SQ_PERF_SEL_CF_INST_FIFO_FULL_SMX: Number of cycles the SMX Export unit was full. Thread-type independent. Should be select value 64. @txsASQ_PERF_SEL_CF_INST_FIFO_FULL_GF: Number of cycles the Geometry Fifo was full. Thread-type independent. Should be select value 65. utBKSQ_PERF_SEL_CF_INST_FIFO_FULL_OTHER: Reserved. Should be select value 66. vXuCSQ_PERF_SEL_CF_INST_FIFO_LEVEL_ALU: Number of credits available for all ALU units. Thread-type independent. Should be select value 67. (whvDSQ_PERF_SEL_CF_INST_FIFO_LEVEL_TF: Number of credits available for TF unit. Thread-type independent. Should be select value 68. 0xpwESQ_PERF_SEL_CF_INST_FIFO_LEVEL_VF: Number of credits available for VF unit. Thread-type independent. Should be select value 69. 8yxxFSQ_PERF_SEL_CF_INST_FIFO_LEVEL_EX: Number of credits available for EX unit. Thread-type independent. Should be select value 70. @zyGSQ_PERF_SEL_CF_INST_FIFO_LEVEL_SMX: Number of credits available for SMX unit. Thread-type independent. Should be select value 71. P{zHSQ_PERF_SEL_CF_INST_FIFO_LEVEL_GF: Number of credits available for Geometry Fifo. Thread-type independent. Should be select value 72. |{ILSQ_PERF_SEL_CF_INST_FIFO_LEVEL_OTHER: Reserved. Should be select value 73. (}h|JSQ_PERF_SEL_CF_INST_FIFO_EMPTY_ALU: Number of ALU units empty on a cycle. Thread-type independent. Should be select value 74. 8~p}KSQ_PERF_SEL_CF_INST_FIFO_EMPTY_TF: Number of cycles the Texture Fetch unit was empty. Thread-type independent. Should be select value 75. H~LSQ_PERF_SEL_CF_INST_FIFO_EMPTY_VF: Number of cycles the Vertex Fetch unit was empty. Thread-type independent. Should be select value 76. XMSQ_PERF_SEL_CF_INST_FIFO_EMPTY_EX: Number of cycles the Export unit was empty. Thread-type independent. Should be select value 77. `NSQ_PERF_SEL_CF_INST_FIFO_EMPTY_SMX: Number of cycles the SMX unit was empty. Thread-type independent. Should be select value 78. pOSQ_PERF_SEL_CF_INST_FIFO_EMPTY_GF: Number of cycles the Geometry fifo was empty. Thread-type independent. Should be select value 79. @PLSQ_PERF_SEL_CF_INST_FIFO_EMPTY_OTHER: Reserved. Should be select value 80. `QSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_ALU_PER_TYPE: Number of instructions outstanding for all ALU units. Thread-type dependent. Should be select value 81. xRSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_TF_PER_TYPE: Number of instructions outstanding for TF unit. Thread-type dependent. Should be select value 82. SSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_VF_PER_TYPE: Number of instructions outstanding for VF unit. Thread-type ependent. Should be select value 83. ؆TSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_EX_PER_TYPE: Number of instructions outstanding for EX unit. Thread-type dependent. Should be select value 84. ȈUSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_SMX_WR_PER_TYPE: Number of write instructions outstanding for SMX unit. Thread-type dependent. Should be select value 85. 艧VSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_SMX_RD_PER_TYPE: Number of read instructions outstanding for SMX unit. Thread-type dependent. Should be select value 86. 0WSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_GF_PER_TYPE: Number of instructions outstanding for Geometry Fifo. Thread-type dependent. Should be select value 87. 0PXSQ_PERF_SEL_CF_INST_ISSUE_LEVEL_OTHER_PER_TYPE: Number of instructions outstanding for non-ALU/TF/VF/EX/SMX/GF. Thread-type dependent. Should be select value 88. 8xYSQ_PERF_SEL_CF_INST_CHECKPOINT: Number of times user specified CF address is executed. Deterministic. Should be select value 89. `ZSQ_PERF_SEL_CF_INST_CHECKPOINT_BEFORE: Number of CF instructions executed including and after the specified CF address. Deterministic. Should be select value 90. [SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_VALID: Number of items valid for execution of instruction at CF address. Deterministic. Should be select value 91. ȏ\SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_VALID_NONE: Number of times no items are valid for execution of instruction at CF address. Deterministic. Should be select value 92. ]SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_ACTIVE: Number of items active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 93. X^SQ_PERF_SEL_CF_INST_CHECKPOINT_ITEMS_ACTIVE_NONE: Number of times no items are active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 94. Г_SQ_PERF_SEL_CF_INST_CHECKPOINT_QUADS_ACTIVE: Number of pixel quads active for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 95. X8`SQ_PERF_SEL_CF_INST_CHECKPOINT_QUADS_VALID: Number of pixel quads valid for execution of instruction at CF address (before whole-quad-mode and valid-pixel-mode bits are applied). Deterministic. Should be select value 96. haSQ_PERF_SEL_CF_INST_CHECKPOINT_THREADS: Number of times a thread first reaches the CF address. Deterministic. Should be select value 97. xbSQ_PERF_SEL_CF_INST_CHECKPOINT_THREAD_LEVEL: Number of threads that have reached the CF address per cycle. Should be select value 98. cSQ_PERF_SEL_CF_INST_FETCH_PER_TYPE: Number of CF fetch requests from cache. Thread-type dependent. Should be select value 99. șdSQ_PERF_SEL_CF_INST_FETCH_RETURNS_PER_TYPE: Number of CF fetch return cycles from cache. Thread-type dependent. Should be select value 100. eSQ_PERF_SEL_CF_INST_FETCH_INSTS_PER_TYPE: Number of CF instructions requested from cache. Thread-type dependent. Should be select value 101. МfSQ_PERF_SEL_CF_INST_FETCH_LEVEL_PER_TYPE: Number of CF fetch requests from cache pending per cycle. Thread-type dependent. Should be select value 102. 8gSQ_PERF_SEL_CF_INST_FETCH_EXTRA_PER_TYPE: Number of times we didn't issue the second instruction in a pair. Does not include instructions after PROGRAM_END. Thread-type dependent. Deterministic. Should be select value 103. PhSQ_PERF_SEL_CF_INST_FETCH_FIFO_SEND: Number of requests passing through the fetch fifo. Thread-type independent. Should be select value 104. XiSQ_PERF_SEL_CF_INST_FETCH_FIFO_LEVEL: Control Flow Fetch fifo entry level. Thread-type independent. Should be select value 105. xjSQ_PERF_SEL_CF_INST_FETCH_FIFO_STALL: Number of cycles when the CF fetch fifo is stalling issues. Thread-type independent. Should be select value 106. kSQ_PERF_SEL_CF_INST_CACHE_FIFO_SEND: Number of requests passing through the cache fifo. Thread-type independent. Should be select value 107. آlySQ_PERF_SEL_CF_INST_CACHE_FIFO_LEVEL: Number of credits in cache. Thread-type independent. Should be select value 108. أmSQ_PERF_SEL_CF_INST_CACHE_FIFO_FULL: Number of cycles when we have no cache credits. Thread-type independent. Should be select value 109. Х褧nSQ_PERF_SEL_CF_INST_ISSUE_DONES: Number of issues that need to be accounted for to avoid overflowing the done fifo. Thread-type independent. Should be select value 110. oSQ_PERF_SEL_CF_INST_ISSUE_DONE_LEVEL: Number of issues pending at any given time that need to be accounted for to avoid overflowing the done fifo. Thread-type independent. Should be select value 111. 8hpSQ_PERF_SEL_CF_INST_ISSUE_DONE_STALL: Stalls triggered to avoid overflowing the done fifo. Thread-type independent. Should be select value 112. PqSQ_PERF_SEL_CF_INST_ISSUE_DONE_FIFO_SEND: Number of items passing through the done fifo. Thread-type independent. Should be select value 113. `rSQ_PERF_SEL_CF_INST_ISSUE_DONE_FIFO_LEVEL: Control Flow Done fifo entry level. Thread-type independent. Should be select value 114. psSQ_PERF_SEL_CF_INST_ALU_UPDATE_FIFO_SEND: Macro sequencer alu update fifo send. Thread-type independent. Should be select value 115. tSQ_PERF_SEL_CF_INST_ALU_UPDATE_FIFO_LEVEL: Macro sequencer alu update fifo level. Thread-type independent. Should be select value 116. ȬuSQ_PERF_SEL_CF_INST_ALU_UPDATE_FIFO_STALL: Number of cycles when the MS alu update fifo is stalling issues and alu returns. Thread-type independent. Should be select value 117. vSQ_PERF_SEL_OFIFO_LEVEL_PER_TYPE: Number of threads and events in the ofifo. Thread-type dependent. Should be select value 118. ЯwSQ_PERF_SEL_SX_EVENT_FIFO_FULL_PER_TYPE: Number of cycles the SX event fifo is full. Thread-type dependent. Should be select value 119. xSQ_PERF_SEL_ALU_CLAUSE_INSTR_GROUPS_PER_TYPE: Number of ALU instruction groups executed. Thread-type dependent. Deterministic. Should be select value 120. @ySQ_PERF_SEL_ALU_CLAUSE_INSTRS_PER_TYPE: Number of ALU individual alu instructions executed. Thread-type dependent. Deterministic. Should be select value 121. PhzSQ_PERF_SEL_ALU_KWATERFALL_PER_TYPE: Number of ALU instruction groups which use const-waterfall. Thread-type dependent. Deterministic. Should be select value 122. {SQ_PERF_SEL_ALU_GPRWATERFALL_PER_TYPE: Number of ALU instruction groups which use gpr-waterfall. Thread-type dependent. Deterministic. Should be select value 123. ȵȴ|SQ_PERF_SEL_ALU_K_INSTR_PER_TYPE: Number of ALU instructions which use one or more constant (literal, kcache, or kfile). Thread-type dependent. Deterministic. Should be select value 124. ට}SQ_PERF_SEL_ALU_ICACHE_BUSY_PER_TYPE: Number of times ALU Icache read was denied - cache busy. Thread-type dependent. Should be select value 125. (~SQ_PERF_SEL_ALU_KCACHE_BUSY_PER_TYPE: Number of times ALU Kcache/Kfile read was denied - cache busy. Thread-type dependent. Should be select value 126. (HSQ_PERF_SEL_ALU_MOVA_IDLE_WAIT_PER_TYPE: Number of instruction cycles idle waiting for MOVA to complete. Thread-type dependent. Should be select value 127. hpSQ_PERF_SEL_ALU_LOCK_WAIT: Number of times (1 every 4 clocks) ALU has clauses in input fifo but no clauses locked -- ALU is idle. Thread-type independent. Should be select value 128. SQ_PERF_SEL_ALU_ICACHE_READS_PER_TYPE: Number of read requests to the ALU I-cache. Thread-type dependent. Deterministic. Should be select value 129. лSQ_PERF_SEL_ALU_KCACHE_READS_PER_TYPE: Number of read requests to the ALU K-cache/K-file. Thread-type dependent. Deterministic. Should be select value 130. нSQ_PERF_SEL_ALU_DONE_FIFO_FULL: Number of times the done-fifo is full and that caused a stall. Thread-type independent. Should be select value 131. SQ_PERF_SEL_ALU_MOVA_WAIT_PER_TYPE: Number of times more than one SIMD tried to execute MOVA, and one was denied access. Thread-type dependent. Should be select value 132. 8PSQ_PERF_SEL_ALU_THREADS_IN_FIFO_PER_TYPE: Number of threads waiting in the alu-seq's input fifo each cycle, of the selected thread type. Should be select value 133. SQ_PERF_SEL_UNUSED_006x SQ_PERF_SEL_UNUSED_007§SQ_PERF_SEL_TV_ICACHE_WAIT_PER_TYPE: Number of cycles the Tex/Vtx Icache denied a read request (busy). Thread-type dependent. Should be select value 136. 8ç§SQ_PERF_SEL_UNUSED_010ççSQ_PERF_SEL_UNUSED_001xħ ħSQ_PERF_SEL_UNUSED_002ŧħSQ_PERF_SEL_TF_TA_STALL_PER_TYPE: Number of times the TF had data to send to TA, but the TA input fifo was full. Thread-type dependent. Should be select value 140. ƧŧSQ_PERF_SEL_VF_VC_INSTR_STALL_PER_TYPE: Number of times the VF had data to send to VC, but the VC instruction input fifo was full. Thread-type dependent. Should be select value 141. ȧ0ǧSQ_PERF_SEL_VF_VC_INDEX_STALL_PER_TYPE: Number of times the VF had data to send to VC, but the VC index input fifo was full. Thread-type dependent. Should be select value 142. ȧhȧSQ_PERF_SEL_UNUSED_003`ɧɧSQ_PERF_SEL_UNUSED_008ʧɧSQ_PERF_SEL_UNUSED_004ʧHʧSQ_PERF_SEL_UNUSED_009˧ʧwSQ_PERF_SEL_EXPORT_INSTR_PER_TYPE: Number of exports (seen by export-seq). Determinstic. Should be select value 147. ̧˧{SQ_PERF_SEL_EXPORT_IDLE: Number of clocks where export unit is idle. Thread-type independent. Should be select value 148. ̧ͧSQ_PERF_SEL_EXPORT_SMX_AL_STALL: Number of clocks SMX export stalled waiting for alloc. Thread-type independent. Should be select value 149. ΧΧSQ_PERF_SEL_EXPORT_PC_AL_STALL: Number of clocks Param.cache alloc was stalled. Thread-type independent. Should be select value 150. ϧϧSQ_PERF_SEL_EXPORT_POS_AL_STALL: Number of clocks Position export alloc was stalled. Thread-type independent. Should be select value 151. Ч ЧSQ_PERF_SEL_EXPORT_PIX_AL_STALL: Number of clocks Pixel export alloc was stalled. Thread-type independent. Should be select value 152. ҧ0ѧSQ_PERF_SEL_EXPORT_POS_CYCLE: Number of position export cycles (4 clocks), * burst count). Thread-type independent. Determinstic. Should be select value 153. 8ӧXҧSQ_PERF_SEL_EXPORT_PIX_CYCLE: Number of pixel export cycles (4 clocks), * burst count). Thread-type independent. Determinstic. Should be select value 154. `ԧӧSQ_PERF_SEL_EXPORT_PC_CYCLE: Number of param.cache export cycles (4 clocks), * burst count). Thread-type independent. Determinstic. Should be select value 155. էԧSQ_PERF_SEL_EXPORT_SMX_CYCLE_PER_TYPE: Number of smx export cycles (4 clocks), * burst count). Thread-type dependent. Determinstic. Should be select value 156. ֧էSQ_PERF_SEL_CACHE_INVAL_ANY: Number of cache invalidation (surface synchronization) operations of any kind. Thread-type independent. Should be select value 157. ا֧SQ_PERF_SEL_CACHE_INVAL_ALL: Number of cache invalidation (surface synchronization) operations that invalidate the whole cache (due to a large invalidation region). Thread-type independent. Should be select value 158. ٧XاSQ_PERF_SEL_CACHE_INVAL_CYCLES: Number of cache invalidation (surface synchronization) cycles, not including full invalidations; indicates the size of the invalidation regions in 4K byte increments. Thread-type independent. Should be select value 159. ڧ٧SQ_PERF_SEL_CF_ICACHE_HITS: Number of CF instruction cache hits (it was found in the cache). Thread-type independent. Should be select value 160. ۧڧSQ_PERF_SEL_TF_ICACHE_HITS: Number of TV instruction cache hits (it was found in the cache). Thread-type independent. Should be select value 161. ܧܧQSQ_PERF_SEL_VF_ICACHE_HITS: DEPRECATED. Do not use. Should be select value 162. ݧܧSQ_PERF_SEL_ALU_ICACHE_HITS: Number of ALU instruction cache hits (it was found in the cache). Thread-type independent. Should be select value 163. ާާSQ_PERF_SEL_ALU_KCACHE_HITS: Number of ALU constant cache hits (it was found in the cache). Thread-type independent. Should be select value 164. ߧSQ_PERF_SEL_CF_ICACHE_MISSES: Number of CF instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 165. hhSQ_PERF_SEL_TF_ICACHE_MISSES: Number of TV instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 166. @SSQ_PERF_SEL_VF_ICACHE_MISSES: DEPRECATED. Do not use. Should be select value 167. SQ_PERF_SEL_ALU_ICACHE_MISSES: Number of ALU instruction cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 168. SQ_PERF_SEL_ALU_KCACHE_MISSES: Number of ALU constant cache misses (it was not found in the cache and has to be fetched from memory). Thread-type independent. Should be select value 169. (SQ_PERF_SEL_CF_ICACHE_DUP_MISSES: Number of CF instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 170. pSQ_PERF_SEL_TF_ICACHE_DUP_MISSES: Number of TV instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 171. hWSQ_PERF_SEL_VF_ICACHE_DUP_MISSES: DEPRECATED. Do not use. Should be select value 172. SQ_PERF_SEL_ALU_ICACHE_DUP_MISSES: Number of ALU instruction cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 173. (SQ_PERF_SEL_ALU_KCACHE_DUP_MISSES: Number of ALU constant cache duplicate misses (it matches a previous cache miss that is currently being fetched from memory). Thread-type independent. Should be select value 174. pSQ_PERF_SEL_CF_ICACHE_ACCESSES: Number of CF instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 175. SQ_PERF_SEL_TF_ICACHE_ACCESSES: Number of TV instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 176. PUSQ_PERF_SEL_VF_ICACHE_ACCESSES: DEPRECATED. Do not use. Should be select value 177. X0SQ_PERF_SEL_ALU_ICACHE_ACCESSES: Number of ALU instruction cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 178. SQ_PERF_SEL_ALU_KCACHE_ACCESSES: Number of ALU constant cache accesses (a request is broken into one or more cache accesses). Equals the sum of hits, misses and duplicate misses. Thread-type independent. Should be select value 179. SQ_PERF_SEL_CF_ICACHE_INPUT_FIFO_ENTRIES: Count of CF instruction cache requests stored in the input FIFO. Thread-type independent. Should be select value 180. 8SQ_PERF_SEL_TF_ICACHE_INPUT_FIFO_ENTRIES: Count of TV instruction cache requests stored in the input FIFO. Thread-type independent. Should be select value 181. `_SQ_PERF_SEL_VF_ICACHE_INPUT_FIFO_ENTRIES: DEPRECATED. Do not use. Should be select value 182. (HSQ_PERF_SEL_ALU_ICACHE_INPUT_FIFO_ENTRIES: Count of ALU instruction cache requests stored in the input FIFO. Thread-type independent. Should be select value 183. PpSQ_PERF_SEL_ALU_KCACHE_INPUT_FIFO_ENTRIES: Count of ALU constant cache requests stored in the input FIFO. Thread-type independent. Should be select value 184. SQ_PERF_SEL_CF_ICACHE_MISS_MEM_STALL: Number of CF instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 185. SQ_PERF_SEL_TF_ICACHE_MISS_MEM_STALL: Number of TV instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 186. X[SQ_PERF_SEL_VF_ICACHE_MISS_MEM_STALL: DEPRECATED. Do not use. Should be select value 187. X8SQ_PERF_SEL_ALU_ICACHE_MISS_MEM_STALL: Number of ALU instruction cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 188. SQ_PERF_SEL_ALU_KCACHE_MISS_MEM_STALL: Number of ALU constant cache cycles that are a cache miss that are stalled because the memory request interface is stalling. Thread-type independent. Should be select value 189. 0SQ_PERF_SEL_CF_ICACHE_MISS_FIFO_STALL: Number of CF instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 190. xSQ_PERF_SEL_TF_ICACHE_MISS_FIFO_STALL: Number of TV instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 191. \SQ_PERF_SEL_VF_ICACHE_MISS_FIFO_STALL: DEPRECATED. Do not use. Should be select value 192. SQ_PERF_SEL_ALU_ICACHE_MISS_FIFO_STALL: Number of ALU instruction cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 193. xHSQ_PERF_SEL_ALU_KCACHE_MISS_FIFO_STALL: Number of ALU constant cache cycles that are a cache miss or duplicate miss that is stalled because the miss (or duplicate miss) FIFO is full. Thread-type independent. Should be select value 194. SQ_PERF_SEL_CF_ICACHE_HIT_STALL: Number of CF instruction cache cycles that are a cache hit but are stalled due to processing previous misses. Thread-type independent. Should be select value 195. 0SQ_PERF_SEL_CF_ICACHE_MISS_LOCKED_STALL: Number of CF instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 196. xSQ_PERF_SEL_TF_ICACHE_MISS_LOCKED_STALL: Number of TV instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 197. ^SQ_PERF_SEL_VF_ICACHE_MISS_LOCKED_STALL: DEPRECATED. Do not use. Should be select value 198. SQ_PERF_SEL_ALU_ICACHE_MISS_LOCKED_STALL: Number of ALU instruction cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 199. P 0 SQ_PERF_SEL_ALU_KCACHE_MISS_LOCKED_STALL: Number of ALU constant cache cycles that are a cache miss that are stalled because all tags are in use so none can be allocated. Thread-type independent. Should be select value 200. SQ_PERF_SEL_CF_ICACHE_LOCKED_TAGS: Count of CF instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 201.  SQ_PERF_SEL_TF_ICACHE_LOCKED_TAGS: Count of TV instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 202. HXSQ_PERF_SEL_VF_ICACHE_LOCKED_TAGS: DEPRECATED. Do not use. Should be select value 203. 8(SQ_PERF_SEL_ALU_ICACHE_LOCKED_TAGS: Count of ALU instruction cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 204. SQ_PERF_SEL_ALU_KCACHE_LOCKED_TAGS: Count of ALU constant cache tags that are currently locked during a cache access cycle (miss, hit, or duplicate miss). Thread-type independent. Should be select value 205. SQ_PERF_SEL_CF_ICACHE_MISS_LOCKED_TAGS: Count of CF instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 206. SQ_PERF_SEL_TF_ICACHE_MISS_LOCKED_TAGS: Count of TV instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 207. X]SQ_PERF_SEL_VF_ICACHE_MISS_LOCKED_TAGS: DEPRECATED. Do not use. Should be select value 208. 8@SQ_PERF_SEL_ALU_ICACHE_MISS_LOCKED_TAGS: Count of ALU instruction cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 209. xSQ_PERF_SEL_ALU_KCACHE_MISS_LOCKED_TAGS: Count of ALU constant cache tags that are currently locked during a cache miss cycle. Thread-type independent. Should be select value 210. SQ_PERF_SEL_CACHE_MEM_REQUESTS: Number of cache to memory controller requests of any type. Thread-type independent. Should be select value 211. SQ_PERF_SEL_CF_ICACHE_MEM_REQUESTS: Number of CF instruction cache to memory controller requests. Thread-type independent. Should be select value 212. SQ_PERF_SEL_TV_ICACHE_MEM_REQUESTS: Number of TV instruction cache to memory controller requests. Thread-type independent. Should be select value 213. SQ_PERF_SEL_ALU_ICACHE_MEM_REQUESTS: Number of ALU instruction cache to memory controller requests. Thread-type independent. Should be select value 214. 8SQ_PERF_SEL_ALU_KCACHE_MEM_REQUESTS: Number of ALU constant cache to memory controller requests. Thread-type independent. Should be select value 215. PXSQ_PERF_SEL_CF_ICACHE_RD_WR_COLLISION: Number of times a read to the CF icache memory was blocked by a write from a memory return. Thread-type independent. Should be select value 216. SQ_PERF_SEL_CF_ICACHE_MISS_HIT_RD_COLLISION: Number of times processing a hit is stalled by processing a now-resident miss. Thread-type independent. Should be select value 217. ! SQ_PERF_SEL_CF_ICACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding CF instruction cache to memory controller requests of any type. Thread-type independent. Should be select value 218. (# "SQ_PERF_SEL_TV_ICACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding TV instruction cache to memory controller requests of any type. Thread-type independent. Should be select value 219. x$p#SQ_PERF_SEL_ALU_ICACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding ALU instruction cache to memory controller requests of any type. Thread-type independent. Should be select value 220. %$SQ_PERF_SEL_ALU_KCACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding ALU constant cache to memory controller requests of any type. Thread-type independent. Should be select value 221. &&SQ_PERF_SEL_CF_ICACHE_MISS_FIFO_MISSES: Count of the number of CF instruction cache misses waiting in the miss FIFO. Thread-type independent. Should be select value 222. ((@'SQ_PERF_SEL_TF_ICACHE_MISS_FIFO_MISSES: Count of the number of TV instruction cache misses waiting in the miss FIFO. Thread-type independent. Should be select value 223. )p(]SQ_PERF_SEL_VF_ICACHE_MISS_FIFO_MISSES: DEPRECATED. Do not use. Should be select value 224. P*X)SQ_PERF_SEL_ALU_ICACHE_MISS_FIFO_MISSES: Count of the number of ALU instruction cache misses waiting in the miss FIFO. Divided by 2. Thread-type independent. Should be select value 225. +*SQ_PERF_SEL_ALU_KCACHE_MISS_FIFO_MISSES: Count of the number of ALU constant cache misses waiting in the miss FIFO. Divided by 2. Thread-type independent. Should be select value 226. ,+SQ_PERF_SEL_CACHE_MEM_REQUESTS_IN_FLIGHT: Count of the number of outstanding cache to memory controller requests of any type. Divided by 2. Thread-type independent. Should be select value 227. - -SQ_PERF_SEL_CACHE_MEM_STALL: Number of cache to memory controller cycles that are stalled. Thread-type independent. Should be select value 228. .8.qSQ_PERF_SEL_TM_TS64_STALL: Clock cycles GRBM stalled due to Timestamp-64 FIFO full. Should be select value 229. /0/SQ_PERF_SEL_TM_ALU_CONST_STALL: Clock cycles GRBM stalled due to ALU constant overflow buffer full. Should be select value 230. 080SQ_PERF_SEL_TM_LOOP_CONST_STALL: Clock cycles GRBM stalled due to Loop constant overflow buffer full. Should be select value 231. 2@1SQ_PERF_SEL_TM_TEX_BASE_CONST_STALL: Clock cycles GRBM stalled due to VertexBase/InstantStart constant overflow buffer full. Should be select value 232. 03`2SQ_PERF_SEL_TM_TEX_SAMPLER_STALL: Clock cycles GRBM stalled due to Texture Sampler constant overflow buffer full. Should be select value 233. H4x3SQ_PERF_SEL_TM_TEX_RESOURCE_STALL: Clock cycles GRBM stalled due to Texture Resource constant overflow buffer full. Should be select value 234. 44SQ_PERF_SEL_UNUSED_0058605SQ_PERF_SEL_TA_TEX_INSTRS_PER_TYPE: Number of texture-fetch instructions executed by the Texture cache, including killed fetches. Thread-type dependent. Determinstic. Should be select value 236. 76SQ_PERF_SEL_TA_VTX_INSTRS_PER_TYPE: Number of vertex-fetch instructions executed by the Texture cache, including killed fetches. Thread-type dependent. Determinstic. Should be select value 237. 87SQ_PERF_SEL_VC_INSTRS_PER_TYPE: Number of instructions executed by the Vertex cache, including killed fetches. Thread-type dependent. Determinstic. Should be select value 238. 99SQ_PERF_SEL_TV_LOCK_WAIT: Number of cycles the TF input FIFO had clauses, none were locked. Thread-type independent, non-deterministic. Should be select value 239. ;0:SQ_PERF_SEL_TA_SRC_C: Number of times an TA fetch (16 pix or verts) was executed as a src-c export. Non-deterministic. Should be select value 240. <H;SQ_PERF_SEL_VC_SRC_C: Number of times a VC fetch (16 pix or verts) was executed as a src-c export. Non-deterministic. Should be select value 241. @=`<SQ_PERF_SEL_TV_KILLED_FETCH_PER_TYPE: Number of fetch instructions killed (vertex semantic failed or gpr out of range). Deterministic. Should be select value 242. x>=SQ_PERF_SEL_TV_NULL_FETCH_PER_TYPE: Number of null fetchs issued (null = issue empty fetch at end of clause due to killed fetches). Deterministic. Should be select value 243. ?>SQ_PERF_SEL_TV_THREADS_IN_FIFO_PER_TYPE: Number of threads waiting in the fetch-seq's input fifo each cycle, of the selected thread type. Should be select value 244. @?SQ_PERF_SEL_EXPORT_SPQ_LEVEL: Internal export per-quadpipe queue level average. Non-deterministic. Should be select value 245. @ySQ_PERF_SEL_EXPORT_SPQ_STALL: Internal export per-quadpipe stall cycles. Non-deterministic. Should be select value 246. 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PGM_END"h;P=\\""=SQ_PGM_END_CF_VS= PGM_END":;ЈЈ""0<SQ_PGM_CF_OFFSET_VS<PGM_CF_OFFSET"8x:XX"":SQ_PGM_START_VS ; PGM_START"P19TT""`9SQ_PGM_EXPORTS_PS9 EXPORT_MODE"/1PP""2SQ_PGM_RESOURCES_PS 2p2 NUM_GPRS"X33 STACK_SIZE"33 DX10_CLAMP"4P4PRIME_CACHE_PGM_EN"H54PRIME_CACHE_ON_DRAW"55FETCH_CACHE_LINES"6H6UNCACHED_FIRST_INST"@76PRIME_CACHE_ENABLE"77PRIME_CACHE_ON_CONST"H8 CLAMP_CONSTS".`0LL""0SQ_PGM_END_FETCH_PS1 PGM_END"-.HH""H/SQ_PGM_END_ALU_PS/ PGM_END"+-DD""-SQ_PGM_END_CF_PS8. PGM_END"@* ,̈̈""p,SQ_PGM_CF_OFFSET_PS,PGM_CF_OFFSET"'*@@""+SQ_PGM_START_PS`+ PGM_START"$(( """x(TCA_DEBUG_BUS_MISC)( REG_WRITE"p) REG_READ"#p% """%TCA_DEBUG_BUS_CG`&& OVERRIDE"'& CORE_ENABLED"`'BLOCK_ENABLED""$ """X$TCA_DEBUG_BUS_GO_TCCD$ GO_CLIENTS" " """"TCA_DEBUG_BUS_GO_TCCC@# GO_CLIENTS"0 ! """x!TCA_DEBUG_BUS_GO_TCCB! GO_CLIENTS"""" TCA_DEBUG_BUS_GO_TCCA`  GO_CLIENTS"P8"""TCA_DEBUG_BUS_ASK_TCCD ASK_CLIENTS"""" TCA_DEBUG_BUS_ASK_TCCCx ASK_CLIENTS"pX"""TCA_DEBUG_BUS_ASK_TCCB ASK_CLIENTS""""@TCA_DEBUG_BUS_ASK_TCCA ASK_CLIENTS"p"""TCA_DEBUG_BUS_BUSY_TCCD  BUSY_CLIENTS""""PTCA_DEBUG_BUS_BUSY_TCCC BUSY_CLIENTS""""TCA_DEBUG_BUS_BUSY_TCCB0 BUSY_CLIENTS""""`TCA_DEBUG_BUS_BUSY_TCCA BUSY_CLIENTS"H x"""TCC_DEBUG_BUS_MISCh DEALLOC" DEALLOC_ALL"` DEALLOC_BUSY"P DEALLOC_REG" REG_WRITE"H REG_READ" """ TCC_DEBUG_BUS_CG h  OVERRIDE"X CORE_ENABLED"BLOCK_ENABLED"P  """ TCC_DEBUG_BUS_MC_RDRETP  MC_RDRET_TAG" MC_RDRET_VLD_TC_TF" P MC_RDRET_VLD_TC_VF" MC_RDRET_VLD_VC_VF"H8"""TCC_DEBUG_BUS_MC_RDREQ8 MC_RDREQ_TAG"MC_RDREQ_SEND_TC_TF"8 MC_RDREQ_SEND_TC_VF"0 MC_RDREQ_SEND_VC_VF" MC_RDREQ_FREE""""TCC_DEBUG_BUS_ARB_GOpARB_GO_CLIENTS"H"""TCC_DEBUG_BUS_ARB_ASKARB_ASK_CLIENTS" """PTCC_DEBUG_BUS_RTNRTN_VLD"H RTN_TYPE"0RTN_SEL"RTN_TAG""""TCC_DEBUG_BUS_CACHE_REQ HCACHE_REQ_VLD"@CACHE_REQ_TYPE"CACHE_REQ_SEL"@ CACHE_REQ_UNCACHED"8 CACHE_REQ_HIT" CACHE_REQ_MISS"8 CACHE_REQ_STALL"0 CACHE_REQ_TAG_STALL"CACHE_REQ_TAG_RENAME"8CACHE_REQ_TAG"00"""TCC_DEBUG_BUS_REQ REQ_CLIENTS""""TCC_DEBUG_BUS_STALL PCACHE_TAG_STALL"HCACHE_TAG_RENAME" CACHE_STALL"@MC_FULL"(LF_FULL" LF_FULL_TC"h  LF_FULL_VC"LF_FULL_CLIENT_TC"hLF_FULL_CLIENT_VC"p0"""TCC_DEBUG_BUS_CLIENT_BUSY BUSY_CLIENTS""""8TCC_DEBUG_BUS_BUSY BUSY_TC_TF"x0 BUSY_TC_VF" BUSY_VC_VF"pBUSY_MC_TC_TF"hBUSY_MC_TC_VF"BUSY_MC_VC_VF"hBUSY_MC_CREDITS"""TCA_DEBUG_DATA(DATAܥ""hTCA_DEBUG_INDEXINDEXڥxܥ""ܥ TCA_CTRL0ݥ`ݥ ARB_MODE0ޥݥFTCA_ARB_MODE_SEL_FIXED: Each L2 can write to an TC on a fixed cycle. ߥxޥ^TCA_ARB_MODE_SEL_RANDOM: Randomly prioritive sources and destinations for return scheduling. `ߥTCA_ARB_MODE_SEL_RANDOM_FAVOR_OLDEST: Same as TCA_ARB_MODE_SEL_RANDOM, but do a pass to schedule the single oldest requets from each client first.  READY_DEPTH"(p RETURN_RATE full rate H 1/2 rate  1/4 rate h 1/8 rate P VF_PRIO" IGNORE_TC_STALL"PIGNORE_VC_STALL"(ץۥ""`ۥTCA_READ_INDEXۥINDEX"եץ""ץTCA_WRITE_INDEXإHإINDEX"إ0٥ WRITE_ALL٥x٥DJust write the registers in the TCA block indicated by INDEX field @ڥWrite all TCA blocks Xԥ8֥̖̖""֥TCC_PERFCOUNTER3_HI֥ PERF_COUNT"ҥԥ"" եTCC_PERFCOUNTER2_HIxե PERF_COUNT"ѥhӥ""ӥTCC_PERFCOUNTER1_HIԥ PERF_COUNT"Хҥ""PҥTCC_PERFCOUNTER0_HIҥ PERF_COUNT"ΥХȖȖ""ХTCC_PERFCOUNTER3_LOW@ѥ PERF_COUNT"8ͥ ϥ""xϥTCC_PERFCOUNTER2_LOWϥ PERF_COUNT"˥ͥ""ΥTCC_PERFCOUNTER1_LOW`Υ PERF_COUNT"H@̥""̥TCC_PERFCOUNTER0_LOW̥ PERF_COUNT"Ť(IĖĖ""ITCC_PERFCOUNTER3_SELECTťI J PERF_SELJhJ9TCC_PERF_SEL_NONE: don't count anything Deterministic. K(K(TCC_PERF_SEL_CYCLES: Number of cycles. XLK@TCC_PERF_SEL_BUSY: Number of cycles we have a request pending. 0MLRTCC_PERF_SEL_BUSY_TC_TF: Number of cycles we have an TC texture request pending. NxMQTCC_PERF_SEL_BUSY_TC_VF: Number of cycles we have an TC vertex request pending. NPNJTCC_PERF_SEL_BUSY_VC_VF: Number of cycles we have an VC request pending. O O(TCC_PERF_SEL_REQS: Number of requests. PPOBTCC_PERF_SEL_REQS_HIT: Number of requests that hit in the cache. QPDTCC_PERF_SEL_REQS_MISS: Number of requests that miss in the cache. Q`Q :TCC_PERF_SEL_REQS_UNCACHED: Number of uncached requests. R R >TCC_PERF_SEL_REQS_CLIENT_0: Number of requests for client 0. hSR >TCC_PERF_SEL_REQS_CLIENT_1: Number of requests for client 1. 0TS >TCC_PERF_SEL_REQS_CLIENT_2: Number of requests for client 2. TxT >TCC_PERF_SEL_REQS_CLIENT_3: Number of requests for client 3. U@U>TCC_PERF_SEL_REQS_CLIENT_4: Number of requests for client 4. VV>TCC_PERF_SEL_REQS_CLIENT_5: Number of requests for client 5. PWV>TCC_PERF_SEL_REQS_CLIENT_6: Number of requests for client 6. XW>TCC_PERF_SEL_REQS_CLIENT_7: Number of requests for client 7. X`X>TCC_PERF_SEL_REQS_CLIENT_8: Number of requests for client 8. Y(Y>TCC_PERF_SEL_REQS_CLIENT_9: Number of requests for client 9. pZY@TCC_PERF_SEL_REQS_CLIENT_10: Number of requests for client 10. 8[Z@TCC_PERF_SEL_REQS_CLIENT_11: Number of requests for client 11. \[@TCC_PERF_SEL_REQS_CLIENT_12: Number of requests for client 12. \H\@TCC_PERF_SEL_REQS_CLIENT_13: Number of requests for client 13. ]]@TCC_PERF_SEL_REQS_CLIENT_14: Number of requests for client 14. X^]@TCC_PERF_SEL_REQS_CLIENT_15: Number of requests for client 15. _^@TCC_PERF_SEL_REQS_CLIENT_16: Number of requests for client 16. _h_@TCC_PERF_SEL_REQS_CLIENT_17: Number of requests for client 17. `0`@TCC_PERF_SEL_REQS_CLIENT_18: Number of requests for client 18. xa`@TCC_PERF_SEL_REQS_CLIENT_19: Number of requests for client 19. @ba@TCC_PERF_SEL_REQS_CLIENT_20: Number of requests for client 20. cb@TCC_PERF_SEL_REQS_CLIENT_21: Number of requests for client 21. cPc @TCC_PERF_SEL_REQS_CLIENT_22: Number of requests for client 22. dd!@TCC_PERF_SEL_REQS_CLIENT_23: Number of requests for client 23. `ed"CTCC_PERF_SEL_REQS_TC_TF: Number of requests from TCs for texture. @fe#\TCC_PERF_SEL_REQS_TC_TF_HIT: Number of requests from TC for texture that hit in the cache. (gf$^TCC_PERF_SEL_REQS_TC_TF_MISS: Number of requests from TC for texture that miss in the cache. gpg%BTCC_PERF_SEL_REQS_TC_VF: Number of requests from TCs for vertex. h8h&HTCC_PERF_SEL_REQS_TC_VF_HIT: Number of requests that hit in the cache. ii'JTCC_PERF_SEL_REQS_TC_VF_MISS: Number of requests that miss in the cache. Pji(6TCC_PERF_SEL_REQS_VC_VF: Number of requests from VC. (kj)PTCC_PERF_SEL_REQS_VC_VF_HIT: Number of requests from VC that hit in the cache. lpk*RTCC_PERF_SEL_REQS_VC_VF_MISS: Number of requests from VC that miss in the cache. lHl+FTCC_PERF_SEL_REQ_LEVEL_TC_TF: Number of pending TC texture requests. mm,ETCC_PERF_SEL_REQ_LEVEL_TC_VF: Number of pending TC vertex requests. hnm->TCC_PERF_SEL_REQ_LEVEL_VC_VF: Number of pending VC requests. 8on.KTCC_PERF_SEL_REQ_LEVEL_CLIENT_0: Number of requests pending for client 0. po/KTCC_PERF_SEL_REQ_LEVEL_CLIENT_1: Number of requests pending for client 1. pPp0KTCC_PERF_SEL_REQ_LEVEL_CLIENT_2: Number of requests pending for client 2. q q1KTCC_PERF_SEL_REQ_LEVEL_CLIENT_3: Number of requests pending for client 3. xrq2KTCC_PERF_SEL_REQ_LEVEL_CLIENT_4: Number of requests pending for client 4. Hsr3KTCC_PERF_SEL_REQ_LEVEL_CLIENT_5: Number of requests pending for client 5. ts4KTCC_PERF_SEL_REQ_LEVEL_CLIENT_6: Number of requests pending for client 6. t`t5KTCC_PERF_SEL_REQ_LEVEL_CLIENT_7: Number of requests pending for client 7. u0u6KTCC_PERF_SEL_REQ_LEVEL_CLIENT_8: Number of requests pending for client 8. vv7KTCC_PERF_SEL_REQ_LEVEL_CLIENT_9: Number of requests pending for client 9. `wv8MTCC_PERF_SEL_REQ_LEVEL_CLIENT_10: Number of requests pending for client 10. 8xw9MTCC_PERF_SEL_REQ_LEVEL_CLIENT_11: Number of requests pending for client 11. yx:MTCC_PERF_SEL_REQ_LEVEL_CLIENT_12: Number of requests pending for client 12. yXy;MTCC_PERF_SEL_REQ_LEVEL_CLIENT_13: Number of requests pending for client 13. z0z<MTCC_PERF_SEL_REQ_LEVEL_CLIENT_14: Number of requests pending for client 14. {{=MTCC_PERF_SEL_REQ_LEVEL_CLIENT_15: Number of requests pending for client 15. p|{>MTCC_PERF_SEL_REQ_LEVEL_CLIENT_16: Number of requests pending for client 16. H}|?MTCC_PERF_SEL_REQ_LEVEL_CLIENT_17: Number of requests pending for client 17. ~}@MTCC_PERF_SEL_REQ_LEVEL_CLIENT_18: Number of requests pending for client 18. ~h~AMTCC_PERF_SEL_REQ_LEVEL_CLIENT_19: Number of requests pending for client 19. @BMTCC_PERF_SEL_REQ_LEVEL_CLIENT_20: Number of requests pending for client 20. CMTCC_PERF_SEL_REQ_LEVEL_CLIENT_21: Number of requests pending for client 21. DMTCC_PERF_SEL_REQ_LEVEL_CLIENT_22: Number of requests pending for client 22. XȁEMTCC_PERF_SEL_REQ_LEVEL_CLIENT_23: Number of requests pending for client 23. F.TCC_PERF_SEL_MC_REQS: Number of MC requests. ؃XGCTCC_PERF_SEL_MC_REQS_TC_TF: Number of MC requests for TC texture. HBTCC_PERF_SEL_MC_REQS_TC_VF: Number of MC requests for TC vertex. `脥I;TCC_PERF_SEL_MC_REQS_VC_VF: Number of MC requests for VC. J7TCC_PERF_SEL_MC_FULL: Number of cycles the MC is full hK;TCC_PERF_SEL_MC_REQ_LEVEL: Number of MC requests pending. (LPTCC_PERF_SEL_MC_REQ_LEVEL_TC_TF: Number of MC requests pending for TC texture. MOTCC_PERF_SEL_MC_REQ_LEVEL_TC_VF: Number of MC requests pending for TC vertex. `؈NHTCC_PERF_SEL_MC_REQ_LEVEL_VC_VF: Number of MC requests pending for VC. (O=TCC_PERF_SEL_MC_CREDIT_LEVEL: Number of MC credits pending. pPQTCC_PERF_SEL_CG_CORE_ENABLED: Number of cycles the shader core clock is enabled ЋHQLTCC_PERF_SEL_CG_BLOCK_ENABLED: Number of cycles the block clock is enabled RATCC_PERF_SEL_LF_FULL: Number of cycles the latency fifo is full hSKTCC_PERF_SEL_LF_FULL_VC: Number of cycles the vertex latency fifo is full 8TLTCC_PERF_SEL_LF_FULL_TC: Number of cycles the texture latency fifo is full (UiTCC_PERF_SEL_LF_FULL_CLIENT_VC: Number of cycles the latency fifo is full for a dedicated vertex client pV_TCC_PERF_SEL_LF_FULL_CLIENT_TC: Number of cycles the latency fifo is full for a non-VC client ؐXW@TCC_PERF_SEL_LF_LEVEL: Number of requests in the latency fifo. XITCC_PERF_SEL_LF_LEVEL_VC_VF: Number of VC requests in the latency fifo. Y`TCC_PERF_SEL_LF_LEVEL_TC_VF: Number of TC vertex requests in the latency fifo for vertex data. xؒZbTCC_PERF_SEL_LF_LEVEL_TC_TF: Number of TC texture requests in the latency fifo for texture data. H[KTCC_PERF_SEL_LF_BLOCK_LEVEL: Number of blocks in use by the latency fifo. @\nTCC_PERF_SEL_LF_BLOCK_LEVEL_VC: Number of blocks in use by the dedicated vertex clients in the latency fifo. 0]eTCC_PERF_SEL_LF_BLOCK_LEVEL_TC: Number of blocks in use by the texture clients in the latency fifo. x^@TCC_PERF_SEL_OF_LEVEL: Number of requests in the output fifos. ȗ@_ITCC_PERF_SEL_OF_LEVEL_VC_VF: Number of VC requests in the output fifos. `PTCC_PERF_SEL_OF_LEVEL_TC_VF: Number of TC vertex requests in the output fifos. x蘥aQTCC_PERF_SEL_OF_LEVEL_TC_TF: Number of TC texture requests in the output fifos. HbJTCC_PERF_SEL_TCA_LEVEL: Number of requests ready for output arbitration. cSTCC_PERF_SEL_TCA_LEVEL_VC_VF: Number of VC requests ready for output arbitration. hdZTCC_PERF_SEL_TCA_LEVEL_TC_VF: Number of TC vertex requests ready for output arbitration. He[TCC_PERF_SEL_TCA_LEVEL_TC_TF: Number of TC texture requests ready for output arbitration. ȝ(fdTCC_PERF_SEL_TCA_LEVEL_CLIENT_0: Number of requests ready for arbitration in the tca for client 0. gdTCC_PERF_SEL_TCA_LEVEL_CLIENT_1: Number of requests ready for arbitration in the tca for client 1. hdTCC_PERF_SEL_TCA_LEVEL_CLIENT_2: Number of requests ready for arbitration in the tca for client 2. idTCC_PERF_SEL_TCA_LEVEL_CLIENT_3: Number of requests ready for arbitration in the tca for client 3. hȠjdTCC_PERF_SEL_TCA_LEVEL_CLIENT_4: Number of requests ready for arbitration in the tca for client 4. PkdTCC_PERF_SEL_TCA_LEVEL_CLIENT_5: Number of requests ready for arbitration in the tca for client 5. 8ldTCC_PERF_SEL_TCA_LEVEL_CLIENT_6: Number of requests ready for arbitration in the tca for client 6. mdTCC_PERF_SEL_TCA_LEVEL_CLIENT_7: Number of requests ready for arbitration in the tca for client 7. hndTCC_PERF_SEL_TCA_LEVEL_CLIENT_8: Number of requests ready for arbitration in the tca for client 8. PodTCC_PERF_SEL_TCA_LEVEL_CLIENT_9: Number of requests ready for arbitration in the tca for client 9. থ8pfTCC_PERF_SEL_TCA_LEVEL_CLIENT_10: Number of requests ready for arbitration in the tca for client 10. Ч(qfTCC_PERF_SEL_TCA_LEVEL_CLIENT_11: Number of requests ready for arbitration in the tca for client 11. rfTCC_PERF_SEL_TCA_LEVEL_CLIENT_12: Number of requests ready for arbitration in the tca for client 12. sfTCC_PERF_SEL_TCA_LEVEL_CLIENT_13: Number of requests ready for arbitration in the tca for client 13. tfTCC_PERF_SEL_TCA_LEVEL_CLIENT_14: Number of requests ready for arbitration in the tca for client 14. 誥ufTCC_PERF_SEL_TCA_LEVEL_CLIENT_15: Number of requests ready for arbitration in the tca for client 15. ثvfTCC_PERF_SEL_TCA_LEVEL_CLIENT_16: Number of requests ready for arbitration in the tca for client 16. pȬwfTCC_PERF_SEL_TCA_LEVEL_CLIENT_17: Number of requests ready for arbitration in the tca for client 17. `xfTCC_PERF_SEL_TCA_LEVEL_CLIENT_18: Number of requests ready for arbitration in the tca for client 18. PyfTCC_PERF_SEL_TCA_LEVEL_CLIENT_19: Number of requests ready for arbitration in the tca for client 19. @zfTCC_PERF_SEL_TCA_LEVEL_CLIENT_20: Number of requests ready for arbitration in the tca for client 20. 0{fTCC_PERF_SEL_TCA_LEVEL_CLIENT_21: Number of requests ready for arbitration in the tca for client 21. x|fTCC_PERF_SEL_TCA_LEVEL_CLIENT_22: Number of requests ready for arbitration in the tca for client 22. h}fTCC_PERF_SEL_TCA_LEVEL_CLIENT_23: Number of requests ready for arbitration in the tca for client 23. 賥X~PTCC_PERF_SEL_CLIENTS_FULL: Number of clients stalled due to a full return fifo ȴ0VTCC_PERF_SEL_CLIENTS_FULL_VC: Number of VC clients stalled due to a full return fifo VTCC_PERF_SEL_CLIENTS_FULL_TC: Number of TC clients stalled due to a full return fifo `/TCC_PERF_SEL_ARB_BURST: Number of bursts sent (BTCC_PERF_SEL_ARB_BURST_VC: Number of bursts sent from VC clients pBTCC_PERF_SEL_ARB_BURST_TC: Number of bursts sent from TC clients 8TCC_PERF_SEL_CACHE_TAG_STALL_TC_TF: Number of cycles the cache is stalled because we can't find a tag we can use for a TC texture request. HjTCC_PERF_SEL_CACHE_TAG_RENAME_TC_TF: Number of tagset name swaps that occurred for a TC texture request. 8TCC_PERF_SEL_CACHE_TAG_STALL_TC_VF: Number of cycles the cache is stalled because we can't find a tag we can use for a TC vertex request. HiTCC_PERF_SEL_CACHE_TAG_RENAME_TC_VF: Number of tagset name swaps that occurred for a TC vertex request. 8TCC_PERF_SEL_CACHE_TAG_STALL_VC_VF: Number of cycles the cache is stalled because we can't find a tag we can use for a VC vertex request. HiTCC_PERF_SEL_CACHE_TAG_RENAME_VC_VF: Number of tagset name swaps that occurred for a VC vertex request. о8YTCC_PERF_SEL_CACHE_STALL: Number of cycles that a cache allocation request was stalled. 1TCC_PERF_SEL_DEALLOC: Number of cache deallocs. PпCTCC_PERF_SEL_DEALLOC_ALL: Number of cache deallocs of all caches. (MTCC_PERF_SEL_DEALLOC_LINES: Number of cache lines specifically deallocated. ¥pOTCC_PERF_SEL_DEALLOC_CYCLES: Number of cycles spent deallocating cache lines. ¥H¥>TCC_PERF_SEL_REG_WRITES: Number of indirect register writes. åå<TCC_PERF_SEL_REG_READS: Number of indirect register reads. `ĥåSTCC_PERF_SEL_DEBUG_BUS: Number of debug events based on TCC_DEBUG_INDEX register. ĥ$TCC_PERF_SEL_DUMMY_LAST: Reserved. `ťť PERF_MODEƥťNPERFMON_COUNTER_MODE_ACCUM: Accumulate increment values over enabled cycles. hǥƥ`PERFMON_COUNTER_MODE_ACTIVE_CYCLES: Count the number of cycles with a nonzero increment value. Hȥǥ[PERFMON_COUNTER_MODE_MAX: Store the largest increment value received over cycles counted. (ɥȥYPERFMON_COUNTER_MODE_DIRTY: Record whether a nonzero increment value was ever received. ɥpɥFPERFMON_COUNTER_MODE_SAMPLE: Just record the latest increment vlaue. ʥ@ʥbPERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT: Count the cycles since a nonzero increment value. (˥^PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT: Count the cycles since a zero increment value. pBƤ""hƤTCC_PERFCOUNTER2_SELECTAƤǤ PERF_SELǤPǤ9TCC_PERF_SEL_NONE: don't count anything Deterministic. xȤȤ(TCC_PERF_SEL_CYCLES: Number of cycles. @ɤȤ@TCC_PERF_SEL_BUSY: Number of cycles we have a request pending. ʤɤRTCC_PERF_SEL_BUSY_TC_TF: Number of cycles we have an TC texture request pending. ʤ`ʤQTCC_PERF_SEL_BUSY_TC_VF: Number of cycles we have an TC vertex request pending. ˤ8ˤJTCC_PERF_SEL_BUSY_VC_VF: Number of cycles we have an VC request pending. p̤̤(TCC_PERF_SEL_REQS: Number of requests. 8̤ͤBTCC_PERF_SEL_REQS_HIT: Number of requests that hit in the cache. ΤͤDTCC_PERF_SEL_REQS_MISS: Number of requests that miss in the cache. ΤHΤ :TCC_PERF_SEL_REQS_UNCACHED: Number of uncached requests. ϤϤ >TCC_PERF_SEL_REQS_CLIENT_0: Number of requests for client 0. PФϤ >TCC_PERF_SEL_REQS_CLIENT_1: Number of requests for client 1. ѤФ >TCC_PERF_SEL_REQS_CLIENT_2: Number of requests for client 2. Ѥ`Ѥ >TCC_PERF_SEL_REQS_CLIENT_3: Number of requests for client 3. Ҥ(Ҥ>TCC_PERF_SEL_REQS_CLIENT_4: Number of requests for client 4. pӤҤ>TCC_PERF_SEL_REQS_CLIENT_5: Number of requests for client 5. 8ԤӤ>TCC_PERF_SEL_REQS_CLIENT_6: Number of requests for client 6. դԤ>TCC_PERF_SEL_REQS_CLIENT_7: Number of requests for client 7. դHդ>TCC_PERF_SEL_REQS_CLIENT_8: Number of requests for client 8. ֤֤>TCC_PERF_SEL_REQS_CLIENT_9: Number of requests for client 9. Xפ֤@TCC_PERF_SEL_REQS_CLIENT_10: Number of requests for client 10. ؤפ@TCC_PERF_SEL_REQS_CLIENT_11: Number of requests for client 11. ؤhؤ@TCC_PERF_SEL_REQS_CLIENT_12: Number of requests for client 12. ٤0٤@TCC_PERF_SEL_REQS_CLIENT_13: Number of requests for client 13. xڤ٤@TCC_PERF_SEL_REQS_CLIENT_14: Number of requests for client 14. @ۤڤ@TCC_PERF_SEL_REQS_CLIENT_15: Number of requests for client 15. ܤۤ@TCC_PERF_SEL_REQS_CLIENT_16: Number of requests for client 16. ܤPܤ@TCC_PERF_SEL_REQS_CLIENT_17: Number of requests for client 17. ݤݤ@TCC_PERF_SEL_REQS_CLIENT_18: Number of requests for client 18. `ޤݤ@TCC_PERF_SEL_REQS_CLIENT_19: Number of requests for client 19. (ߤޤ@TCC_PERF_SEL_REQS_CLIENT_20: Number of requests for client 20. ߤpߤ@TCC_PERF_SEL_REQS_CLIENT_21: Number of requests for client 21. 8 @TCC_PERF_SEL_REQS_CLIENT_22: Number of requests for client 22. !@TCC_PERF_SEL_REQS_CLIENT_23: Number of requests for client 23. H"CTCC_PERF_SEL_REQS_TC_TF: Number of requests from TCs for texture. (#\TCC_PERF_SEL_REQS_TC_TF_HIT: Number of requests from TC for texture that hit in the cache. p$^TCC_PERF_SEL_REQS_TC_TF_MISS: Number of requests from TC for texture that miss in the cache. X%BTCC_PERF_SEL_REQS_TC_VF: Number of requests from TCs for vertex. &HTCC_PERF_SEL_REQS_TC_VF_HIT: Number of requests that hit in the cache. x'JTCC_PERF_SEL_REQS_TC_VF_MISS: Number of requests that miss in the cache. 8(6TCC_PERF_SEL_REQS_VC_VF: Number of requests from VC. )PTCC_PERF_SEL_REQS_VC_VF_HIT: Number of requests from VC that hit in the cache. X*RTCC_PERF_SEL_REQS_VC_VF_MISS: Number of requests from VC that miss in the cache. 0+FTCC_PERF_SEL_REQ_LEVEL_TC_TF: Number of pending TC texture requests. ,ETCC_PERF_SEL_REQ_LEVEL_TC_VF: Number of pending TC vertex requests. P->TCC_PERF_SEL_REQ_LEVEL_VC_VF: Number of pending VC requests. .KTCC_PERF_SEL_REQ_LEVEL_CLIENT_0: Number of requests pending for client 0. h/KTCC_PERF_SEL_REQ_LEVEL_CLIENT_1: Number of requests pending for client 1. 80KTCC_PERF_SEL_REQ_LEVEL_CLIENT_2: Number of requests pending for client 2. 1KTCC_PERF_SEL_REQ_LEVEL_CLIENT_3: Number of requests pending for client 3. `2KTCC_PERF_SEL_REQ_LEVEL_CLIENT_4: Number of requests pending for client 4. 03KTCC_PERF_SEL_REQ_LEVEL_CLIENT_5: Number of requests pending for client 5. x4KTCC_PERF_SEL_REQ_LEVEL_CLIENT_6: Number of requests pending for client 6. H5KTCC_PERF_SEL_REQ_LEVEL_CLIENT_7: Number of requests pending for client 7. 6KTCC_PERF_SEL_REQ_LEVEL_CLIENT_8: Number of requests pending for client 8. p7KTCC_PERF_SEL_REQ_LEVEL_CLIENT_9: Number of requests pending for client 9. H8MTCC_PERF_SEL_REQ_LEVEL_CLIENT_10: Number of requests pending for client 10. 9MTCC_PERF_SEL_REQ_LEVEL_CLIENT_11: Number of requests pending for client 11. h:MTCC_PERF_SEL_REQ_LEVEL_CLIENT_12: Number of requests pending for client 12. @;MTCC_PERF_SEL_REQ_LEVEL_CLIENT_13: Number of requests pending for client 13. <MTCC_PERF_SEL_REQ_LEVEL_CLIENT_14: Number of requests pending for client 14. =MTCC_PERF_SEL_REQ_LEVEL_CLIENT_15: Number of requests pending for client 15. X>MTCC_PERF_SEL_REQ_LEVEL_CLIENT_16: Number of requests pending for client 16. 0?MTCC_PERF_SEL_REQ_LEVEL_CLIENT_17: Number of requests pending for client 17. x@MTCC_PERF_SEL_REQ_LEVEL_CLIENT_18: Number of requests pending for client 18. PAMTCC_PERF_SEL_REQ_LEVEL_CLIENT_19: Number of requests pending for client 19. (BMTCC_PERF_SEL_REQ_LEVEL_CLIENT_20: Number of requests pending for client 20. CMTCC_PERF_SEL_REQ_LEVEL_CLIENT_21: Number of requests pending for client 21. hDMTCC_PERF_SEL_REQ_LEVEL_CLIENT_22: Number of requests pending for client 22. @EMTCC_PERF_SEL_REQ_LEVEL_CLIENT_23: Number of requests pending for client 23. F.TCC_PERF_SEL_MC_REQS: Number of MC requests. @GCTCC_PERF_SEL_MC_REQS_TC_TF: Number of MC requests for TC texture. HBTCC_PERF_SEL_MC_REQS_TC_VF: Number of MC requests for TC vertex. HI;TCC_PERF_SEL_MC_REQS_VC_VF: Number of MC requests for VC. J7TCC_PERF_SEL_MC_FULL: Number of cycles the MC is full PK;TCC_PERF_SEL_MC_REQ_LEVEL: Number of MC requests pending. LPTCC_PERF_SEL_MC_REQ_LEVEL_TC_TF: Number of MC requests pending for TC texture. xMOTCC_PERF_SEL_MC_REQ_LEVEL_TC_VF: Number of MC requests pending for TC vertex. HNHTCC_PERF_SEL_MC_REQ_LEVEL_VC_VF: Number of MC requests pending for VC. O=TCC_PERF_SEL_MC_CREDIT_LEVEL: Number of MC credits pending. XPQTCC_PERF_SEL_CG_CORE_ENABLED: Number of cycles the shader core clock is enabled 0QLTCC_PERF_SEL_CG_BLOCK_ENABLED: Number of cycles the block clock is enabled RATCC_PERF_SEL_LF_FULL: Number of cycles the latency fifo is full P SKTCC_PERF_SEL_LF_FULL_VC: Number of cycles the vertex latency fifo is full TLTCC_PERF_SEL_LF_FULL_TC: Number of cycles the texture latency fifo is full  h UiTCC_PERF_SEL_LF_FULL_CLIENT_VC: Number of cycles the latency fifo is full for a dedicated vertex client X V_TCC_PERF_SEL_LF_FULL_CLIENT_TC: Number of cycles the latency fifo is full for a non-VC client @ W@TCC_PERF_SEL_LF_LEVEL: Number of requests in the latency fifo. XITCC_PERF_SEL_LF_LEVEL_VC_VF: Number of VC requests in the latency fifo. xY`TCC_PERF_SEL_LF_LEVEL_TC_VF: Number of TC vertex requests in the latency fifo for vertex data. `ZbTCC_PERF_SEL_LF_LEVEL_TC_TF: Number of TC texture requests in the latency fifo for texture data. 0[KTCC_PERF_SEL_LF_BLOCK_LEVEL: Number of blocks in use by the latency fifo. (x\nTCC_PERF_SEL_LF_BLOCK_LEVEL_VC: Number of blocks in use by the dedicated vertex clients in the latency fifo. p]eTCC_PERF_SEL_LF_BLOCK_LEVEL_TC: Number of blocks in use by the texture clients in the latency fifo. `^@TCC_PERF_SEL_OF_LEVEL: Number of requests in the output fifos. (_ITCC_PERF_SEL_OF_LEVEL_VC_VF: Number of VC requests in the output fifos. `PTCC_PERF_SEL_OF_LEVEL_TC_VF: Number of TC vertex requests in the output fifos. `aQTCC_PERF_SEL_OF_LEVEL_TC_TF: Number of TC texture requests in the output fifos. 0bJTCC_PERF_SEL_TCA_LEVEL: Number of requests ready for output arbitration. xcSTCC_PERF_SEL_TCA_LEVEL_VC_VF: Number of VC requests ready for output arbitration. PdZTCC_PERF_SEL_TCA_LEVEL_TC_VF: Number of TC vertex requests ready for output arbitration. 0e[TCC_PERF_SEL_TCA_LEVEL_TC_TF: Number of TC texture requests ready for output arbitration. fdTCC_PERF_SEL_TCA_LEVEL_CLIENT_0: Number of requests ready for arbitration in the tca for client 0. gdTCC_PERF_SEL_TCA_LEVEL_CLIENT_1: Number of requests ready for arbitration in the tca for client 1. hdTCC_PERF_SEL_TCA_LEVEL_CLIENT_2: Number of requests ready for arbitration in the tca for client 2. hidTCC_PERF_SEL_TCA_LEVEL_CLIENT_3: Number of requests ready for arbitration in the tca for client 3. PjdTCC_PERF_SEL_TCA_LEVEL_CLIENT_4: Number of requests ready for arbitration in the tca for client 4. 8kdTCC_PERF_SEL_TCA_LEVEL_CLIENT_5: Number of requests ready for arbitration in the tca for client 5. ldTCC_PERF_SEL_TCA_LEVEL_CLIENT_6: Number of requests ready for arbitration in the tca for client 6. !h mdTCC_PERF_SEL_TCA_LEVEL_CLIENT_7: Number of requests ready for arbitration in the tca for client 7. !P!ndTCC_PERF_SEL_TCA_LEVEL_CLIENT_8: Number of requests ready for arbitration in the tca for client 8. "8"odTCC_PERF_SEL_TCA_LEVEL_CLIENT_9: Number of requests ready for arbitration in the tca for client 9. # #pfTCC_PERF_SEL_TCA_LEVEL_CLIENT_10: Number of requests ready for arbitration in the tca for client 10. $$qfTCC_PERF_SEL_TCA_LEVEL_CLIENT_11: Number of requests ready for arbitration in the tca for client 11. %%rfTCC_PERF_SEL_TCA_LEVEL_CLIENT_12: Number of requests ready for arbitration in the tca for client 12. &%sfTCC_PERF_SEL_TCA_LEVEL_CLIENT_13: Number of requests ready for arbitration in the tca for client 13. '&tfTCC_PERF_SEL_TCA_LEVEL_CLIENT_14: Number of requests ready for arbitration in the tca for client 14. x('ufTCC_PERF_SEL_TCA_LEVEL_CLIENT_15: Number of requests ready for arbitration in the tca for client 15. h)(vfTCC_PERF_SEL_TCA_LEVEL_CLIENT_16: Number of requests ready for arbitration in the tca for client 16. X*)wfTCC_PERF_SEL_TCA_LEVEL_CLIENT_17: Number of requests ready for arbitration in the tca for client 17. H+*xfTCC_PERF_SEL_TCA_LEVEL_CLIENT_18: Number of requests ready for arbitration in the tca for client 18. 8,+yfTCC_PERF_SEL_TCA_LEVEL_CLIENT_19: Number of requests ready for arbitration in the tca for client 19. (-,zfTCC_PERF_SEL_TCA_LEVEL_CLIENT_20: Number of requests ready for arbitration in the tca for client 20. .p-{fTCC_PERF_SEL_TCA_LEVEL_CLIENT_21: Number of requests ready for arbitration in the tca for client 21. /`.|fTCC_PERF_SEL_TCA_LEVEL_CLIENT_22: Number of requests ready for arbitration in the tca for client 22. /P/}fTCC_PERF_SEL_TCA_LEVEL_CLIENT_23: Number of requests ready for arbitration in the tca for client 23. 0@0~PTCC_PERF_SEL_CLIENTS_FULL: Number of clients stalled due to a full return fifo 11VTCC_PERF_SEL_CLIENTS_FULL_VC: Number of VC clients stalled due to a full return fifo 21VTCC_PERF_SEL_CLIENTS_FULL_TC: Number of TC clients stalled due to a full return fifo H32/TCC_PERF_SEL_ARB_BURST: Number of bursts sent 43BTCC_PERF_SEL_ARB_BURST_VC: Number of bursts sent from VC clients 4X4BTCC_PERF_SEL_ARB_BURST_TC: Number of bursts sent from TC clients 5 5TCC_PERF_SEL_CACHE_TAG_STALL_TC_TF: Number of cycles the cache is stalled because we can't find a tag we can use for a TC texture request. 606jTCC_PERF_SEL_CACHE_TAG_RENAME_TC_TF: Number of tagset name swaps that occurred for a TC texture request. 7 7TCC_PERF_SEL_CACHE_TAG_STALL_TC_VF: Number of cycles the cache is stalled because we can't find a tag we can use for a TC vertex request. 808iTCC_PERF_SEL_CACHE_TAG_RENAME_TC_VF: Number of tagset name swaps that occurred for a TC vertex request. 9 9TCC_PERF_SEL_CACHE_TAG_STALL_VC_VF: Number of cycles the cache is stalled because we can't find a tag we can use for a VC vertex request. :0:iTCC_PERF_SEL_CACHE_TAG_RENAME_VC_VF: Number of tagset name swaps that occurred for a VC vertex request. ; ;YTCC_PERF_SEL_CACHE_STALL: Number of cycles that a cache allocation request was stalled. p<<1TCC_PERF_SEL_DEALLOC: Number of cache deallocs. 8=<CTCC_PERF_SEL_DEALLOC_ALL: Number of cache deallocs of all caches. >=MTCC_PERF_SEL_DEALLOC_LINES: Number of cache lines specifically deallocated. >X>OTCC_PERF_SEL_DEALLOC_CYCLES: Number of cycles spent deallocating cache lines. ?0?>TCC_PERF_SEL_REG_WRITES: Number of indirect register writes. p@?<TCC_PERF_SEL_REG_READS: Number of indirect register reads. HA@STCC_PERF_SEL_DEBUG_BUS: Number of debug events based on TCC_DEBUG_INDEX register. A$TCC_PERF_SEL_DUMMY_LAST: Reserved. HBB PERF_MODEhCBNPERFMON_COUNTER_MODE_ACCUM: Accumulate increment values over enabled cycles. PDC`PERFMON_COUNTER_MODE_ACTIVE_CYCLES: Count the number of cycles with a nonzero increment value. 0ED[PERFMON_COUNTER_MODE_MAX: Store the largest increment value received over cycles counted. FxEYPERFMON_COUNTER_MODE_DIRTY: Record whether a nonzero increment value was ever received. FXFFPERFMON_COUNTER_MODE_SAMPLE: Just record the latest increment vlaue. G(GbPERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT: Count the cycles since a nonzero increment value. H^PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT: Count the cycles since a zero increment value. PB""@CTCC_PERFCOUNTER1_SELECTؾCC PERF_SELD(D9TCC_PERF_SEL_NONE: don't count anything Deterministic. PED(TCC_PERF_SEL_CYCLES: Number of cycles. FE@TCC_PERF_SEL_BUSY: Number of cycles we have a request pending. F`FRTCC_PERF_SEL_BUSY_TC_TF: Number of cycles we have an TC texture request pending. G8GQTCC_PERF_SEL_BUSY_TC_VF: Number of cycles we have an TC vertex request pending. HHJTCC_PERF_SEL_BUSY_VC_VF: Number of cycles we have an VC request pending. HIH(TCC_PERF_SEL_REQS: Number of requests. JIBTCC_PERF_SEL_REQS_HIT: Number of requests that hit in the cache. JXJDTCC_PERF_SEL_REQS_MISS: Number of requests that miss in the cache. K K :TCC_PERF_SEL_REQS_UNCACHED: Number of uncached requests. `LK >TCC_PERF_SEL_REQS_CLIENT_0: Number of requests for client 0. (ML >TCC_PERF_SEL_REQS_CLIENT_1: Number of requests for client 1. MpM >TCC_PERF_SEL_REQS_CLIENT_2: Number of requests for client 2. N8N >TCC_PERF_SEL_REQS_CLIENT_3: Number of requests for client 3. OO>TCC_PERF_SEL_REQS_CLIENT_4: Number of requests for client 4. HPO>TCC_PERF_SEL_REQS_CLIENT_5: Number of requests for client 5. QP>TCC_PERF_SEL_REQS_CLIENT_6: Number of requests for client 6. QXQ>TCC_PERF_SEL_REQS_CLIENT_7: Number of requests for client 7. R R>TCC_PERF_SEL_REQS_CLIENT_8: Number of requests for client 8. hSR>TCC_PERF_SEL_REQS_CLIENT_9: Number of requests for client 9. 0TS@TCC_PERF_SEL_REQS_CLIENT_10: Number of requests for client 10. TxT@TCC_PERF_SEL_REQS_CLIENT_11: Number of requests for client 11. U@U@TCC_PERF_SEL_REQS_CLIENT_12: Number of requests for client 12. VV@TCC_PERF_SEL_REQS_CLIENT_13: Number of requests for client 13. PWV@TCC_PERF_SEL_REQS_CLIENT_14: Number of requests for client 14. XW@TCC_PERF_SEL_REQS_CLIENT_15: Number of requests for client 15. X`X@TCC_PERF_SEL_REQS_CLIENT_16: Number of requests for client 16. Y(Y@TCC_PERF_SEL_REQS_CLIENT_17: Number of requests for client 17. pZY@TCC_PERF_SEL_REQS_CLIENT_18: Number of requests for client 18. 8[Z@TCC_PERF_SEL_REQS_CLIENT_19: Number of requests for client 19. \[@TCC_PERF_SEL_REQS_CLIENT_20: Number of requests for client 20. \H\@TCC_PERF_SEL_REQS_CLIENT_21: Number of requests for client 21. ]] @TCC_PERF_SEL_REQS_CLIENT_22: Number of requests for client 22. X^]!@TCC_PERF_SEL_REQS_CLIENT_23: Number of requests for client 23. _^"CTCC_PERF_SEL_REQS_TC_TF: Number of requests from TCs for texture. `h_#\TCC_PERF_SEL_REQS_TC_TF_HIT: Number of requests from TC for texture that hit in the cache. `P`$^TCC_PERF_SEL_REQS_TC_TF_MISS: Number of requests from TC for texture that miss in the cache. a8a%BTCC_PERF_SEL_REQS_TC_VF: Number of requests from TCs for vertex. bb&HTCC_PERF_SEL_REQS_TC_VF_HIT: Number of requests that hit in the cache. Xcb'JTCC_PERF_SEL_REQS_TC_VF_MISS: Number of requests that miss in the cache. dc(6TCC_PERF_SEL_REQS_VC_VF: Number of requests from VC. d`d)PTCC_PERF_SEL_REQS_VC_VF_HIT: Number of requests from VC that hit in the cache. e8e*RTCC_PERF_SEL_REQS_VC_VF_MISS: Number of requests from VC that miss in the cache. ff+FTCC_PERF_SEL_REQ_LEVEL_TC_TF: Number of pending TC texture requests. hgf,ETCC_PERF_SEL_REQ_LEVEL_TC_VF: Number of pending TC vertex requests. 0hg->TCC_PERF_SEL_REQ_LEVEL_VC_VF: Number of pending VC requests. ixh.KTCC_PERF_SEL_REQ_LEVEL_CLIENT_0: Number of requests pending for client 0. iHi/KTCC_PERF_SEL_REQ_LEVEL_CLIENT_1: Number of requests pending for client 1. jj0KTCC_PERF_SEL_REQ_LEVEL_CLIENT_2: Number of requests pending for client 2. pkj1KTCC_PERF_SEL_REQ_LEVEL_CLIENT_3: Number of requests pending for client 3. @lk2KTCC_PERF_SEL_REQ_LEVEL_CLIENT_4: Number of requests pending for client 4. ml3KTCC_PERF_SEL_REQ_LEVEL_CLIENT_5: Number of requests pending for client 5. mXm4KTCC_PERF_SEL_REQ_LEVEL_CLIENT_6: Number of requests pending for client 6. n(n5KTCC_PERF_SEL_REQ_LEVEL_CLIENT_7: Number of requests pending for client 7. on6KTCC_PERF_SEL_REQ_LEVEL_CLIENT_8: Number of requests pending for client 8. Ppo7KTCC_PERF_SEL_REQ_LEVEL_CLIENT_9: Number of requests pending for client 9. (qp8MTCC_PERF_SEL_REQ_LEVEL_CLIENT_10: Number of requests pending for client 10. rpq9MTCC_PERF_SEL_REQ_LEVEL_CLIENT_11: Number of requests pending for client 11. rHr:MTCC_PERF_SEL_REQ_LEVEL_CLIENT_12: Number of requests pending for client 12. s s;MTCC_PERF_SEL_REQ_LEVEL_CLIENT_13: Number of requests pending for client 13. ts<MTCC_PERF_SEL_REQ_LEVEL_CLIENT_14: Number of requests pending for client 14. `ut=MTCC_PERF_SEL_REQ_LEVEL_CLIENT_15: Number of requests pending for client 15. 8vu>MTCC_PERF_SEL_REQ_LEVEL_CLIENT_16: Number of requests pending for client 16. wv?MTCC_PERF_SEL_REQ_LEVEL_CLIENT_17: Number of requests pending for client 17. wXw@MTCC_PERF_SEL_REQ_LEVEL_CLIENT_18: Number of requests pending for client 18. x0xAMTCC_PERF_SEL_REQ_LEVEL_CLIENT_19: Number of requests pending for client 19. yyBMTCC_PERF_SEL_REQ_LEVEL_CLIENT_20: Number of requests pending for client 20. pzyCMTCC_PERF_SEL_REQ_LEVEL_CLIENT_21: Number of requests pending for client 21. H{zDMTCC_PERF_SEL_REQ_LEVEL_CLIENT_22: Number of requests pending for client 22. |{EMTCC_PERF_SEL_REQ_LEVEL_CLIENT_23: Number of requests pending for client 23. |h|F.TCC_PERF_SEL_MC_REQS: Number of MC requests. } }GCTCC_PERF_SEL_MC_REQS_TC_TF: Number of MC requests for TC texture. h~}HBTCC_PERF_SEL_MC_REQS_TC_VF: Number of MC requests for TC vertex. (~I;TCC_PERF_SEL_MC_REQS_VC_VF: Number of MC requests for VC. pJ7TCC_PERF_SEL_MC_FULL: Number of cycles the MC is full 0K;TCC_PERF_SEL_MC_REQ_LEVEL: Number of MC requests pending. LPTCC_PERF_SEL_MC_REQ_LEVEL_TC_TF: Number of MC requests pending for TC texture. XȁMOTCC_PERF_SEL_MC_REQ_LEVEL_TC_VF: Number of MC requests pending for TC vertex. (NHTCC_PERF_SEL_MC_REQ_LEVEL_VC_VF: Number of MC requests pending for VC. pO=TCC_PERF_SEL_MC_CREDIT_LEVEL: Number of MC credits pending. Ȅ8PQTCC_PERF_SEL_CG_CORE_ENABLED: Number of cycles the shader core clock is enabled QLTCC_PERF_SEL_CG_BLOCK_ENABLED: Number of cycles the block clock is enabled `RATCC_PERF_SEL_LF_FULL: Number of cycles the latency fifo is full 0SKTCC_PERF_SEL_LF_FULL_VC: Number of cycles the vertex latency fifo is full xTLTCC_PERF_SEL_LF_FULL_TC: Number of cycles the texture latency fifo is full HUiTCC_PERF_SEL_LF_FULL_CLIENT_VC: Number of cycles the latency fifo is full for a dedicated vertex client ؉8V_TCC_PERF_SEL_LF_FULL_CLIENT_TC: Number of cycles the latency fifo is full for a non-VC client W@TCC_PERF_SEL_LF_LEVEL: Number of requests in the latency fifo. p芤XITCC_PERF_SEL_LF_LEVEL_VC_VF: Number of VC requests in the latency fifo. XY`TCC_PERF_SEL_LF_LEVEL_TC_VF: Number of TC vertex requests in the latency fifo for vertex data. @ZbTCC_PERF_SEL_LF_LEVEL_TC_TF: Number of TC texture requests in the latency fifo for texture data. [KTCC_PERF_SEL_LF_BLOCK_LEVEL: Number of blocks in use by the latency fifo. X\nTCC_PERF_SEL_LF_BLOCK_LEVEL_VC: Number of blocks in use by the dedicated vertex clients in the latency fifo. P]eTCC_PERF_SEL_LF_BLOCK_LEVEL_TC: Number of blocks in use by the texture clients in the latency fifo. @^@TCC_PERF_SEL_OF_LEVEL: Number of requests in the output fifos. _ITCC_PERF_SEL_OF_LEVEL_VC_VF: Number of VC requests in the output fifos. hؑ`PTCC_PERF_SEL_OF_LEVEL_TC_VF: Number of TC vertex requests in the output fifos. @aQTCC_PERF_SEL_OF_LEVEL_TC_TF: Number of TC texture requests in the output fifos. bJTCC_PERF_SEL_TCA_LEVEL: Number of requests ready for output arbitration. 蔤XcSTCC_PERF_SEL_TCA_LEVEL_VC_VF: Number of VC requests ready for output arbitration. ȕ0dZTCC_PERF_SEL_TCA_LEVEL_TC_VF: Number of TC vertex requests ready for output arbitration. e[TCC_PERF_SEL_TCA_LEVEL_TC_TF: Number of TC texture requests ready for output arbitration. fdTCC_PERF_SEL_TCA_LEVEL_CLIENT_0: Number of requests ready for arbitration in the tca for client 0. xؗgdTCC_PERF_SEL_TCA_LEVEL_CLIENT_1: Number of requests ready for arbitration in the tca for client 1. `hdTCC_PERF_SEL_TCA_LEVEL_CLIENT_2: Number of requests ready for arbitration in the tca for client 2. HidTCC_PERF_SEL_TCA_LEVEL_CLIENT_3: Number of requests ready for arbitration in the tca for client 3. 0jdTCC_PERF_SEL_TCA_LEVEL_CLIENT_4: Number of requests ready for arbitration in the tca for client 4. xkdTCC_PERF_SEL_TCA_LEVEL_CLIENT_5: Number of requests ready for arbitration in the tca for client 5. `ldTCC_PERF_SEL_TCA_LEVEL_CLIENT_6: Number of requests ready for arbitration in the tca for client 6. 蝤HmdTCC_PERF_SEL_TCA_LEVEL_CLIENT_7: Number of requests ready for arbitration in the tca for client 7. О0ndTCC_PERF_SEL_TCA_LEVEL_CLIENT_8: Number of requests ready for arbitration in the tca for client 8. odTCC_PERF_SEL_TCA_LEVEL_CLIENT_9: Number of requests ready for arbitration in the tca for client 9. pfTCC_PERF_SEL_TCA_LEVEL_CLIENT_10: Number of requests ready for arbitration in the tca for client 10. qfTCC_PERF_SEL_TCA_LEVEL_CLIENT_11: Number of requests ready for arbitration in the tca for client 11. 衤rfTCC_PERF_SEL_TCA_LEVEL_CLIENT_12: Number of requests ready for arbitration in the tca for client 12. آsfTCC_PERF_SEL_TCA_LEVEL_CLIENT_13: Number of requests ready for arbitration in the tca for client 13. pȣtfTCC_PERF_SEL_TCA_LEVEL_CLIENT_14: Number of requests ready for arbitration in the tca for client 14. `ufTCC_PERF_SEL_TCA_LEVEL_CLIENT_15: Number of requests ready for arbitration in the tca for client 15. PvfTCC_PERF_SEL_TCA_LEVEL_CLIENT_16: Number of requests ready for arbitration in the tca for client 16. @wfTCC_PERF_SEL_TCA_LEVEL_CLIENT_17: Number of requests ready for arbitration in the tca for client 17. 0xfTCC_PERF_SEL_TCA_LEVEL_CLIENT_18: Number of requests ready for arbitration in the tca for client 18. xyfTCC_PERF_SEL_TCA_LEVEL_CLIENT_19: Number of requests ready for arbitration in the tca for client 19. hzfTCC_PERF_SEL_TCA_LEVEL_CLIENT_20: Number of requests ready for arbitration in the tca for client 20. X{fTCC_PERF_SEL_TCA_LEVEL_CLIENT_21: Number of requests ready for arbitration in the tca for client 21. H|fTCC_PERF_SEL_TCA_LEVEL_CLIENT_22: Number of requests ready for arbitration in the tca for client 22. ତ8}fTCC_PERF_SEL_TCA_LEVEL_CLIENT_23: Number of requests ready for arbitration in the tca for client 23. (~PTCC_PERF_SEL_CLIENTS_FULL: Number of clients stalled due to a full return fifo VTCC_PERF_SEL_CLIENTS_FULL_VC: Number of VC clients stalled due to a full return fifo xதVTCC_PERF_SEL_CLIENTS_FULL_TC: Number of TC clients stalled due to a full return fifo 0/TCC_PERF_SEL_ARB_BURST: Number of bursts sent xBTCC_PERF_SEL_ARB_BURST_VC: Number of bursts sent from VC clients @BTCC_PERF_SEL_ARB_BURST_TC: Number of bursts sent from TC clients вTCC_PERF_SEL_CACHE_TAG_STALL_TC_TF: Number of cycles the cache is stalled because we can't find a tag we can use for a TC texture request. jTCC_PERF_SEL_CACHE_TAG_RENAME_TC_TF: Number of tagset name swaps that occurred for a TC texture request. дTCC_PERF_SEL_CACHE_TAG_STALL_TC_VF: Number of cycles the cache is stalled because we can't find a tag we can use for a TC vertex request. iTCC_PERF_SEL_CACHE_TAG_RENAME_TC_VF: Number of tagset name swaps that occurred for a TC vertex request. жTCC_PERF_SEL_CACHE_TAG_STALL_VC_VF: Number of cycles the cache is stalled because we can't find a tag we can use for a VC vertex request. iTCC_PERF_SEL_CACHE_TAG_RENAME_VC_VF: Number of tagset name swaps that occurred for a VC vertex request. YTCC_PERF_SEL_CACHE_STALL: Number of cycles that a cache allocation request was stalled. X踤1TCC_PERF_SEL_DEALLOC: Number of cache deallocs. CTCC_PERF_SEL_DEALLOC_ALL: Number of cache deallocs of all caches. hMTCC_PERF_SEL_DEALLOC_LINES: Number of cache lines specifically deallocated. л@OTCC_PERF_SEL_DEALLOC_CYCLES: Number of cycles spent deallocating cache lines. >TCC_PERF_SEL_REG_WRITES: Number of indirect register writes. X༤<TCC_PERF_SEL_REG_READS: Number of indirect register reads. 0STCC_PERF_SEL_DEBUG_BUS: Number of debug events based on TCC_DEBUG_INDEX register. x$TCC_PERF_SEL_DUMMY_LAST: Reserved. 0x PERF_MODEPNPERFMON_COUNTER_MODE_ACCUM: Accumulate increment values over enabled cycles. 8`PERFMON_COUNTER_MODE_ACTIVE_CYCLES: Count the number of cycles with a nonzero increment value. ¤[PERFMON_COUNTER_MODE_MAX: Store the largest increment value received over cycles counted. ¤`¤YPERFMON_COUNTER_MODE_DIRTY: Record whether a nonzero increment value was ever received. ä@äFPERFMON_COUNTER_MODE_SAMPLE: Just record the latest increment vlaue. ĤĤbPERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT: Count the cycles since a nonzero increment value. Ĥ^PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT: Count the cycles since a zero increment value. 轣ȿ"" TCC_PERFCOUNTER0_SELECT;x PERF_SEL9TCC_PERF_SEL_NONE: don't count anything Deterministic. 0£(TCC_PERF_SEL_CYCLES: Number of cycles. £x£@TCC_PERF_SEL_BUSY: Number of cycles we have a request pending. ã@ãRTCC_PERF_SEL_BUSY_TC_TF: Number of cycles we have an TC texture request pending. ģģQTCC_PERF_SEL_BUSY_TC_VF: Number of cycles we have an TC vertex request pending. xţģJTCC_PERF_SEL_BUSY_VC_VF: Number of cycles we have an VC request pending. (ƣţ(TCC_PERF_SEL_REQS: Number of requests. ƣpƣBTCC_PERF_SEL_REQS_HIT: Number of requests that hit in the cache. ǣ8ǣDTCC_PERF_SEL_REQS_MISS: Number of requests that miss in the cache. xȣȣ :TCC_PERF_SEL_REQS_UNCACHED: Number of uncached requests. @ɣȣ >TCC_PERF_SEL_REQS_CLIENT_0: Number of requests for client 0. ʣɣ >TCC_PERF_SEL_REQS_CLIENT_1: Number of requests for client 1. ʣPʣ >TCC_PERF_SEL_REQS_CLIENT_2: Number of requests for client 2. ˣˣ >TCC_PERF_SEL_REQS_CLIENT_3: Number of requests for client 3. `̣ˣ>TCC_PERF_SEL_REQS_CLIENT_4: Number of requests for client 4. (̣ͣ>TCC_PERF_SEL_REQS_CLIENT_5: Number of requests for client 5. ͣpͣ>TCC_PERF_SEL_REQS_CLIENT_6: Number of requests for client 6. Σ8Σ>TCC_PERF_SEL_REQS_CLIENT_7: Number of requests for client 7. ϣϣ>TCC_PERF_SEL_REQS_CLIENT_8: Number of requests for client 8. HУϣ>TCC_PERF_SEL_REQS_CLIENT_9: Number of requests for client 9. ѣУ@TCC_PERF_SEL_REQS_CLIENT_10: Number of requests for client 10. ѣXѣ@TCC_PERF_SEL_REQS_CLIENT_11: Number of requests for client 11. ң ң@TCC_PERF_SEL_REQS_CLIENT_12: Number of requests for client 12. hӣң@TCC_PERF_SEL_REQS_CLIENT_13: Number of requests for client 13. 0ԣӣ@TCC_PERF_SEL_REQS_CLIENT_14: Number of requests for client 14. ԣxԣ@TCC_PERF_SEL_REQS_CLIENT_15: Number of requests for client 15. գ@գ@TCC_PERF_SEL_REQS_CLIENT_16: Number of requests for client 16. ֣֣@TCC_PERF_SEL_REQS_CLIENT_17: Number of requests for client 17. Pף֣@TCC_PERF_SEL_REQS_CLIENT_18: Number of requests for client 18. أף@TCC_PERF_SEL_REQS_CLIENT_19: Number of requests for client 19. أ`أ@TCC_PERF_SEL_REQS_CLIENT_20: Number of requests for client 20. ٣(٣@TCC_PERF_SEL_REQS_CLIENT_21: Number of requests for client 21. pڣ٣ @TCC_PERF_SEL_REQS_CLIENT_22: Number of requests for client 22. 8ۣڣ!@TCC_PERF_SEL_REQS_CLIENT_23: Number of requests for client 23. ܣۣ"CTCC_PERF_SEL_REQS_TC_TF: Number of requests from TCs for texture. ܣHܣ#\TCC_PERF_SEL_REQS_TC_TF_HIT: Number of requests from TC for texture that hit in the cache. ݣ(ݣ$^TCC_PERF_SEL_REQS_TC_TF_MISS: Number of requests from TC for texture that miss in the cache. ޣޣ%BTCC_PERF_SEL_REQS_TC_VF: Number of requests from TCs for vertex. `ߣޣ&HTCC_PERF_SEL_REQS_TC_VF_HIT: Number of requests that hit in the cache. 0ߣ'JTCC_PERF_SEL_REQS_TC_VF_MISS: Number of requests that miss in the cache. x(6TCC_PERF_SEL_REQS_VC_VF: Number of requests from VC. 8)PTCC_PERF_SEL_REQS_VC_VF_HIT: Number of requests from VC that hit in the cache. *RTCC_PERF_SEL_REQS_VC_VF_MISS: Number of requests from VC that miss in the cache. p+FTCC_PERF_SEL_REQ_LEVEL_TC_TF: Number of pending TC texture requests. @,ETCC_PERF_SEL_REQ_LEVEL_TC_VF: Number of pending TC vertex requests. ->TCC_PERF_SEL_REQ_LEVEL_VC_VF: Number of pending VC requests. P.KTCC_PERF_SEL_REQ_LEVEL_CLIENT_0: Number of requests pending for client 0. /KTCC_PERF_SEL_REQ_LEVEL_CLIENT_1: Number of requests pending for client 1. x0KTCC_PERF_SEL_REQ_LEVEL_CLIENT_2: Number of requests pending for client 2. H1KTCC_PERF_SEL_REQ_LEVEL_CLIENT_3: Number of requests pending for client 3. 2KTCC_PERF_SEL_REQ_LEVEL_CLIENT_4: Number of requests pending for client 4. `3KTCC_PERF_SEL_REQ_LEVEL_CLIENT_5: Number of requests pending for client 5. 04KTCC_PERF_SEL_REQ_LEVEL_CLIENT_6: Number of requests pending for client 6. 5KTCC_PERF_SEL_REQ_LEVEL_CLIENT_7: Number of requests pending for client 7. X6KTCC_PERF_SEL_REQ_LEVEL_CLIENT_8: Number of requests pending for client 8. (7KTCC_PERF_SEL_REQ_LEVEL_CLIENT_9: Number of requests pending for client 9. p8MTCC_PERF_SEL_REQ_LEVEL_CLIENT_10: Number of requests pending for client 10. H9MTCC_PERF_SEL_REQ_LEVEL_CLIENT_11: Number of requests pending for client 11. :MTCC_PERF_SEL_REQ_LEVEL_CLIENT_12: Number of requests pending for client 12. ;MTCC_PERF_SEL_REQ_LEVEL_CLIENT_13: Number of requests pending for client 13. `<MTCC_PERF_SEL_REQ_LEVEL_CLIENT_14: Number of requests pending for client 14. 8=MTCC_PERF_SEL_REQ_LEVEL_CLIENT_15: Number of requests pending for client 15. >MTCC_PERF_SEL_REQ_LEVEL_CLIENT_16: Number of requests pending for client 16. X?MTCC_PERF_SEL_REQ_LEVEL_CLIENT_17: Number of requests pending for client 17. 0@MTCC_PERF_SEL_REQ_LEVEL_CLIENT_18: Number of requests pending for client 18. AMTCC_PERF_SEL_REQ_LEVEL_CLIENT_19: Number of requests pending for client 19. pBMTCC_PERF_SEL_REQ_LEVEL_CLIENT_20: Number of requests pending for client 20. HCMTCC_PERF_SEL_REQ_LEVEL_CLIENT_21: Number of requests pending for client 21. DMTCC_PERF_SEL_REQ_LEVEL_CLIENT_22: Number of requests pending for client 22. hEMTCC_PERF_SEL_REQ_LEVEL_CLIENT_23: Number of requests pending for client 23. @F.TCC_PERF_SEL_MC_REQS: Number of MC requests. xGCTCC_PERF_SEL_MC_REQS_TC_TF: Number of MC requests for TC texture. @HBTCC_PERF_SEL_MC_REQS_TC_VF: Number of MC requests for TC vertex. I;TCC_PERF_SEL_MC_REQS_VC_VF: Number of MC requests for VC. HJ7TCC_PERF_SEL_MC_FULL: Number of cycles the MC is full K;TCC_PERF_SEL_MC_REQ_LEVEL: Number of MC requests pending. XLPTCC_PERF_SEL_MC_REQ_LEVEL_TC_TF: Number of MC requests pending for TC texture. 0MOTCC_PERF_SEL_MC_REQ_LEVEL_TC_VF: Number of MC requests pending for TC vertex. xNHTCC_PERF_SEL_MC_REQ_LEVEL_VC_VF: Number of MC requests pending for VC. PO=TCC_PERF_SEL_MC_CREDIT_LEVEL: Number of MC credits pending. PQTCC_PERF_SEL_CG_CORE_ENABLED: Number of cycles the shader core clock is enabled xQLTCC_PERF_SEL_CG_BLOCK_ENABLED: Number of cycles the block clock is enabled @RATCC_PERF_SEL_LF_FULL: Number of cycles the latency fifo is full SKTCC_PERF_SEL_LF_FULL_VC: Number of cycles the vertex latency fifo is full XTLTCC_PERF_SEL_LF_FULL_TC: Number of cycles the texture latency fifo is full (UiTCC_PERF_SEL_LF_FULL_CLIENT_VC: Number of cycles the latency fifo is full for a dedicated vertex client V_TCC_PERF_SEL_LF_FULL_CLIENT_TC: Number of cycles the latency fifo is full for a non-VC client W@TCC_PERF_SEL_LF_LEVEL: Number of requests in the latency fifo. PXITCC_PERF_SEL_LF_LEVEL_VC_VF: Number of VC requests in the latency fifo. 8 Y`TCC_PERF_SEL_LF_LEVEL_TC_VF: Number of TC vertex requests in the latency fifo for vertex data. ZbTCC_PERF_SEL_LF_LEVEL_TC_TF: Number of TC texture requests in the latency fifo for texture data. h [KTCC_PERF_SEL_LF_BLOCK_LEVEL: Number of blocks in use by the latency fifo. 8 \nTCC_PERF_SEL_LF_BLOCK_LEVEL_VC: Number of blocks in use by the dedicated vertex clients in the latency fifo. 0 ]eTCC_PERF_SEL_LF_BLOCK_LEVEL_TC: Number of blocks in use by the texture clients in the latency fifo. ^@TCC_PERF_SEL_OF_LEVEL: Number of requests in the output fifos. p _ITCC_PERF_SEL_OF_LEVEL_VC_VF: Number of VC requests in the output fifos. H`PTCC_PERF_SEL_OF_LEVEL_TC_VF: Number of TC vertex requests in the output fifos. aQTCC_PERF_SEL_OF_LEVEL_TC_TF: Number of TC texture requests in the output fifos. hbJTCC_PERF_SEL_TCA_LEVEL: Number of requests ready for output arbitration. 8cSTCC_PERF_SEL_TCA_LEVEL_VC_VF: Number of VC requests ready for output arbitration. dZTCC_PERF_SEL_TCA_LEVEL_TC_VF: Number of TC vertex requests ready for output arbitration. e[TCC_PERF_SEL_TCA_LEVEL_TC_TF: Number of TC texture requests ready for output arbitration. pfdTCC_PERF_SEL_TCA_LEVEL_CLIENT_0: Number of requests ready for arbitration in the tca for client 0. XgdTCC_PERF_SEL_TCA_LEVEL_CLIENT_1: Number of requests ready for arbitration in the tca for client 1. @hdTCC_PERF_SEL_TCA_LEVEL_CLIENT_2: Number of requests ready for arbitration in the tca for client 2. (idTCC_PERF_SEL_TCA_LEVEL_CLIENT_3: Number of requests ready for arbitration in the tca for client 3. pjdTCC_PERF_SEL_TCA_LEVEL_CLIENT_4: Number of requests ready for arbitration in the tca for client 4. XkdTCC_PERF_SEL_TCA_LEVEL_CLIENT_5: Number of requests ready for arbitration in the tca for client 5. @ldTCC_PERF_SEL_TCA_LEVEL_CLIENT_6: Number of requests ready for arbitration in the tca for client 6. (mdTCC_PERF_SEL_TCA_LEVEL_CLIENT_7: Number of requests ready for arbitration in the tca for client 7. ndTCC_PERF_SEL_TCA_LEVEL_CLIENT_8: Number of requests ready for arbitration in the tca for client 8. odTCC_PERF_SEL_TCA_LEVEL_CLIENT_9: Number of requests ready for arbitration in the tca for client 9. pfTCC_PERF_SEL_TCA_LEVEL_CLIENT_10: Number of requests ready for arbitration in the tca for client 10. xqfTCC_PERF_SEL_TCA_LEVEL_CLIENT_11: Number of requests ready for arbitration in the tca for client 11. hrfTCC_PERF_SEL_TCA_LEVEL_CLIENT_12: Number of requests ready for arbitration in the tca for client 12. X sfTCC_PERF_SEL_TCA_LEVEL_CLIENT_13: Number of requests ready for arbitration in the tca for client 13. H! tfTCC_PERF_SEL_TCA_LEVEL_CLIENT_14: Number of requests ready for arbitration in the tca for client 14. 8"!ufTCC_PERF_SEL_TCA_LEVEL_CLIENT_15: Number of requests ready for arbitration in the tca for client 15. (#"vfTCC_PERF_SEL_TCA_LEVEL_CLIENT_16: Number of requests ready for arbitration in the tca for client 16. $p#wfTCC_PERF_SEL_TCA_LEVEL_CLIENT_17: Number of requests ready for arbitration in the tca for client 17. %`$xfTCC_PERF_SEL_TCA_LEVEL_CLIENT_18: Number of requests ready for arbitration in the tca for client 18. %P%yfTCC_PERF_SEL_TCA_LEVEL_CLIENT_19: Number of requests ready for arbitration in the tca for client 19. &@&zfTCC_PERF_SEL_TCA_LEVEL_CLIENT_20: Number of requests ready for arbitration in the tca for client 20. '0'{fTCC_PERF_SEL_TCA_LEVEL_CLIENT_21: Number of requests ready for arbitration in the tca for client 21. ( (|fTCC_PERF_SEL_TCA_LEVEL_CLIENT_22: Number of requests ready for arbitration in the tca for client 22. ))}fTCC_PERF_SEL_TCA_LEVEL_CLIENT_23: Number of requests ready for arbitration in the tca for client 23. **~PTCC_PERF_SEL_CLIENTS_FULL: Number of clients stalled due to a full return fifo p+*VTCC_PERF_SEL_CLIENTS_FULL_VC: Number of VC clients stalled due to a full return fifo P,+VTCC_PERF_SEL_CLIENTS_FULL_TC: Number of TC clients stalled due to a full return fifo -,/TCC_PERF_SEL_ARB_BURST: Number of bursts sent -P-BTCC_PERF_SEL_ARB_BURST_VC: Number of bursts sent from VC clients ..BTCC_PERF_SEL_ARB_BURST_TC: Number of bursts sent from TC clients /.TCC_PERF_SEL_CACHE_TAG_STALL_TC_TF: Number of cycles the cache is stalled because we can't find a tag we can use for a TC texture request. 0/jTCC_PERF_SEL_CACHE_TAG_RENAME_TC_TF: Number of tagset name swaps that occurred for a TC texture request. 10TCC_PERF_SEL_CACHE_TAG_STALL_TC_VF: Number of cycles the cache is stalled because we can't find a tag we can use for a TC vertex request. 21iTCC_PERF_SEL_CACHE_TAG_RENAME_TC_VF: Number of tagset name swaps that occurred for a TC vertex request. 32TCC_PERF_SEL_CACHE_TAG_STALL_VC_VF: Number of cycles the cache is stalled because we can't find a tag we can use for a VC vertex request. 43iTCC_PERF_SEL_CACHE_TAG_RENAME_VC_VF: Number of tagset name swaps that occurred for a VC vertex request. x54YTCC_PERF_SEL_CACHE_STALL: Number of cycles that a cache allocation request was stalled. 0651TCC_PERF_SEL_DEALLOC: Number of cache deallocs. 6x6CTCC_PERF_SEL_DEALLOC_ALL: Number of cache deallocs of all caches. 7@7MTCC_PERF_SEL_DEALLOC_LINES: Number of cache lines specifically deallocated. 88OTCC_PERF_SEL_DEALLOC_CYCLES: Number of cycles spent deallocating cache lines. p98>TCC_PERF_SEL_REG_WRITES: Number of indirect register writes. 0:9<TCC_PERF_SEL_REG_READS: Number of indirect register reads. ;x:STCC_PERF_SEL_DEBUG_BUS: Number of debug events based on TCC_DEBUG_INDEX register. P;$TCC_PERF_SEL_DUMMY_LAST: Reserved. <P< PERF_MODE(=<NPERFMON_COUNTER_MODE_ACCUM: Accumulate increment values over enabled cycles. >p=`PERFMON_COUNTER_MODE_ACTIVE_CYCLES: Count the number of cycles with a nonzero increment value. >X>[PERFMON_COUNTER_MODE_MAX: Store the largest increment value received over cycles counted. ?8?YPERFMON_COUNTER_MODE_DIRTY: Record whether a nonzero increment value was ever received. @@FPERFMON_COUNTER_MODE_SAMPLE: Just record the latest increment vlaue. A@bPERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT: Count the cycles since a nonzero increment value. A^PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT: Count the cycles since a zero increment value. p`""TCC_INVALIDATE INVALIDATE"謣""0 TCC_VF_CTRL حVF_MAX_LF_DEPTH"0VF_MAX_CLIENT_LF_DEPTH"ண0 VF_HASH_MODEx:TCC_HASH_MODE_SEL_RANDOM: Use a pseudo-random hash mode. 8@TCC_HASH_MODE_SEL_LINEAR: Use the lsbs as the cacheline index. @TCC_HASH_MODE_SEL_DENSE_LFSR: Use a hash based on a dense lfsr PȱETCC_HASH_MODE_SEL_SIMPLE_XOR: Use a hash based on a simple xor tree 8aTCC_HASH_MODE_SEL_RANDOM_XOR_SIMPLE_XOR: Use the xor of the random hash and the simple xor tree \TCC_HASH_MODE_SEL_RANDOM_XOR_DENSE_LFSR: Use the xor of the random hash and the dense lfsr `dTCC_HASH_MODE_SEL_DENSE_LFSR_XOR_SIMPLE_XOR: Use the xor of the dense lfsr and the simple xor tree 跣X VF_CACHE_MODE`.TCC_CACHE_MODE_SEL_NORMAL: Normal operation. (?TCC_CACHE_MODE_SEL_FORCE_MISS: Always fetch data from memory. p5TCC_CACHE_MODE_SEL_FORCE_HIT: Do no memory fetches. @ VF_ARB_DELAY"8踣VF_BURST_SIZE"蹣VF_IGNORE_CLIENT_STALL"@VF_IGNORE_CLIENT_URGENCY"8VF_PRIO"@໣VF_IGNORE_DEALLOC(/Process VGT deallocation requests for vertex. ༣#Ignore VGT deallocation requests. VF_TAGSET_RENAME_EN"@h"" TCC_TF_CTRL XTF_MAX_LF_DEPTH"TF_MAX_CLIENT_LF_DEPTH"` TF_HASH_MODEp:TCC_HASH_MODE_SEL_RANDOM: Use a pseudo-random hash mode. 8@TCC_HASH_MODE_SEL_LINEAR: Use the lsbs as the cacheline index. @TCC_HASH_MODE_SEL_DENSE_LFSR: Use a hash based on a dense lfsr ؠPETCC_HASH_MODE_SEL_SIMPLE_XOR: Use a hash based on a simple xor tree aTCC_HASH_MODE_SEL_RANDOM_XOR_SIMPLE_XOR: Use the xor of the random hash and the simple xor tree \TCC_HASH_MODE_SEL_RANDOM_XOR_DENSE_LFSR: Use the xor of the random hash and the dense lfsr 袣dTCC_HASH_MODE_SEL_DENSE_LFSR_XOR_SIMPLE_XOR: Use the xor of the dense lfsr and the simple xor tree pࣣ 0TF_CACHE_MODE褣x.TCC_CACHE_MODE_SEL_NORMAL: Normal operation. 0?TCC_CACHE_MODE_SEL_FORCE_MISS: Always fetch data from memory. 5TCC_CACHE_MODE_SEL_FORCE_HIT: Do no memory fetches. Ȧ TF_ARB_DELAY"pTF_BURST_SIZE"pTF_IGNORE_CLIENT_STALL" ȨTF_IGNORE_CLIENT_URGENCY"xTF_PRIO"ȫhTF_IGNORE_DEALLOC 0Process VGT deallocation requests for texture. h#Ignore VGT deallocation requests. TF_TAGSET_RENAME_EN"؍"" TCC_CTRL`LF_FIFO_DEPTH"XMC_FIFO_DEPTH"hDISABLE_UNCACHED_ALT_TAGPNormal operation 蒣ADisable use of alternate tag when uncached requests are stalled OF_FIFO_DEPTH"hLF_BLOCK_SIZE"X CACHE_SIZE蕣Full x01/2 1/4 P1/8 H@PARTITION_SIZE蘣!Shared Vertex and Texture Cache 0*Vertex: 1/2 Cache ; Texture: 1/2 Cache *Vertex: 1/4 Cache ; Texture: 3/4 Cache FORCE_DEALLOC_ALL"ȋP""TCC_DEBUG_DATAHDATA`@""TCC_DEBUG_INDEX0茣HINDEXPERF_BIT_INDEX"؊""(TCC_READ_INDEXINDEX"Xh""TCC_WRITE_INDEXXINDEX" WRITE_ALL@DJust write the registers in the TCC block indicated by INDEX field Write all TCC blocks PxЀ""" VC_DEBUG_REG16ȁxRG_RP_L1_cmd_rdy"p RG_RP_L1_thread_id" Ȃ RG_RP_L1_thread_type"Ѓx RG_RP_L1_first_instr_of_vv"x(  rddone_valid" Є rddone_thread_id"ȅxrddone_thread_type"  spare"mx"""yVC_DEBUG_REG15 ypyrpdc_data_rdy"hzzrpdc_data_format"{zrpdc_num_format_all"{h{ rpdc_signed_rf_mode_all"p|| rpdc_format_comp_all"}| rpdc_dst_sel_w"}p}rpdc_dst_sel_z"h~~rpdc_dst_sel_y"~rpdc_dst_sel_x"hrpdc_end_of_group"spare"g`n"""nVC_DEBUG_REG14Xooend_phase_grp"oo cycle_cnt"pPp rpdc_cycle"@qprpdc_sync_phase"qq flt_sel_en"r8r out_buf_sel4"0sr last_phase_cycle0"ss last_phase_cycle1"t0t last_phase_cycle2"(ut last_phase_cycle3"uu  in_buf_sel"pv vout_buf_sel_nxt"wv xy_flt_en2"whw zw_flt_en2"x spare"pZg """HhVC_DEBUG_REG13 hhxbuf_en"i@iybuf_en"(jizbuf_en"jj wbuf_en"hk k xmux_sel3"lk ymux_sel"l`l zmux_sel3"Hmm wmux_sel"mspare" OZ """8[VC_DEBUG_REG12[[L1_cmd_fifo_we"\8\L1_fifo_empty"0]\ L1_fifo_full"]] L1_fifo_re"^(^L1_first_instr_of_vv"(_^L1_cache_wbuf_full"__L1_cache_wbuf_sel"x`(`L1_cache_rbuf_empty" a`L1_cache_rbuf_sel"axa L1_cache_rbuf_done"pb b L1_cache_rbuf_swap"cb  L1_p0hdfifo"chc  L1_pipe0dr"Pdd  L1_pipe1dr"dd L1_pipe2dr"eHe L1_pipe3dr"8fegpr_data_phase_sel"ffVC_data_gpr_phase"8g spare"PCO """OVC_DEBUG_REG11P@PTD_sync_simd_id"8QPTD_sync_valid"QQSMX_sync_simd_id"R8RSMX_sync_valid"0SR L1_cycle_ctr"SS L1_curr_simd_busy_p0"T8T L1_rdata_avail_p0"0UT L1_simd_id_p0"UUL1_phase0_avail_p0"V0VL1_phase1_avail_p0"(WVL1_phase2_avail_p0"WWL1_phase3_avail_p0"xX(XL1_valid_event_p0" YXL1_phase_grp_cnt_p0"YxYL1_phase_grp_total_p0"(Zspare"h2C """DVC_DEBUG_REG10DpDL1_phase_sent_p0"hEEL1_last_phase"FE L1_cycle_p0"F`FL1_last_xfer_of_req_p0"`GGL1_stalled_event_p0"HG L1_output_data_mux_p2"HhH realign_dword"`IIL1_endian_swap_p3"JIRP_busy"JXJ L2a_fifo_we"HKJL2a_fifo_empty"KKL2a_fifo_full"LHL L2b_fifo_we"8MLL2b_fifo_empty"MML2b_fifo_full"N8N L2_fifo_re"Nspare"/2 """03VC_DEBUG_REG933L2b_bank0_valid"404CC_RP_L2_b0_ready"(54L2b_bank1_valid"55CC_RP_L2_b1_ready"x6(6L2b_bank2_valid" 76CC_RP_L2_b2_ready"7x7L2b_bank3_valid"p8 8CC_RP_L2_b3_ready"98L2_rdy_to_xfer"9p9 L2_null_request"h:: L2_req_invalid";: RP_CC_L2_b0_re";h; RP_CC_L2_b1_re"`<< RP_CC_L2_b2_re"=<RP_CC_L2_b3_re"=`= L2_p0hdfifo"H>> L2_pipe0dr">> L2_p1hdp0"?@? L2_pipe1dr"(@? L2_p2hdp1"@@ L2_pipe2dr"hA A L2_p3hdp2"BA L2_pipe3dr"B`BL2_last_index_p3"Cspare"(0"""x0VC_DEBUG_REG8 10 MAX_LOCAL_LATENCY"1x1 MIN_LOCAL_LATENCY" 2spare"x"""hVC_DEBUG_REG7  RS_MI_reset" `  odd_wr_sel_q"X!!even_wr_sel_q""!odd_fifo_rd_state_q""X"even_fifo_rd_state_q"P## MI_CC_rtr"##odd_b_fifo_full"$P$odd_a_fifo_full"H%$even_b_fifo_full"%% even_a_fifo_full"&H&  pipe_freeze"8'& VC_MC_rdreq1_free_q"'' VC_MC_rdreq0_free_q"(8( GCA_MC_rdreq1_send"0)(GCA_MC_rdreq0_send")) req_1_freeze"*0* req_0_freeze"(+*vcmi1_req1_send"++vcmi1_req0_send"x,(,odd_b_fifo_empty" -,odd_a_fifo_empty"-x-even_b_fifo_empty"p. .even_a_fifo_empty"/. CC_MI_rdy"h/spare"h """@VC_DEBUG_REG6 hr_vld"8 mc0_bank_sel"0mc0_conflicts_mc1"mc_rdret0_vld"0mc_rdret1_vld"(VC_MC_rdnfo1_stall"VC_MC_rdnfo0_stall"x(vcmi0_mc_rdret0_tid"  vcmi0_mc_rdret1_tid"x  urg_ctr0"` urg_ctr1" stall_thld"Xspare"p """0 VC_DEBUG_REG5 even_t1_hit_way_d1_q" 8 even_t0_hit_way_d1_q"@ odd_t1_fetch_sector_d1_q" odd_t1_cnt_busy" @ odd_t0_fetch_sector_d1_q"@ odd_t0_cnt_busy" even_t1_fetch_sector_d1_q"Heven_t1_cnt_busy"Heven_t0_fetch_sector_d1_q"even_t0_cnt_busy"HNC"0input_fifo_re"input_fifo_we"0input_fifo_empty"(input_fifo_full"odd_cnt_overflow_d1_q"0spare""""8VC_DEBUG_REG4 even_cnt_overflow_d1_q"@odd_cache_line_in_use_d1_q"Heven_cache_line_in_use_d1_q"multicycle_stall"H CC_RG_rtr"0 MI_CC_rtr"RP_CC_L2b_rtr"x0 RG_CC_rdy" odd_debug_bus"x even_debug_bus" spare"hP"""VC_DEBUG_REG3 Peven_t0_fetch_way_d1_q"even_t0_fetch_sector_d1_q"Xeven_t0_cache_miss_d1_q"`even_t0_bank_mask_d1_q" even_t0_addr_d1_q"` even_t0_valid_d1_q"`odd_t1_fetch_way_d1_q"odd_t1_fetch_sector_d1_q"hhodd_t1_cache_miss_d1_q"odd_t1_bank_mask_d1_q"spare""""0VC_DEBUG_REG2 odd_t1_addr_d1_q"0odd_t1_valid_d1_q"0odd_t0_fetch_way_d1_q"odd_t0_fetch_sector_d1_q"8 odd_t0_cache_miss_d1_q"@ odd_t0_bank_mask_d1_q"odd_t0_addr_d1_q"@odd_t0_valid_d1_q"8odd_t1_hit_way_d1_q" spare"8ע"""PVC_DEBUG_REG1 RS_RG_reset"H fetch_valid"0 fetch_start" fetch_phase"(conflict_serialization"  conflict"x clamp_conflict"p instr_fifo_full" index_fifo_full"p VC_skewed_indices"h RP_RG_L2a_rtr" CC_RG_rtr"`RP_RG_L1_fifo_read"P RG_CC_rdy"RG_RP_L2a_rdy"P vcrg4_rts"8 vcrg3_rts" vcrg2_rts"0RG_RP_L1_valids_rdy"(RG_RP_L1_cmd_rdy" vcrg1_rts" spare"բע"""آVC_DEBUG_REG0آXآinstr_fifo_empty"P٢٢instr_fifo_we"٢٢index_fifo_empty"ڢPڢindex_fifo_we"Pۢڢadj_mem_request_size"ܢۢexternal_pipe_freeze"ܢXܢinternal_pipe_freeze"Xݢݢvcrg_calc_stall"ޢݢvcrg3_relative_index"ޢ`ޢ  vcrg3_count"Xߢߢvcrg3_last_index_of_vv"ߢߢRG_busy"P SH_cmd_send"@SH_VC_fetch_valid"VC_cmd_gpr_phase"@spare"XԢ@֢LL""֢VC_PERFCOUNTER3_LOW֢ PERFCOUNTER_LOW"ҢԢ@@"" բVC_PERFCOUNTER2_LOWxբ PERFCOUNTER_LOW"xѢ`Ӣ44""ӢVC_PERFCOUNTER1_LOWԢ PERFCOUNTER_LOW"ТѢ((""@ҢVC_PERFCOUNTER0_LOWҢ PERFCOUNTER_LOW"΢ТHH""ТVC_PERFCOUNTER3_HI(Ѣ PERFCOUNTER_HI"(͢Ϣ<<""`ϢVC_PERFCOUNTER2_HIϢ PERFCOUNTER_HI"ˢ͢00""͢VC_PERFCOUNTER1_HIH΢ PERFCOUNTER_HI"@ʢ0̢$$""̢VC_PERFCOUNTER0_HI̢ PERFCOUNTER_HI"ȢʢDD""ˢVC_PERFCOUNTER3_SELECThˢPERFCOUNTER_SELECT"PǢ@ɢ88""ɢVC_PERFCOUNTER2_SELECTɢPERFCOUNTER_SELECT"Ǣ,,"" ȢVC_PERFCOUNTER1_SELECTxȢPERFCOUNTER_SELECT" ""ؙVC_PERFCOUNTER0_SELECT0PERFCOUNTER_SELECT=8Ț2RG_VERTICES : Number of vertices processed by RG 0RG_CLAMPED : Number of vertices clamped by RG 8HRG_MEGA_REQUEST : Count the number of mega's transferred from L1 to RB ;RG_RB_REQUEST : Count of requests to get 4 verts from RB @ȝ5RG_MEGAFETCH : Count of megafetches processed by RG BRG_END_OF_GROUP : Count of end_of_group signals received from SQ ПP?RG_CONFLICT : Number of vertex pairs that conflict in the L2 ARG_BYTES_REQUESTED_4_0 : Number of byte requests created by RG `ࠢARG_BYTES_REQUESTED_6_5 : Number of byte requests created by RG  RG_SPARE0 : Reserved for RG ТP BCC_STALLS : Number of clocks CC stalled due to memory latency  9CC_HITS : L1 Requests that resulted in a cache hit Pأ :CC_MISSES : L1 Requests that resulted in a cache miss  ACC_SECTOR_MISSES : L1 Requests that resulted in a sector miss Х`4CC_L2a_STALLS : CC stalled due to L2a FIFO not RTR KCC_TCC_STALLS : CC stalled due to TCC not able to accept requests p覢FCC_MULTICYCLE_STALLS : CC stalled due to serialization of TCC rdreq 8ACC_EVEN_ALLOC_STALLS : CC stalled due to even allocation stall @CC_ODD_ALLOC_STALLS : CC stalled due to odd allocation stall ȩH?CC_EVEN_OVFLOW_STALLS : CC stalled due to even counter busy >CC_ODD_OVFLOW_STALLS : CC stalled due to odd counter busy Hت0CC_IN_FIFO_EMPTY : CC input FIFO is empty /CC_IN_FIFO_FULL : CC input FIFO is full ЬHFCC_FREEZE : CC frozen due to one of the stall conditions 0CC_TCC_REQUEST : Read Request to the TC 0Э CC_SPARE0 : Reserved for CC خx CC_SPARE1 : Reserved for CC  CC_SPARE2 : Reserved for CC (ȯ CC_SPARE3 : Reserved for CC аp CC_SPARE4 : Reserved for CC ERP_SP_DATA_VALID : Number of clocks of valid data returned to SP `豢;RP_L1_PIPE_STALL : Number of clocks RP L1 pipe is stalled ( BRP_RB_PIPE_STALL : Number of clocks RP ReconBuff pipe is stalled p!CTC_LAT_BIN_0 : Number of cycles MC latency between 0 and 64 8"CTC_LAT_BIN_1 : Number of cycles MC latency between 64 and 128 #CTC_LAT_BIN_2 : Number of cycles MC latency between 128 and 192 Hȵ$CTC_LAT_BIN_3 : Number of cycles MC latency between 192 and 256 %CTC_LAT_BIN_4 : Number of cycles MC latency between 256 and 320 طX&CTC_LAT_BIN_5 : Number of cycles MC latency between 320 and 384 'CTC_LAT_BIN_6 : Number of cycles MC latency between 384 and 448 h踢(CTC_LAT_BIN_7 : Number of cycles MC latency between 448 and 512 ) RP_SPARE0 : Reserved for RP X* RP_SPARE1 : Reserved for RP `+ RP_SPARE2 : Reserved for RP , RP_SPARE3 : Reserved for RP P- RP_SPARE4 : Reserved for RP x.ADC_QUAD_VALIDS : Number of valid vertexes returned to the SP / DC_SPARE0 : Reserved for DC Ⱦh0 DC_SPARE1 : Reserved for DC p1 DC_SPARE2 : Reserved for DC 82BSQ_VC_SEND : Number of clocks the SQ is passing data to the VC 3`VC_STARVED_IDLE : Number of clock cycles the VC is idle and waiting for more data from the SQ h4CVC_BUSY : Number of clock cycles the VC is busy processing data ¢0¢53VC_IDLE : Number of clock cycles the VC is idle `â¢66VC_CLK_EN : Number of cycles the VC clock is enabled Ģâ7 VC_SPARE0 : Reserved for VC ĢPĢ8 VC_SPARE1 : Reserved for VC XŢĢ9 VC_SPARE2 : Reserved for VC ƢŢ: VC_SPARE3 : Reserved for VC ƢHƢ; VC_SPARE4 : Reserved for VC Ƣ< VC_SPARE5 : Reserved for VC 0""CGTT_VC_CLK_CTRL ؒ ON_DELAY"ȓxOFF_HYSTERESIS"p SOFT_OVERRIDE7"ȔSOFT_OVERRIDE6"pSOFT_OVERRIDE5"hSOFT_OVERRIDE4"SOFT_OVERRIDE3"hSOFT_OVERRIDE2"`SOFT_OVERRIDE1"SOFT_OVERRIDE0"""ȏ VC_CONFIGh  WRITE_DIS"GPR_DATA_PHASE_SEL"hGPR_SEND_PHASE_SEL"@ ""h VC_ENHANCEMISC" ""VC_DEBUG_DATA` DATA` ""芢VC_DEBUG_CNTL@VC_DEBUG_INDX苢VC_RESET_LAT_COUNTERS"؇""(VC_PROG_FIFO_CNTLЈ L2a_PROG_DEPTH"x( L2c_PROG_DEPTH"ЉRB_PROG_DEPTH"y""؄VC_CNTL_STATUSx0RP_BUSY"ЅRG_BUSY"pVC_BUSY" CLAMP_DETECT"`r(z""pzVC_CNTL{zL1_INVALIDATE"{p{ L1_FORCE_HIT"h||L1_FORCE_MISS"}|L1_UNCACHED_SURF_SYNC"}p}L2_REQ_CREDIT_CTR"h~~  L2_CREDIT_WE"~ REQ_LATENCY_RESX1X System Clock P2X System Clock 4X System Clock 88X System Clock 0؁16X System Clock Ђx32X System Clock p64X System Clock 128X System Clock prTT""(sCGTT_TCP_CLK_CTRL ss ON_DELAY"pt tOFF_HYSTERESIS"utSOFT_OVERRIDE7"upuSOFT_OVERRIDE6"hvvSOFT_OVERRIDE5"wvSOFT_OVERRIDE4"whwSOFT_OVERRIDE3"`xxSOFT_OVERRIDE2"yxSOFT_OVERRIDE1"`ySOFT_OVERRIDE0"po`qPP""qTCP_PERFCOUNTER3_LOWr PERFCOUNTER_LOW"moDD""@pTCP_PERFCOUNTER2_LOWp PERFCOUNTER_LOW"lpn88""nTCP_PERFCOUNTER1_LOW o PERFCOUNTER_LOW"kl,,""PmTCP_PERFCOUNTER0_LOWm PERFCOUNTER_LOW"ikLL""kTCP_PERFCOUNTER3_HI0l PERFCOUNTER_HI"0hj@@""hjTCP_PERFCOUNTER2_HIj PERFCOUNTER_HI"fh44""hTCP_PERFCOUNTER1_HIPi PERFCOUNTER_HI"He8g((""gTCP_PERFCOUNTER0_HIg PERFCOUNTER_HI"ceHH""fTCP_PERFCOUNTER3_SELECTpfPERFCOUNTER_SELECT"XbHd<<""dTCP_PERFCOUNTER2_SELECTdPERFCOUNTER_SELECT"(b00""(cTCP_PERFCOUNTER1_SELECTcPERFCOUNTER_SELECT"$$""TCP_PERFCOUNTER0_SELECTPPERFCOUNTER_SELECTP,R7XX_TA_TCP_STARVE_CYCLES : TA starves TCP *R7XX_TCP_TA_STALL_CYCLES : TCP stalls TA H*R7XX_TD_TCP_STALL_CYCLES : TD stalls TCP x=R7XX_TCC_TCP_STALL_CYCLES : Total cycles any TCC stalls TCP 0.R7XX_TCC0_TCP_STALL_CYCLES : TCC0 stalls TCP x.R7XX_TCC1_TCP_STALL_CYCLES : TCC1 stalls TCP 0.R7XX_TCC2_TCP_STALL_CYCLES : TCC2 stalls TCP X.R7XX_TCC3_TCP_STALL_CYCLES : TCC3 stalls TCP  .R7XX_TCC4_TCP_STALL_CYCLES : TCC4 stalls TCP X .R7XX_TCC5_TCP_STALL_CYCLES : TCC5 stalls TCP  .R7XX_TCC6_TCP_STALL_CYCLES : TCC6 stalls TCP 8 .R7XX_TCC7_TCP_STALL_CYCLES : TCC7 stalls TCP 1R7XX_TCP_LOD_STALL_CYCLES : Per Pixel LOD stall 8 ;R7XX_TCP_TAGCONFLICT_STALL_CYCLES : Tagram conflict stall x BR7XX_TCP_ALLOC_STALL_CYCLES : Alloc on inflight cache line stall @ ?R7XX_TCP_LFIFO_STALL_CYCLES : Memory Latency fifos full stall ?R7XX_TCP_RFIFO_STALL_CYCLES : Memory Request fifos full stall P<R7XX_TCP_FFIFO_STALL_CYCLES : Memory Free fifos full stall 7R7XX_TCP_CFIFO_STALL_CYCLES : Control Fifo full stall H:R7XX_TCP_READCONFLICT_STALL_CYCLES : Read conflict stall /R7XX_TCP_PENDING_STALL_CYCLES : Pending stall H2R7XX_TCP_READFIFO_STALL_CYCLES : Read fifo stall h&R7XX_TCP_LATENCY : Total TCP latency (7R7XX_TCC_REQ_LATENCY : Total TCP->TCC request latency p8R7XX_TCC0_REQ_LATENCY : Total TCP->TCC request latency 09R7XX_TCC1_REQ_LATENCY : Total TCP->TCC1 request latency h9R7XX_TCC2_REQ_LATENCY : Total TCP->TCC2 request latency (9R7XX_TCC3_REQ_LATENCY : Total TCP->TCC3 request latency p9R7XX_TCC4_REQ_LATENCY : Total TCP->TCC4 request latency 09R7XX_TCC5_REQ_LATENCY : Total TCP->TCC5 request latency h9R7XX_TCC6_REQ_LATENCY : Total TCP->TCC6 request latency (9R7XX_TCC7_REQ_LATENCY : Total TCP->TCC7 request latency p 5R7XX_TCC_FREE_LATENCY : Total TCP->TCC free latency 0!7R7XX_TCC0_FREE_LATENCY : Total TCP->TCC0 free latency h"7R7XX_TCC1_FREE_LATENCY : Total TCP->TCC1 free latency (#7R7XX_TCC2_FREE_LATENCY : Total TCP->TCC2 free latency p$7R7XX_TCC3_FREE_LATENCY : Total TCP->TCC3 free latency 0%7R7XX_TCC4_FREE_LATENCY : Total TCP->TCC4 free latency h&7R7XX_TCC5_FREE_LATENCY : Total TCP->TCC5 free latency ( '7R7XX_TCC6_FREE_LATENCY : Total TCP->TCC6 free latency p (7R7XX_TCC7_FREE_LATENCY : Total TCP->TCC7 free latency !0!)8R7XX_TCP_TCC_REQ : Total requests from TCP to all TCCs `"!*2R7XX_TCP_TCC0_REQ : TCP issues a request to TCC0 #"+2R7XX_TCP_TCC1_REQ : TCP issues a request to TCC1 #`#,2R7XX_TCP_TCC2_REQ : TCP issues a request to TCC2 $$-2R7XX_TCP_TCC3_REQ : TCP issues a request to TCC3 @%$.2R7XX_TCP_TCC4_REQ : TCP issues a request to TCC4 %%/2R7XX_TCP_TCC5_REQ : TCP issues a request to TCC5 &@&02R7XX_TCP_TCC6_REQ : TCP issues a request to TCC6 h'&12R7XX_TCP_TCC7_REQ : TCP issues a request to TCC7 (('27R7XX_TCC_TCP_RDRET : Total rdret from all TCCs to TCP (p(32R7XX_TCC0_TCP_RDRET : TCC0 issues a rdret to TCP )()42R7XX_TCC1_TCP_RDRET : TCC1 issues a rdret to TCP P*)52R7XX_TCC2_TCP_RDRET : TCC2 issues a rdret to TCP +*62R7XX_TCC3_TCP_RDRET : TCC3 issues a rdret to TCP +P+72R7XX_TCC4_TCP_RDRET : TCC4 issues a rdret to TCP x,,82R7XX_TCC5_TCP_RDRET : TCC5 issues a rdret to TCP 0-,92R7XX_TCC6_TCP_RDRET : TCC6 issues a rdret to TCP -x-:2R7XX_TCC7_TCP_RDRET : TCC7 issues a rdret to TCP .0.;'R7XX_TOTAL_PIXELS : Total pixel count P/.<.R7XX_UNCACHED_PIXELS : Total uncached pixels 0/=3R7XX_FMT_1_PIXELS : Pixels that use 1-bit formats 0P0>3R7XX_FMT_8_PIXELS : Pixels that use 8-bit formats 11?5R7XX_FMT_16_PIXELS : Pixels that use 16-bit formats @21@5R7XX_FMT_32_PIXELS : Pixels that use 32-bit formats 32A;R7XX_FMT_32_AS_8_PIXELS : Pixels that use 32_AS_8 formats 3H3B>R7XX_FMT_32_AS_16_PIXELS : Pixels that use 32_AS_8_8 formats 44CER7XX_FMT_64_2_CYCLE_PIXELS : Pixels that use 64-bit 2-cycle formats h54DER7XX_FMT_64_1_CYCLE_PIXELS : Pixels that use 64-bit 1-cycle formats (65E5R7XX_FMT_96_PIXELS : Pixels that use 96-bit formats 6p6FGR7XX_FMT_128_4_CYCLE_PIXELS : Pixels that use 128-bit 4-cycle formats 7@7GGR7XX_FMT_128_1_CYCLE_PIXELS : Pixels that use 128-bit 1-cycle formats 88H2R7XX_FMT_BC1_PIXELS : Pixels that use BC1 format 898I2R7XX_FMT_BC2_PIXELS : Pixels that use BC2 format 99J2R7XX_FMT_BC3_PIXELS : Pixels that use BC3 format :8:K2R7XX_FMT_BC4_PIXELS : Pixels that use BC4 format `;:L2R7XX_FMT_BC5_PIXELS : Pixels that use BC5 format (<;M?R7XX_FMT_I8_PIXELS : Pixels that use 8-bit interlaced formats <p<NAR7XX_FMT_I16_PIXELS : Pixels that use 16-bit interlaced formats =8=OAR7XX_FMT_I32_PIXELS : Pixels that use 32-bit interlaced formats >>PGR7XX_FMT_I32_AS_8_PIXELS : Pixels that use 32_AS_8 interlaced formats X?>QJR7XX_FMT_I32_AS_16_PIXELS : Pixels that use 32_AS_8_8 interlaced formats @?R;R7XX_FMT_D16_PIXELS : Pixels that use 16-bit depth format @`@S;R7XX_FMT_D32_PIXELS : Pixels that use 32-bit depth format A AT:R7XX_FMT_V8_PIXELS : Pixels that use 8-bit vertex format XBAU<R7XX_FMT_V16_PIXELS : Pixels that use 16-bit vertex format CBV<R7XX_FMT_V32_PIXELS : Pixels that use 32-bit vertex format C`CWLR7XX_FMT_V64_2_CYCLE_PIXELS : Pixels that use 64-bit 2-cycle vertex format D0DXLR7XX_FMT_V64_1_CYCLE_PIXELS : Pixels that use 64-bit 1-cycle vertex format EEYNR7XX_FMT_V128_4_CYCLE_PIXELS : Pixels that use 128-bit 4-cycle vertex format hFEZNR7XX_FMT_V128_2_CYCLE_PIXELS : Pixels that use 128-bit 2-cycle vertex format @GF[NR7XX_FMT_V128_1_CYCLE_PIXELS : Pixels that use 128-bit 1-cycle vertex format HG\OR7XX_ARR_LINEAR_GENERAL_PIXELS : Pixels that use linear general memory tiling H`H]OR7XX_ARR_LINEAR_ALIGNED_PIXELS : Pixels that use linear aligned memory tiling I8I^CR7XX_ARR_1D_THIN1_PIXELS : Pixels that use 1d thin1 memory tiling JJ_CR7XX_ARR_1D_THICK_PIXELS : Pixels that use 1d thick memory tiling HKJ`CR7XX_ARR_2D_THIN1_PIXELS : Pixels that use 2d thin1 memory tiling LKaCR7XX_ARR_2D_THIN2_PIXELS : Pixels that use 2d thin2 memory tiling LXLbCR7XX_ARR_2D_THIN4_PIXELS : Pixels that use 2d thin4 memory tiling M McCR7XX_ARR_2D_THICK_PIXELS : Pixels that use 2d thick memory tiling hNMdCR7XX_ARR_2B_THIN1_PIXELS : Pixels that use 2b thin1 memory tiling 0ONeCR7XX_ARR_2B_THIN2_PIXELS : Pixels that use 2b thin2 memory tiling OxOfCR7XX_ARR_2B_THIN4_PIXELS : Pixels that use 2b thin4 memory tiling P@PgCR7XX_ARR_2B_THICK_PIXELS : Pixels that use 2b thick memory tiling QQhCR7XX_ARR_3D_THIN1_PIXELS : Pixels that use 3d thin1 memory tiling PRQiCR7XX_ARR_3D_THICK_PIXELS : Pixels that use 3d thick memory tiling SRjCR7XX_ARR_3B_THIN1_PIXELS : Pixels that use 3b thin1 memory tiling S`SkCR7XX_ARR_3B_THICK_PIXELS : Pixels that use 3b thick memory tiling T(Tl8R7XX_DIM_1D_PIXELS : Pixels that belong to 1D surfaces `UTm8R7XX_DIM_2D_PIXELS : Pixels that belong to 2D surfaces VUn8R7XX_DIM_3D_PIXELS : Pixels that belong to 3D surfaces VhVo<R7XX_DIM_CUBE_PIXELS : Pixels that belong to Cube surfaces W(WpDR7XX_DIM_1D_ARRAY_PIXELS : Pixels that belong to 1D Array surfaces pXWqDR7XX_DIM_2D_ARRAY_PIXELS : Pixels that belong to 2D Array surfaces 8YXrBR7XX_DIM_2D_MSAA_PIXELS : Pixels that belong to 2D MSAA surfaces ZYsNR7XX_DIM_2D_ARRAY_MSAA_PIXELS : Pixels that belong to 2D MSAA Array surfaces ZXZtHR7XX_DIM_CUBE_ARRAY_PIXELS : Pixels that belong to Cube Array surfaces [([uDR7XX_VGT_TCP_INVALIDATE : Number of cache invalidates from the VGT `\[v0R7XX_TA_TCP_STATE_READ : Number of state reads ]\w:R7XX_TCP_TAGRAM0_REQ : L1 Requests, (Tagram 0) 64B units ]h]x:R7XX_TCP_TAGRAM1_REQ : L1 Requests, (Tagram 1) 64B units ^(^y:R7XX_TCP_TAGRAM2_REQ : L1 Requests, (Tagram 2) 64B units `_^z:R7XX_TCP_TAGRAM3_REQ : L1 Requests, (Tagram 3) 64B units `_{8R7XX_TCP_GATE_EN1 : TCP interface clocks are turned on `h`|3R7XX_TCP_GATE_EN2 : TCP core clocks are turned on a a};R7XX_TCP_CORE_REG_SCLK_VLD : TCP reg clocks are turned on a~<R7XX_FMT_V96_PIXELS : Pixels that use 96-bit vertex format X8 ""TCP_DEBUG_DATADATA""" TCP_DEBUG_INDEXxINDEX"0""x TCP_CREDIT MC_CREDIT"p LFIFO_CREDIT"h CNTRL_FIFO_CREDIT"REQ_FIFO_CREDIT"hFREE_FIFO_CREDIT" TD_CREDIT"h""TCP_CHAN_STEERXCHAN0"CHAN1"PCHAN2"8 CHAN3" CHAN4"x0CHAN5"CHAN6"pCHAN7""" TCP_CNTL x0 FORCE_HIT" FORCE_MISS"pL1_SIZE@8K 4K P2K 1K 0 PARTITION_MODE0*Vertex: Full Cache ; Texture: Full Cache x*Vertex: 1/2 Cache ; Texture: 1/2 Cache (*Vertex: 1/4 Cache ; Texture: 3/4 Cache @DISABLE_AUTOINVALIDATE"FORCE_INVALIDATE_ALL"HDISABLE_Z_MAP"HDISABLE_CUBEMAP_FORCE_ARRAY"DISABLE_V_MAP"P0 ""x TCP_STATUS TCP_BUSY"H""TCP_READ_INDEXp READ_INDEX"""TCP_WRITE_INDEXh WRITE_INDEX" WRITE_ALL"X""TCP_INVALIDATESTART"""@ TA_SCRATCH SCRATCH"ޡ""TA_PERFCOUNTER1_LOW0 PERFCOUNTER_LOW"h֡ߡ""hߡTA_PERFCOUNTER1_HIߡ PERFCOUNTER_HI"ԡ֡""8סTA_PERFCOUNTER1_SELECTססPERFCOUNTER_SELECT"8ءء PERF_MODEX١ءNPERFMON_COUNTER_MODE_ACCUM: Accumulate increment values over enabled cycles. @ڡ١`PERFMON_COUNTER_MODE_ACTIVE_CYCLES: Count the number of cycles with a nonzero increment value. ۡڡ[PERFMON_COUNTER_MODE_MAX: Store the largest increment value received over cycles counted. ܡhۡYPERFMON_COUNTER_MODE_DIRTY: Record whether a nonzero increment value was ever received. ܡHܡFPERFMON_COUNTER_MODE_SAMPLE: Just record the latest increment vlaue. ݡݡbPERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT: Count the cycles since a nonzero increment value. ޡ^PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT: Count the cycles since a zero increment value. ӡpաXX""աTA_PERFCOUNTER0_LOW֡ PERFCOUNTER_LOW"ԡTT""PԡTA_PERFCOUNTER0_HIԡ PERFCOUNTER_HI"H(PP""TA_PERFCOUNTER0_SELECTؘ̡(PERFCOUNTER_SELECTDЙpTA_BUSY : Cycles TA is active >GRADIENT_BUSY : Cycles Gradient calculations block is active X5GRADIENT_FIFO_BUSY : Cycles Gradient FIFO is active :LOD_BUSY : Cycles LOD/Aniso calculations block is active Ȝ`+LOD_FIFO_BUSY : Cycles LOD FIFO is active 4ADDRESSER_BUSY : Cycles Addressing block is active @ȝ7ADDRESSER_FIFO_BUSY : Cycles Addresser FIFO is active /ALIGNER_BUSY : Cycles Aligner block is active @9PIX_0_QUAD : Cycles of valid quads with no valid pixels  7PIX_1_QUAD : Cycles of valid quads with 1 valid pixel @Ƞ 8PIX_2_QUAD : Cycles of valid quads with 2 valid pixels 8PIX_3_QUAD : Cycles of valid quads with 3 valid pixels H 8PIX_4_QUAD : Cycles of valid quads with 4 valid pixels P RESERVED ࣡ RESERVED p( RESERVED ,INPUT_CYCLES : Valid cycles coming from SH hdGRADIENT_BALANCING_CYCLES : Cycles inserted by gradient multicycling purely to sync with other TAs ئPFGRADIENT_CYCLES : Total valid cycles driven by gradient multicycling `WALKER_BALANCING_CYCLES : Cycles inserted by sample multicycling purely to sync with other TAs BWALKER_CYCLES : Total valid cycles driven by sample multicycling pШdALIGNER_BALANCING_CYCLES : Cycles inserted by alignment multicycling purely to sync with other TAs @GALIGNER_CYCLES : Total valid cycles driven aligner multicycling to TC Ъ RESERVED EMIP_1_CYCLE_PIXELS : Pixels requiring samples from only 1 mip level h諡AMIP_2_CYCLE_PIXELS : Pixels requiring samples from 2 mip levels 8KVOL_1_CYCLE_PIXELS : Pixels requiring samples from only 1 vol/array level GVOL_2_CYCLE_PIXELS : Pixels requiring samples from 2 vol/array levels خPGBILIN_POINT_1_CYCLE_PIXELS : Pixels requiring 1 bilinear/point sample PBICUBIC_4_CYCLE_PIXELS : Pixels requiring 4 bilinear samples to form a bicubic @ RESERVED а RESERVED  =MIPMAP_LOD_0_SAMPLES : Samples requesting from MipMap LOD 0 `ౡ!=MIPMAP_LOD_1_SAMPLES : Samples requesting from MipMap LOD 1 ("=MIPMAP_LOD_2_SAMPLES : Samples requesting from MipMap LOD 2 p#=MIPMAP_LOD_3_SAMPLES : Samples requesting from MipMap LOD 3 8$=MIPMAP_LOD_4_SAMPLES : Samples requesting from MipMap LOD 4 %=MIPMAP_LOD_5_SAMPLES : Samples requesting from MipMap LOD 5 Hȵ&=MIPMAP_LOD_6_SAMPLES : Samples requesting from MipMap LOD 6 '=MIPMAP_LOD_7_SAMPLES : Samples requesting from MipMap LOD 7 طX(=MIPMAP_LOD_8_SAMPLES : Samples requesting from MipMap LOD 8 )=MIPMAP_LOD_9_SAMPLES : Samples requesting from MipMap LOD 9 h踡*?MIPMAP_LOD_10_SAMPLES : Samples requesting from MipMap LOD 10 0+?MIPMAP_LOD_11_SAMPLES : Samples requesting from MipMap LOD 11 x,?MIPMAP_LOD_12_SAMPLES : Samples requesting from MipMap LOD 12 @-?MIPMAP_LOD_13_SAMPLES : Samples requesting from MipMap LOD 13 .?MIPMAP_LOD_14_SAMPLES : Samples requesting from MipMap LOD 14 м/ RESERVED ؽ`08ANISO_1_1_QUADS : Quads with 1:1 anisotropic filtering 18ANISO_2_1_QUADS : Quads with 2:1 anisotropic filtering Xྡ28ANISO_3_1_QUADS : Quads with 3:1 anisotropic filtering 38ANISO_4_1_QUADS : Quads with 4:1 anisotropic filtering `48ANISO_5_1_QUADS : Quads with 5:1 anisotropic filtering 58ANISO_6_1_QUADS : Quads with 6:1 anisotropic filtering X¡68ANISO_7_1_QUADS : Quads with 7:1 anisotropic filtering á¡78ANISO_8_1_QUADS : Quads with 8:1 anisotropic filtering á`á88ANISO_9_1_QUADS : Quads with 9:1 anisotropic filtering ġ ġ9:ANISO_10_1_QUADS : Quads with 10:1 anisotropic filtering Xšġ::ANISO_11_1_QUADS : Quads with 11:1 anisotropic filtering ơš;:ANISO_12_1_QUADS : Quads with 12:1 anisotropic filtering ơ`ơ<:ANISO_13_1_QUADS : Quads with 13:1 anisotropic filtering ǡ ǡ=:ANISO_14_1_QUADS : Quads with 14:1 anisotropic filtering Xȡǡ>:ANISO_15_1_QUADS : Quads with 15:1 anisotropic filtering ɡȡ?:ANISO_16_1_QUADS : Quads with 16:1 anisotropic filtering ɡ`ɡ@FTA_REG_SCLK_VLD : Clock gate enable for GRBM register reads & writes ʡ0ʡATTA_LOCAL_CG_DYN_SCLK_GRP0_EN : Clock gate enable for non-harvestable texture logic ˡˡBPTA_LOCAL_CG_DYN_SCLK_GRP1_EN : Clock gate enable for harvestable texture logic ˡCTA_LOCAL_CG_DYN_SCLK_GRP1_MEMS_EN : Clock gate enable for harvestable texture logic as well as GRBM register reads & writes (primarily Border Color RAM related) ͡`͡ PERF_MODE8Ρ͡NPERFMON_COUNTER_MODE_ACCUM: Accumulate increment values over enabled cycles. ϡΡ`PERFMON_COUNTER_MODE_ACTIVE_CYCLES: Count the number of cycles with a nonzero increment value. Сhϡ[PERFMON_COUNTER_MODE_MAX: Store the largest increment value received over cycles counted. СPСYPERFMON_COUNTER_MODE_DIRTY: Record whether a nonzero increment value was ever received. ѡ0ѡFPERFMON_COUNTER_MODE_SAMPLE: Just record the latest increment vlaue. ҡҡbPERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT: Count the cycles since a nonzero increment value. ҡ^PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT: Count the cycles since a zero increment value. 44""TA_DEBUG_DATAhDATA"X00""TA_DEBUG_INDEXINDEX"聡""X TA_CGTT_CTRL  ON_DELAY"POFF_HYSTERESIS"HSOFT_OVERRIDE7"SOFT_OVERRIDE6"HSOFT_OVERRIDE5"@SOFT_OVERRIDE4"蒡SOFT_OVERRIDE3"@SOFT_OVERRIDE2"8蓡SOFT_OVERRIDE1"SOFT_OVERRIDE0"q` "" TA_STATUSP FG_PFIFO_EMPTYB" FG_LFIFO_EMPTYB"PFG_SFIFO_EMPTYB"HFL_PFIFO_EMPTYB"FL_LFIFO_EMPTYB"HFL_SFIFO_EMPTYB"@FA_PFIFO_EMPTYB"臡FA_LFIFO_EMPTYB"@FA_SFIFO_EMPTYB"0舡IN_BUSY"ЉFG_BUSY"p(LA_BUSY"ȊFL_BUSY"hTA_BUSY"PFA_BUSY"AL_BUSY"HBUSY" nq""@r TA_CNTL_AUX@trrDISABLE_CUBE_WRAPs0s-Force Clamp X,Y policy to wrap for CubeMaps sAllow other clamp modest 0vttDISABLE_CUBE_ANISOu0uAllow Aniso with CubeMaps uDisable Aniso with CubeMaps 0zvvGETLOD_SELECTw wUSampler and Resource clamped LOD in Resource View space, Zero fraction for MipPoint xxOSampler and Resource clamped LOD in Resource View space, Fraction kept always XyxBSampler clamped LOD in Resource View space, Fraction kept always yPSampler and Resource clamped LOD in Resource space, Zero fraction for MipPoint |zzSYNC_GRADIENT{ {Gradient Sync on Instruction {Gradient Sync on Phase ~x|| SYNC_WALKER`}}Walker Sync on Instruction }Walker Sync on Phase X~~ SYNC_ALIGNERP~Aligner Sync on Instruction Aligner Sync on Phase HBILINEAR_PRECISION@6-bit bilinear weights always $8-bit bilinear weights if possible kn""nTA_CNTLo8oGRADIENT_CREDIT"0poWALKER_CREDIT"ppALIGNER_CREDIT"0q TD_FIFO_CREDIT" jk""@l TA_INDEXll WRITE_INDEX"m8m WRITE_ALL"m READ_INDEX"hj""j TD_SCRATCH8k SCRATCH"@g(i""xiTD_PERFCOUNTER0_LOWi PERFCOUNTER_LOW"8Mg""hTD_PERFCOUNTER0_HI`h PERFCOUNTER_HI"KM""NTD_PERFCOUNTER0_SELECT``NNPERFCOUNTER_SELECTXONTD_BUSY : Cycles TD is active OO RESERVED xP0P RESERVED QP RESERVED QPQ RESERVED (RQ RESERVED RpR RESERVED HSS RESERVED TS-INPUT_BUSY : Cycles input section is active THT /OUTPUT_BUSY : Cycles output section is active UU ASAMPLE_LATENCY_FIFO_BUSY : Cycles sample latency fifo is active PVU ECONSTANT_LATENCY_FIFO_BUSY : Cycles constant latency fifo is active WV +FASTPATH_BUSY : Cycles fastpath is active WHW )SH_FIFO_BUSY : Cycles SH fifo is active hXW2PHASE_SYNC_BUSY : Cycles phase sync logic active YX3DATAOUT_FIFO_BUSY : Cycles dataout fifo is active ZhYWLATENCY_FIFO_BUSY_PIPE_IDLE : Cycles latency fifo is active and rest of block is idle ZHZ4SYNC_PHASE_COUNT : Cycles spent sync'g output data x[[7VC_DATA_RETURN : Cycles spent returning VC data to SH P\[QSTALL_DUE_TO_VC : Cycles stalling texture data, while VC data is returned to SH ]\JSTALL_DUE_TO_RSP : Cycles stalling texture data, while RSP asserts stall ^h]VSTALL_DUE_TO_VC_OR_RSP : Cycles stalling texture data due to either VC or RSP stalls ^H^FTD_REG_SCLK_VLD : Clock gate enable for GRBM register reads & writes __TTD_LOCAL_CG_DYN_SCLK_GRP0_EN : Clock gate enable for non-harvestable texture logic _PTD_LOCAL_CG_DYN_SCLK_GRP1_EN : Clock gate enable for harvestable texture logic ` a PERF_MODEahaNPERFMON_COUNTER_MODE_ACCUM: Accumulate increment values over enabled cycles. b@b`PERFMON_COUNTER_MODE_ACTIVE_CYCLES: Count the number of cycles with a nonzero increment value. c(c[PERFMON_COUNTER_MODE_MAX: Store the largest increment value received over cycles counted. ddYPERFMON_COUNTER_MODE_DIRTY: Record whether a nonzero increment value was ever received. pedFPERFMON_COUNTER_MODE_SAMPLE: Just record the latest increment vlaue. XfebPERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT: Count the cycles since a nonzero increment value. f^PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT: Count the cycles since a zero increment value. hJHL""LTD_DEBUG_DATALDATA"CJ""0KTD_DEBUG_INDEXKINDEX"AC""C TD_CGTT_CTRL D8D ON_DELAY"(EDOFF_HYSTERESIS"EESOFT_OVERRIDE7"xF(FSOFT_OVERRIDE6" GFSOFT_OVERRIDE5"GxGSOFT_OVERRIDE4"pH HSOFT_OVERRIDE3"IHSOFT_OVERRIDE2"IpISOFT_OVERRIDE1"JSOFT_OVERRIDE0"?0B""xB TD_STATUSBBUSY"`<x?""?TD_CNTLh@@SYNC_PHASE_SH"A@SYNC_PHASE_VC_SMX"hA PAD_STALL_EN"X:<"" = TD_INDEX=x= WRITE_INDEX"`>> WRITE_ALL"> READ_INDEX"P8:"" ;TD_FILTER4_35;x; WEIGHT_1"< WEIGHT_0"H68""9TD_FILTER4_349p9 WEIGHT_1": WEIGHT_0"@46""7TD_FILTER4_337h7 WEIGHT_1"8 WEIGHT_0"824""5TD_FILTER4_325`5 WEIGHT_1"6 WEIGHT_0"002||""3TD_FILTER4_313X3 WEIGHT_1"3 WEIGHT_0"(.0xx""0TD_FILTER4_301P1 WEIGHT_1"1 WEIGHT_0" ,.tt"".TD_FILTER4_29/H/ WEIGHT_1"/ WEIGHT_0"*,pp"",TD_FILTER4_28-@- WEIGHT_1"- WEIGHT_0"(*ll""*TD_FILTER4_27+8+ WEIGHT_1"+ WEIGHT_0"&(hh""(TD_FILTER4_26x)0) WEIGHT_1") WEIGHT_0"$&dd""&TD_FILTER4_25p'(' WEIGHT_1"' WEIGHT_0"!x$``""$TD_FILTER4_24h% % WEIGHT_1"% WEIGHT_0"p"\\"""TD_FILTER4_23`## WEIGHT_1"# WEIGHT_0"h XX"" TD_FILTER4_22X!! WEIGHT_1"! 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@@""!TD_PS_SAMPLER16_CLEARTYPE_KERNELhWIDTH"HEIGHT"<<""!TD_PS_SAMPLER15_CLEARTYPE_KERNELPWIDTH"HEIGHT"88""!TD_PS_SAMPLER14_CLEARTYPE_KERNEL8WIDTH"HEIGHT"h44""!TD_PS_SAMPLER13_CLEARTYPE_KERNELh WIDTH"HEIGHT"P00""!TD_PS_SAMPLER12_CLEARTYPE_KERNELPWIDTH"HEIGHT"8,,""!TD_PS_SAMPLER11_CLEARTYPE_KERNEL8WIDTH"HEIGHT"ޠ ((""!TD_PS_SAMPLER10_CLEARTYPE_KERNEL WIDTH"xHEIGHT"pܠߠ$$""`ߠ TD_PS_SAMPLER9_CLEARTYPE_KERNELߠWIDTH"`HEIGHT"Xڠܠ ""Hݠ TD_PS_SAMPLER8_CLEARTYPE_KERNELݠݠWIDTH"@ޠHEIGHT"@ؠڠ""0۠ TD_PS_SAMPLER7_CLEARTYPE_KERNEL۠۠WIDTH"(ܠHEIGHT"(֠ؠ""٠ TD_PS_SAMPLER6_CLEARTYPE_KERNEL٠p٠WIDTH"ڠHEIGHT"Ԡ֠""נ TD_PS_SAMPLER5_CLEARTYPE_KERNELנXנWIDTH"נHEIGHT"ѠԠ""Ԡ TD_PS_SAMPLER4_CLEARTYPE_KERNELՠ@ՠWIDTH"ՠHEIGHT"ϠpҠ ""Ҡ TD_PS_SAMPLER3_CLEARTYPE_KERNELpӠ(ӠWIDTH"ӠHEIGHT"͠XР""Р TD_PS_SAMPLER2_CLEARTYPE_KERNELXѠѠWIDTH"ѠHEIGHT"ˠ@Π""Π TD_PS_SAMPLER1_CLEARTYPE_KERNEL@ϠΠWIDTH"ϠHEIGHT"0ʠ(̠""̠ TD_PS_SAMPLER0_CLEARTYPE_KERNEL(̠͠WIDTH"͠HEIGHT"Ƞʠ""ˠTD_PS_SAMPLER17_BORDER_ALPHA`ˠ BORDER_ALPHA"0Ǡ(ɠ ""ɠTD_PS_SAMPLER16_BORDER_ALPHAɠ BORDER_ALPHA"ŠǠ""ȠTD_PS_SAMPLER15_BORDER_ALPHA`Ƞ BORDER_ALPHA"0Ġ(Ơ""ƠTD_PS_SAMPLER14_BORDER_ALPHAƠ BORDER_ALPHA" Ġܤܤ""ŠTD_PS_SAMPLER13_BORDER_ALPHA`Š BORDER_ALPHA"0(à̤̤""àTD_PS_SAMPLER12_BORDER_ALPHAà BORDER_ALPHA""" TD_PS_SAMPLER11_BORDER_ALPHA`  BORDER_ALPHA"8(""TD_PS_SAMPLER10_BORDER_ALPHA BORDER_ALPHA"""TD_PS_SAMPLER9_BORDER_ALPHA` BORDER_ALPHA"H8""TD_PS_SAMPLER8_BORDER_ALPHA轠 BORDER_ALPHA"й||""TD_PS_SAMPLER7_BORDER_ALPHAp BORDER_ALPHA"XHll""TD_PS_SAMPLER6_BORDER_ALPHA BORDER_ALPHA"චи\\""(TD_PS_SAMPLER5_BORDER_ALPHA BORDER_ALPHA"hXLL""TD_PS_SAMPLER4_BORDER_ALPHA BORDER_ALPHA"ൠ<<""8TD_PS_SAMPLER3_BORDER_ALPHA BORDER_ALPHA"xh,,""TD_PS_SAMPLER2_BORDER_ALPHA BORDER_ALPHA"""HTD_PS_SAMPLER1_BORDER_ALPHA BORDER_ALPHA"x ""бTD_PS_SAMPLER0_BORDER_ALPHA( BORDER_ALPHA" ""`TD_PS_SAMPLER17_BORDER_BLUE BORDER_BLUE"""TD_PS_SAMPLER16_BORDER_BLUEH BORDER_BLUE"@(""TD_PS_SAMPLER15_BORDER_BLUEح BORDER_BLUE"Щ""TD_PS_SAMPLER14_BORDER_BLUEh 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event window is active P98(VGT_SPI_ESVERT_VALID: ES Vert is valid :95VGT_SPI_ESVERT_EOV: ES vert end of vector is active :X:1VGT_SPI_ESVERT_STALLED: ES vert pipe is stalled ;;;VGT_SPI_ESVERT_STARVED_BUSY: ES vert pipe is starved busy H<;;VGT_SPI_ESVERT_STARVED_IDLE: ES vert pipe is starved idle =</VGT_SPI_ESVERT_STATIC: ES vert pipe is static =H=6VGT_SPI_ESTHREAD_IS_EVENT: ES Thread Event Indicator x>>1VGT_SPI_ESTHREAD_SEND: ES Thread Send is active 8?> 6VGT_SPI_GSPRIM_VALID: ES GS Primitive send is active @? =VGT_SPI_GSPRIM_EOV: ES GS Primitive end of vector is active @P@ 6VGT_SPI_GSPRIM_CONT: ES GS Primitive Continued Event AA 4VGT_SPI_GSPRIM_STALLED: ES GS Primitive is stalled HBA >VGT_SPI_GSPRIM_STARVED_BUSY: ES GS Primitive is starved busy CB>VGT_SPI_GSPRIM_STARVED_IDLE: ES GS Primitive is starved idle CXC2VGT_SPI_GSPRIM_STATIC: ES GS Primitive is static DDHVGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE: GS Thread event window is active `ED?VGT_SPI_GSTHREAD_IS_EVENT: GS Thread event is being processed FE0VGT_SPI_GSTHREAD_SEND: GS Thread is being sent F`FHVGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE: VS Thread event window is active G0G#VGT_SPI_VSVERT_SEND: VS vert send @HG+VGT_SPI_VSVERT_EOV: VS vert end of vector HH1VGT_SPI_VSVERT_STALLED: VS vert pipe is stalled I@I;VGT_SPI_VSVERT_STARVED_BUSY: VS vert pipe is starved busy xJJ;VGT_SPI_VSVERT_STARVED_IDLE: VS vert pipe is starved idle 0KJ/VGT_SPI_VSVERT_STATIC: VS vert pipe is static KxK6VGT_SPI_VSTHREAD_IS_EVENT: VS Thread Event Indicator L8L0VGT_SPI_VSTHREAD_SEND: VS Thread is being sent MLOVGT_PA_EVENT_WINDOW_ACTIVE: VGT to Primitive Assembler Event Window is active HNMCVGT_PA_CLIPV_SEND: VGT to Primitive Assembler clipv is being sent ONLVGT_PA_CLIPV_FIRSTVERT: VGT to Primitive Assembler clipv is the first vert O`OBVGT_PA_CLIPV_STALLED: VGT to Primitive Assembler pipe is stalled P(P LVGT_PA_CLIPV_STARVED_BUSY: VGT to Primitive Assembler pipe is starved_busy QP!LVGT_PA_CLIPV_STARVED_IDLE: VGT to Primitive Assembler pipe is starved_idle HRQ"@VGT_PA_CLIPV_STATIC: VGT to Primitive Assembler pipe is static SR#=VGT_PA_CLIPP_SEND: VGT to Primitive Assembler is being sent SXS$<VGT_PA_CLIPP_EOP: VGT to Primitive Assembler end of packet TT%DVGT_PA_CLIPP_IS_EVENT: VGT to Primitive Assembler event transition pUT&NVGT_PA_CLIPP_NULL_PRIM: VGT to Primitive Assembler null primitive is present HVU'TVGT_PA_CLIPP_NEW_VTX_VECT: VGT to Primitive Assembler new vertex vector is present WV(BVGT_PA_CLIPP_STALLED: VGT to Primitive Assembler pipe is stalled WXW)LVGT_PA_CLIPP_STARVED_BUSY: VGT to Primitive Assembler pipe is starved_busy X(X*LVGT_PA_CLIPP_STARVED_IDLE: VGT to Primitive Assembler pipe is starved_idle xYX+@VGT_PA_CLIPP_STATIC: VGT to Primitive Assembler pipe is static @ZY,=VGT_PA_CLIPS_SEND: VGT to Primitive Assembler is being sent [Z-BVGT_PA_CLIPS_STALLED: VGT to Primitive Assembler pipe is stalled [P[.LVGT_PA_CLIPS_STARVED_BUSY: VGT to Primitive Assembler pipe is starved_busy \ \/LVGT_PA_CLIPS_STARVED_IDLE: VGT to Primitive Assembler pipe is starved_idle p]\0@VGT_PA_CLIPS_STATIC: VGT to Primitive Assembler pipe is static @^]1LRBIU_FIFOS_EVENT_WINDOW_ACTIVE: RBIU Fifo generated event window is active _^2;RBIU_IM_FIFO_STARVED: rbiu immediate data fifo is starved _H_3;RBIU_IM_FIFO_STALLED: rbiu immediate data fifo is stalled ``48RBIU_DR_FIFO_STARVED: rbiu dma request fifo is starved @a`58RBIU_DR_FIFO_STALLED: rbiu dma request fifo is stalled ba6;RBIU_DI_FIFO_STARVED: rbiu draw initiator fifo is starved bHb7;RBIU_DI_FIFO_STALLED: rbiu draw initiator fifo is stalled xcc8/MC_LAT_BIN_0: Memory Controller Latency Bin 0 0dc9/MC_LAT_BIN_1: Memory Controller Latency Bin 1 dxd:/MC_LAT_BIN_2: Memory Controller Latency Bin 2 e0e;/MC_LAT_BIN_3: Memory Controller Latency Bin 3 Xfe</MC_LAT_BIN_4: Memory Controller Latency Bin 4 gf=/MC_LAT_BIN_5: Memory Controller Latency Bin 5 gXg>/MC_LAT_BIN_6: Memory Controller Latency Bin 6 hh?/MC_LAT_BIN_7: Memory Controller Latency Bin 7 0ih@(vgt_busy: Number of cycles VGT is busy ixiA4vgt_gs_busy: Number of cycles VGT GS block is busy j0jBTesvert_stalled_es_tbl: esvert transfers are stalled because of ES table being full kkCTesvert_stalled_gs_tbl: esvert transfers are stalled because of GS table being full hlkDIesvert_stalled_gs_event: esvert transfers are stalled because of events HmlEZesvert_stalled_gsprim: esvert transfers are stalled because of GS prim interface is full nmFTgsprim_stalled_es_tbl: gsprim transfers are stalled because of ES table being full nhnGTgsprim_stalled_gs_tbl: gsprim transfers are stalled because of GS table being full o@oHIgsprim_stalled_gs_event: gsprim transfers are stalled because of events ppIZgsprim_stalled_esvert: gsprim transfers are stalled because of ES vert interface is full qpJ]esthread_stalled_es_rb_full: ES thread sends are stalled because the ES ring buffer is full hrqKQesthread_stalled_spi_bp: ES thread is stalled due to back pressure from the SPI HsrLUcounters_avail_stalled: GS thread send is stalled because no counters are available (tsM\gs_rb_space_avail_stalled: GS thread send is stalled because the GS/VS ring buffer is full uptNtgs_issue_rtr_stalled: GS thread send is stalled due to something other than the counters or ring buffer being full uhuORgsthread_stalled: GS thread send is stalled. Inclusive of the 3 counters above. 8w@vPes_cache_invld_stalled: one GS thread is stalling another from starting its es cache invalidation or a GS thread is waiting on the cache to be invalidated. This counter will never be 0. 0xwQmwait_for_es_done_stalled: GS thread SM is ready to move to the next stage as soon as the ES thread finishes yxxRUcm_stalled_by_gog: the output fifo to the GOG is full and the CM wants to send data yXySZcm_reading_stalled: the GOG can accept data and the CM should be sending data, but isn't z8zTPcm_stalled_by_gsfetch_done: all CM state machines are waiting for gsfetch_done {{UAgog_vs_tbl_stalled: GOG is stalled because the VS table is full h|{VMgog_out_indx_stalled: GOG is stalled by back pressure from the output block @}|WMgog_out_prim_stalled: GOG is stalled by back pressure from the output block (~}X_gs_rb_invld_stalled: Unable to invalidate GS/VS ring buffer because invalidation fifo is full ~p~Y>gog_busy: Counts number of cycles that the GOG block is busy 8Z^reused_vs_indices: Counts number of reused indices, excluding GS scenario G and tessellation [?sclk_reg_vld_event: Counts number of cycles sclk_reg is valid h耟\Csclk_input_vld_event: Counts number of cycles sclk_input is valid 0]Asclk_core_vld_event: Counts number of cycles sclk_core is valid x^Csclk_inval_vld_event: Counts number of cycles sclk_inval is valid @_=sclk_gs_vld_event: Counts number of cycles sclk_gs is valid (("" VGT_PERFCOUNTER2_SELECT0x PERF_SEL`HGVGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE: Esthread event window is active (VGT_SPI_ESVERT_VALID: ES Vert is valid @5VGT_SPI_ESVERT_EOV: ES vert end of vector is active p1VGT_SPI_ESVERT_STALLED: ES vert pipe is stalled 0;VGT_SPI_ESVERT_STARVED_BUSY: ES vert pipe is starved busy x;VGT_SPI_ESVERT_STARVED_IDLE: ES vert pipe is starved idle 8/VGT_SPI_ESVERT_STATIC: ES vert pipe is static h6VGT_SPI_ESTHREAD_IS_EVENT: ES Thread Event Indicator 1VGT_SPI_ESTHREAD_SEND: ES Thread Send is active h 6VGT_SPI_GSPRIM_VALID: ES GS Primitive send is active ( =VGT_SPI_GSPRIM_EOV: ES GS Primitive end of vector is active h 6VGT_SPI_GSPRIM_CONT: ES GS Primitive Continued Event 4VGT_SPI_GSPRIM_STALLED: ES GS Primitive is stalled h >VGT_SPI_GSPRIM_STARVED_BUSY: ES GS Primitive is starved busy 0>VGT_SPI_GSPRIM_STARVED_IDLE: ES GS Primitive is starved idle h2VGT_SPI_GSPRIM_STATIC: ES GS Primitive is static 8HVGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE: GS Thread event window is active ?VGT_SPI_GSTHREAD_IS_EVENT: GS Thread event is being processed H0VGT_SPI_GSTHREAD_SEND: GS Thread is being sent HVGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE: VS Thread event window is active 0#VGT_SPI_VSVERT_SEND: VS vert send x+VGT_SPI_VSVERT_EOV: VS vert end of vector (1VGT_SPI_VSVERT_STALLED: VS vert pipe is stalled X;VGT_SPI_VSVERT_STARVED_BUSY: VS vert pipe is starved busy ;VGT_SPI_VSVERT_STARVED_IDLE: VS vert pipe is starved idle `/VGT_SPI_VSVERT_STATIC: VS vert pipe is static 6VGT_SPI_VSTHREAD_IS_EVENT: VS Thread Event Indicator H0VGT_SPI_VSTHREAD_SEND: VS Thread is being sent OVGT_PA_EVENT_WINDOW_ACTIVE: VGT to Primitive Assembler Event Window is active hCVGT_PA_CLIPV_SEND: VGT to Primitive Assembler clipv is being sent 0LVGT_PA_CLIPV_FIRSTVERT: VGT to Primitive Assembler clipv is the first vert BVGT_PA_CLIPV_STALLED: VGT to Primitive Assembler pipe is stalled P LVGT_PA_CLIPV_STARVED_BUSY: VGT to Primitive Assembler pipe is starved_busy !LVGT_PA_CLIPV_STARVED_IDLE: VGT to Primitive Assembler pipe is starved_idle h"@VGT_PA_CLIPV_STATIC: VGT to Primitive Assembler pipe is static 0#=VGT_PA_CLIPP_SEND: VGT to Primitive Assembler is being sent p$<VGT_PA_CLIPP_EOP: VGT to Primitive Assembler end of packet 8%DVGT_PA_CLIPP_IS_EVENT: VGT to Primitive Assembler event transition &NVGT_PA_CLIPP_NULL_PRIM: VGT to Primitive Assembler null primitive is present X'TVGT_PA_CLIPP_NEW_VTX_VECT: VGT to Primitive Assembler new vertex vector is present 0 (BVGT_PA_CLIPP_STALLED: VGT to Primitive Assembler pipe is stalled )LVGT_PA_CLIPP_STARVED_BUSY: VGT to Primitive Assembler pipe is starved_busy P *LVGT_PA_CLIPP_STARVED_IDLE: VGT to Primitive Assembler pipe is starved_idle  +@VGT_PA_CLIPP_STATIC: VGT to Primitive Assembler pipe is static ` ,=VGT_PA_CLIPS_SEND: VGT to Primitive Assembler is being sent ( -BVGT_PA_CLIPS_STALLED: VGT to Primitive Assembler pipe is stalled x .LVGT_PA_CLIPS_STARVED_BUSY: VGT to Primitive Assembler pipe is starved_busy H/LVGT_PA_CLIPS_STARVED_IDLE: VGT to Primitive Assembler pipe is starved_idle 0@VGT_PA_CLIPS_STATIC: VGT to Primitive Assembler pipe is static X1LRBIU_FIFOS_EVENT_WINDOW_ACTIVE: RBIU Fifo generated event window is active (2;RBIU_IM_FIFO_STARVED: rbiu immediate data fifo is starved `3;RBIU_IM_FIFO_STALLED: rbiu immediate data fifo is stalled 48RBIU_DR_FIFO_STARVED: rbiu dma request fifo is starved h58RBIU_DR_FIFO_STALLED: rbiu dma request fifo is stalled (6;RBIU_DI_FIFO_STARVED: rbiu draw initiator fifo is starved `7;RBIU_DI_FIFO_STALLED: rbiu draw initiator fifo is stalled 8/MC_LAT_BIN_0: Memory Controller Latency Bin 0 `9/MC_LAT_BIN_1: Memory Controller Latency Bin 1 :/MC_LAT_BIN_2: Memory Controller Latency Bin 2 @;/MC_LAT_BIN_3: Memory Controller Latency Bin 3 </MC_LAT_BIN_4: Memory Controller Latency Bin 4 @=/MC_LAT_BIN_5: Memory Controller Latency Bin 5 h>/MC_LAT_BIN_6: Memory Controller Latency Bin 6 ?/MC_LAT_BIN_7: Memory Controller Latency Bin 7 h@(vgt_busy: Number of cycles VGT is busy A4vgt_gs_busy: Number of cycles VGT GS block is busy `BTesvert_stalled_es_tbl: esvert transfers are stalled because of ES table being full 8CTesvert_stalled_gs_tbl: esvert transfers are stalled because of GS table being full DIesvert_stalled_gs_event: esvert transfers are stalled because of events PEZesvert_stalled_gsprim: esvert transfers are stalled because of GS prim interface is full 0 FTgsprim_stalled_es_tbl: gsprim transfers are stalled because of ES table being full !!GTgsprim_stalled_gs_tbl: gsprim transfers are stalled because of GS table being full h"!HIgsprim_stalled_gs_event: gsprim transfers are stalled because of events H#"IZgsprim_stalled_esvert: gsprim transfers are stalled because of ES vert interface is full 0$#J]esthread_stalled_es_rb_full: ES thread sends are stalled because the ES ring buffer is full %x$KQesthread_stalled_spi_bp: ES thread is stalled due to back pressure from the SPI %P%LUcounters_avail_stalled: GS thread send is stalled because no counters are available &0&M\gs_rb_space_avail_stalled: GS thread send is stalled because the GS/VS ring buffer is full ''Ntgs_issue_rtr_stalled: GS thread send is stalled due to something other than the counters or ring buffer being full ((ORgsthread_stalled: GS thread send is stalled. Inclusive of the 3 counters above. )(Pes_cache_invld_stalled: one GS thread is stalling another from starting its es cache invalidation or a GS thread is waiting on the cache to be invalidated. This counter will never be 0. * *Qmwait_for_es_done_stalled: GS thread SM is ready to move to the next stage as soon as the ES thread finishes ++RUcm_stalled_by_gog: the output fifo to the GOG is full and the CM wants to send data ,+SZcm_reading_stalled: the GOG can accept data and the CM should be sending data, but isn't h-,TPcm_stalled_by_gsfetch_done: all CM state machines are waiting for gsfetch_done 0.-UAgog_vs_tbl_stalled: GOG is stalled because the VS table is full /x.VMgog_out_indx_stalled: GOG is stalled by back pressure from the output block /P/WMgog_out_prim_stalled: GOG is stalled by back pressure from the output block 0(0X_gs_rb_invld_stalled: Unable to invalidate GS/VS ring buffer because invalidation fifo is full 11Y>gog_busy: Counts number of cycles that the GOG block is busy x21Z^reused_vs_indices: Counts number of reused indices, excluding GS scenario G and tessellation @32[?sclk_reg_vld_event: Counts number of cycles sclk_reg is valid 43\Csclk_input_vld_event: Counts number of cycles sclk_input is valid 4P4]Asclk_core_vld_event: Counts number of cycles sclk_core is valid 55^Csclk_inval_vld_event: Counts number of cycles sclk_inval is valid 5_=sclk_gs_vld_event: Counts number of cycles sclk_gs is valid PN $$"" xVGT_PERFCOUNTER1_SELECTМ PERF_SEL`蝞`GVGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE: Esthread event window is active 0(VGT_SPI_ESVERT_VALID: ES Vert is valid X5VGT_SPI_ESVERT_EOV: ES vert end of vector is active 1VGT_SPI_ESVERT_STALLED: ES vert pipe is stalled РX;VGT_SPI_ESVERT_STARVED_BUSY: ES vert pipe is starved busy ;VGT_SPI_ESVERT_STARVED_IDLE: ES vert pipe is starved idle Hء/VGT_SPI_ESVERT_STATIC: ES vert pipe is static 6VGT_SPI_ESTHREAD_IS_EVENT: ES Thread Event Indicator P1VGT_SPI_ESTHREAD_SEND: ES Thread Send is active  6VGT_SPI_GSPRIM_VALID: ES GS Primitive send is active HȤ =VGT_SPI_GSPRIM_EOV: ES GS Primitive end of vector is active  6VGT_SPI_GSPRIM_CONT: ES GS Primitive Continued Event P 4VGT_SPI_GSPRIM_STALLED: ES GS Primitive is stalled  >VGT_SPI_GSPRIM_STARVED_BUSY: ES GS Primitive is starved busy PЧ>VGT_SPI_GSPRIM_STARVED_IDLE: ES GS Primitive is starved idle 2VGT_SPI_GSPRIM_STATIC: ES GS Primitive is static ةPHVGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE: GS Thread event window is active ?VGT_SPI_GSTHREAD_IS_EVENT: GS Thread event is being processed X語0VGT_SPI_GSTHREAD_SEND: GS Thread is being sent (HVGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE: VS Thread event window is active Ьp#VGT_SPI_VSVERT_SEND: VS vert send +VGT_SPI_VSVERT_EOV: VS vert end of vector 8ȭ1VGT_SPI_VSVERT_STALLED: VS vert pipe is stalled ;VGT_SPI_VSVERT_STARVED_BUSY: VS vert pipe is starved busy @;VGT_SPI_VSVERT_STARVED_IDLE: VS vert pipe is starved idle x/VGT_SPI_VSVERT_STATIC: VS vert pipe is static 86VGT_SPI_VSTHREAD_IS_EVENT: VS Thread Event Indicator 0VGT_SPI_VSTHREAD_SEND: VS Thread is being sent Ȳ8OVGT_PA_EVENT_WINDOW_ACTIVE: VGT to Primitive Assembler Event Window is active CVGT_PA_CLIPV_SEND: VGT to Primitive Assembler clipv is being sent `سLVGT_PA_CLIPV_FIRSTVERT: VGT to Primitive Assembler clipv is the first vert (BVGT_PA_CLIPV_STALLED: VGT to Primitive Assembler pipe is stalled p LVGT_PA_CLIPV_STARVED_BUSY: VGT to Primitive Assembler pipe is starved_busy ȶ@!LVGT_PA_CLIPV_STARVED_IDLE: VGT to Primitive Assembler pipe is starved_idle "@VGT_PA_CLIPV_STATIC: VGT to Primitive Assembler pipe is static Xط#=VGT_PA_CLIPP_SEND: VGT to Primitive Assembler is being sent $<VGT_PA_CLIPP_EOP: VGT to Primitive Assembler end of packet ๞`%DVGT_PA_CLIPP_IS_EVENT: VGT to Primitive Assembler event transition (&NVGT_PA_CLIPP_NULL_PRIM: VGT to Primitive Assembler null primitive is present 'TVGT_PA_CLIPP_NEW_VTX_VECT: VGT to Primitive Assembler new vertex vector is present Xػ(BVGT_PA_CLIPP_STALLED: VGT to Primitive Assembler pipe is stalled ()LVGT_PA_CLIPP_STARVED_BUSY: VGT to Primitive Assembler pipe is starved_busy p*LVGT_PA_CLIPP_STARVED_IDLE: VGT to Primitive Assembler pipe is starved_idle @+@VGT_PA_CLIPP_STATIC: VGT to Primitive Assembler pipe is static ,=VGT_PA_CLIPS_SEND: VGT to Primitive Assembler is being sent Pп-BVGT_PA_CLIPS_STALLED: VGT to Primitive Assembler pipe is stalled .LVGT_PA_CLIPS_STARVED_BUSY: VGT to Primitive Assembler pipe is starved_busy h/LVGT_PA_CLIPS_STARVED_IDLE: VGT to Primitive Assembler pipe is starved_idle ž8ž0@VGT_PA_CLIPS_STATIC: VGT to Primitive Assembler pipe is static ÞÞ1LRBIU_FIFOS_EVENT_WINDOW_ACTIVE: RBIU Fifo generated event window is active HĞÞ2;RBIU_IM_FIFO_STARVED: rbiu immediate data fifo is starved ŞĞ3;RBIU_IM_FIFO_STALLED: rbiu immediate data fifo is stalled ŞPŞ48RBIU_DR_FIFO_STARVED: rbiu dma request fifo is starved ƞƞ58RBIU_DR_FIFO_STALLED: rbiu dma request fifo is stalled HǞƞ6;RBIU_DI_FIFO_STARVED: rbiu draw initiator fifo is starved ȞǞ7;RBIU_DI_FIFO_STALLED: rbiu draw initiator fifo is stalled ȞPȞ8/MC_LAT_BIN_0: Memory Controller Latency Bin 0 xɞɞ9/MC_LAT_BIN_1: Memory Controller Latency Bin 1 0ʞɞ:/MC_LAT_BIN_2: Memory Controller Latency Bin 2 ʞxʞ;/MC_LAT_BIN_3: Memory Controller Latency Bin 3 ˞0˞</MC_LAT_BIN_4: Memory Controller Latency Bin 4 X̞˞=/MC_LAT_BIN_5: Memory Controller Latency Bin 5 ̞͞>/MC_LAT_BIN_6: Memory Controller Latency Bin 6 ͞X͞?/MC_LAT_BIN_7: Memory Controller Latency Bin 7 xΞΞ@(vgt_busy: Number of cycles VGT is busy 0ϞΞA4vgt_gs_busy: Number of cycles VGT GS block is busy ОxϞBTesvert_stalled_es_tbl: esvert transfers are stalled because of ES table being full ОPОCTesvert_stalled_gs_tbl: esvert transfers are stalled because of GS table being full ў(ўDIesvert_stalled_gs_event: esvert transfers are stalled because of events ҞўEZesvert_stalled_gsprim: esvert transfers are stalled because of GS prim interface is full hӞҞFTgsprim_stalled_es_tbl: gsprim transfers are stalled because of ES table being full @ԞӞGTgsprim_stalled_gs_tbl: gsprim transfers are stalled because of GS table being full ՞ԞHIgsprim_stalled_gs_event: gsprim transfers are stalled because of events ՞X՞IZgsprim_stalled_esvert: gsprim transfers are stalled because of ES vert interface is full ֞8֞J]esthread_stalled_es_rb_full: ES thread sends are stalled because the ES ring buffer is full מ מKQesthread_stalled_spi_bp: ES thread is stalled due to back pressure from the SPI ؞מLUcounters_avail_stalled: GS thread send is stalled because no counters are available pٞ؞M\gs_rb_space_avail_stalled: GS thread send is stalled because the GS/VS ring buffer is full hڞٞNtgs_issue_rtr_stalled: GS thread send is stalled due to something other than the counters or ring buffer being full @۞ڞORgsthread_stalled: GS thread send is stalled. Inclusive of the 3 counters above. ܞ۞Pes_cache_invld_stalled: one GS thread is stalling another from starting its es cache invalidation or a GS thread is waiting on the cache to be invalidated. This counter will never be 0. xݞܞQmwait_for_es_done_stalled: GS thread SM is ready to move to the next stage as soon as the ES thread finishes XޞݞRUcm_stalled_by_gog: the output fifo to the GOG is full and the CM wants to send data 8ߞޞSZcm_reading_stalled: the GOG can accept data and the CM should be sending data, but isn't ߞTPcm_stalled_by_gsfetch_done: all CM state machines are waiting for gsfetch_done XUAgog_vs_tbl_stalled: GOG is stalled because the VS table is full VMgog_out_indx_stalled: GOG is stalled by back pressure from the output block WMgog_out_prim_stalled: GOG is stalled by back pressure from the output block pX_gs_rb_invld_stalled: Unable to invalidate GS/VS ring buffer because invalidation fifo is full 8Y>gog_busy: Counts number of cycles that the GOG block is busy Z^reused_vs_indices: Counts number of reused indices, excluding GS scenario G and tessellation h[?sclk_reg_vld_event: Counts number of cycles sclk_reg is valid 0\Csclk_input_vld_event: Counts number of cycles sclk_input is valid x]Asclk_core_vld_event: Counts number of cycles sclk_core is valid @^Csclk_inval_vld_event: Counts number of cycles sclk_inval is valid _=sclk_gs_vld_event: Counts number of cycles sclk_gs is valid @FN "" OVGT_PERFCOUNTER0_SELECTxOO PERF_SEL`PPGVGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE: Esthread event window is active @QP(VGT_SPI_ESVERT_VALID: ES Vert is valid RQ5VGT_SPI_ESVERT_EOV: ES vert end of vector is active RHR1VGT_SPI_ESVERT_STALLED: ES vert pipe is stalled xSS;VGT_SPI_ESVERT_STARVED_BUSY: ES vert pipe is starved busy 8TS;VGT_SPI_ESVERT_STARVED_IDLE: ES vert pipe is starved idle TT/VGT_SPI_ESVERT_STATIC: ES vert pipe is static U8U6VGT_SPI_ESTHREAD_IS_EVENT: ES Thread Event Indicator hVU1VGT_SPI_ESTHREAD_SEND: ES Thread Send is active (WV 6VGT_SPI_GSPRIM_VALID: ES GS Primitive send is active WpW =VGT_SPI_GSPRIM_EOV: ES GS Primitive end of vector is active X8X 6VGT_SPI_GSPRIM_CONT: ES GS Primitive Continued Event hYX 4VGT_SPI_GSPRIM_STALLED: ES GS Primitive is stalled 0ZY >VGT_SPI_GSPRIM_STARVED_BUSY: ES GS Primitive is starved busy ZxZ>VGT_SPI_GSPRIM_STARVED_IDLE: ES GS Primitive is starved idle [@[2VGT_SPI_GSPRIM_STATIC: ES GS Primitive is static \[HVGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE: GS Thread event window is active H]\?VGT_SPI_GSTHREAD_IS_EVENT: GS Thread event is being processed ^]0VGT_SPI_GSTHREAD_SEND: GS Thread is being sent ^H^HVGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE: VS Thread event window is active x__#VGT_SPI_VSVERT_SEND: VS vert send (`_+VGT_SPI_VSVERT_EOV: VS vert end of vector `p`1VGT_SPI_VSVERT_STALLED: VS vert pipe is stalled a(a;VGT_SPI_VSVERT_STARVED_BUSY: VS vert pipe is starved busy `ba;VGT_SPI_VSVERT_STARVED_IDLE: VS vert pipe is starved idle cb/VGT_SPI_VSVERT_STATIC: VS vert pipe is static c`c6VGT_SPI_VSTHREAD_IS_EVENT: VS Thread Event Indicator d d0VGT_SPI_VSTHREAD_SEND: VS Thread is being sent hedOVGT_PA_EVENT_WINDOW_ACTIVE: VGT to Primitive Assembler Event Window is active 0feCVGT_PA_CLIPV_SEND: VGT to Primitive Assembler clipv is being sent gxfLVGT_PA_CLIPV_FIRSTVERT: VGT to Primitive Assembler clipv is the first vert gHgBVGT_PA_CLIPV_STALLED: VGT to Primitive Assembler pipe is stalled hh LVGT_PA_CLIPV_STARVED_BUSY: VGT to Primitive Assembler pipe is starved_busy hih!LVGT_PA_CLIPV_STARVED_IDLE: VGT to Primitive Assembler pipe is starved_idle 0ji"@VGT_PA_CLIPV_STATIC: VGT to Primitive Assembler pipe is static jxj#=VGT_PA_CLIPP_SEND: VGT to Primitive Assembler is being sent k@k$<VGT_PA_CLIPP_EOP: VGT to Primitive Assembler end of packet ll%DVGT_PA_CLIPP_IS_EVENT: VGT to Primitive Assembler event transition Xml&NVGT_PA_CLIPP_NULL_PRIM: VGT to Primitive Assembler null primitive is present 0nm'TVGT_PA_CLIPP_NEW_VTX_VECT: VGT to Primitive Assembler new vertex vector is present nxn(BVGT_PA_CLIPP_STALLED: VGT to Primitive Assembler pipe is stalled o@o)LVGT_PA_CLIPP_STARVED_BUSY: VGT to Primitive Assembler pipe is starved_busy pp*LVGT_PA_CLIPP_STARVED_IDLE: VGT to Primitive Assembler pipe is starved_idle `qp+@VGT_PA_CLIPP_STATIC: VGT to Primitive Assembler pipe is static (rq,=VGT_PA_CLIPS_SEND: VGT to Primitive Assembler is being sent rpr-BVGT_PA_CLIPS_STALLED: VGT to Primitive Assembler pipe is stalled s8s.LVGT_PA_CLIPS_STARVED_BUSY: VGT to Primitive Assembler pipe is starved_busy tt/LVGT_PA_CLIPS_STARVED_IDLE: VGT to Primitive Assembler pipe is starved_idle Xut0@VGT_PA_CLIPS_STATIC: VGT to Primitive Assembler pipe is static (vu1LRBIU_FIFOS_EVENT_WINDOW_ACTIVE: RBIU Fifo generated event window is active vpv2;RBIU_IM_FIFO_STARVED: rbiu immediate data fifo is starved w0w3;RBIU_IM_FIFO_STALLED: rbiu immediate data fifo is stalled hxw48RBIU_DR_FIFO_STARVED: rbiu dma request fifo is starved (yx58RBIU_DR_FIFO_STALLED: rbiu dma request fifo is stalled ypy6;RBIU_DI_FIFO_STARVED: rbiu draw initiator fifo is starved z0z7;RBIU_DI_FIFO_STALLED: rbiu draw initiator fifo is stalled `{z8/MC_LAT_BIN_0: Memory Controller Latency Bin 0 |{9/MC_LAT_BIN_1: Memory Controller Latency Bin 1 |`|:/MC_LAT_BIN_2: Memory Controller Latency Bin 2 }};/MC_LAT_BIN_3: Memory Controller Latency Bin 3 @~}</MC_LAT_BIN_4: Memory Controller Latency Bin 4 ~~=/MC_LAT_BIN_5: Memory Controller Latency Bin 5 @>/MC_LAT_BIN_6: Memory Controller Latency Bin 6 h?/MC_LAT_BIN_7: Memory Controller Latency Bin 7 @(vgt_busy: Number of cycles VGT is busy Ё`A4vgt_gs_busy: Number of cycles VGT GS block is busy BTesvert_stalled_es_tbl: esvert transfers are stalled because of ES table being full CTesvert_stalled_gs_tbl: esvert transfers are stalled because of GS table being full PȃDIesvert_stalled_gs_event: esvert transfers are stalled because of events 0EZesvert_stalled_gsprim: esvert transfers are stalled because of GS prim interface is full xFTgsprim_stalled_es_tbl: gsprim transfers are stalled because of ES table being full PGTgsprim_stalled_gs_tbl: gsprim transfers are stalled because of GS table being full (HIgsprim_stalled_gs_event: gsprim transfers are stalled because of events IZgsprim_stalled_esvert: gsprim transfers are stalled because of ES vert interface is full x؈J]esthread_stalled_es_rb_full: ES thread sends are stalled because the ES ring buffer is full PKQesthread_stalled_spi_bp: ES thread is stalled due to back pressure from the SPI 0LUcounters_avail_stalled: GS thread send is stalled because no counters are available xM\gs_rb_space_avail_stalled: GS thread send is stalled because the GS/VS ring buffer is full XNtgs_issue_rtr_stalled: GS thread send is stalled due to something other than the counters or ring buffer being full PORgsthread_stalled: GS thread send is stalled. Inclusive of the 3 counters above. (Pes_cache_invld_stalled: one GS thread is stalling another from starting its es cache invalidation or a GS thread is waiting on the cache to be invalidated. This counter will never be 0. hQmwait_for_es_done_stalled: GS thread SM is ready to move to the next stage as soon as the ES thread finishes `RUcm_stalled_by_gog: the output fifo to the GOG is full and the CM wants to send data ؑ@SZcm_reading_stalled: the GOG can accept data and the CM should be sending data, but isn't TPcm_stalled_by_gsfetch_done: all CM state machines are waiting for gsfetch_done xUAgog_vs_tbl_stalled: GOG is stalled because the VS table is full PVMgog_out_indx_stalled: GOG is stalled by back pressure from the output block (WMgog_out_prim_stalled: GOG is stalled by back pressure from the output block pX_gs_rb_invld_stalled: Unable to invalidate GS/VS ring buffer because invalidation fifo is full ؖXY>gog_busy: Counts number of cycles that the GOG block is busy Z^reused_vs_indices: Counts number of reused indices, excluding GS scenario G and tessellation [?sclk_reg_vld_event: Counts number of cycles sclk_reg is valid PИ\Csclk_input_vld_event: Counts number of cycles sclk_input is valid ]Asclk_core_vld_event: Counts number of cycles sclk_core is valid `^Csclk_inval_vld_event: Counts number of cycles sclk_inval is valid (_=sclk_gs_vld_event: Counts number of cycles sclk_gs is valid `8F""" GVGT_DEBUG_REG28 G`Gdi_prim_type_p1_q"XHHvect1_used_p1_q"IHinvalid_group_p5_q"IXIshift_vect_valid_p5_q"XJJ grp_continued"KJ grp_state_sel"KXKgrp_sub_prim_type"PLLgrp_output_path"LLgrp_vr_st_gs_mode"MPMgrp_event_flag"Mgrp_components_valid"p*8""" (9VGT_DEBUG_REG2799 pipe0_dr"h: :gsc0_dr";: pipe1_dr";`;tm_pt_event_rtr"P<< pipe0_rtr"<< gsc0_rtr"=H= pipe1_rtr"@>=last_indx_of_prim_p1_q">>indices_to_send_p0_q"?H? event_flag_p1_q"8@?  eop_p1_q"@@ gs_out_prim_type_p0_q"A@Agsc_null_primitive_p0_q"@BA gsc_eop_p0_q"BBgsc_2cycle_output"C@Cgsc_2nd_cycle_p0_q"8DClast_indx_of_vsprim"DDfirst_vsprim_of_gsprim_p0_q"E@E gsc_indx_count_p0_q"Elast_vsprim_of_gsprim"X(*""" 8+VGT_DEBUG_REG26++grbm_fifo_empty",8,grbm_fifo_full"0-, grbm_fifo_we"-- grbm_fifo_re".0.draw_initiator_valid_q"8/.event_initiator_valid_q"//event_addr_valid_q"080dma_request_valid_q"010immed_data_valid_q"11 min_indx_valid_q"202 max_indx_valid_q"(32 indx_offset_valid_q"33 grbm_fifo_rdata_reg_id"404grbm_fifo_rdata_state"(54 free_cnt_q"55SPARE0"p6 6rbiu_di_fifo_we"76rbiu_dr_fifo_we"7p7rbiu_im_fifo_we"8SPARE1"@&("""  )VGT_DEBUG_REG25)x)avail_gs_rb_space_r0_q"(*SPARE"&""" 'VGT_DEBUG_REG24'`'avail_es_rb_space_r0_q"(SPARE" `""" VGT_DEBUG_REG23P frmt_busy"rcm_frmt_vert_rtr"Prcm_frmt_prim_rtr"@ prim_r3_rtr" prim_r2_rtr"8 vert_r3_rtr"  vert_r2_rtr"x vert_r1_rtr"`   vert_r0_rtr"! prim_fifo_empty"!`! prim_fifo_full"X""  vert_dr_r2_q"#"  prim_dr_r2_q"#X#  vert_dr_r1_q"P$$ vert_dr_r0_q"$$new_verts_r2_q"%P%verts_sent_r2_q"% SPARE"""" VGT_DEBUG_REG22@ cm_state0"( cm_state1" cm_state2"h  cm_state3" cm_state4"`  cm_state5"H  cm_state6" cm_state7"@ cm_state8"( cm_state9" cm_state10"h  cm_state11" cm_state12"` cm_state13"H cm_state14" cm_state15"@""" VGT_DEBUG_REG210out_indx_fifo_empty"0indx_side_fifo_empty" pipe0_dr"p( pipe1_dr" pipe2_dr"hvsthread_buff_empty"`out_indx_fifo_full"indx_side_fifo_full"` pipe0_rtr"H  pipe1_rtr"  pipe2_rtr"@ vsthread_buff_full"8  indx_count_q"indx_side_count_minus_one"@indx_side_indx_valid"@ indx_state_r2_q" indx_event_r2_q" @  eov_r2_q"0 indx_prim_type_r2_q" indx_gs_mode_r2_q" 0 continued_r2_q"( strmout_valid3_r2" strmout_valid2_r2"x(strmout_valid1_r2"strmout_valid0_r2"""" VGT_DEBUG_REG20`issue_vs_thread_cnt_q"`alloc_counter_q" curr_dealloc_distance_q"hnew_allocate_q"hcurr_slot_in_vtx_vect_q"int_vtx_counter_q"ٝx""" VGT_DEBUG_REG19p separate_out_busy" separate_out_indx_busy"xprim_buffer_empty"p prim_buffer_full"pa_clips_fifo_busy"ppa_clipp_fifo_busy"hVGT_PA_clips_rtr_q"VGT_PA_clipp_rtr_q"hspi_vsthread_fifo_busy"p spi_vsvert_fifo_busy" pa_clipv_fifo_busy"p  hold_prim"h VGT_SPI_vsthread_rtr_q" VGT_SPI_vsvert_rtr_q"pVGT_PA_clipv_rtr_q"h new_packet_q"buffered_prim_event"hbuffered_prim_null_primitive"p buffered_prim_eop"(buffered_prim_eject_vtx_vect"buffered_prim_type_event"0extra_dealloc_xfer_needed"8extra_dealloc_xfer_q"num_new_unique_rel_indx"@null_terminate_vtx_vector" filter_event"՝ٝ""" ٝVGT_DEBUG_REG18xڝ(ڝrbiu_gs_cache_inval" ۝ڝinvld_state_q"۝x۝waiting_for_gs_invld_q"xܝ(ܝgs_rb_invalidated" ݝܝes_rb_invalidated"ݝxݝinput_fifo_empty_r0"pޝ ޝinput_fifo_full_r0"ߝޝ input_fifo_free"ߝpߝ  two_valid_r0"h  one_valid_r0" invld_gs_busy"h invld_nongs_busy"`invld_tm_fifo_full"invld_tm_gs_rb_invalidated"htm_invld_gs_valid"hinvld_tm_es_rb_invalidated"tm_invld_es_valid"h cp_invld_q"`input_fifo_empty_r0_q" SPARE"֝""" P֝VGT_DEBUG_REG17ם֝gog_out_prim_rel_indx2_5_0"םXםgog_out_prim_rel_indx1_5_0"`؝؝ gog_out_prim_rel_indx0_5_0"؝gog_out_indx_13_0"0""" HÝVGT_DEBUG_REG16ÝÝ gog_busy"ĝ@ĝ gog_state_q"(ŝĝr0_rtr"ŝŝr1_rtr"pƝ Ɲr1_upstream_rtr"ǝƝr2_vs_tbl_rtr"ǝpǝ r2_prim_rtr"Xȝȝ  r2_indx_rtr"ȝȝ r2_rtr"ɝPɝ gog_tm_vs_event_rtr"Pʝɝ r3_force_vs_tbl_we_rtr"ʝʝ indx_valid_r2_q"˝P˝prim_valid_r2_q"@̝˝ valid_r2_q"̝̝prim_valid_r1_q"͝@͝indx_valid_r1_q"0Ν͝ valid_r1_q"ΝΝindx_valid_r0_q"ϝ0ϝprim_valid_r0_q" Нϝ valid_r0_q"НxН send_event_q"xѝ ѝvs_pending_state_r2_q"(ҝѝtm_gog_vs_event_valid"ҝҝgog_out_prim_state_sel"ӝ0ӝgog_out_prim_event_flag"0ԝӝgog_out_prim_eop"ԝԝgog_out_prim_eject_vtx_vect"8՝out_gog_prim_read"""" VGT_DEBUG_REG15 Pcm_busy"@counters_busy"gog_cm_output_fifo_free"Houtput_fifo_empty"@output_fifo_full"轝counters_full"@max_counters_avail"8辝 st_cut_mode_q"࿝gs_done_cnt_r0_q"8read_thread_id"0compute_mode_q" module_num_q"0gs_issued_cnt_q_4_0"x""" ȱVGT_DEBUG_REG14 p vs_invld_state_q"Ȳvs_issue_state_q"ȳpcompute_es_done_state_q"x extra_gs_rb_invld_cnt_q"(дtm_rbiu_es_rd_state_sel"ص gs_rb_invld_cnt_r0_q"0 send_event_q"0ضes_rb_invld_cnt_r0_q"ෝ smx_es_done_cnt_r0_q"8gs_rb_space_avail_r0"踝SPARE"` """ ЩVGT_DEBUG_REG13 x(gs_state10_r0_q" Ъgs_state11_r0_q"ȫxgs_state12_r0_q"p gs_state13_r0_q"Ȭ gs_state14_r0_q"pgs_state15_r0_q"hgs_tbl_wrptr_r0_q" num_gs_q"` es_split"Xes_rb_roll_over_r3"active_cm_sm_r0_q"ؠ """ (VGT_DEBUG_REG12 Сgs_state0_r0_q"x(gs_state1_r0_q" Тgs_state2_r0_q"ȣx gs_state3_r0_q"p gs_state4_r0_q"Ȥgs_state5_r0_q"pgs_state6_r0_q"hgs_state7_r0_q"gs_state8_r0_q"hgs_state9_r0_q"hcm_tm_counters_avail" gs_ready" """ `VGT_DEBUG_REG11 tm_busy"X tm_noif_busy"H tm_out_busy"es_rb_dealloc_fifo_busy"Pvs_dealloc_tbl_busy"@ vs_tbl_busy"spi_gsthread_fifo_busy"Hspi_esthread_fifo_busy"Hcm_tm_counters_busy"葝 SPARE"@ counters_busy_r0"8蒝 counters_avail_r0"蓝 counters_available_r0"@ vs_event_fifo_rtr"@蔝VGT_SPI_gsthread_rtr_q"VGT_SPI_esthread_rtr_q"H gs_issue_rtr"@tm_pt_event_rtr" vs_r0_rtr"8 gs_r0_rtr" ؘ es_r0_rtr"șxgog_tm_vs_event_rtr"p tm_rcm_gs_event_rtr"Țtm_rcm_gs_tbl_rtr"ptm_rcm_es_tbl_rtr"hvs_event_fifo_empty"vs_event_fifo_full"hes_rb_dealloc_fifo_full"hvs_dealloc_tbl_full"vs_tbl_full_r0"h es_tbl_empty"no_active_states_r0"y """ VGT_DEBUG_REG108index_buffer_depth_r1_q"8舝instanceid_r0_q"艝 gs_rb_space_avail_r3_q"@ es_rb_space_avail_r2_q"0d@z """ zVGT_DEBUG_REG9@{zindices_to_send_r2_q"{{valid_indices_r3"|@| eop_r0_q"(}| eop_indx_r3"}} eop_prim_r3"h~ ~ es_eov_r3"~es_tbl_state_r3_q"hpending_es_send_r3_q"h pending_es_flush_r3" gs_tbl_num_es_per_gs_r3_q"ȁp gs_tbl_prim_cnt_r3_q"p gs_tbl_eop_r3_q"Ȃgs_tbl_state_r3_q"ȃpgs_pending_state_r3_q"x invalidate_rb_roll_over_q" Єes_passthru_r2_q"ȅxstate_sel_r1_q"p state_sel_r0_q"Ȇnull_primitive_r0_q"Rd""" dVGT_DEBUG_REG8 ePe rcm_busy"@fercm_noif_busy"ffSPARE"g8gspi_gsprim_fifo_busy_q"@hgspi_esvert_fifo_busy_q"hhgs_tbl_valid_r3_q"i@i valid_r0_q"(ji valid_r1_q"jj valid_r2"hk k  valid_r2_q"lk r0_rtr"l`l r1_rtr"Hmm  r2_indx_rtr"mm r2_rtr"n@n es_gs_rtr"0ongs_event_fifo_rtr"ootm_rcm_gs_event_rtr"p0pgs_tbl_r3_rtr"0qpVGT_SPI_gsprim_skid_rtr_q"qqVGT_SPI_gsprim_rtr_q"r8rtm_rcm_gs_tbl_rtr"0srtm_rcm_es_tbl_rtr"ssVGT_SPI_esvert_rtr_q"t8t r2_no_bp_rtr"0uthold_for_es_flush"uugs_event_fifo_empty"v0vgsprim_buff_empty_q"(wvgsprim_buff_full_q"wwte_prim_fifo_empty"xx(xte_prim_fifo_full" yxte_vert_fifo_empty"xyte_vert_fifo_full"GS""" hSVGT_DEBUG_REG7TS grp_vr_valid"ThT pipe0_dr"PUU pipe1_dr"UU vr_grp_read"VHV pipe0_rtr"0WV pipe1_rtr"WWout_vr_indx_read"X0Xout_vr_prim_read"(YXindices_to_send_q"YY valid_indices"xZ(Z last_indx_of_prim"[Z  indx0_new_d"[p[ indx1_new_d"X\\ indx2_new_d"\\ indx2_hit_d"]P] indx1_hit_d"8^] indx0_hit_d"^^st_vertex_reuse_off_r0_q"_@_last_group_of_instance_r0_q"@`_null_primitive_r0_q"`` eop_r0_q"a8aeject_vtx_vect_r1_d"0basub_prim_type_r0_q"bbgs_scenario_a_r0_q"c0cgs_scenario_b_r0_q"ccomponents_valid_r0_q"x=H""" PHVGT_DEBUG_REG6HHreset_indx_state_q"IPIshift_vect_valid_p2_q"XJJshift_vect1_comp_en_p2_q"KJ shift_vect0_reset_match_p2_q"KhKshift_vect1_reset_match_p2_q"xL Lnum_indx_in_group_p2_q"(MLlast_group_of_inst_p2_q"MMmulti_cycle_mode_p2_q"N0Nindx_shift_is_one_p2_q"8ONindx_shift_is_two_p2_q"OOindx_stride_is_four_p2_q"P@Pshift_vect_continued_p2_q"HQPshift_event_flag_p2_q"QQreset_prim_p3"HRshift_partial_prim_p3"P;=""" @>VGT_DEBUG_REG5>>current_shift_q"?@?current_stride_pre"8@?current_stride_q"@@ first_prim_partial"A8Asecond_prim_partial"0BAcurr_prim_partial"BBnext_stride_q"C0Cnext_prim_partial"(DCafter_prim_partial"DDextract_group"E(Eshifter_word_count_q"(FEshifter_space_avail"FFshifter_load_needed"(G!shifter_waiting_for_first_load_q");""" <VGT_DEBUG_REG4<p<di_index_counter_q_15_0" =current_instance_q_15_0")""" )VGT_DEBUG_REG3x*0* pipe0_dr"+* pipe1_dr"+p+ pipe2_dr"X,, pipe3_dr",, pipe4_dr"-P- pipe5_dr"@.-grp_out_fifo_empty"..grp_out_fifo_full"/@/ pipe0_rtr"(0/  pipe1_rtr"00  pipe2_rtr"h1 1  pipe3_rtr"21  pipe4_rtr"2`2  pipe5_rtr"H33 vgt_flush_q"33strmout_flush_q"4H4di_major_mode_p1_q_0"H54 gs_mode_p1_q"55di_event_flag_p1_q"6H6di_state_sel_p1_q"@76draw_opaq_en_p1_q"77draw_opaq_active_q"8@8di_source_select_p1_q"@98ready_to_read_di"99di_first_group_of_inst_q":H:last_shift_of_instance":current_shift_is_vect1_q"8""" VGT_DEBUG_REG2( dma_busy"rbiu_dma_valid"p( rbiu_read"dma_rdreq_dr_q"pmc_rdreq_sent_cnt_q"p dma_bfa_rdreq_frozen"  bfa_dma_rdreq_freeze"x last_rdreq_in_dma_op"( dma_mask_fifo_empty_q"0dma_data_fifo_empty_q"dma_data_fifo_full"x0 stage1_dr"  stage1_rtr" p  stage2_dr"X!! stage2_rtr"!! stage3_dr""P" stage3_rtr"8#" stage4_dr"## stage4_rtr"$0$dma_skid_fifo_empty"(%$dma_skid_fifo_full"%%dma_grp_valid"x&(& grp_dma_read" '&current_data_valid"'x'second_128bit_read"h( ( mask_kill"(instances_remaining"""" VGT_DEBUG_REG1 8rbiu_im_fifo_empty"0rbiu_im_fifo_full"rbiu_di_fifo_empty"0rbiu_di_fifo_full"(rbiu_dr_fifo_empty"rbiu_dr_fifo_full"x(rbiu_grp_di_valid" grp_rbiu_di_read"xdma_grp_valid"p   grp_dma_read"   grp_vr_valid" p  vr_grp_read"`   grp_pt_valid"  pt_grp_read" X  grp_te_valid"H  te_grp_read" vr_out_indx_valid" H out_vr_indx_read"@ vr_out_prim_valid"out_vr_prim_read"@pt_out_indx_valid"8out_pt_data_read"pt_out_prim_valid"8out_pt_prim_read"0te_out_data_valid"out_te_data_read"0 grp_gs_valid"  gs_grp_read"xgog_out_indx_valid"p out_gog_indx_read"gog_out_prim_valid"pout_gog_prim_read"8""" VGT_DEBUG_REG0 0vgt_busy_extended"vgt_nodma_busy_extended"8 vgt_busy"(vgt_nodma_busy" rbiu_busy"p dma_request_busy" dma_busy"h mc_xl8r_busy"X grp_busy"  vr_grp_busy"P  pt_grp_busy"8  te_grp_busy" gs_busy"x0  rcm_busy"tm_busy"pcm_busy"X gog_busy" frmt_busy"Pinvld_gs_busy"@SPARE"invld_nongs_busy"@combined_out_busy"@spi_vs_interfaces_busy"pa_interfaces_busy"@ reg_clk_busy"8input_clk_busy"core_clk_busy"8 gs_clk_busy"(inval_clk_busy"sclk_core_vld"p( sclk_gs_vld"sclk_inval_vld"("" XVGT_CNTL_STATUS VGT_OUT_INDX_BUSY"X VGT_OUT_BUSY"H VGT_PT_BUSY" VGT_TE_BUSY"@ VGT_VR_BUSY"0 VGT_GRP_BUSY"VGT_DMA_REQ_BUSY"0 VGT_DMA_BUSY"  VGT_GS_BUSY"x  VGT_BUSY""" VGT_DEBUG_DATAH DATApڜ0"" VGT_DEBUG_CNTLVGT_DEBUG_INDXٜڜ||"" 8ۜCGTT_VGT_CLK_CTRL ۜۜ ON_DELAY"ܜ0ܜOFF_HYSTERESIS"(ݜܜSOFT_OVERRIDE7"ݜݜSOFT_OVERRIDE6"xޜ(ޜSOFT_OVERRIDE5"ߜޜ GS_OVERRIDE"ߜpߜINVAL_OVERRIDE"hCORE_OVERRIDE"RBIU_INPUT_OVERRIDE"h REG_OVERRIDE"8֜xٜ88"" ٜVGT_GS_MAX_VERT_OUT ڜ MAX_VERT_OUT"Ԝ֜xx"" לVGT_COHER_INVAL_DURATIONל`ל INVAL_DURATION_VC"X؜؜ INVAL_DURATION_TC"؜ INVAL_DURATION_ALL"0Ӝ(՜00"" ՜&VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE՜ VERTEX_STRIDE"ќӜ,,"" Ԝ+VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZEhԜ SIZE"@М0Ҝ(("" ҜVGT_STRMOUT_DRAW_OPAQUE_OFFSETҜ OFFSET"ΜМll"" ќ!VGT_STRMOUT_BUFFER_FILLED_SIZE_3pќ SIZE"P͜@Ϝhh"" Ϝ!VGT_STRMOUT_BUFFER_FILLED_SIZE_2Ϝ SIZE"˜͜dd"" (Μ!VGT_STRMOUT_BUFFER_FILLED_SIZE_1Μ SIZE"`ʜP̜``"" ̜!VGT_STRMOUT_BUFFER_FILLED_SIZE_0͜ SIZE"ȜʜPP"" 8˜VGT_STRMOUT_BASE_OFFSET_HI_3˜ BASE_OFFSET"pǜ`ɜLL"" ɜVGT_STRMOUT_BASE_OFFSET_HI_2ʜ BASE_OFFSET"ŜǜHH"" HȜVGT_STRMOUT_BASE_OFFSET_HI_1Ȝ BASE_OFFSET"ĜpƜDD"" ƜVGT_STRMOUT_BASE_OFFSET_HI_0(ǜ BASE_OFFSET"ÜŜ"" XŜVGT_STRMOUT_BASE_OFFSET_3Ŝ BASE_OFFSET"Ü"" ÜVGT_STRMOUT_BASE_OFFSET_2@Ĝ BASE_OFFSET"8 œ"" xœVGT_STRMOUT_BASE_OFFSET_1œ BASE_OFFSET"輜"" VGT_STRMOUT_BASE_OFFSET_0` BASE_OFFSET"x`  "" VGT_STRMOUT_BUFFER_ENX BUFFER_0_EN" BUFFER_1_EN"P BUFFER_2_EN" BUFFER_3_EN""" HVGT_STRMOUT_BUFFER_BASE_3 BASE""" غVGT_STRMOUT_BUFFER_BASE_20 BASE"("" hVGT_STRMOUT_BUFFER_BASE_1 BASE"؊؊"" VGT_STRMOUT_BUFFER_BASE_0P BASE"H0"" VGT_STRMOUT_VTX_STRIDE_3ග STRIDE"ز"" VGT_STRMOUT_VTX_STRIDE_2p STRIDE"hP"" VGT_STRMOUT_VTX_STRIDE_1 STRIDE"౜ԊԊ"" 8VGT_STRMOUT_VTX_STRIDE_0 STRIDE"p  "" ȰVGT_STRMOUT_BUFFER_OFFSET_3 OFFSET""" XVGT_STRMOUT_BUFFER_OFFSET_2 OFFSET""" 譜VGT_STRMOUT_BUFFER_OFFSET_1@ OFFSET"8 ܊܊"" xVGT_STRMOUT_BUFFER_OFFSET_0Ь OFFSET"Ȩ"" VGT_STRMOUT_BUFFER_SIZE_3` SIZE"X@"" VGT_STRMOUT_BUFFER_SIZE_2 SIZE"襜Ч"" (VGT_STRMOUT_BUFFER_SIZE_1 SIZE"P`ЊЊ"" VGT_STRMOUT_BUFFER_SIZE_0 SIZE"@ȣ"" VGT_STRMOUT_ENp STREAMOUTPSTREAMOUT OFF STREAMOUT ON ؝؈؈"" VGT_MC_LAT_CNTL`MC_TIME_STAMP_RESX"0 -> 992 max latency, step of 32 "0 -> 496 max latency, step of 16 H"0 -> 248 max latency, step of 8 "0 -> 124 max latency, step of 4 pPԈԈ"" VGT_GS_VERTEX_REUSE VERT_REUSE"蜜"" 8VGT_GS_PER_VS GS_PER_VS"̈̈"" ЛVGT_ES_PER_GS( ES_PER_GS"ȈȈ"" hVGT_GS_PER_ES GS_PER_ES"ĈĈ"" VGT_CACHE_INVALIDATIONX8CACHE_INVALIDATION ДVC_ONLY: VC_ONLY hTC_ONLY: TC_ONLY VC_AND_TC: VC_AND_TC VS_NO_EXTRA_BUFFER"XAUTO_INVLD_EN"H  USE_GS_DONE" DIS_RANGE_FULL_INVLD"P GS_LATE_ALLOC_EN"H|8ll"" VGT_GS_OUT_PRIM_TYPE萜8 OUTPRIM_TYPEؑPOINTLIST: POINTLIST x LINESTRIP: LINESTRIP TRISTRIP: TRISTRIP (z|@@"" } VGT_GS_MODE 8`}}MODE@~}GS_OFF: GS_OFF ~~GS_SCENARIO_A: GS_SCENARIO_A 0GS_SCENARIO_B: GS_SCENARIO_B GS_SCENARIO_G: GS_SCENARIO_G ؀ ES_PASSTHRUp passthru_dis  passthru_en (` CUT_MODEHGS_CUT_1024: GS_CUT_1024 胜GS_CUT_512: GS_CUT_512 0GS_CUT_256: GS_CUT_256 ЄGS_CUT_128: GS_CUT_128 ȅ RESERVED_0"h MODE_HI"  RESERVED_1"`  GS_C_PACK_EN"P  RESERVED_2"  COMPUTE_MODE@ compute_dis ؉ compute_en xȊFAST_COMPUTE_MODE`fast_compute_dis fast_compute_en ؍PELEMENT_INFO_EN@茜element_info_en_dis element_info_en_en 0PARTIAL_THD_AT_EOI Ȏpartial_thd_at_eoi_dis hpartial_thd_at_eoi_en hwzTT"" zGC_USER_SHADER_PIPE_CONFIG{P{INACTIVE_QD_PIPES"{INACTIVE_SIMDS"PuwPP"" 8xCC_GC_SHADER_PIPE_CONFIGxx WRITE_DIS"y0yINACTIVE_QD_PIPES"yINACTIVE_SIMDS"su"" vVGT_LAST_COPY_STATEvpv SRC_STATE_ID"w DST_STATE_ID"XrHt"" tVGT_DRAW_INIT_FIFO_DEPTHtDRAW_INIT_FIFO_DEPTH"pr"" (sVGT_DMA_REQ_FIFO_DEPTHsDMA_REQ_FIFO_DEPTH"poXq"" qVGT_DMA_DATA_FIFO_DEPTHr DMA_DATA_FIFO_DEPTH"Jo"" @pVGT_VTX_VECT_EJECT_REGp PRIM_COUNT"%J<<"" PKVGT_GROUP_VECT_1_FMT_CNTLSKKX_CONV L8L_VGT_GRP_INDEX_16: VGT_GRP_INDEX_16 16 bits from stream with index offset and clamp M M_VGT_GRP_INDEX_32: VGT_GRP_INDEX_32 32 bits from stream with index offset and clamp NNRVGT_GRP_UINT_16: VGT_GRP_UINT_16 16 bits from stream as unsigned int pONRVGT_GRP_UINT_32: VGT_GRP_UINT_32 32 bits from stream as unsigned int HPOPVGT_GRP_SINT_16: VGT_GRP_SINT_16 16 bits from stream as signed int QPPVGT_GRP_SINT_32: VGT_GRP_SINT_32 32 bits from stream as signed int QhQLVGT_GRP_FLOAT_32: VGT_GRP_FLOAT_32 32 bits from stream as float R8RTVGT_GRP_AUTO_PRIM: VGT_GRP_AUTO_PRIM 24 bits from auto primitive counter SjVGT_GRP_FIX_1_23_TO_FLOAT: VGT_GRP_FIX_1_23_TO_FLOAT 24 bit barycentric value from tessellation engine XTT X_OFFSET"\TTY_CONV U@U_VGT_GRP_INDEX_16: VGT_GRP_INDEX_16 16 bits from stream with index offset and clamp V(V_VGT_GRP_INDEX_32: VGT_GRP_INDEX_32 32 bits from stream with index offset and clamp WWRVGT_GRP_UINT_16: VGT_GRP_UINT_16 16 bits from stream as unsigned int xXWRVGT_GRP_UINT_32: VGT_GRP_UINT_32 32 bits from stream as unsigned int PYXPVGT_GRP_SINT_16: VGT_GRP_SINT_16 16 bits from stream as signed int (ZYPVGT_GRP_SINT_32: VGT_GRP_SINT_32 32 bits from stream as signed int ZpZLVGT_GRP_FLOAT_32: VGT_GRP_FLOAT_32 32 bits from stream as float [@[TVGT_GRP_AUTO_PRIM: VGT_GRP_AUTO_PRIM 24 bits from auto primitive counter \jVGT_GRP_FIX_1_23_TO_FLOAT: VGT_GRP_FIX_1_23_TO_FLOAT 24 bit barycentric value from tessellation engine `]]  Y_OFFSET"e]^Z_CONV ^H^_VGT_GRP_INDEX_16: VGT_GRP_INDEX_16 16 bits from stream with index offset and clamp _0__VGT_GRP_INDEX_32: VGT_GRP_INDEX_32 32 bits from stream with index offset and clamp ``RVGT_GRP_UINT_16: VGT_GRP_UINT_16 16 bits from stream as unsigned int a`RVGT_GRP_UINT_32: VGT_GRP_UINT_32 32 bits from stream as unsigned int XbaPVGT_GRP_SINT_16: VGT_GRP_SINT_16 16 bits from stream as signed int 0cbPVGT_GRP_SINT_32: VGT_GRP_SINT_32 32 bits from stream as signed int dxcLVGT_GRP_FLOAT_32: VGT_GRP_FLOAT_32 32 bits from stream as float dHdTVGT_GRP_AUTO_PRIM: VGT_GRP_AUTO_PRIM 24 bits from auto primitive counter ejVGT_GRP_FIX_1_23_TO_FLOAT: VGT_GRP_FIX_1_23_TO_FLOAT 24 bit barycentric value from tessellation engine hf f Z_OFFSET"nfgW_CONV gPg_VGT_GRP_INDEX_16: VGT_GRP_INDEX_16 16 bits from stream with index offset and clamp h8h_VGT_GRP_INDEX_32: VGT_GRP_INDEX_32 32 bits from stream with index offset and clamp i iRVGT_GRP_UINT_16: VGT_GRP_UINT_16 16 bits from stream as unsigned int jiRVGT_GRP_UINT_32: VGT_GRP_UINT_32 32 bits from stream as unsigned int `kjPVGT_GRP_SINT_16: VGT_GRP_SINT_16 16 bits from stream as signed int 8lkPVGT_GRP_SINT_32: VGT_GRP_SINT_32 32 bits from stream as signed int mlLVGT_GRP_FLOAT_32: VGT_GRP_FLOAT_32 32 bits from stream as float mPmTVGT_GRP_AUTO_PRIM: VGT_GRP_AUTO_PRIM 24 bits from auto primitive counter (njVGT_GRP_FIX_1_23_TO_FLOAT: VGT_GRP_FIX_1_23_TO_FLOAT 24 bit barycentric value from tessellation engine (o W_OFFSET"x&88"" X&VGT_GROUP_VECT_0_FMT_CNTL.&&X_CONV '@'_VGT_GRP_INDEX_16: VGT_GRP_INDEX_16 16 bits from stream with index offset and clamp (((_VGT_GRP_INDEX_32: VGT_GRP_INDEX_32 32 bits from stream with index offset and clamp ))RVGT_GRP_UINT_16: VGT_GRP_UINT_16 16 bits from stream as unsigned int x*)RVGT_GRP_UINT_32: VGT_GRP_UINT_32 32 bits from stream as unsigned int P+*PVGT_GRP_SINT_16: VGT_GRP_SINT_16 16 bits from stream as signed int (,+PVGT_GRP_SINT_32: VGT_GRP_SINT_32 32 bits from stream as signed int ,p,LVGT_GRP_FLOAT_32: VGT_GRP_FLOAT_32 32 bits from stream as float -@-TVGT_GRP_AUTO_PRIM: VGT_GRP_AUTO_PRIM 24 bits from auto primitive counter .jVGT_GRP_FIX_1_23_TO_FLOAT: VGT_GRP_FIX_1_23_TO_FLOAT 24 bit barycentric value from tessellation engine `// X_OFFSET"7/0Y_CONV 0P0_VGT_GRP_INDEX_16: VGT_GRP_INDEX_16 16 bits from stream with index offset and clamp 181_VGT_GRP_INDEX_32: VGT_GRP_INDEX_32 32 bits from stream with index offset and clamp 2 2RVGT_GRP_UINT_16: VGT_GRP_UINT_16 16 bits from stream as unsigned int 32RVGT_GRP_UINT_32: VGT_GRP_UINT_32 32 bits from stream as unsigned int `43PVGT_GRP_SINT_16: VGT_GRP_SINT_16 16 bits from stream as signed int 854PVGT_GRP_SINT_32: VGT_GRP_SINT_32 32 bits from stream as signed int 65LVGT_GRP_FLOAT_32: VGT_GRP_FLOAT_32 32 bits from stream as float 6P6TVGT_GRP_AUTO_PRIM: VGT_GRP_AUTO_PRIM 24 bits from auto primitive counter (7jVGT_GRP_FIX_1_23_TO_FLOAT: VGT_GRP_FIX_1_23_TO_FLOAT 24 bit barycentric value from tessellation engine p8(8  Y_OFFSET"@89Z_CONV 9X9_VGT_GRP_INDEX_16: VGT_GRP_INDEX_16 16 bits from stream with index offset and clamp :@:_VGT_GRP_INDEX_32: VGT_GRP_INDEX_32 32 bits from stream with index offset and clamp ;(;RVGT_GRP_UINT_16: VGT_GRP_UINT_16 16 bits from stream as unsigned int <<RVGT_GRP_UINT_32: VGT_GRP_UINT_32 32 bits from stream as unsigned int h=<PVGT_GRP_SINT_16: VGT_GRP_SINT_16 16 bits from stream as signed int @>=PVGT_GRP_SINT_32: VGT_GRP_SINT_32 32 bits from stream as signed int ?>LVGT_GRP_FLOAT_32: VGT_GRP_FLOAT_32 32 bits from stream as float ?X?TVGT_GRP_AUTO_PRIM: VGT_GRP_AUTO_PRIM 24 bits from auto primitive counter 0@jVGT_GRP_FIX_1_23_TO_FLOAT: VGT_GRP_FIX_1_23_TO_FLOAT 24 bit barycentric value from tessellation engine xA0A Z_OFFSET"IABW_CONV C`B_VGT_GRP_INDEX_16: VGT_GRP_INDEX_16 16 bits from stream with index offset and clamp CHC_VGT_GRP_INDEX_32: VGT_GRP_INDEX_32 32 bits from stream with index offset and clamp D0DRVGT_GRP_UINT_16: VGT_GRP_UINT_16 16 bits from stream as unsigned int EERVGT_GRP_UINT_32: VGT_GRP_UINT_32 32 bits from stream as unsigned int pFEPVGT_GRP_SINT_16: VGT_GRP_SINT_16 16 bits from stream as signed int HGFPVGT_GRP_SINT_32: VGT_GRP_SINT_32 32 bits from stream as signed int HGLVGT_GRP_FLOAT_32: VGT_GRP_FLOAT_32 32 bits from stream as float H`HTVGT_GRP_AUTO_PRIM: VGT_GRP_AUTO_PRIM 24 bits from auto primitive counter 8IjVGT_GRP_FIX_1_23_TO_FLOAT: VGT_GRP_FIX_1_23_TO_FLOAT 24 bit barycentric value from tessellation engine 8J W_OFFSET"h44"" HVGT_GROUP_VECT_1_CNTL COMP_X_ENx0 disable enable ` COMP_Y_EN8  disable enable " !h! COMP_Z_EN!! disable @"enable H$"(# COMP_W_EN#p# disable $enable $$STRIDE"@%SHIFT"00"" 8VGT_GROUP_VECT_0_CNTL COMP_X_ENh  disable enable P COMP_Y_EN( disable penable xX COMP_Z_EN disable 0enable 8 COMP_W_EN` disable enable STRIDE"0SHIFT"x,,"" VGT_GROUP_DECR DECR"`(("" `VGT_GROUP_FIRST_DECR FIRST_DECR"$$"" (VGT_GROUP_PRIM_TYPEx PRIM_TYPEp$VGT_GRP_3D_POINT: VGT_GRP_3D_POINT "VGT_GRP_3D_LINE: VGT_GRP_3D_LINE ` VGT_GRP_3D_TRI: VGT_GRP_3D_TRI h"VGT_GRP_3D_RECT: VGT_GRP_3D_RECT "VGT_GRP_3D_QUAD: VGT_GRP_3D_QUAD X2VGT_GRP_2D_COPY_RECT_V0: VGT_GRP_2D_COPY_RECT_V0 2VGT_GRP_2D_COPY_RECT_V1: VGT_GRP_2D_COPY_RECT_V1 82VGT_GRP_2D_COPY_RECT_V2: VGT_GRP_2D_COPY_RECT_V2 2VGT_GRP_2D_COPY_RECT_V3: VGT_GRP_2D_COPY_RECT_V3 8 ,VGT_GRP_2D_FILL_RECT: VGT_GRP_2D_FILL_RECT H "VGT_GRP_2D_LINE: VGT_GRP_2D_LINE  VGT_GRP_2D_TRI: VGT_GRP_2D_TRI 8 2VGT_GRP_PRIM_INDEX_LINE: VGT_GRP_PRIM_INDEX_LINE ` 0VGT_GRP_PRIM_INDEX_TRI: VGT_GRP_PRIM_INDEX_TRI 2VGT_GRP_PRIM_INDEX_QUAD: VGT_GRP_PRIM_INDEX_QUAD `*VGT_GRP_3D_LINE_ADJ: VGT_GRP_3D_LINE_ADJ (VGT_GRP_3D_TRI_ADJ: VGT_GRP_3D_TRI_ADJ  RETAIN_ORDER h IReorder strip/fan/loop/polygon into lists with correct provoking vertex 8 ARetain primitive index order as they appear in the input stream  ` RETAIN_QUADS Decompose quads into triangles P 3Retain quads (legal only for tessellation engine)  ` PRIM_ORDER VGT_GRP_LIST: VGT_GRP_LIST HVGT_GRP_STRIP: VGT_GRP_STRIP HVGT_GRP_FAN: VGT_GRP_FAN VGT_GRP_LOOP: VGT_GRP_LOOP 0"VGT_GRP_POLYGON: VGT_GRP_POLYGON p  "" VGT_HOS_REUSE_DEPTH REUSE_DEPTH""" XVGT_HOS_MIN_TESS_LEVEL MIN_TESS""" VGT_HOS_MAX_TESS_LEVEL@ MAX_TESS"x("" x VGT_HOS_CNTL TESS_MODE""" HVGT_OUTPUT_PATH_CNTL PATH_SELECT0.VGT_OUTPATH_VTX_REUSE: VGT_OUTPATH_VTX_REUSE P*VGT_OUTPATH_TESS_EN: VGT_OUTPATH_TESS_EN ,VGT_OUTPATH_PASSTHRU: VGT_OUTPATH_PASSTHRU H,VGT_OUTPATH_GS_BLOCK: VGT_OUTPATH_GS_BLOCK PP"" P VGT_ENHANCEMI_TIMESTAMP_RES@.0 -> 992 Clocks latency range in steps of 32 h.0 -> 496 Clocks latency range in steps of 16 .0 -> 248 Clocks latency range in steps of 8 h.0 -> 124 Clocks latency range in steps of 4 0MISC"hX"" VGT_MULTI_PRIM_IB_RESET_ENP RESET_ENmulti_prim reset off 8multi_prim reset on   "" @VGT_MULTI_PRIM_IB_RESET_INDX RESET_INDX"xh\\"" VGT_OUT_DEALLOC_CNTL DEALLOC_DIST"XX"" HVGT_VERTEX_REUSE_BLOCK_CNTLVTX_REUSE_DEPTH""" VGT_INDX_OFFSET0 INDX_OFFSET"@ "" pVGT_MIN_VTX_INDX MIN_INDX"ߛ"" VGT_MAX_VTX_INDX` MAX_INDX"`ޛH"" VGT_INSTANCE_STEP_RATE_1 STEP_RATE"ۛޛ"" 0ߛVGT_INSTANCE_STEP_RATE_0ߛ STEP_RATE"PٛPܛ"" ܛVGT_REUSE_OFFܛ@ݛ REUSE_OFFݛݛ Reuse on ޛ Reuse off ֛ٛ"" ڛVGT_VTX_CNT_ENpڛڛ VTX_CNT_ENHۛۛ Auto off ۛ Auto on כ"" hכVGT_PRIMITIVEID_ENכ؛PRIMITIVEID_EN؛X؛suppress PrimitiveID output ٛoutput primitiveID XX"" PVGT_PRIMITIVE_TYPE PRIM_TYPE8JDI_PT_NONE: DI_PT_NONE None (does not create draw trigger) ;DI_PT_POINTLIST: DI_PT_POINTLIST Point List @›9DI_PT_LINELIST: DI_PT_LINELIST Line List ۛ;DI_PT_LINESTRIP: DI_PT_LINESTRIP Line Strip ÛHÛ7DI_PT_TRILIST: DI_PT_TRILIST Tri List ěě5DI_PT_TRIFAN: DI_PT_TRIFAN Tri Fan @śě9DI_PT_TRISTRIP: DI_PT_TRISTRIP Tri Strip ƛś:DI_PT_UNUSED_0: DI_PT_UNUSED_0 Reserved 1 ƛHƛ:DI_PT_UNUSED_1: DI_PT_UNUSED_1 Reserved 2 ǛǛ :DI_PT_UNUSED_2: DI_PT_UNUSED_2 Reserved 3 PțǛ FDI_PT_LINELIST_ADJ: DI_PT_LINELIST_ADJ Adjacent Line List ɛț HDI_PT_LINESTRIP_ADJ: DI_PT_LINESTRIP_ADJ Adjacent Line Strip ɛhɛ DDI_PT_TRILIST_ADJ: DI_PT_TRILIST_ADJ Adjacent Tri List ʛ0ʛ FDI_PT_TRISTRIP_ADJ: DI_PT_TRISTRIP_ADJ Adjacent Tri Strip x˛˛:DI_PT_UNUSED_3: DI_PT_UNUSED_3 Reserved 3 8̛˛:DI_PT_UNUSED_4: DI_PT_UNUSED_4 Reserved 4 ̛͛UDI_PT_TRI_WITH_WFLAGS: DI_PT_TRI_WITH_WFLAGS Tri List w/Flags (legacy R128) ͛`͛9DI_PT_RECTLIST: DI_PT_RECTLIST Rect List Λ Λ9DI_PT_LINELOOP: DI_PT_LINELOOP Line LOOP XϛΛ9DI_PT_QUADLIST: DI_PT_QUADLIST Quad List Лϛ;DI_PT_QUADSTRIP: DI_PT_QUADSTRIP Quad Strip Л`Л6DI_PT_POLYGON: DI_PT_POLYGON Polygon ћ ћPDI_PT_2D_COPY_RECT_LIST_V0: DI_PT_2D_COPY_RECT_LIST_V0 2D Copy Rect List V0 қћPDI_PT_2D_COPY_RECT_LIST_V1: DI_PT_2D_COPY_RECT_LIST_V1 2D Copy Rect List V1 `ӛқPDI_PT_2D_COPY_RECT_LIST_V2: DI_PT_2D_COPY_RECT_LIST_V2 2D Copy Rect List V2 8ԛӛPDI_PT_2D_COPY_RECT_LIST_V3: DI_PT_2D_COPY_RECT_LIST_V3 2D Copy Rect List V3 ՛ԛJDI_PT_2D_FILL_RECT_LIST: DI_PT_2D_FILL_RECT_LIST 2D Fill Rect List ՛P՛BDI_PT_2D_LINE_STRIP: DI_PT_2D_LINE_STRIP 2D Line Strip ֛EDI_PT_2D_TRI_STRIP: DI_PT_2D_TRI_STRIP 2D Triangle Strip tt"" ཛVGT_NUM_INSTANCES8 NUM_INSTANCES"(pp"" xVGT_NUM_INDICESм NUM_INDICES"P0\\"" VGT_INDEX_TYPEع INDEX_TYPE躛h>DI_INDEX_SIZE_16_BIT: DI_INDEX_SIZE_16_BIT 16 bits per index 0>DI_INDEX_SIZE_32_BIT: DI_INDEX_SIZE_32_BIT 32 bits per index 赛ȷ"" VGT_IMMED_DATAp DATA"`xx"" VGT_DMA_MAX_SIZE MAX_SIZE"tt"" H VGT_DMA_SIZE NUM_INDICES"h"" سVGT_DMA_NUM_INSTANCES0 NUM_INSTANCES"ଛ||"" 0VGT_DMA_INDEX_TYPE0Э INDEX_TYPE)VGT_INDEX_16: VGT_INDEX_16 16-bit index Ȯ)VGT_INDEX_32: VGT_INDEX_32 32-bit index Я SWAP_MODE.VGT_DMA_SWAP_NONE: VGT_DMA_SWAP_NONE No swap `аOVGT_DMA_SWAP_16_BIT: VGT_DMA_SWAP_16_BIT 16-bit swap 0xAABBCCDD -> 0xBBAADDCC 8OVGT_DMA_SWAP_32_BIT: VGT_DMA_SWAP_32_BIT 32-bit swap 0xAABBCCDD -> 0xDDCCBBAA KVGT_DMA_SWAP_WORD: VGT_DMA_SWAP_WORD word swap 0xAABBCCDD -> 0xCCDDAABB x"" ȫ VGT_DMA_BASE BASE_ADDR"("" `VGT_DMA_BASE_HI BASE_ADDR"s"" VGT_EVENT_ADDRESS_REGP ADDRESS_LOW"gs"" sVGT_EVENT_INITIATORছ8tt EVENT_TYPE/0ut&Reserved_0x00: Reserved -- available uxu&Reserved_0x01: Reserved -- available v(v&Reserved_0x02: Reserved -- available @wv&Reserved_0x03: Reserved -- available xwCACHE_FLUSH_TS: Destination Cache Flush with Timestamp -- Inserted by the driver to cause the CBs, DBs, and SX to flush all prior rendering in any destination cache, wait for write confirm, then signal the CP. yxhCONTEXT_DONE: GFXDEC Context Done -- Inserted by the CP on the first GFXDEC state update after a draw. zyCACHE_FLUSH: Destination Caches Flushed -- Inserted by the driver to cause the CBs, DBs, and SX to flush all prior rendering in any destination cache to memory (No Timestamp is Generated). {{%VIZQUERY_START: No longer supported (|{#VIZQUERY_END: No longer supported }p| SC_WAIT_WC: SC Wait for WC from CP -- Inserted by the CP to inform the SC to wait for the write confirm signal (wire) from the CP before submitting future pixel vectors. This is used to synchronize 2D source surface (brush, a.ka. texture) with user of that surface. ~~ MPASS_PS_CP_REFETCH: Multi-Pass Pixel Shader CP Refetch -- Inserted by the driver to inform the SC it needs to report to CP to refetch buffer for multi-pass pixel shader or continue. 8@ MPASS_PS_RST_START: Multi-Pass Pixel Shader Reset Start -- Inserted by the driver just before an INDIRECT_BUFFER_MP packet to instruct the SC to reset the multi-pass start pixel vector. h MPASS_PS_INCR_START: Multi-Pass Pixel Shader Increment Start -- Inserted by the driver to instruct the SC to increment the multi-pass start vector by vectors_per_pass. ` tRST_PIX_CNT: Reset SQ's auto Pixel Counter AND reset SC's multi-pass pixel vector count -- Inserted by the driver. 0HRST_VTX_CNT: Reset SQ's auto Vertex Counter -- Inserted by the driver. xgVS_PARTIAL_FLUSH: Used to flush all work between the CP and the ES, GS, VS shaders including the VGT. 8hPS_PARTIAL_FLUSH: Used to flush all work between the CP and the ES, GS, VS, PS shaders including scan conversion, primitive assembly, and VGT. 腛&Reserved_0x11: Reserved -- available 0&Reserved_0x12: Reserved -- available H&Reserved_0x13: Reserved -- available ЈCACHE_FLUSH_AND_INV_TS_EVENT: Destination Cache Flush and Invalidate with Timestamp -- Inserted by the driver to cause the CBs, DBs, and SX to flush and invalidate all prior rendering in any destination cache, wait for write confirm, then signal the CP. ZPASS_DONE: Write ZPASS counts to memory -- Inserted by the driver to instruct the DBs to write out the ZPASS counters to memory. Used to support DX10 occlusion queries. pHCACHE_FLUSH_AND_INV_EVENT: Destination Cache Flush and Invalidate -- Inserted by the driver to cause the CBs, DBs, and SX to flush and invalidated all prior rendering in any destination cache to memory (No Timestamp is Generated). X^PERFCOUNTER_START: Start enabled event based Performance counters -- Inserted by the driver. PsPERFCOUNTER_STOP: Stop enabled event based Performance counters that are event-enabled -- Inserted by the driver. LPIPELINESTAT_START: Start pipeline/strmout stat -- Inserted by the driver. hKPIPELINESTAT_STOP: Stop pipeline/strmout stat -- Inserted by the driver. 8PERFCOUNTER_SAMPLE: Sample the performance counters of all blocks -- Inserted by the driver to read the performance counters. @~FLUSH_ES_OUTPUT: Flush Export Shader Output -- Inserted by the VGT to instruct the SMX to flush all the ES output to memory. HFLUSH_GS_OUTPUT: Flush Geometry Shader Output -- Inserted by the VGT to instruct the SMX to flush all the GS output to memory. XPSAMPLE_PIPELINESTAT: Sample Pipeline Statistics counters -- Inserted by the driver to request the GPU to sample counters associated with pipelinestats. The CP will subsequently write them to memory. SO_VGTSTREAMOUT_FLUSH: VGT Streamout Flush -- This event will cause VGT to update the read only offsets registers and then send a VGT_CP_strmout_flushed to instruct the CP to read the offsets. 蔛 SAMPLE_STREAMOUTSTATS: Sample Streamout Statitics counters -- Inserted by the driver to request the GPU to sample counters associated with streamout. The CP will subsequently write them to memory. 88!RESET_VTX_CNT: Reset Vertex Count -- Inserted by the driver to reset the auto index count for vertex count. There are tow counters one for gs and non-gs and these should be reset seperately H"BLOCK_CONTEXT_DONE: Block Managed State (SQCONSDEC) Context Done - Inserted by the CP on the first SQCONSDEC constant update after a draw. #*Reserved_0x23: Reserved -- not available @${VGT_FLUSH: VGT Flush - Inserted by the driver to cause the VGT to be flushed. Used when GS ring buffer sizes are changed @%*Reserved_0x25: Reserved -- not available p&=SQ_NON_EVENT: SQ Non-Event -- This event is reserved for SQ 'SC_SEND_DB_VPZ: SC Send Depth Block VPort Z -- Inserted by the driver to cause the SC to send the vport array Zmin and Zmax values to the DBs. М(BOTTOM_OF_PIPE_TS: Bottom of the Pipe Timestamp -- Inserted by the driver to request a bottom of pipe timestamp be sent to memory, no flushing required. h):FLUSH_SX_TS: Flush SX Timestamp - Inserted by the driver to cause the SX to flush its caches, then signal the CP. The other destination caches must also signal the CP for this event. All responses to the CP must be in the order the TS were received, regardless if the cache is required to otherwise act upon it. h*yDB_CACHE_FLUSH_AND_INV: DB Flush and Invalidate - Inserted by the driver when the depth surface is paged out of memory. +FLUSH_AND_INV_DB_DATA_TS: Flush and Invalidate DB's Data Cache Only - Inserted by the driver to cause the DB to flush and invalidate only its data cache, wait for write confirm, then signal the CP. The other destination caches must also signal the CP for this event. All responses to the CP must be in the order the TS were received, regardless if the cache is required to otherwise act upon it. Ȣ,FLUSH_AND_INV_DB_META: Flush and Invalidate DB's Meta (htile) Only - Inserted by the driver to cause the DB to flush and invalidate only its Meta cache. 裛-FLUSH_AND_INV_CB_DATA_TS: Flush and Invalidate CB's Data Cache Only - Inserted by the driver to cause the CB to flush and invalidate only its data cache, wait for write confirm, then signal the CP. The other destination caches must also signal the CP for this event. All responses to the CP must be in the order the TS were received, regardless if the cache is required to otherwise act upon it. .FLUSH_AND_INV_CB_META: Flush and Invalidate CB's Meta (cmask/fmask) Only - Inserted by the driver to cause the CB to flush and invalidate only its Meta cache. 8 ADDRESS_HI"اEXTENDED_EVENT"xf`h"" hVGT_DRAW_INITIATORliXiSOURCE_SELECTjiDI_SRC_SEL_DMA: VGT DMA Data jHj&DI_SRC_SEL_IMMEDIATE: Immediate Data hkj-DI_SRC_SEL_AUTO_INDEX: Auto-increment Index k(DI_SRC_SEL_RESERVED: Reserved - unused npll MAJOR_MODEmmDI_MAJOR_MODE_0: DI_MAJOR_MODE_0 Normal (Implicit) Mode -- applies only to prim types 0-21. Some VGT state registers are ignored (their values implied) in this mode. 0njDI_MAJOR_MODE_1: DI_MAJOR_MODE_1 Explicit Mode -- Configuration completely specified by state registers. o0oSPRITE_EN_R6XX"Hqo pNOT_EOPphp normal eop psuppress eop qq USE_OPAQUEr0rnon-opaque draw r opaque draw cfЇЇ"" @gGFX_COPY_STATEg SRC_STATE_ID"a`d""" dPA_SC_DEBUG_REG1Pee REG1_FIELD0"e REG1_FIELD1"]Xb""" bPA_SC_DEBUG_REG0Hcc REG0_FIELD0"c REG0_FIELD1"S8^""" ^SETUP_DEBUG_REG58_^ attr_indx_sort2_gated"__ attr_indx_sort1_gated"`@`provoking_vtx_gated"8a`event_id_gated"avalid_prim_gated" QXT""" TSETUP_DEBUG_REG4XUU attr_indx_sort0_gated"VU null_prim_gated"VXV backfacing_gated"PWW st_indx_gated"WWclipped_gated"XPXdealloc_slot_gated"HYX xmajor_gated"YYdiamond_rule_gated"ZHZ type_gated"0[Z fpov_gated"[[pmode_prim_gated"x\0\ event_gated"]\ eop_gated"p]valid_prim_gated"`NQ""" QSETUP_DEBUG_REG3R@Ry_sort2_gated_22_8"8SRx_sort2_gated_22_8"Svalid_prim_gated"KN""" (OSETUP_DEBUG_REG2OOy_sort1_gated_22_8"xP(Px_sort1_gated_22_8"Pvalid_prim_gated"(CL""" hLSETUP_DEBUG_REG1MLy_sort0_gated_22_8"MhMx_sort0_gated_22_8"Nvalid_prim_gated"8C""" CSETUP_DEBUG_REG0 DHDsu_baryc_cntl_state"@EDsu_cntl_state"EE pmode_state"F8F ge_stallb" GF geom_enable"GxGsu_clip_baryc_free"hH H su_clip_rtr"IH pfifo_busy"I`I su_cntl_busy"PJJ geom_busy"JJpa_reg_sclk_vld"PKpa_dyn_sclk_vld"08""" 8SXIFCCG_DEBUG_REG3989 ALWAYS_ZERO"8:9vertex_fifo_entriesavailable":: %statevar_bits_vs_out_ccdist1_vec_ena";P; %statevar_bits_vs_out_ccdist0_vec_ena"`<<available_positions"=<current_state"=`=vertex_fifo_empty"X>>vertex_fifo_full"?>sx0_receive_fifo_empty"?`?sx0_receive_fifo_full"h@@vgt_to_ccgen_fifo_empty"A@vgt_to_ccgen_fifo_full"ApAccgen_to_clipcc_fifo_full"xB Bsx0_receive_fifo_write"Bccgen_to_clipcc_write"x(1""" X1SXIFCCG_DEBUG_REG2 11sx_aux"2P2sx_request_indx"H32 req_active_verts"33req_active_verts_loaded"4P4vgt_to_ccgen_state_var_indx"X55vgt_to_ccgen_active_verts"65vgt_to_ccgen_firstvert"6`6sx_pending_fifo_empty"h77sx_pending_fifo_full"7sx_pending_fifo_contents""(""" @)SXIFCCG_DEBUG_REG1 ))sx_pending_rd_sp_id"*@*sx_pending_rd_aux_inc"@+*sx_to_pa_empty"++available_positions",@, sx_pending_advance"8-, sx_receive_indx"--"statevar_bits_vs_out_misc_vec_ena".H.statevar_bits_disable_sp"@/.aux_sel"// pasx_req_cnt"@0param_cache_base"p#""" #SXIFCCG_DEBUG_REG0h$$nan_kill_flag"%$position_address"%h% point_address"p&&sx_pending_rd_state_var_indx" '&sx_pending_rd_req_mask"'x'sx_pending_rd_pci" (sx_pending_rd_aux_sel"h""" CLIPPER_DEBUG_REG19 `sm3_prim_end_state"sm3_ps_expand"`sm3_clip_vert_cnt"X sm3_vertex_clip_cnt"sm3_inv_to_clip_data_valid_1"hsm3_inv_to_clip_data_valid_0"p sm3_current_state"0 )sm3_clip_to_clipga_clip_to_outsm_cnt_eq0" sm3_clip_to_outsm_fifo_full"!8!sm3_highest_priority_seq"@"!sm3_outputcliptoclipga_0""sm3_clprim_to_clip_prim_valid"`""" CLIPPER_DEBUG_REG18 Xsm2_prim_end_state"sm2_ps_expand"Xsm2_clip_vert_cnt"P sm2_vertex_clip_cnt"sm2_inv_to_clip_data_valid_1"`sm2_inv_to_clip_data_valid_0"hsm2_current_state"()sm2_clip_to_clipga_clip_to_outsm_cnt_eq0"sm2_clip_to_outsm_fifo_full"0sm2_highest_priority_seq"8sm2_outputcliptoclipga_0"sm2_clprim_to_clip_prim_valid"X""" CLIPPER_DEBUG_REG17 P sm1_prim_end_state" sm1_ps_expand" P sm1_clip_vert_cnt"H sm1_vertex_clip_cnt" sm1_inv_to_clip_data_valid_1" X sm1_inv_to_clip_data_valid_0"`  sm1_current_state"  )sm1_clip_to_clipga_clip_to_outsm_cnt_eq0"xsm1_clip_to_outsm_fifo_full"(sm1_highest_priority_seq"0sm1_outputcliptoclipga_0"sm1_clprim_to_clip_prim_valid"`P""" CLIPPER_DEBUG_REG16 Hsm0_prim_end_state"sm0_ps_expand"Hsm0_clip_vert_cnt"@ sm0_vertex_clip_cnt"sm0_inv_to_clip_data_valid_1"Psm0_inv_to_clip_data_valid_0"Xsm0_current_state")sm0_clip_to_clipga_clip_to_outsm_cnt_eq0"psm0_clip_to_outsm_fifo_full"x sm0_highest_priority_seq"(sm0_outputcliptoclipga_0"sm0_clprim_to_clip_prim_valid"""" (CLIPPER_DEBUG_REG15%vertval_bits_vertex_vertex_store_msb"@*primic_to_clprim_fifo_vertex_store_indx_2"h*primic_to_clprim_fifo_vertex_store_indx_1"(*primic_to_clprim_fifo_vertex_store_indx_0"primic_to_clprim_valid"X""" PCLIPPER_DEBUG_REG14 #clprim_in_back_vertex_store_indx_2"`#clprim_in_back_vertex_store_indx_1"x #clprim_in_back_vertex_store_indx_0"0"outputclprimtoclip_null_primitive"clprim_in_back_end_of_packet"@"clprim_in_back_first_prim_of_slot"Xclprim_in_back_deallocate_slot"clprim_in_back_event_id"`clprim_in_back_event"prim_back_valid"ښ """  CLIPPER_DEBUG_REG13xclprim_in_back_state_var_indx"0point_clip_candidate"0prim_nan_kill"clprim_clip_primitive"8clprim_cull_primitive"8prim_back_valid""vertval_bits_vertex_cc_next_valid"H clipcc_vertex_store_indx"Xvte_out_orig_fifo_fifo_empty"clipcode_fifo_fifo_empty"`ccgen_to_clipcc_fifo_empty"pclip_priority_seq_indx_out_cnt" outsm_clr_rd_orig_vertices"xoutsm_clr_rd_clipsm_wait"(outsm_clr_fifo_contents"(outsm_clr_fifo_full"outsm_clr_fifo_advanceread"0outsm_clr_fifo_write"ʚۚ """ PۚCLIPPER_DEBUG_REG12ۚۚ ALWAYS_ZERO"ܚHܚ%clip_priority_available_vte_out_clip"hݚݚ #clip_priority_available_clip_verts"ޚݚclip_priority_seq_indx_out"ޚpޚclip_priority_seq_indx_vert"xߚ ߚclip_priority_seq_indx_load"8ߚ&clipsm3_clprim_to_clip_clip_primitive""clipsm3_clprim_to_clip_prim_valid"H&clipsm2_clprim_to_clip_clip_primitive"h"clipsm2_clprim_to_clip_prim_valid"(&clipsm1_clprim_to_clip_clip_primitive""clipsm1_clprim_to_clip_prim_valid"8&clipsm0_clprim_to_clip_clip_primitive""clipsm0_clprim_to_clip_prim_valid"ĚP˚ """ ˚CLIPPER_DEBUG_REG11X̚˚clipsm3_clip_to_clipga_event"͚̚clipsm2_clip_to_clipga_event"͚h͚clipsm1_clip_to_clipga_event"Κ Κclipsm0_clip_to_clipga_event"@ϚΚ&clipsm3_clip_to_clipga_clip_primitive"КϚ&clipsm2_clip_to_clipga_clip_primitive"К`К&clipsm1_clip_to_clipga_clip_primitive"њ њ&clipsm0_clip_to_clipga_clip_primitive"HҚњ)clipsm3_clip_to_clipga_clip_to_outsm_cnt"ӚҚ )clipsm2_clip_to_clipga_clip_to_outsm_cnt"Ӛ`Ӛ)clipsm1_clip_to_clipga_clip_to_outsm_cnt"Ԛ Ԛ)clipsm0_clip_to_clipga_clip_to_outsm_cnt"@՚Ԛ"clipsm3_clip_to_clipga_prim_valid"՚՚"clipsm2_clip_to_clipga_prim_valid"֚P֚"clipsm1_clip_to_clipga_prim_valid"hךך"clipsm0_clip_to_clipga_prim_valid"0ؚך-clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt"ؚؚ-clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt"ٚPٚ-clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt"ښ-clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt"XŚ """ ŚCLIPPER_DEBUG_REG10hƚƚ *clipsm3_clprim_to_clip_param_cache_indx_0"(ǚƚ +clipsm3_clprim_to_clip_vertex_store_indx_2"ǚǚ+clipsm3_clprim_to_clip_vertex_store_indx_1"Ț@Ț+clipsm3_clprim_to_clip_vertex_store_indx_0"`ɚɚclipsm3_clprim_to_clip_event" ʚɚ&clipsm3_clprim_to_clip_null_primitive"xʚ"clipsm3_clprim_to_clip_prim_valid"0 """ CLIPPER_DEBUG_REG09 8ؽ$clipsm3_clprim_to_clip_clip_code_or" clipsm3_clprim_to_clip_event_id"H&clipsm3_clprim_to_clip_state_var_indx"p&clipsm3_clprim_to_clip_clip_primitive"0'clipsm3_clprim_to_clip_deallocate_slot"*clipsm3_clprim_to_clip_first_prim_of_slot"šHš%clipsm3_clprim_to_clip_end_of_packet"hÚÚclipsm3_clprim_to_clip_event"(ĚÚ&clipsm3_clprim_to_clip_null_primitive"Ě"clipsm3_clprim_to_clip_prim_valid"8""" CLIPPER_DEBUG_REG08Hේ *clipsm2_clprim_to_clip_param_cache_indx_0" +clipsm2_clprim_to_clip_vertex_store_indx_2"ȹ`+clipsm2_clprim_to_clip_vertex_store_indx_1" +clipsm2_clprim_to_clip_vertex_store_indx_0"@ບclipsm2_clprim_to_clip_event"&clipsm2_clprim_to_clip_null_primitive"X"clipsm2_clprim_to_clip_prim_valid"""" `CLIPPER_DEBUG_REG07 $clipsm2_clprim_to_clip_clip_code_or"аp clipsm2_clprim_to_clip_event_id"(&clipsm2_clprim_to_clip_state_var_indx"P豚&clipsm2_clprim_to_clip_clip_primitive"'clipsm2_clprim_to_clip_deallocate_slot"гh*clipsm2_clprim_to_clip_first_prim_of_slot"(%clipsm2_clprim_to_clip_end_of_packet"H贚clipsm2_clprim_to_clip_event"&clipsm2_clprim_to_clip_null_primitive"`"clipsm2_clprim_to_clip_prim_valid"x""" hCLIPPER_DEBUG_REG06( *clipsm1_clprim_to_clip_param_cache_indx_0"誚 +clipsm1_clprim_to_clip_vertex_store_indx_2"@+clipsm1_clprim_to_clip_vertex_store_indx_1"h+clipsm1_clprim_to_clip_vertex_store_indx_0" clipsm1_clprim_to_clip_event"୚x&clipsm1_clprim_to_clip_null_primitive"8"clipsm1_clprim_to_clip_prim_valid"""" @CLIPPER_DEBUG_REG05 $clipsm1_clprim_to_clip_clip_code_or"P clipsm1_clprim_to_clip_event_id"p&clipsm1_clprim_to_clip_state_var_indx"0ȣ&clipsm1_clprim_to_clip_clip_primitive"'clipsm1_clprim_to_clip_deallocate_slot"H*clipsm1_clprim_to_clip_first_prim_of_slot"p%clipsm1_clprim_to_clip_end_of_packet"(Ȧclipsm1_clprim_to_clip_event"觚&clipsm1_clprim_to_clip_null_primitive"@"clipsm1_clprim_to_clip_prim_valid"X""" HCLIPPER_DEBUG_REG04 *clipsm0_clprim_to_clip_param_cache_indx_0"Ȝ` +clipsm0_clprim_to_clip_vertex_store_indx_2" +clipsm0_clprim_to_clip_vertex_store_indx_1"H+clipsm0_clprim_to_clip_vertex_store_indx_0"clipsm0_clprim_to_clip_event"X&clipsm0_clprim_to_clip_null_primitive""clipsm0_clprim_to_clip_prim_valid"В"""  CLIPPER_DEBUG_REG03 ؓx$clipsm0_clprim_to_clip_clip_code_or"0 clipsm0_clprim_to_clip_event_id"P蔚&clipsm0_clprim_to_clip_state_var_indx"&clipsm0_clprim_to_clip_clip_primitive"Жh'clipsm0_clprim_to_clip_deallocate_slot"(*clipsm0_clprim_to_clip_first_prim_of_slot"P藚%clipsm0_clprim_to_clip_end_of_packet"clipsm0_clprim_to_clip_event"ș`&clipsm0_clprim_to_clip_null_primitive" "clipsm0_clprim_to_clip_prim_valid"xx""" ȅCLIPPER_DEBUG_REG02p clip_extra_bc_valid"Ȇclip_vert_vte_valid"ȇpclip_to_outsm_clip_seq_indx" "clip_to_outsm_vertex_store_indx_2"8؈ "clip_to_outsm_vertex_store_indx_1""clip_to_outsm_vertex_store_indx_0"Hclip_to_clipga_extra_bc_coords"`clip_to_clipga_vte_naninf_kill"clip_to_outsm_end_of_packet"Ȍh!clip_to_outsm_first_prim_of_slot"x clip_to_outsm_clipped_prim"0Ѝclip_to_outsm_null_primitive"clip_ga_bc_fifo_full"8clip_to_ga_fifo_full"@菚clip_ga_bc_fifo_write"clip_to_ga_fifo_write"Hclip_to_outsm_fifo_advanceread"clip_to_outsm_fifo_empty"g`y""" yCLIPPER_DEBUG_REG01Pzz ALWAYS_ZERO"zzclip_extra_bc_valid"{P{ clip_vert_vte_valid"X|{ clip_to_outsm_vertex_deallocate"}|clip_to_outsm_deallocate_slot"}h}clip_to_outsm_null_primitive"~ ~)vte_positions_vte_clip_vte_naninf_kill_2"H~)vte_positions_vte_clip_vte_naninf_kill_1")vte_positions_vte_clip_vte_naninf_kill_0"`vte_out_clip_rd_extra_bc_valid"x vte_out_clip_rd_vte_naninf_kill"0Ё"vte_out_clip_rd_vertex_store_indx"clip_ga_bc_fifo_write"8clip_to_ga_fifo_write"H胚#vte_out_clip_fifo_fifo_advanceread"vte_out_clip_fifo_fifo_empty"@f h""" phCLIPPER_DEBUG_REG00ih ALWAYS_ZERO"ihiclip_ga_bc_fifo_write"hjj su_clip_baryc_free"kj clip_to_ga_fifo_write"kpk clip_to_ga_fifo_full"xl l primic_to_clprim_fifo_empty"(mlprimic_to_clprim_fifo_full"mmclip_to_outsm_fifo_empty"n0nclip_to_outsm_fifo_full"8onvgt_to_clipp_fifo_empty"oovgt_to_clipp_fifo_full"p@pvgt_to_clips_fifo_empty"Hqpvgt_to_clips_fifo_full"qqclipcode_fifo_fifo_empty"rPrclipcode_fifo_full"Xsrvte_out_clip_fifo_fifo_empty"tsvte_out_clip_fifo_fifo_full"t`tvte_out_orig_fifo_fifo_empty"puuvte_out_orig_fifo_fifo_full" vuccgen_to_clipcc_fifo_empty"vxvccgen_to_clipcc_fifo_full"w(wclip_to_outsm_fifo_write"8xwvte_out_orig_fifo_fifo_write"xvgt_to_clipp_fifo_write"df܋܋"" gPA_SC_DEBUG_DATA`g DATAhcHe؋؋"" ePA_SC_DEBUG_CNTLeSC_DEBUG_INDXac"" 0dPA_SU_DEBUG_DATAd DATA`pb"" bPA_SU_DEBUG_CNTLcSU_DEBUG_INDX _a"" PaPA_SC_CNTL_STATUSaMPASS_OVERFLOW"]_PP"" _PA_SU_CNTL_STATUS@`SU_BUSY"H\0^"" ^PA_CL_CNTL_STATUS^CL_BUSY"Z\܊܊"" ]PA_SC_PERFCOUNTER3_HIp] PERF_COUNT"hYP[؊؊"" [PA_SC_PERFCOUNTER3_LOW\ PERF_COUNT"WYԊԊ"" 8ZPA_SC_PERFCOUNTER2_HIZ PERF_COUNT"VpXЊЊ"" XPA_SC_PERFCOUNTER2_LOW Y PERF_COUNT"UW̊̊"" XWPA_SC_PERFCOUNTER1_HIW PERF_COUNT"SUȊȊ"" UPA_SC_PERFCOUNTER1_LOW@V PERF_COUNT"8R TĊĊ"" xTPA_SC_PERFCOUNTER0_HIT PERF_COUNT"8pR"" SPA_SC_PERFCOUNTER0_LOW`S PERF_COUNT"0p"" qPA_SC_PERFCOUNTER3_SELECT`qq PERF_SELrqSC_SRPS_WINDOW_VALID: SC_SRPS_WINDOW_VALID Number of clocks event-window is valid at stage register/primitive setup srSC_PSSW_WINDOW_VALID: SC_PSSW_WINDOW_VALID Number of clocks event-window is valid at primitive setup/supertile walker ttvSC_TPQZ_WINDOW_VALID: SC_TPQZ_WINDOW_VALID Number of clocks event-window is valid at tile picker/quad-z uuySC_QZQP_WINDOW_VALID: SC_QZQP_WINDOW_VALID Number of clocks event-window is valid at quad-z/quad processor vvwSC_TRPK_WINDOW_VALID: SC_TRPK_WINDOW_VALID Number of clocks event-window is valid at tile reorder/packer wwSC_SRPS_WINDOW_VALID_BUSY: SC_SRPS_WINDOW_VALID_BUSY Number of clocks event-window is valid at stage register/primitive setup with SC busy xxSC_PSSW_WINDOW_VALID_BUSY: SC_PSSW_WINDOW_VALID_BUSY Number of clocks event-window is valid at primitive setup/supertile walker with SC busy z8ySC_TPQZ_WINDOW_VALID_BUSY: SC_TPQZ_WINDOW_VALID_BUSY Number of clocks event-window is valid at tile picker/quad-z with SC busy {HzSC_QZQP_WINDOW_VALID_BUSY: SC_QZQP_WINDOW_VALID_BUSY Number of clocks event-window is valid at quad-z/quad processor with SC busy |X{ SC_TRPK_WINDOW_VALID_BUSY: SC_TRPK_WINDOW_VALID_BUSY Number of clocks event-window is valid at tile reorder/packer with SC busy |h| FSC_STARVED_BY_PA: SC_STARVED_BY_PA sc starved by pa }8} XSC_STALLED_BY_PRIMFIFO: SC_STALLED_BY_PRIMFIFO sc stalled by primitive fifo ~~ PSC_STARVED_BY_DB_TILE: SC_STARVED_BY_DB_TILE sc starved by db tile ~ PSC_STARVED_BY_DB_QUAD: SC_STARVED_BY_DB_QUAD sc starved by db quad h^SC_STALLED_BY_TILEORDERFIFO: SC_STALLED_BY_TILEORDERFIFO sc stalled by tile order fifo @SSC_STALLED_BY_TILEFIFO: SC_STALLED_BY_TILEFIFO sc stalled by tile fifo SSC_STALLED_BY_QUADFIFO: SC_STALLED_BY_QUADFIFO sc stalled by quad fifo `PSC_STALLED_BY_DB_TILE: SC_STALLED_BY_DB_TILE sc stalled by db tile ȃ8PSC_STALLED_BY_DB_QUAD: SC_STALLED_BY_DB_QUAD sc stalled by db quad FSC_STALLED_BY_SX: SC_STALLED_BY_SX sc stalled by sx hHSC_STALLED_BY_SPI: SC_STALLED_BY_SPI sc stalled by spi PaSC_SCISSOR_DISCARD: SC_SCISSOR_DISCARD primitive completely discarded by scissor @kSC_BB_DISCARD: SC_BB_DISCARD primitive discarded by bounding-box check, no pixels hit 8mSC_MULTICHIP_PRIM_DISCARD: SC_MULTICHIP_PRIM_DISCARD primitive completely discarded by optimization GSC_SUPERTILE_COUNT: SC_SUPERTILE_COUNT supertile count 艙PYSC_SUPERTILE_PER_PRIM_H0: SC_SUPERTILE_PER_PRIM_H0 prims with < 2 supertiles Ȋ0YSC_SUPERTILE_PER_PRIM_H1: SC_SUPERTILE_PER_PRIM_H1 prims with < 4 supertiles YSC_SUPERTILE_PER_PRIM_H2: SC_SUPERTILE_PER_PRIM_H2 prims with < 8 supertiles YSC_SUPERTILE_PER_PRIM_H3: SC_SUPERTILE_PER_PRIM_H3 prims with < 16 supertiles hЌYSC_SUPERTILE_PER_PRIM_H4: SC_SUPERTILE_PER_PRIM_H4 prims with < 32 supertiles HYSC_SUPERTILE_PER_PRIM_H5: SC_SUPERTILE_PER_PRIM_H5 prims with < 64 supertiles (YSC_SUPERTILE_PER_PRIM_H6: SC_SUPERTILE_PER_PRIM_H6 prims with < 128 supertiles p YSC_SUPERTILE_PER_PRIM_H7: SC_SUPERTILE_PER_PRIM_H7 prims with < 256 supertiles 萙P!YSC_SUPERTILE_PER_PRIM_H8: SC_SUPERTILE_PER_PRIM_H8 prims with < 512 supertiles ȑ0"YSC_SUPERTILE_PER_PRIM_H9: SC_SUPERTILE_PER_PRIM_H9 prims with < 1K supertiles #ZSC_SUPERTILE_PER_PRIM_H10: SC_SUPERTILE_PER_PRIM_H10 prims with < 2K supertiles $ZSC_SUPERTILE_PER_PRIM_H11: SC_SUPERTILE_PER_PRIM_H11 prims with < 4K supertiles hГ%ZSC_SUPERTILE_PER_PRIM_H12: SC_SUPERTILE_PER_PRIM_H12 prims with < 8K supertiles H&ZSC_SUPERTILE_PER_PRIM_H13: SC_SUPERTILE_PER_PRIM_H13 prims with < 16K supertiles ('ZSC_SUPERTILE_PER_PRIM_H14: SC_SUPERTILE_PER_PRIM_H14 prims with < 32K supertiles p(ZSC_SUPERTILE_PER_PRIM_H15: SC_SUPERTILE_PER_PRIM_H15 prims with < 64K supertiles 藙P)ZSC_SUPERTILE_PER_PRIM_H16: SC_SUPERTILE_PER_PRIM_H16 prims with < 1M supertiles 0*OSC_TILE_PER_PRIM_H0: SC_TILE_PER_PRIM_H0 prims with < 2 tiles +OSC_TILE_PER_PRIM_H1: SC_TILE_PER_PRIM_H1 prims with < 4 tiles p,OSC_TILE_PER_PRIM_H2: SC_TILE_PER_PRIM_H2 prims with < 8 tiles H-OSC_TILE_PER_PRIM_H3: SC_TILE_PER_PRIM_H3 prims with < 16 tiles .OSC_TILE_PER_PRIM_H4: SC_TILE_PER_PRIM_H4 prims with < 32 tiles h/OSC_TILE_PER_PRIM_H5: SC_TILE_PER_PRIM_H5 prims with < 64 tiles Н@0OSC_TILE_PER_PRIM_H6: SC_TILE_PER_PRIM_H6 prims with < 128 tiles 1OSC_TILE_PER_PRIM_H7: SC_TILE_PER_PRIM_H7 prims with < 256 tiles 2OSC_TILE_PER_PRIM_H8: SC_TILE_PER_PRIM_H8 prims with < 512 tiles Xȟ3OSC_TILE_PER_PRIM_H9: SC_TILE_PER_PRIM_H9 prims with < 1K tiles 04PSC_TILE_PER_PRIM_H10: SC_TILE_PER_PRIM_H10 prims with < 2K tiles x5PSC_TILE_PER_PRIM_H11: SC_TILE_PER_PRIM_H11 prims with < 4K tiles ࢙P6PSC_TILE_PER_PRIM_H12: SC_TILE_PER_PRIM_H12 prims with < 8K tiles (7PSC_TILE_PER_PRIM_H13: SC_TILE_PER_PRIM_H13 prims with < 16K tiles 8PSC_TILE_PER_PRIM_H14: SC_TILE_PER_PRIM_H14 prims with < 32K tiles hؤ9PSC_TILE_PER_PRIM_H15: SC_TILE_PER_PRIM_H15 prims with < 64K tiles @:PSC_TILE_PER_PRIM_H16: SC_TILE_PER_PRIM_H16 prims with < 1M tiles (;aSC_TILE_PER_SUPERTILE_H0: SC_TILE_PER_SUPERTILE_H0 supertiles walked with 0 tiles hit p<aSC_TILE_PER_SUPERTILE_H1: SC_TILE_PER_SUPERTILE_H1 supertiles walked with 1 tiles hit X=aSC_TILE_PER_SUPERTILE_H2: SC_TILE_PER_SUPERTILE_H2 supertiles walked with 2 tiles hit ਖ਼@>aSC_TILE_PER_SUPERTILE_H3: SC_TILE_PER_SUPERTILE_H3 supertiles walked with 3 tiles hit Ȫ(?aSC_TILE_PER_SUPERTILE_H4: SC_TILE_PER_SUPERTILE_H4 supertiles walked with 4 tiles hit @aSC_TILE_PER_SUPERTILE_H5: SC_TILE_PER_SUPERTILE_H5 supertiles walked with 5 tiles hit AaSC_TILE_PER_SUPERTILE_H6: SC_TILE_PER_SUPERTILE_H6 supertiles walked with 6 tiles hit ଙBaSC_TILE_PER_SUPERTILE_H7: SC_TILE_PER_SUPERTILE_H7 supertiles walked with 7 tiles hit hȭCaSC_TILE_PER_SUPERTILE_H8: SC_TILE_PER_SUPERTILE_H8 supertiles walked with 8 tiles hit PDaSC_TILE_PER_SUPERTILE_H9: SC_TILE_PER_SUPERTILE_H9 supertiles walked with 9 tiles hit 8EbSC_TILE_PER_SUPERTILE_H10: SC_TILE_PER_SUPERTILE_H10 supertiles walked with 10 tiles hit FbSC_TILE_PER_SUPERTILE_H11: SC_TILE_PER_SUPERTILE_H11 supertiles walked with 11 tiles hit hGbSC_TILE_PER_SUPERTILE_H12: SC_TILE_PER_SUPERTILE_H12 supertiles walked with 12 tiles hit PHbSC_TILE_PER_SUPERTILE_H13: SC_TILE_PER_SUPERTILE_H13 supertiles walked with 13 tiles hit س8IbSC_TILE_PER_SUPERTILE_H14: SC_TILE_PER_SUPERTILE_H14 supertiles walked with 14 tiles hit JbSC_TILE_PER_SUPERTILE_H15: SC_TILE_PER_SUPERTILE_H15 supertiles walked with 15 tiles hit KbSC_TILE_PER_SUPERTILE_H16: SC_TILE_PER_SUPERTILE_H16 supertiles walked with 16 tiles hit LTSC_TILE_PICKED_H1: SC_TILE_PICKED_H1 number of times 1 tile picked `ȶMUSC_TILE_PICKED_H2: SC_TILE_PICKED_H2 number of times 2 tiles picked PNjSC_TILE_PICKED_CONFLICT: SC_TILE_PICKED_CONFLICT number of times 1 tile picked b/c of conflict HOqSC_QZ0_MULTICHIP_TILE_DISCARD: SC_QZ0_MULTICHIP_TILE_DISCARD tiles discarded by optimization; quad-z pipe 0 @PqSC_QZ1_MULTICHIP_TILE_DISCARD: SC_QZ1_MULTICHIP_TILE_DISCARD tiles discarded by optimization; quad-z pipe 1 QPSC_QZ0_TILE_COUNT: SC_QZ0_TILE_COUNT tile count; quad-z pipe 0 `RPSC_QZ1_TILE_COUNT: SC_QZ1_TILE_COUNT tile count; quad-z pipe 1 ؼ8S`SC_QZ0_TILE_COVERED_COUNT: SC_QZ0_TILE_COVERED_COUNT tile covered count; quad-z pipe 0 T`SC_QZ1_TILE_COVERED_COUNT: SC_QZ1_TILE_COVERED_COUNT tile covered count; quad-z pipe 1 UhSC_QZ0_TILE_NOT_COVERED_COUNT: SC_QZ0_TILE_NOT_COVERED_COUNT tile not covered count; quad-z pipe 0 VhSC_QZ1_TILE_NOT_COVERED_COUNT: SC_QZ1_TILE_NOT_COVERED_COUNT tile not covered count; quad-z pipe 1 这WjSC_QZ0_QUAD_PER_TILE_H0: SC_QZ0_QUAD_PER_TILE_H0 tiles walked with 0 quads hit; quad-z pipe 0 XjSC_QZ0_QUAD_PER_TILE_H1: SC_QZ0_QUAD_PER_TILE_H1 tiles walked with 1 quads hit; quad-z pipe 0 p™YjSC_QZ0_QUAD_PER_TILE_H2: SC_QZ0_QUAD_PER_TILE_H2 tiles walked with 2 quads hit; quad-z pipe 0 `ٙZjSC_QZ0_QUAD_PER_TILE_H3: SC_QZ0_QUAD_PER_TILE_H3 tiles walked with 3 quads hit; quad-z pipe 0 PęÙ[jSC_QZ0_QUAD_PER_TILE_H4: SC_QZ0_QUAD_PER_TILE_H4 tiles walked with 4 quads hit; quad-z pipe 0 @řę\jSC_QZ0_QUAD_PER_TILE_H5: SC_QZ0_QUAD_PER_TILE_H5 tiles walked with 5 quads hit; quad-z pipe 0 0ƙř]jSC_QZ0_QUAD_PER_TILE_H6: SC_QZ0_QUAD_PER_TILE_H6 tiles walked with 6 quads hit; quad-z pipe 0 Ǚxƙ^jSC_QZ0_QUAD_PER_TILE_H7: SC_QZ0_QUAD_PER_TILE_H7 tiles walked with 7 quads hit; quad-z pipe 0 șhǙ_jSC_QZ0_QUAD_PER_TILE_H8: SC_QZ0_QUAD_PER_TILE_H8 tiles walked with 8 quads hit; quad-z pipe 0 əXș`jSC_QZ0_QUAD_PER_TILE_H9: SC_QZ0_QUAD_PER_TILE_H9 tiles walked with 9 quads hit; quad-z pipe 0 əHəakSC_QZ0_QUAD_PER_TILE_H10: SC_QZ0_QUAD_PER_TILE_H10 tiles walked with 10 quads hit; quad-z pipe 0 ʙ8ʙbkSC_QZ0_QUAD_PER_TILE_H11: SC_QZ0_QUAD_PER_TILE_H11 tiles walked with 11 quads hit; quad-z pipe 0 ˙(˙ckSC_QZ0_QUAD_PER_TILE_H12: SC_QZ0_QUAD_PER_TILE_H12 tiles walked with 12 quads hit; quad-z pipe 0 ̙̙dkSC_QZ0_QUAD_PER_TILE_H13: SC_QZ0_QUAD_PER_TILE_H13 tiles walked with 13 quads hit; quad-z pipe 0 ͙͙ekSC_QZ0_QUAD_PER_TILE_H14: SC_QZ0_QUAD_PER_TILE_H14 tiles walked with 14 quads hit; quad-z pipe 0 Ι͙fkSC_QZ0_QUAD_PER_TILE_H15: SC_QZ0_QUAD_PER_TILE_H15 tiles walked with 15 quads hit; quad-z pipe 0 ϙΙgkSC_QZ0_QUAD_PER_TILE_H16: SC_QZ0_QUAD_PER_TILE_H16 tiles walked with 16 quads hit; quad-z pipe 0 ЙϙhjSC_QZ1_QUAD_PER_TILE_H0: SC_QZ1_QUAD_PER_TILE_H0 tiles walked with 0 quads hit; quad-z pipe 1 pљЙijSC_QZ1_QUAD_PER_TILE_H1: SC_QZ1_QUAD_PER_TILE_H1 tiles walked with 1 quads hit; quad-z pipe 1 `ҙљjjSC_QZ1_QUAD_PER_TILE_H2: SC_QZ1_QUAD_PER_TILE_H2 tiles walked with 2 quads hit; quad-z pipe 1 PәҙkjSC_QZ1_QUAD_PER_TILE_H3: SC_QZ1_QUAD_PER_TILE_H3 tiles walked with 3 quads hit; quad-z pipe 1 @ԙәljSC_QZ1_QUAD_PER_TILE_H4: SC_QZ1_QUAD_PER_TILE_H4 tiles walked with 4 quads hit; quad-z pipe 1 0ՙԙmjSC_QZ1_QUAD_PER_TILE_H5: SC_QZ1_QUAD_PER_TILE_H5 tiles walked with 5 quads hit; quad-z pipe 1 ֙xՙnjSC_QZ1_QUAD_PER_TILE_H6: SC_QZ1_QUAD_PER_TILE_H6 tiles walked with 6 quads hit; quad-z pipe 1 יh֙ojSC_QZ1_QUAD_PER_TILE_H7: SC_QZ1_QUAD_PER_TILE_H7 tiles walked with 7 quads hit; quad-z pipe 1 ؙXיpjSC_QZ1_QUAD_PER_TILE_H8: SC_QZ1_QUAD_PER_TILE_H8 tiles walked with 8 quads hit; quad-z pipe 1 ؙHؙqjSC_QZ1_QUAD_PER_TILE_H9: SC_QZ1_QUAD_PER_TILE_H9 tiles walked with 9 quads hit; quad-z pipe 1 ٙ8ٙrkSC_QZ1_QUAD_PER_TILE_H10: SC_QZ1_QUAD_PER_TILE_H10 tiles walked with 10 quads hit; quad-z pipe 1 ڙ(ڙskSC_QZ1_QUAD_PER_TILE_H11: SC_QZ1_QUAD_PER_TILE_H11 tiles walked with 11 quads hit; quad-z pipe 1 ۙۙtkSC_QZ1_QUAD_PER_TILE_H12: SC_QZ1_QUAD_PER_TILE_H12 tiles walked with 12 quads hit; quad-z pipe 1 ܙܙukSC_QZ1_QUAD_PER_TILE_H13: SC_QZ1_QUAD_PER_TILE_H13 tiles walked with 13 quads hit; quad-z pipe 1 ݙܙvkSC_QZ1_QUAD_PER_TILE_H14: SC_QZ1_QUAD_PER_TILE_H14 tiles walked with 14 quads hit; quad-z pipe 1 ޙݙwkSC_QZ1_QUAD_PER_TILE_H15: SC_QZ1_QUAD_PER_TILE_H15 tiles walked with 15 quads hit; quad-z pipe 1 ߙޙxkSC_QZ1_QUAD_PER_TILE_H16: SC_QZ1_QUAD_PER_TILE_H16 tiles walked with 16 quads hit; quad-z pipe 1 XߙyPSC_QZ0_QUAD_COUNT: SC_QZ0_QUAD_COUNT quad count; quad-z pipe 0 0zPSC_QZ1_QUAD_COUNT: SC_QZ1_QUAD_COUNT quad count; quad-z pipe 1 x{TSC_QUAD0_NOT_PICKED_TB_R6XX: SC_QUAD0_NOT_PICKED_TB_GPU6 deprecated for GPU7 P|TSC_QUAD1_NOT_PICKED_TB_R6XX: SC_QUAD1_NOT_PICKED_TB_GPU6 deprecated for GPU7 (}TSC_QUAD2_NOT_PICKED_TB_R6XX: SC_QUAD2_NOT_PICKED_TB_GPU6 deprecated for GPU7 ~TSC_QUAD3_NOT_PICKED_TB_R6XX: SC_QUAD3_NOT_PICKED_TB_GPU6 deprecated for GPU7 x_SC_P0_HIZ_TILE_COUNT: SC_P0_HIZ_TILE_COUNT total tiles surviving hi-z; db pipe 0 `_SC_P1_HIZ_TILE_COUNT: SC_P1_HIZ_TILE_COUNT total tiles surviving hi-z; db pipe 1 H_SC_P2_HIZ_TILE_COUNT: SC_P2_HIZ_TILE_COUNT total tiles surviving hi-z; db pipe 2 0_SC_P3_HIZ_TILE_COUNT: SC_P3_HIZ_TILE_COUNT total tiles surviving hi-z; db pipe 3 (xmSC_P0_HIZ_QUAD_PER_TILE_H0: SC_P0_HIZ_QUAD_PER_TILE_H0 tiles with 0 quads surviving hi-z; db pipe 0 pmSC_P0_HIZ_QUAD_PER_TILE_H1: SC_P0_HIZ_QUAD_PER_TILE_H1 tiles with 1 quads surviving hi-z; db pipe 0 hmSC_P0_HIZ_QUAD_PER_TILE_H2: SC_P0_HIZ_QUAD_PER_TILE_H2 tiles with 2 quads surviving hi-z; db pipe 0 `mSC_P0_HIZ_QUAD_PER_TILE_H3: SC_P0_HIZ_QUAD_PER_TILE_H3 tiles with 3 quads surviving hi-z; db pipe 0 XmSC_P0_HIZ_QUAD_PER_TILE_H4: SC_P0_HIZ_QUAD_PER_TILE_H4 tiles with 4 quads surviving hi-z; db pipe 0 PmSC_P0_HIZ_QUAD_PER_TILE_H5: SC_P0_HIZ_QUAD_PER_TILE_H5 tiles with 5 quads surviving hi-z; db pipe 0 HmSC_P0_HIZ_QUAD_PER_TILE_H6: SC_P0_HIZ_QUAD_PER_TILE_H6 tiles with 6 quads surviving hi-z; db pipe 0 @mSC_P0_HIZ_QUAD_PER_TILE_H7: SC_P0_HIZ_QUAD_PER_TILE_H7 tiles with 7 quads surviving hi-z; db pipe 0 8mSC_P0_HIZ_QUAD_PER_TILE_H8: SC_P0_HIZ_QUAD_PER_TILE_H8 tiles with 8 quads surviving hi-z; db pipe 0 0mSC_P0_HIZ_QUAD_PER_TILE_H9: SC_P0_HIZ_QUAD_PER_TILE_H9 tiles with 9 quads surviving hi-z; db pipe 0 (nSC_P0_HIZ_QUAD_PER_TILE_H10: SC_P0_HIZ_QUAD_PER_TILE_H10 tiles with 10 quads surviving hi-z; db pipe 0 nSC_P0_HIZ_QUAD_PER_TILE_H11: SC_P0_HIZ_QUAD_PER_TILE_H11 tiles with 11 quads surviving hi-z; db pipe 0 nSC_P0_HIZ_QUAD_PER_TILE_H12: SC_P0_HIZ_QUAD_PER_TILE_H12 tiles with 12 quads surviving hi-z; db pipe 0 nSC_P0_HIZ_QUAD_PER_TILE_H13: SC_P0_HIZ_QUAD_PER_TILE_H13 tiles with 13 quads surviving hi-z; db pipe 0 nSC_P0_HIZ_QUAD_PER_TILE_H14: SC_P0_HIZ_QUAD_PER_TILE_H14 tiles with 14 quads surviving hi-z; db pipe 0 nSC_P0_HIZ_QUAD_PER_TILE_H15: SC_P0_HIZ_QUAD_PER_TILE_H15 tiles with 15 quads surviving hi-z; db pipe 0 nSC_P0_HIZ_QUAD_PER_TILE_H16: SC_P0_HIZ_QUAD_PER_TILE_H16 tiles with 16 quads surviving hi-z; db pipe 0 mSC_P1_HIZ_QUAD_PER_TILE_H0: SC_P0_HIZ_QUAD_PER_TILE_H0 tiles with 0 quads surviving hi-z; db pipe 1 mSC_P1_HIZ_QUAD_PER_TILE_H1: SC_P0_HIZ_QUAD_PER_TILE_H1 tiles with 1 quads surviving hi-z; db pipe 1 mSC_P1_HIZ_QUAD_PER_TILE_H2: SC_P1_HIZ_QUAD_PER_TILE_H2 tiles with 2 quads surviving hi-z; db pipe 1 mSC_P1_HIZ_QUAD_PER_TILE_H3: SC_P1_HIZ_QUAD_PER_TILE_H3 tiles with 3 quads surviving hi-z; db pipe 1 mSC_P1_HIZ_QUAD_PER_TILE_H4: SC_P1_HIZ_QUAD_PER_TILE_H4 tiles with 4 quads surviving hi-z; db pipe 1 xmSC_P1_HIZ_QUAD_PER_TILE_H5: SC_P1_HIZ_QUAD_PER_TILE_H5 tiles with 5 quads surviving hi-z; db pipe 1 pmSC_P1_HIZ_QUAD_PER_TILE_H6: SC_P1_HIZ_QUAD_PER_TILE_H6 tiles with 6 quads surviving hi-z; db pipe 1 hmSC_P1_HIZ_QUAD_PER_TILE_H7: SC_P1_HIZ_QUAD_PER_TILE_H7 tiles with 7 quads surviving hi-z; db pipe 1 `mSC_P1_HIZ_QUAD_PER_TILE_H8: SC_P1_HIZ_QUAD_PER_TILE_H8 tiles with 8 quads surviving hi-z; db pipe 1 XmSC_P1_HIZ_QUAD_PER_TILE_H9: SC_P1_HIZ_QUAD_PER_TILE_H9 tiles with 9 quads surviving hi-z; db pipe 1 PnSC_P1_HIZ_QUAD_PER_TILE_H10: SC_P1_HIZ_QUAD_PER_TILE_H10 tiles with 10 quads surviving hi-z; db pipe 1 HnSC_P1_HIZ_QUAD_PER_TILE_H11: SC_P1_HIZ_QUAD_PER_TILE_H11 tiles with 11 quads surviving hi-z; db pipe 1 @nSC_P1_HIZ_QUAD_PER_TILE_H12: SC_P1_HIZ_QUAD_PER_TILE_H12 tiles with 12 quads surviving hi-z; db pipe 1 8nSC_P1_HIZ_QUAD_PER_TILE_H13: SC_P1_HIZ_QUAD_PER_TILE_H13 tiles with 13 quads surviving hi-z; db pipe 1 0nSC_P1_HIZ_QUAD_PER_TILE_H14: SC_P1_HIZ_QUAD_PER_TILE_H14 tiles with 14 quads surviving hi-z; db pipe 1 (xnSC_P1_HIZ_QUAD_PER_TILE_H15: SC_P1_HIZ_QUAD_PER_TILE_H15 tiles with 15 quads surviving hi-z; db pipe 1 pnSC_P1_HIZ_QUAD_PER_TILE_H16: SC_P1_HIZ_QUAD_PER_TILE_H16 tiles with 16 quads surviving hi-z; db pipe 1  h mSC_P2_HIZ_QUAD_PER_TILE_H0: SC_P2_HIZ_QUAD_PER_TILE_H0 tiles with 0 quads surviving hi-z; db pipe 2  ` mSC_P2_HIZ_QUAD_PER_TILE_H1: SC_P2_HIZ_QUAD_PER_TILE_H1 tiles with 1 quads surviving hi-z; db pipe 2  X mSC_P2_HIZ_QUAD_PER_TILE_H2: SC_P2_HIZ_QUAD_PER_TILE_H2 tiles with 2 quads surviving hi-z; db pipe 2 P mSC_P2_HIZ_QUAD_PER_TILE_H3: SC_P2_HIZ_QUAD_PER_TILE_H3 tiles with 3 quads surviving hi-z; db pipe 2 H mSC_P2_HIZ_QUAD_PER_TILE_H4: SC_P2_HIZ_QUAD_PER_TILE_H4 tiles with 4 quads surviving hi-z; db pipe 2 @mSC_P2_HIZ_QUAD_PER_TILE_H5: SC_P2_HIZ_QUAD_PER_TILE_H5 tiles with 5 quads surviving hi-z; db pipe 2 8mSC_P2_HIZ_QUAD_PER_TILE_H6: SC_P2_HIZ_QUAD_PER_TILE_H6 tiles with 6 quads surviving hi-z; db pipe 2 0mSC_P2_HIZ_QUAD_PER_TILE_H7: SC_P2_HIZ_QUAD_PER_TILE_H7 tiles with 7 quads surviving hi-z; db pipe 2 (mSC_P2_HIZ_QUAD_PER_TILE_H8: SC_P2_HIZ_QUAD_PER_TILE_H8 tiles with 8 quads surviving hi-z; db pipe 2  mSC_P2_HIZ_QUAD_PER_TILE_H9: SC_P2_HIZ_QUAD_PER_TILE_H9 tiles with 9 quads surviving hi-z; db pipe 2 nSC_P2_HIZ_QUAD_PER_TILE_H10: SC_P2_HIZ_QUAD_PER_TILE_H10 tiles with 10 quads surviving hi-z; db pipe 2 nSC_P2_HIZ_QUAD_PER_TILE_H11: SC_P2_HIZ_QUAD_PER_TILE_H11 tiles with 11 quads surviving hi-z; db pipe 2 nSC_P2_HIZ_QUAD_PER_TILE_H12: SC_P2_HIZ_QUAD_PER_TILE_H12 tiles with 12 quads surviving hi-z; db pipe 2 nSC_P2_HIZ_QUAD_PER_TILE_H13: SC_P2_HIZ_QUAD_PER_TILE_H13 tiles with 13 quads surviving hi-z; db pipe 2 nSC_P2_HIZ_QUAD_PER_TILE_H14: SC_P2_HIZ_QUAD_PER_TILE_H14 tiles with 14 quads surviving hi-z; db pipe 2 nSC_P2_HIZ_QUAD_PER_TILE_H15: SC_P2_HIZ_QUAD_PER_TILE_H15 tiles with 15 quads surviving hi-z; db pipe 2 nSC_P2_HIZ_QUAD_PER_TILE_H16: SC_P2_HIZ_QUAD_PER_TILE_H16 tiles with 16 quads surviving hi-z; db pipe 2 mSC_P3_HIZ_QUAD_PER_TILE_H0: SC_P3_HIZ_QUAD_PER_TILE_H0 tiles with 0 quads surviving hi-z; db pipe 3 mSC_P3_HIZ_QUAD_PER_TILE_H1: SC_P3_HIZ_QUAD_PER_TILE_H1 tiles with 1 quads surviving hi-z; db pipe 3 mSC_P3_HIZ_QUAD_PER_TILE_H2: SC_P3_HIZ_QUAD_PER_TILE_H2 tiles with 2 quads surviving hi-z; db pipe 3 xmSC_P3_HIZ_QUAD_PER_TILE_H3: SC_P3_HIZ_QUAD_PER_TILE_H3 tiles with 3 quads surviving hi-z; db pipe 3 pmSC_P3_HIZ_QUAD_PER_TILE_H4: SC_P3_HIZ_QUAD_PER_TILE_H4 tiles with 4 quads surviving hi-z; db pipe 3 hmSC_P3_HIZ_QUAD_PER_TILE_H5: SC_P3_HIZ_QUAD_PER_TILE_H5 tiles with 5 quads surviving hi-z; db pipe 3 ` mSC_P3_HIZ_QUAD_PER_TILE_H6: SC_P3_HIZ_QUAD_PER_TILE_H6 tiles with 6 quads surviving hi-z; db pipe 3 X! mSC_P3_HIZ_QUAD_PER_TILE_H7: SC_P3_HIZ_QUAD_PER_TILE_H7 tiles with 7 quads surviving hi-z; db pipe 3 P"!mSC_P3_HIZ_QUAD_PER_TILE_H8: SC_P3_HIZ_QUAD_PER_TILE_H8 tiles with 8 quads surviving hi-z; db pipe 3 H#"mSC_P3_HIZ_QUAD_PER_TILE_H9: SC_P3_HIZ_QUAD_PER_TILE_H9 tiles with 9 quads surviving hi-z; db pipe 3 @$#nSC_P3_HIZ_QUAD_PER_TILE_H10: SC_P3_HIZ_QUAD_PER_TILE_H10 tiles with 10 quads surviving hi-z; db pipe 3 8%$nSC_P3_HIZ_QUAD_PER_TILE_H11: SC_P3_HIZ_QUAD_PER_TILE_H11 tiles with 11 quads surviving hi-z; db pipe 3 0&%nSC_P3_HIZ_QUAD_PER_TILE_H12: SC_P3_HIZ_QUAD_PER_TILE_H12 tiles with 12 quads surviving hi-z; db pipe 3 ('x&nSC_P3_HIZ_QUAD_PER_TILE_H13: SC_P3_HIZ_QUAD_PER_TILE_H13 tiles with 13 quads surviving hi-z; db pipe 3 (p'nSC_P3_HIZ_QUAD_PER_TILE_H14: SC_P3_HIZ_QUAD_PER_TILE_H14 tiles with 14 quads surviving hi-z; db pipe 3 )h(nSC_P3_HIZ_QUAD_PER_TILE_H15: SC_P3_HIZ_QUAD_PER_TILE_H15 tiles with 15 quads surviving hi-z; db pipe 3 *`)nSC_P3_HIZ_QUAD_PER_TILE_H16: SC_P3_HIZ_QUAD_PER_TILE_H16 tiles with 16 quads surviving hi-z; db pipe 3 *X*_SC_P0_HIZ_QUAD_COUNT: SC_P0_HIZ_QUAD_COUNT total quads surviving hi-z; db pipe 0 +@+_SC_P1_HIZ_QUAD_COUNT: SC_P1_HIZ_QUAD_COUNT total quads surviving hi-z; db pipe 1 ,(,_SC_P2_HIZ_QUAD_COUNT: SC_P2_HIZ_QUAD_COUNT total quads surviving hi-z; db pipe 2 --_SC_P3_HIZ_QUAD_COUNT: SC_P3_HIZ_QUAD_COUNT total quads surviving hi-z; db pipe 3 .-lSC_P0_DETAIL_QUAD_COUNT: SC_P0_DETAIL_QUAD_COUNT total quads surviving detail sampler; db pipe 0 /.lSC_P1_DETAIL_QUAD_COUNT: SC_P1_DETAIL_QUAD_COUNT total quads surviving detail sampler; db pipe 1 0/lSC_P2_DETAIL_QUAD_COUNT: SC_P2_DETAIL_QUAD_COUNT total quads surviving detail sampler; db pipe 2 p10lSC_P3_DETAIL_QUAD_COUNT: SC_P3_DETAIL_QUAD_COUNT total quads surviving detail sampler; db pipe 3 h21pSC_P0_DETAIL_QUAD_WITH_1_PIX: SC_P0_DETAIL_QUAD_WITH_1_PIX quads with 1 pixel surviving detail; db pipe 0 `32qSC_P0_DETAIL_QUAD_WITH_2_PIX: SC_P0_DETAIL_QUAD_WITH_2_PIX quads with 2 pixels surviving detail; db pipe 0 X43qSC_P0_DETAIL_QUAD_WITH_3_PIX: SC_P0_DETAIL_QUAD_WITH_3_PIX quads with 3 pixels surviving detail; db pipe 0 P54qSC_P0_DETAIL_QUAD_WITH_4_PIX: SC_P0_DETAIL_QUAD_WITH_4_PIX quads with 4 pixels surviving detail; db pipe 0 H65pSC_P1_DETAIL_QUAD_WITH_1_PIX: SC_P1_DETAIL_QUAD_WITH_1_PIX quads with 1 pixel surviving detail; db pipe 1 @76qSC_P1_DETAIL_QUAD_WITH_2_PIX: SC_P1_DETAIL_QUAD_WITH_2_PIX quads with 2 pixels surviving detail; db pipe 1 887qSC_P1_DETAIL_QUAD_WITH_3_PIX: SC_P1_DETAIL_QUAD_WITH_3_PIX quads with 3 pixels surviving detail; db pipe 1 098qSC_P1_DETAIL_QUAD_WITH_4_PIX: SC_P1_DETAIL_QUAD_WITH_4_PIX quads with 4 pixels surviving detail; db pipe 1 (:x9pSC_P2_DETAIL_QUAD_WITH_1_PIX: SC_P2_DETAIL_QUAD_WITH_1_PIX quads with 1 pixel surviving detail; db pipe 2 ;p:qSC_P2_DETAIL_QUAD_WITH_2_PIX: SC_P2_DETAIL_QUAD_WITH_2_PIX quads with 2 pixels surviving detail; db pipe 2 <h;qSC_P2_DETAIL_QUAD_WITH_3_PIX: SC_P2_DETAIL_QUAD_WITH_3_PIX quads with 3 pixels surviving detail; db pipe 2 =`<qSC_P2_DETAIL_QUAD_WITH_4_PIX: SC_P2_DETAIL_QUAD_WITH_4_PIX quads with 4 pixels surviving detail; db pipe 2 >X=pSC_P3_DETAIL_QUAD_WITH_1_PIX: SC_P3_DETAIL_QUAD_WITH_1_PIX quads with 1 pixel surviving detail; db pipe 3 ?P>qSC_P3_DETAIL_QUAD_WITH_2_PIX: SC_P3_DETAIL_QUAD_WITH_2_PIX quads with 2 pixels surviving detail; db pipe 3 ?H?qSC_P3_DETAIL_QUAD_WITH_3_PIX: SC_P3_DETAIL_QUAD_WITH_3_PIX quads with 3 pixels surviving detail; db pipe 3 @@@qSC_P3_DETAIL_QUAD_WITH_4_PIX: SC_P3_DETAIL_QUAD_WITH_4_PIX quads with 4 pixels surviving detail; db pipe 3 A8AWSC_EARLYZ_QUAD_COUNT: SC_EARLYZ_QUAD_COUNT total quads surviving early-z BBcSC_EARLYZ_QUAD_WITH_1_PIX: SC_EARLYZ_QUAD_WITH_1_PIX quads with 1 pixel surviving early-z CCdSC_EARLYZ_QUAD_WITH_2_PIX: SC_EARLYZ_QUAD_WITH_2_PIX quads with 2 pixels surviving early-z DCdSC_EARLYZ_QUAD_WITH_3_PIX: SC_EARLYZ_QUAD_WITH_3_PIX quads with 3 pixels surviving early-z pEDdSC_EARLYZ_QUAD_WITH_4_PIX: SC_EARLYZ_QUAD_WITH_4_PIX quads with 4 pixels surviving early-z PFEYSC_TILE_REORDER_DB_CONFLICT_R6XX: SC_TILE_REORDER_DB_CONFLICT_GPU6 deprecated for GPU7 8GF`SC_PKR_QUAD_PER_ROW_H1: SC_PKR_QUAD_PER_ROW_H1 packer row outputs with 1 valid quad HG`SC_PKR_QUAD_PER_ROW_H2: SC_PKR_QUAD_PER_ROW_H2 packer row outputs with 2 valid quad IhH`SC_PKR_QUAD_PER_ROW_H3: SC_PKR_QUAD_PER_ROW_H3 packer row outputs with 3 valid quad IPI`SC_PKR_QUAD_PER_ROW_H4: SC_PKR_QUAD_PER_ROW_H4 packer row outputs with 4 valid quad J8JQSC_PKR_END_OF_VECTOR: SC_PKR_END_OF_VECTOR number of pixel vectors KKTSC_PKR_CONTROL_XFER: SC_PKR_CONTROL_XFER number of control transfers LK|SC_PKR_DBHANG_FORCE_EOV: SC_PKR_DBHANG_FORCE_EOV number of times partial vector ejected b/c of DB hang condition ML]SC_REG_SCLK_BUSY: SC_REG_SCLK_BUSY number of cycles register clock is busy xNMhSC_GRP0_DYN_SCLK_BUSY: SC_GRP0_DYN_SCLK_BUSY number of cycles group0 dynamic clock is busy hONhSC_GRP1_DYN_SCLK_BUSY: SC_GRP1_DYN_SCLK_BUSY number of cycles group1 dynamic clock is busy XPOhSC_GRP2_DYN_SCLK_BUSY: SC_GRP2_DYN_SCLK_BUSY number of cycles group2 dynamic clock is busy HQPhSC_GRP3_DYN_SCLK_BUSY: SC_GRP3_DYN_SCLK_BUSY number of cycles group3 dynamic clock is busy QhSC_GRP4_DYN_SCLK_BUSY: SC_GRP4_DYN_SCLK_BUSY number of cycles group4 dynamic clock is busy "" PA_SC_PERFCOUNTER2_SELECTX PERF_SEL菘SC_SRPS_WINDOW_VALID: SC_SRPS_WINDOW_VALID Number of clocks event-window is valid at stage register/primitive setup SC_PSSW_WINDOW_VALID: SC_PSSW_WINDOW_VALID Number of clocks event-window is valid at primitive setup/supertile walker vSC_TPQZ_WINDOW_VALID: SC_TPQZ_WINDOW_VALID Number of clocks event-window is valid at tile picker/quad-z ySC_QZQP_WINDOW_VALID: SC_QZQP_WINDOW_VALID Number of clocks event-window is valid at quad-z/quad processor wSC_TRPK_WINDOW_VALID: SC_TRPK_WINDOW_VALID Number of clocks event-window is valid at tile reorder/packer ȕSC_SRPS_WINDOW_VALID_BUSY: SC_SRPS_WINDOW_VALID_BUSY Number of clocks event-window is valid at stage register/primitive setup with SC busy 薘SC_PSSW_WINDOW_VALID_BUSY: SC_PSSW_WINDOW_VALID_BUSY Number of clocks event-window is valid at primitive setup/supertile walker with SC busy 0SC_TPQZ_WINDOW_VALID_BUSY: SC_TPQZ_WINDOW_VALID_BUSY Number of clocks event-window is valid at tile picker/quad-z with SC busy @SC_QZQP_WINDOW_VALID_BUSY: SC_QZQP_WINDOW_VALID_BUSY Number of clocks event-window is valid at quad-z/quad processor with SC busy P SC_TRPK_WINDOW_VALID_BUSY: SC_TRPK_WINDOW_VALID_BUSY Number of clocks event-window is valid at tile reorder/packer with SC busy 蚘` FSC_STARVED_BY_PA: SC_STARVED_BY_PA sc starved by pa ț0 XSC_STALLED_BY_PRIMFIFO: SC_STALLED_BY_PRIMFIFO sc stalled by primitive fifo  PSC_STARVED_BY_DB_TILE: SC_STARVED_BY_DB_TILE sc starved by db tile x蜘 PSC_STARVED_BY_DB_QUAD: SC_STARVED_BY_DB_QUAD sc starved by db quad `^SC_STALLED_BY_TILEORDERFIFO: SC_STALLED_BY_TILEORDERFIFO sc stalled by tile order fifo 8SSC_STALLED_BY_TILEFIFO: SC_STALLED_BY_TILEFIFO sc stalled by tile fifo SSC_STALLED_BY_QUADFIFO: SC_STALLED_BY_QUADFIFO sc stalled by quad fifo 蠘XPSC_STALLED_BY_DB_TILE: SC_STALLED_BY_DB_TILE sc stalled by db tile 0PSC_STALLED_BY_DB_QUAD: SC_STALLED_BY_DB_QUAD sc stalled by db quad FSC_STALLED_BY_SX: SC_STALLED_BY_SX sc stalled by sx `آHSC_STALLED_BY_SPI: SC_STALLED_BY_SPI sc stalled by spi HaSC_SCISSOR_DISCARD: SC_SCISSOR_DISCARD primitive completely discarded by scissor 8kSC_BB_DISCARD: SC_BB_DISCARD primitive discarded by bounding-box check, no pixels hit 0mSC_MULTICHIP_PRIM_DISCARD: SC_MULTICHIP_PRIM_DISCARD primitive completely discarded by optimization xGSC_SUPERTILE_COUNT: SC_SUPERTILE_COUNT supertile count ৘HYSC_SUPERTILE_PER_PRIM_H0: SC_SUPERTILE_PER_PRIM_H0 prims with < 2 supertiles (YSC_SUPERTILE_PER_PRIM_H1: SC_SUPERTILE_PER_PRIM_H1 prims with < 4 supertiles YSC_SUPERTILE_PER_PRIM_H2: SC_SUPERTILE_PER_PRIM_H2 prims with < 8 supertiles 詘YSC_SUPERTILE_PER_PRIM_H3: SC_SUPERTILE_PER_PRIM_H3 prims with < 16 supertiles `ȪYSC_SUPERTILE_PER_PRIM_H4: SC_SUPERTILE_PER_PRIM_H4 prims with < 32 supertiles @YSC_SUPERTILE_PER_PRIM_H5: SC_SUPERTILE_PER_PRIM_H5 prims with < 64 supertiles YSC_SUPERTILE_PER_PRIM_H6: SC_SUPERTILE_PER_PRIM_H6 prims with < 128 supertiles h YSC_SUPERTILE_PER_PRIM_H7: SC_SUPERTILE_PER_PRIM_H7 prims with < 256 supertiles ஘H!YSC_SUPERTILE_PER_PRIM_H8: SC_SUPERTILE_PER_PRIM_H8 prims with < 512 supertiles ("YSC_SUPERTILE_PER_PRIM_H9: SC_SUPERTILE_PER_PRIM_H9 prims with < 1K supertiles #ZSC_SUPERTILE_PER_PRIM_H10: SC_SUPERTILE_PER_PRIM_H10 prims with < 2K supertiles 谘$ZSC_SUPERTILE_PER_PRIM_H11: SC_SUPERTILE_PER_PRIM_H11 prims with < 4K supertiles `ȱ%ZSC_SUPERTILE_PER_PRIM_H12: SC_SUPERTILE_PER_PRIM_H12 prims with < 8K supertiles @&ZSC_SUPERTILE_PER_PRIM_H13: SC_SUPERTILE_PER_PRIM_H13 prims with < 16K supertiles 'ZSC_SUPERTILE_PER_PRIM_H14: SC_SUPERTILE_PER_PRIM_H14 prims with < 32K supertiles h(ZSC_SUPERTILE_PER_PRIM_H15: SC_SUPERTILE_PER_PRIM_H15 prims with < 64K supertiles ൘H)ZSC_SUPERTILE_PER_PRIM_H16: SC_SUPERTILE_PER_PRIM_H16 prims with < 1M supertiles (*OSC_TILE_PER_PRIM_H0: SC_TILE_PER_PRIM_H0 prims with < 2 tiles +OSC_TILE_PER_PRIM_H1: SC_TILE_PER_PRIM_H1 prims with < 4 tiles hط,OSC_TILE_PER_PRIM_H2: SC_TILE_PER_PRIM_H2 prims with < 8 tiles @-OSC_TILE_PER_PRIM_H3: SC_TILE_PER_PRIM_H3 prims with < 16 tiles .OSC_TILE_PER_PRIM_H4: SC_TILE_PER_PRIM_H4 prims with < 32 tiles `/OSC_TILE_PER_PRIM_H5: SC_TILE_PER_PRIM_H5 prims with < 64 tiles Ȼ80OSC_TILE_PER_PRIM_H6: SC_TILE_PER_PRIM_H6 prims with < 128 tiles 1OSC_TILE_PER_PRIM_H7: SC_TILE_PER_PRIM_H7 prims with < 256 tiles x輘2OSC_TILE_PER_PRIM_H8: SC_TILE_PER_PRIM_H8 prims with < 512 tiles P3OSC_TILE_PER_PRIM_H9: SC_TILE_PER_PRIM_H9 prims with < 1K tiles (4PSC_TILE_PER_PRIM_H10: SC_TILE_PER_PRIM_H10 prims with < 2K tiles p5PSC_TILE_PER_PRIM_H11: SC_TILE_PER_PRIM_H11 prims with < 4K tiles P6PSC_TILE_PER_PRIM_H12: SC_TILE_PER_PRIM_H12 prims with < 8K tiles (7PSC_TILE_PER_PRIM_H13: SC_TILE_PER_PRIM_H13 prims with < 16K tiles ˜˜8PSC_TILE_PER_PRIM_H14: SC_TILE_PER_PRIM_H14 prims with < 32K tiles hؘ9PSC_TILE_PER_PRIM_H15: SC_TILE_PER_PRIM_H15 prims with < 64K tiles @ĘØ:PSC_TILE_PER_PRIM_H16: SC_TILE_PER_PRIM_H16 prims with < 1M tiles (ŘĘ;aSC_TILE_PER_SUPERTILE_H0: SC_TILE_PER_SUPERTILE_H0 supertiles walked with 0 tiles hit ƘpŘ<aSC_TILE_PER_SUPERTILE_H1: SC_TILE_PER_SUPERTILE_H1 supertiles walked with 1 tiles hit ƘXƘ=aSC_TILE_PER_SUPERTILE_H2: SC_TILE_PER_SUPERTILE_H2 supertiles walked with 2 tiles hit ǘ@ǘ>aSC_TILE_PER_SUPERTILE_H3: SC_TILE_PER_SUPERTILE_H3 supertiles walked with 3 tiles hit Ș(Ș?aSC_TILE_PER_SUPERTILE_H4: SC_TILE_PER_SUPERTILE_H4 supertiles walked with 4 tiles hit ɘɘ@aSC_TILE_PER_SUPERTILE_H5: SC_TILE_PER_SUPERTILE_H5 supertiles walked with 5 tiles hit ʘɘAaSC_TILE_PER_SUPERTILE_H6: SC_TILE_PER_SUPERTILE_H6 supertiles walked with 6 tiles hit ˘ʘBaSC_TILE_PER_SUPERTILE_H7: SC_TILE_PER_SUPERTILE_H7 supertiles walked with 7 tiles hit h̘˘CaSC_TILE_PER_SUPERTILE_H8: SC_TILE_PER_SUPERTILE_H8 supertiles walked with 8 tiles hit P̘͘DaSC_TILE_PER_SUPERTILE_H9: SC_TILE_PER_SUPERTILE_H9 supertiles walked with 9 tiles hit 8Θ͘EbSC_TILE_PER_SUPERTILE_H10: SC_TILE_PER_SUPERTILE_H10 supertiles walked with 10 tiles hit ϘΘFbSC_TILE_PER_SUPERTILE_H11: SC_TILE_PER_SUPERTILE_H11 supertiles walked with 11 tiles hit ИhϘGbSC_TILE_PER_SUPERTILE_H12: SC_TILE_PER_SUPERTILE_H12 supertiles walked with 12 tiles hit ИPИHbSC_TILE_PER_SUPERTILE_H13: SC_TILE_PER_SUPERTILE_H13 supertiles walked with 13 tiles hit ј8јIbSC_TILE_PER_SUPERTILE_H14: SC_TILE_PER_SUPERTILE_H14 supertiles walked with 14 tiles hit Ҙ ҘJbSC_TILE_PER_SUPERTILE_H15: SC_TILE_PER_SUPERTILE_H15 supertiles walked with 15 tiles hit ӘӘKbSC_TILE_PER_SUPERTILE_H16: SC_TILE_PER_SUPERTILE_H16 supertiles walked with 16 tiles hit ԘӘLTSC_TILE_PICKED_H1: SC_TILE_PICKED_H1 number of times 1 tile picked `՘ԘMUSC_TILE_PICKED_H2: SC_TILE_PICKED_H2 number of times 2 tiles picked P֘՘NjSC_TILE_PICKED_CONFLICT: SC_TILE_PICKED_CONFLICT number of times 1 tile picked b/c of conflict Hט֘OqSC_QZ0_MULTICHIP_TILE_DISCARD: SC_QZ0_MULTICHIP_TILE_DISCARD tiles discarded by optimization; quad-z pipe 0 @ؘטPqSC_QZ1_MULTICHIP_TILE_DISCARD: SC_QZ1_MULTICHIP_TILE_DISCARD tiles discarded by optimization; quad-z pipe 1 ؘ٘QPSC_QZ0_TILE_COUNT: SC_QZ0_TILE_COUNT tile count; quad-z pipe 0 ٘`٘RPSC_QZ1_TILE_COUNT: SC_QZ1_TILE_COUNT tile count; quad-z pipe 1 ژ8ژS`SC_QZ0_TILE_COVERED_COUNT: SC_QZ0_TILE_COVERED_COUNT tile covered count; quad-z pipe 0 ۘ ۘT`SC_QZ1_TILE_COVERED_COUNT: SC_QZ1_TILE_COVERED_COUNT tile covered count; quad-z pipe 1 ܘܘUhSC_QZ0_TILE_NOT_COVERED_COUNT: SC_QZ0_TILE_NOT_COVERED_COUNT tile not covered count; quad-z pipe 0 ݘܘVhSC_QZ1_TILE_NOT_COVERED_COUNT: SC_QZ1_TILE_NOT_COVERED_COUNT tile not covered count; quad-z pipe 1 ޘݘWjSC_QZ0_QUAD_PER_TILE_H0: SC_QZ0_QUAD_PER_TILE_H0 tiles walked with 0 quads hit; quad-z pipe 0 ߘޘXjSC_QZ0_QUAD_PER_TILE_H1: SC_QZ0_QUAD_PER_TILE_H1 tiles walked with 1 quads hit; quad-z pipe 0 pߘYjSC_QZ0_QUAD_PER_TILE_H2: SC_QZ0_QUAD_PER_TILE_H2 tiles walked with 2 quads hit; quad-z pipe 0 `ZjSC_QZ0_QUAD_PER_TILE_H3: SC_QZ0_QUAD_PER_TILE_H3 tiles walked with 3 quads hit; quad-z pipe 0 P[jSC_QZ0_QUAD_PER_TILE_H4: SC_QZ0_QUAD_PER_TILE_H4 tiles walked with 4 quads hit; quad-z pipe 0 @\jSC_QZ0_QUAD_PER_TILE_H5: SC_QZ0_QUAD_PER_TILE_H5 tiles walked with 5 quads hit; quad-z pipe 0 0]jSC_QZ0_QUAD_PER_TILE_H6: SC_QZ0_QUAD_PER_TILE_H6 tiles walked with 6 quads hit; quad-z pipe 0 x^jSC_QZ0_QUAD_PER_TILE_H7: SC_QZ0_QUAD_PER_TILE_H7 tiles walked with 7 quads hit; quad-z pipe 0 h_jSC_QZ0_QUAD_PER_TILE_H8: SC_QZ0_QUAD_PER_TILE_H8 tiles walked with 8 quads hit; quad-z pipe 0 X`jSC_QZ0_QUAD_PER_TILE_H9: SC_QZ0_QUAD_PER_TILE_H9 tiles walked with 9 quads hit; quad-z pipe 0 HakSC_QZ0_QUAD_PER_TILE_H10: SC_QZ0_QUAD_PER_TILE_H10 tiles walked with 10 quads hit; quad-z pipe 0 8bkSC_QZ0_QUAD_PER_TILE_H11: SC_QZ0_QUAD_PER_TILE_H11 tiles walked with 11 quads hit; quad-z pipe 0 (ckSC_QZ0_QUAD_PER_TILE_H12: SC_QZ0_QUAD_PER_TILE_H12 tiles walked with 12 quads hit; quad-z pipe 0 dkSC_QZ0_QUAD_PER_TILE_H13: SC_QZ0_QUAD_PER_TILE_H13 tiles walked with 13 quads hit; quad-z pipe 0 ekSC_QZ0_QUAD_PER_TILE_H14: SC_QZ0_QUAD_PER_TILE_H14 tiles walked with 14 quads hit; quad-z pipe 0 fkSC_QZ0_QUAD_PER_TILE_H15: SC_QZ0_QUAD_PER_TILE_H15 tiles walked with 15 quads hit; quad-z pipe 0 gkSC_QZ0_QUAD_PER_TILE_H16: SC_QZ0_QUAD_PER_TILE_H16 tiles walked with 16 quads hit; quad-z pipe 0 hjSC_QZ1_QUAD_PER_TILE_H0: SC_QZ1_QUAD_PER_TILE_H0 tiles walked with 0 quads hit; quad-z pipe 1 pijSC_QZ1_QUAD_PER_TILE_H1: SC_QZ1_QUAD_PER_TILE_H1 tiles walked with 1 quads hit; quad-z pipe 1 `jjSC_QZ1_QUAD_PER_TILE_H2: SC_QZ1_QUAD_PER_TILE_H2 tiles walked with 2 quads hit; quad-z pipe 1 PkjSC_QZ1_QUAD_PER_TILE_H3: SC_QZ1_QUAD_PER_TILE_H3 tiles walked with 3 quads hit; quad-z pipe 1 @ljSC_QZ1_QUAD_PER_TILE_H4: SC_QZ1_QUAD_PER_TILE_H4 tiles walked with 4 quads hit; quad-z pipe 1 0mjSC_QZ1_QUAD_PER_TILE_H5: SC_QZ1_QUAD_PER_TILE_H5 tiles walked with 5 quads hit; quad-z pipe 1 xnjSC_QZ1_QUAD_PER_TILE_H6: SC_QZ1_QUAD_PER_TILE_H6 tiles walked with 6 quads hit; quad-z pipe 1 hojSC_QZ1_QUAD_PER_TILE_H7: SC_QZ1_QUAD_PER_TILE_H7 tiles walked with 7 quads hit; quad-z pipe 1 XpjSC_QZ1_QUAD_PER_TILE_H8: SC_QZ1_QUAD_PER_TILE_H8 tiles walked with 8 quads hit; quad-z pipe 1 HqjSC_QZ1_QUAD_PER_TILE_H9: SC_QZ1_QUAD_PER_TILE_H9 tiles walked with 9 quads hit; quad-z pipe 1 8rkSC_QZ1_QUAD_PER_TILE_H10: SC_QZ1_QUAD_PER_TILE_H10 tiles walked with 10 quads hit; quad-z pipe 1 (skSC_QZ1_QUAD_PER_TILE_H11: SC_QZ1_QUAD_PER_TILE_H11 tiles walked with 11 quads hit; quad-z pipe 1 tkSC_QZ1_QUAD_PER_TILE_H12: SC_QZ1_QUAD_PER_TILE_H12 tiles walked with 12 quads hit; quad-z pipe 1 ukSC_QZ1_QUAD_PER_TILE_H13: SC_QZ1_QUAD_PER_TILE_H13 tiles walked with 13 quads hit; quad-z pipe 1 vkSC_QZ1_QUAD_PER_TILE_H14: SC_QZ1_QUAD_PER_TILE_H14 tiles walked with 14 quads hit; quad-z pipe 1 wkSC_QZ1_QUAD_PER_TILE_H15: SC_QZ1_QUAD_PER_TILE_H15 tiles walked with 15 quads hit; quad-z pipe 1 xkSC_QZ1_QUAD_PER_TILE_H16: SC_QZ1_QUAD_PER_TILE_H16 tiles walked with 16 quads hit; quad-z pipe 1 XyPSC_QZ0_QUAD_COUNT: SC_QZ0_QUAD_COUNT quad count; quad-z pipe 0 0zPSC_QZ1_QUAD_COUNT: SC_QZ1_QUAD_COUNT quad count; quad-z pipe 1 x{TSC_QUAD0_NOT_PICKED_TB_R6XX: SC_QUAD0_NOT_PICKED_TB_GPU6 deprecated for GPU7 P|TSC_QUAD1_NOT_PICKED_TB_R6XX: SC_QUAD1_NOT_PICKED_TB_GPU6 deprecated for GPU7 (}TSC_QUAD2_NOT_PICKED_TB_R6XX: SC_QUAD2_NOT_PICKED_TB_GPU6 deprecated for GPU7 ~TSC_QUAD3_NOT_PICKED_TB_R6XX: SC_QUAD3_NOT_PICKED_TB_GPU6 deprecated for GPU7 x_SC_P0_HIZ_TILE_COUNT: SC_P0_HIZ_TILE_COUNT total tiles surviving hi-z; db pipe 0 `_SC_P1_HIZ_TILE_COUNT: SC_P1_HIZ_TILE_COUNT total tiles surviving hi-z; db pipe 1 H_SC_P2_HIZ_TILE_COUNT: SC_P2_HIZ_TILE_COUNT total tiles surviving hi-z; db pipe 2 0_SC_P3_HIZ_TILE_COUNT: SC_P3_HIZ_TILE_COUNT total tiles surviving hi-z; db pipe 3 (xmSC_P0_HIZ_QUAD_PER_TILE_H0: SC_P0_HIZ_QUAD_PER_TILE_H0 tiles with 0 quads surviving hi-z; db pipe 0 pmSC_P0_HIZ_QUAD_PER_TILE_H1: SC_P0_HIZ_QUAD_PER_TILE_H1 tiles with 1 quads surviving hi-z; db pipe 0  hmSC_P0_HIZ_QUAD_PER_TILE_H2: SC_P0_HIZ_QUAD_PER_TILE_H2 tiles with 2 quads surviving hi-z; db pipe 0  ` mSC_P0_HIZ_QUAD_PER_TILE_H3: SC_P0_HIZ_QUAD_PER_TILE_H3 tiles with 3 quads surviving hi-z; db pipe 0  X mSC_P0_HIZ_QUAD_PER_TILE_H4: SC_P0_HIZ_QUAD_PER_TILE_H4 tiles with 4 quads surviving hi-z; db pipe 0 P mSC_P0_HIZ_QUAD_PER_TILE_H5: SC_P0_HIZ_QUAD_PER_TILE_H5 tiles with 5 quads surviving hi-z; db pipe 0 H mSC_P0_HIZ_QUAD_PER_TILE_H6: SC_P0_HIZ_QUAD_PER_TILE_H6 tiles with 6 quads surviving hi-z; db pipe 0 @ mSC_P0_HIZ_QUAD_PER_TILE_H7: SC_P0_HIZ_QUAD_PER_TILE_H7 tiles with 7 quads surviving hi-z; db pipe 0 8mSC_P0_HIZ_QUAD_PER_TILE_H8: SC_P0_HIZ_QUAD_PER_TILE_H8 tiles with 8 quads surviving hi-z; db pipe 0 0mSC_P0_HIZ_QUAD_PER_TILE_H9: SC_P0_HIZ_QUAD_PER_TILE_H9 tiles with 9 quads surviving hi-z; db pipe 0 (nSC_P0_HIZ_QUAD_PER_TILE_H10: SC_P0_HIZ_QUAD_PER_TILE_H10 tiles with 10 quads surviving hi-z; db pipe 0  nSC_P0_HIZ_QUAD_PER_TILE_H11: SC_P0_HIZ_QUAD_PER_TILE_H11 tiles with 11 quads surviving hi-z; db pipe 0 nSC_P0_HIZ_QUAD_PER_TILE_H12: SC_P0_HIZ_QUAD_PER_TILE_H12 tiles with 12 quads surviving hi-z; db pipe 0 nSC_P0_HIZ_QUAD_PER_TILE_H13: SC_P0_HIZ_QUAD_PER_TILE_H13 tiles with 13 quads surviving hi-z; db pipe 0 nSC_P0_HIZ_QUAD_PER_TILE_H14: SC_P0_HIZ_QUAD_PER_TILE_H14 tiles with 14 quads surviving hi-z; db pipe 0 nSC_P0_HIZ_QUAD_PER_TILE_H15: SC_P0_HIZ_QUAD_PER_TILE_H15 tiles with 15 quads surviving hi-z; db pipe 0 nSC_P0_HIZ_QUAD_PER_TILE_H16: SC_P0_HIZ_QUAD_PER_TILE_H16 tiles with 16 quads surviving hi-z; db pipe 0 mSC_P1_HIZ_QUAD_PER_TILE_H0: SC_P0_HIZ_QUAD_PER_TILE_H0 tiles with 0 quads surviving hi-z; db pipe 1 mSC_P1_HIZ_QUAD_PER_TILE_H1: SC_P0_HIZ_QUAD_PER_TILE_H1 tiles with 1 quads surviving hi-z; db pipe 1 mSC_P1_HIZ_QUAD_PER_TILE_H2: SC_P1_HIZ_QUAD_PER_TILE_H2 tiles with 2 quads surviving hi-z; db pipe 1 mSC_P1_HIZ_QUAD_PER_TILE_H3: SC_P1_HIZ_QUAD_PER_TILE_H3 tiles with 3 quads surviving hi-z; db pipe 1 mSC_P1_HIZ_QUAD_PER_TILE_H4: SC_P1_HIZ_QUAD_PER_TILE_H4 tiles with 4 quads surviving hi-z; db pipe 1 xmSC_P1_HIZ_QUAD_PER_TILE_H5: SC_P1_HIZ_QUAD_PER_TILE_H5 tiles with 5 quads surviving hi-z; db pipe 1 pmSC_P1_HIZ_QUAD_PER_TILE_H6: SC_P1_HIZ_QUAD_PER_TILE_H6 tiles with 6 quads surviving hi-z; db pipe 1 hmSC_P1_HIZ_QUAD_PER_TILE_H7: SC_P1_HIZ_QUAD_PER_TILE_H7 tiles with 7 quads surviving hi-z; db pipe 1 `mSC_P1_HIZ_QUAD_PER_TILE_H8: SC_P1_HIZ_QUAD_PER_TILE_H8 tiles with 8 quads surviving hi-z; db pipe 1 X mSC_P1_HIZ_QUAD_PER_TILE_H9: SC_P1_HIZ_QUAD_PER_TILE_H9 tiles with 9 quads surviving hi-z; db pipe 1 P! nSC_P1_HIZ_QUAD_PER_TILE_H10: SC_P1_HIZ_QUAD_PER_TILE_H10 tiles with 10 quads surviving hi-z; db pipe 1 H"!nSC_P1_HIZ_QUAD_PER_TILE_H11: SC_P1_HIZ_QUAD_PER_TILE_H11 tiles with 11 quads surviving hi-z; db pipe 1 @#"nSC_P1_HIZ_QUAD_PER_TILE_H12: SC_P1_HIZ_QUAD_PER_TILE_H12 tiles with 12 quads surviving hi-z; db pipe 1 8$#nSC_P1_HIZ_QUAD_PER_TILE_H13: SC_P1_HIZ_QUAD_PER_TILE_H13 tiles with 13 quads surviving hi-z; db pipe 1 0%$nSC_P1_HIZ_QUAD_PER_TILE_H14: SC_P1_HIZ_QUAD_PER_TILE_H14 tiles with 14 quads surviving hi-z; db pipe 1 (&x%nSC_P1_HIZ_QUAD_PER_TILE_H15: SC_P1_HIZ_QUAD_PER_TILE_H15 tiles with 15 quads surviving hi-z; db pipe 1 'p&nSC_P1_HIZ_QUAD_PER_TILE_H16: SC_P1_HIZ_QUAD_PER_TILE_H16 tiles with 16 quads surviving hi-z; db pipe 1 (h'mSC_P2_HIZ_QUAD_PER_TILE_H0: SC_P2_HIZ_QUAD_PER_TILE_H0 tiles with 0 quads surviving hi-z; db pipe 2 )`(mSC_P2_HIZ_QUAD_PER_TILE_H1: SC_P2_HIZ_QUAD_PER_TILE_H1 tiles with 1 quads surviving hi-z; db pipe 2 *X)mSC_P2_HIZ_QUAD_PER_TILE_H2: SC_P2_HIZ_QUAD_PER_TILE_H2 tiles with 2 quads surviving hi-z; db pipe 2 +P*mSC_P2_HIZ_QUAD_PER_TILE_H3: SC_P2_HIZ_QUAD_PER_TILE_H3 tiles with 3 quads surviving hi-z; db pipe 2 +H+mSC_P2_HIZ_QUAD_PER_TILE_H4: SC_P2_HIZ_QUAD_PER_TILE_H4 tiles with 4 quads surviving hi-z; db pipe 2 ,@,mSC_P2_HIZ_QUAD_PER_TILE_H5: SC_P2_HIZ_QUAD_PER_TILE_H5 tiles with 5 quads surviving hi-z; db pipe 2 -8-mSC_P2_HIZ_QUAD_PER_TILE_H6: SC_P2_HIZ_QUAD_PER_TILE_H6 tiles with 6 quads surviving hi-z; db pipe 2 .0.mSC_P2_HIZ_QUAD_PER_TILE_H7: SC_P2_HIZ_QUAD_PER_TILE_H7 tiles with 7 quads surviving hi-z; db pipe 2 /(/mSC_P2_HIZ_QUAD_PER_TILE_H8: SC_P2_HIZ_QUAD_PER_TILE_H8 tiles with 8 quads surviving hi-z; db pipe 2 0 0mSC_P2_HIZ_QUAD_PER_TILE_H9: SC_P2_HIZ_QUAD_PER_TILE_H9 tiles with 9 quads surviving hi-z; db pipe 2 11nSC_P2_HIZ_QUAD_PER_TILE_H10: SC_P2_HIZ_QUAD_PER_TILE_H10 tiles with 10 quads surviving hi-z; db pipe 2 22nSC_P2_HIZ_QUAD_PER_TILE_H11: SC_P2_HIZ_QUAD_PER_TILE_H11 tiles with 11 quads surviving hi-z; db pipe 2 33nSC_P2_HIZ_QUAD_PER_TILE_H12: SC_P2_HIZ_QUAD_PER_TILE_H12 tiles with 12 quads surviving hi-z; db pipe 2 44nSC_P2_HIZ_QUAD_PER_TILE_H13: SC_P2_HIZ_QUAD_PER_TILE_H13 tiles with 13 quads surviving hi-z; db pipe 2 54nSC_P2_HIZ_QUAD_PER_TILE_H14: SC_P2_HIZ_QUAD_PER_TILE_H14 tiles with 14 quads surviving hi-z; db pipe 2 65nSC_P2_HIZ_QUAD_PER_TILE_H15: SC_P2_HIZ_QUAD_PER_TILE_H15 tiles with 15 quads surviving hi-z; db pipe 2 76nSC_P2_HIZ_QUAD_PER_TILE_H16: SC_P2_HIZ_QUAD_PER_TILE_H16 tiles with 16 quads surviving hi-z; db pipe 2 87mSC_P3_HIZ_QUAD_PER_TILE_H0: SC_P3_HIZ_QUAD_PER_TILE_H0 tiles with 0 quads surviving hi-z; db pipe 3 98mSC_P3_HIZ_QUAD_PER_TILE_H1: SC_P3_HIZ_QUAD_PER_TILE_H1 tiles with 1 quads surviving hi-z; db pipe 3 :9mSC_P3_HIZ_QUAD_PER_TILE_H2: SC_P3_HIZ_QUAD_PER_TILE_H2 tiles with 2 quads surviving hi-z; db pipe 3 x;:mSC_P3_HIZ_QUAD_PER_TILE_H3: SC_P3_HIZ_QUAD_PER_TILE_H3 tiles with 3 quads surviving hi-z; db pipe 3 p<;mSC_P3_HIZ_QUAD_PER_TILE_H4: SC_P3_HIZ_QUAD_PER_TILE_H4 tiles with 4 quads surviving hi-z; db pipe 3 h=<mSC_P3_HIZ_QUAD_PER_TILE_H5: SC_P3_HIZ_QUAD_PER_TILE_H5 tiles with 5 quads surviving hi-z; db pipe 3 `>=mSC_P3_HIZ_QUAD_PER_TILE_H6: SC_P3_HIZ_QUAD_PER_TILE_H6 tiles with 6 quads surviving hi-z; db pipe 3 X?>mSC_P3_HIZ_QUAD_PER_TILE_H7: SC_P3_HIZ_QUAD_PER_TILE_H7 tiles with 7 quads surviving hi-z; db pipe 3 P@?mSC_P3_HIZ_QUAD_PER_TILE_H8: SC_P3_HIZ_QUAD_PER_TILE_H8 tiles with 8 quads surviving hi-z; db pipe 3 HA@mSC_P3_HIZ_QUAD_PER_TILE_H9: SC_P3_HIZ_QUAD_PER_TILE_H9 tiles with 9 quads surviving hi-z; db pipe 3 @BAnSC_P3_HIZ_QUAD_PER_TILE_H10: SC_P3_HIZ_QUAD_PER_TILE_H10 tiles with 10 quads surviving hi-z; db pipe 3 8CBnSC_P3_HIZ_QUAD_PER_TILE_H11: SC_P3_HIZ_QUAD_PER_TILE_H11 tiles with 11 quads surviving hi-z; db pipe 3 0DCnSC_P3_HIZ_QUAD_PER_TILE_H12: SC_P3_HIZ_QUAD_PER_TILE_H12 tiles with 12 quads surviving hi-z; db pipe 3 (ExDnSC_P3_HIZ_QUAD_PER_TILE_H13: SC_P3_HIZ_QUAD_PER_TILE_H13 tiles with 13 quads surviving hi-z; db pipe 3 FpEnSC_P3_HIZ_QUAD_PER_TILE_H14: SC_P3_HIZ_QUAD_PER_TILE_H14 tiles with 14 quads surviving hi-z; db pipe 3 GhFnSC_P3_HIZ_QUAD_PER_TILE_H15: SC_P3_HIZ_QUAD_PER_TILE_H15 tiles with 15 quads surviving hi-z; db pipe 3 H`GnSC_P3_HIZ_QUAD_PER_TILE_H16: SC_P3_HIZ_QUAD_PER_TILE_H16 tiles with 16 quads surviving hi-z; db pipe 3 HXH_SC_P0_HIZ_QUAD_COUNT: SC_P0_HIZ_QUAD_COUNT total quads surviving hi-z; db pipe 0 I@I_SC_P1_HIZ_QUAD_COUNT: SC_P1_HIZ_QUAD_COUNT total quads surviving hi-z; db pipe 1 J(J_SC_P2_HIZ_QUAD_COUNT: SC_P2_HIZ_QUAD_COUNT total quads surviving hi-z; db pipe 2 KK_SC_P3_HIZ_QUAD_COUNT: SC_P3_HIZ_QUAD_COUNT total quads surviving hi-z; db pipe 3 LKlSC_P0_DETAIL_QUAD_COUNT: SC_P0_DETAIL_QUAD_COUNT total quads surviving detail sampler; db pipe 0 MLlSC_P1_DETAIL_QUAD_COUNT: SC_P1_DETAIL_QUAD_COUNT total quads surviving detail sampler; db pipe 1 NMlSC_P2_DETAIL_QUAD_COUNT: SC_P2_DETAIL_QUAD_COUNT total quads surviving detail sampler; db pipe 2 pONlSC_P3_DETAIL_QUAD_COUNT: SC_P3_DETAIL_QUAD_COUNT total quads surviving detail sampler; db pipe 3 hPOpSC_P0_DETAIL_QUAD_WITH_1_PIX: SC_P0_DETAIL_QUAD_WITH_1_PIX quads with 1 pixel surviving detail; db pipe 0 `QPqSC_P0_DETAIL_QUAD_WITH_2_PIX: SC_P0_DETAIL_QUAD_WITH_2_PIX quads with 2 pixels surviving detail; db pipe 0 XRQqSC_P0_DETAIL_QUAD_WITH_3_PIX: SC_P0_DETAIL_QUAD_WITH_3_PIX quads with 3 pixels surviving detail; db pipe 0 PSRqSC_P0_DETAIL_QUAD_WITH_4_PIX: SC_P0_DETAIL_QUAD_WITH_4_PIX quads with 4 pixels surviving detail; db pipe 0 HTSpSC_P1_DETAIL_QUAD_WITH_1_PIX: SC_P1_DETAIL_QUAD_WITH_1_PIX quads with 1 pixel surviving detail; db pipe 1 @UTqSC_P1_DETAIL_QUAD_WITH_2_PIX: SC_P1_DETAIL_QUAD_WITH_2_PIX quads with 2 pixels surviving detail; db pipe 1 8VUqSC_P1_DETAIL_QUAD_WITH_3_PIX: SC_P1_DETAIL_QUAD_WITH_3_PIX quads with 3 pixels surviving detail; db pipe 1 0WVqSC_P1_DETAIL_QUAD_WITH_4_PIX: SC_P1_DETAIL_QUAD_WITH_4_PIX quads with 4 pixels surviving detail; db pipe 1 (XxWpSC_P2_DETAIL_QUAD_WITH_1_PIX: SC_P2_DETAIL_QUAD_WITH_1_PIX quads with 1 pixel surviving detail; db pipe 2 YpXqSC_P2_DETAIL_QUAD_WITH_2_PIX: SC_P2_DETAIL_QUAD_WITH_2_PIX quads with 2 pixels surviving detail; db pipe 2 ZhYqSC_P2_DETAIL_QUAD_WITH_3_PIX: SC_P2_DETAIL_QUAD_WITH_3_PIX quads with 3 pixels surviving detail; db pipe 2 [`ZqSC_P2_DETAIL_QUAD_WITH_4_PIX: SC_P2_DETAIL_QUAD_WITH_4_PIX quads with 4 pixels surviving detail; db pipe 2 \X[pSC_P3_DETAIL_QUAD_WITH_1_PIX: SC_P3_DETAIL_QUAD_WITH_1_PIX quads with 1 pixel surviving detail; db pipe 3 ]P\qSC_P3_DETAIL_QUAD_WITH_2_PIX: SC_P3_DETAIL_QUAD_WITH_2_PIX quads with 2 pixels surviving detail; db pipe 3 ]H]qSC_P3_DETAIL_QUAD_WITH_3_PIX: SC_P3_DETAIL_QUAD_WITH_3_PIX quads with 3 pixels surviving detail; db pipe 3 ^@^qSC_P3_DETAIL_QUAD_WITH_4_PIX: SC_P3_DETAIL_QUAD_WITH_4_PIX quads with 4 pixels surviving detail; db pipe 3 _8_WSC_EARLYZ_QUAD_COUNT: SC_EARLYZ_QUAD_COUNT total quads surviving early-z ``cSC_EARLYZ_QUAD_WITH_1_PIX: SC_EARLYZ_QUAD_WITH_1_PIX quads with 1 pixel surviving early-z aadSC_EARLYZ_QUAD_WITH_2_PIX: SC_EARLYZ_QUAD_WITH_2_PIX quads with 2 pixels surviving early-z badSC_EARLYZ_QUAD_WITH_3_PIX: SC_EARLYZ_QUAD_WITH_3_PIX quads with 3 pixels surviving early-z pcbdSC_EARLYZ_QUAD_WITH_4_PIX: SC_EARLYZ_QUAD_WITH_4_PIX quads with 4 pixels surviving early-z PdcYSC_TILE_REORDER_DB_CONFLICT_R6XX: SC_TILE_REORDER_DB_CONFLICT_GPU6 deprecated for GPU7 8ed`SC_PKR_QUAD_PER_ROW_H1: SC_PKR_QUAD_PER_ROW_H1 packer row outputs with 1 valid quad fe`SC_PKR_QUAD_PER_ROW_H2: SC_PKR_QUAD_PER_ROW_H2 packer row outputs with 2 valid quad ghf`SC_PKR_QUAD_PER_ROW_H3: SC_PKR_QUAD_PER_ROW_H3 packer row outputs with 3 valid quad gPg`SC_PKR_QUAD_PER_ROW_H4: SC_PKR_QUAD_PER_ROW_H4 packer row outputs with 4 valid quad h8hQSC_PKR_END_OF_VECTOR: SC_PKR_END_OF_VECTOR number of pixel vectors iiTSC_PKR_CONTROL_XFER: SC_PKR_CONTROL_XFER number of control transfers ji|SC_PKR_DBHANG_FORCE_EOV: SC_PKR_DBHANG_FORCE_EOV number of times partial vector ejected b/c of DB hang condition kj]SC_REG_SCLK_BUSY: SC_REG_SCLK_BUSY number of cycles register clock is busy xlkhSC_GRP0_DYN_SCLK_BUSY: SC_GRP0_DYN_SCLK_BUSY number of cycles group0 dynamic clock is busy hmlhSC_GRP1_DYN_SCLK_BUSY: SC_GRP1_DYN_SCLK_BUSY number of cycles group1 dynamic clock is busy XnmhSC_GRP2_DYN_SCLK_BUSY: SC_GRP2_DYN_SCLK_BUSY number of cycles group2 dynamic clock is busy HonhSC_GRP3_DYN_SCLK_BUSY: SC_GRP3_DYN_SCLK_BUSY number of cycles group3 dynamic clock is busy ohSC_GRP4_DYN_SCLK_BUSY: SC_GRP4_DYN_SCLK_BUSY number of cycles group4 dynamic clock is busy ʖ"" PA_SC_PERFCOUNTER1_SELECTH PERF_SELحSC_SRPS_WINDOW_VALID: SC_SRPS_WINDOW_VALID Number of clocks event-window is valid at stage register/primitive setup ஗SC_PSSW_WINDOW_VALID: SC_PSSW_WINDOW_VALID Number of clocks event-window is valid at primitive setup/supertile walker 诗vSC_TPQZ_WINDOW_VALID: SC_TPQZ_WINDOW_VALID Number of clocks event-window is valid at tile picker/quad-z 谗ySC_QZQP_WINDOW_VALID: SC_QZQP_WINDOW_VALID Number of clocks event-window is valid at quad-z/quad processor 豗wSC_TRPK_WINDOW_VALID: SC_TRPK_WINDOW_VALID Number of clocks event-window is valid at tile reorder/packer 貗SC_SRPS_WINDOW_VALID_BUSY: SC_SRPS_WINDOW_VALID_BUSY Number of clocks event-window is valid at stage register/primitive setup with SC busy شSC_PSSW_WINDOW_VALID_BUSY: SC_PSSW_WINDOW_VALID_BUSY Number of clocks event-window is valid at primitive setup/supertile walker with SC busy 赗 SC_TPQZ_WINDOW_VALID_BUSY: SC_TPQZ_WINDOW_VALID_BUSY Number of clocks event-window is valid at tile picker/quad-z with SC busy 0SC_QZQP_WINDOW_VALID_BUSY: SC_QZQP_WINDOW_VALID_BUSY Number of clocks event-window is valid at quad-z/quad processor with SC busy @ SC_TRPK_WINDOW_VALID_BUSY: SC_TRPK_WINDOW_VALID_BUSY Number of clocks event-window is valid at tile reorder/packer with SC busy ظP FSC_STARVED_BY_PA: SC_STARVED_BY_PA sc starved by pa XSC_STALLED_BY_PRIMFIFO: SC_STALLED_BY_PRIMFIFO sc stalled by primitive fifo PSC_STARVED_BY_DB_TILE: SC_STARVED_BY_DB_TILE sc starved by db tile hغ PSC_STARVED_BY_DB_QUAD: SC_STARVED_BY_DB_QUAD sc starved by db quad P^SC_STALLED_BY_TILEORDERFIFO: SC_STALLED_BY_TILEORDERFIFO sc stalled by tile order fifo (SSC_STALLED_BY_TILEFIFO: SC_STALLED_BY_TILEFIFO sc stalled by tile fifo pSSC_STALLED_BY_QUADFIFO: SC_STALLED_BY_QUADFIFO sc stalled by quad fifo ؾHPSC_STALLED_BY_DB_TILE: SC_STALLED_BY_DB_TILE sc stalled by db tile PSC_STALLED_BY_DB_QUAD: SC_STALLED_BY_DB_QUAD sc stalled by db quad FSC_STALLED_BY_SX: SC_STALLED_BY_SX sc stalled by sx PHSC_STALLED_BY_SPI: SC_STALLED_BY_SPI sc stalled by spi 8—aSC_SCISSOR_DISCARD: SC_SCISSOR_DISCARD primitive completely discarded by scissor (חkSC_BB_DISCARD: SC_BB_DISCARD primitive discarded by bounding-box check, no pixels hit ėp×mSC_MULTICHIP_PRIM_DISCARD: SC_MULTICHIP_PRIM_DISCARD primitive completely discarded by optimization ėhėGSC_SUPERTILE_COUNT: SC_SUPERTILE_COUNT supertile count ŗ8ŗYSC_SUPERTILE_PER_PRIM_H0: SC_SUPERTILE_PER_PRIM_H0 prims with < 2 supertiles ƗƗYSC_SUPERTILE_PER_PRIM_H1: SC_SUPERTILE_PER_PRIM_H1 prims with < 4 supertiles ǗƗYSC_SUPERTILE_PER_PRIM_H2: SC_SUPERTILE_PER_PRIM_H2 prims with < 8 supertiles pȗǗYSC_SUPERTILE_PER_PRIM_H3: SC_SUPERTILE_PER_PRIM_H3 prims with < 16 supertiles PɗȗYSC_SUPERTILE_PER_PRIM_H4: SC_SUPERTILE_PER_PRIM_H4 prims with < 32 supertiles 0ʗɗYSC_SUPERTILE_PER_PRIM_H5: SC_SUPERTILE_PER_PRIM_H5 prims with < 64 supertiles ˗xʗYSC_SUPERTILE_PER_PRIM_H6: SC_SUPERTILE_PER_PRIM_H6 prims with < 128 supertiles ˗X˗ YSC_SUPERTILE_PER_PRIM_H7: SC_SUPERTILE_PER_PRIM_H7 prims with < 256 supertiles ̗8̗!YSC_SUPERTILE_PER_PRIM_H8: SC_SUPERTILE_PER_PRIM_H8 prims with < 512 supertiles ͗͗"YSC_SUPERTILE_PER_PRIM_H9: SC_SUPERTILE_PER_PRIM_H9 prims with < 1K supertiles Η͗#ZSC_SUPERTILE_PER_PRIM_H10: SC_SUPERTILE_PER_PRIM_H10 prims with < 2K supertiles pϗΗ$ZSC_SUPERTILE_PER_PRIM_H11: SC_SUPERTILE_PER_PRIM_H11 prims with < 4K supertiles PЗϗ%ZSC_SUPERTILE_PER_PRIM_H12: SC_SUPERTILE_PER_PRIM_H12 prims with < 8K supertiles 0їЗ&ZSC_SUPERTILE_PER_PRIM_H13: SC_SUPERTILE_PER_PRIM_H13 prims with < 16K supertiles җxї'ZSC_SUPERTILE_PER_PRIM_H14: SC_SUPERTILE_PER_PRIM_H14 prims with < 32K supertiles җXҗ(ZSC_SUPERTILE_PER_PRIM_H15: SC_SUPERTILE_PER_PRIM_H15 prims with < 64K supertiles ӗ8ӗ)ZSC_SUPERTILE_PER_PRIM_H16: SC_SUPERTILE_PER_PRIM_H16 prims with < 1M supertiles ԗԗ*OSC_TILE_PER_PRIM_H0: SC_TILE_PER_PRIM_H0 prims with < 2 tiles ՗ԗ+OSC_TILE_PER_PRIM_H1: SC_TILE_PER_PRIM_H1 prims with < 4 tiles X֗՗,OSC_TILE_PER_PRIM_H2: SC_TILE_PER_PRIM_H2 prims with < 8 tiles 0ח֗-OSC_TILE_PER_PRIM_H3: SC_TILE_PER_PRIM_H3 prims with < 16 tiles ؗxח.OSC_TILE_PER_PRIM_H4: SC_TILE_PER_PRIM_H4 prims with < 32 tiles ؗPؗ/OSC_TILE_PER_PRIM_H5: SC_TILE_PER_PRIM_H5 prims with < 64 tiles ٗ(ٗ0OSC_TILE_PER_PRIM_H6: SC_TILE_PER_PRIM_H6 prims with < 128 tiles ڗڗ1OSC_TILE_PER_PRIM_H7: SC_TILE_PER_PRIM_H7 prims with < 256 tiles hۗڗ2OSC_TILE_PER_PRIM_H8: SC_TILE_PER_PRIM_H8 prims with < 512 tiles @ܗۗ3OSC_TILE_PER_PRIM_H9: SC_TILE_PER_PRIM_H9 prims with < 1K tiles ݗܗ4PSC_TILE_PER_PRIM_H10: SC_TILE_PER_PRIM_H10 prims with < 2K tiles ݗ`ݗ5PSC_TILE_PER_PRIM_H11: SC_TILE_PER_PRIM_H11 prims with < 4K tiles ޗ8ޗ6PSC_TILE_PER_PRIM_H12: SC_TILE_PER_PRIM_H12 prims with < 8K tiles ߗߗ7PSC_TILE_PER_PRIM_H13: SC_TILE_PER_PRIM_H13 prims with < 16K tiles xߗ8PSC_TILE_PER_PRIM_H14: SC_TILE_PER_PRIM_H14 prims with < 32K tiles P9PSC_TILE_PER_PRIM_H15: SC_TILE_PER_PRIM_H15 prims with < 64K tiles (:PSC_TILE_PER_PRIM_H16: SC_TILE_PER_PRIM_H16 prims with < 1M tiles p;aSC_TILE_PER_SUPERTILE_H0: SC_TILE_PER_SUPERTILE_H0 supertiles walked with 0 tiles hit X<aSC_TILE_PER_SUPERTILE_H1: SC_TILE_PER_SUPERTILE_H1 supertiles walked with 1 tiles hit @=aSC_TILE_PER_SUPERTILE_H2: SC_TILE_PER_SUPERTILE_H2 supertiles walked with 2 tiles hit (>aSC_TILE_PER_SUPERTILE_H3: SC_TILE_PER_SUPERTILE_H3 supertiles walked with 3 tiles hit ?aSC_TILE_PER_SUPERTILE_H4: SC_TILE_PER_SUPERTILE_H4 supertiles walked with 4 tiles hit @aSC_TILE_PER_SUPERTILE_H5: SC_TILE_PER_SUPERTILE_H5 supertiles walked with 5 tiles hit AaSC_TILE_PER_SUPERTILE_H6: SC_TILE_PER_SUPERTILE_H6 supertiles walked with 6 tiles hit hBaSC_TILE_PER_SUPERTILE_H7: SC_TILE_PER_SUPERTILE_H7 supertiles walked with 7 tiles hit PCaSC_TILE_PER_SUPERTILE_H8: SC_TILE_PER_SUPERTILE_H8 supertiles walked with 8 tiles hit 8DaSC_TILE_PER_SUPERTILE_H9: SC_TILE_PER_SUPERTILE_H9 supertiles walked with 9 tiles hit EbSC_TILE_PER_SUPERTILE_H10: SC_TILE_PER_SUPERTILE_H10 supertiles walked with 10 tiles hit hFbSC_TILE_PER_SUPERTILE_H11: SC_TILE_PER_SUPERTILE_H11 supertiles walked with 11 tiles hit PGbSC_TILE_PER_SUPERTILE_H12: SC_TILE_PER_SUPERTILE_H12 supertiles walked with 12 tiles hit 8HbSC_TILE_PER_SUPERTILE_H13: SC_TILE_PER_SUPERTILE_H13 supertiles walked with 13 tiles hit IbSC_TILE_PER_SUPERTILE_H14: SC_TILE_PER_SUPERTILE_H14 supertiles walked with 14 tiles hit JbSC_TILE_PER_SUPERTILE_H15: SC_TILE_PER_SUPERTILE_H15 supertiles walked with 15 tiles hit KbSC_TILE_PER_SUPERTILE_H16: SC_TILE_PER_SUPERTILE_H16 supertiles walked with 16 tiles hit hLTSC_TILE_PICKED_H1: SC_TILE_PICKED_H1 number of times 1 tile picked HMUSC_TILE_PICKED_H2: SC_TILE_PICKED_H2 number of times 2 tiles picked 8NjSC_TILE_PICKED_CONFLICT: SC_TILE_PICKED_CONFLICT number of times 1 tile picked b/c of conflict 0OqSC_QZ0_MULTICHIP_TILE_DISCARD: SC_QZ0_MULTICHIP_TILE_DISCARD tiles discarded by optimization; quad-z pipe 0 (xPqSC_QZ1_MULTICHIP_TILE_DISCARD: SC_QZ1_MULTICHIP_TILE_DISCARD tiles discarded by optimization; quad-z pipe 1 pQPSC_QZ0_TILE_COUNT: SC_QZ0_TILE_COUNT tile count; quad-z pipe 0 HRPSC_QZ1_TILE_COUNT: SC_QZ1_TILE_COUNT tile count; quad-z pipe 1 S`SC_QZ0_TILE_COVERED_COUNT: SC_QZ0_TILE_COVERED_COUNT tile covered count; quad-z pipe 0 T`SC_QZ1_TILE_COVERED_COUNT: SC_QZ1_TILE_COVERED_COUNT tile covered count; quad-z pipe 1 UhSC_QZ0_TILE_NOT_COVERED_COUNT: SC_QZ0_TILE_NOT_COVERED_COUNT tile not covered count; quad-z pipe 0 VhSC_QZ1_TILE_NOT_COVERED_COUNT: SC_QZ1_TILE_NOT_COVERED_COUNT tile not covered count; quad-z pipe 1 xWjSC_QZ0_QUAD_PER_TILE_H0: SC_QZ0_QUAD_PER_TILE_H0 tiles walked with 0 quads hit; quad-z pipe 0 hXjSC_QZ0_QUAD_PER_TILE_H1: SC_QZ0_QUAD_PER_TILE_H1 tiles walked with 1 quads hit; quad-z pipe 0 XYjSC_QZ0_QUAD_PER_TILE_H2: SC_QZ0_QUAD_PER_TILE_H2 tiles walked with 2 quads hit; quad-z pipe 0 HZjSC_QZ0_QUAD_PER_TILE_H3: SC_QZ0_QUAD_PER_TILE_H3 tiles walked with 3 quads hit; quad-z pipe 0 8[jSC_QZ0_QUAD_PER_TILE_H4: SC_QZ0_QUAD_PER_TILE_H4 tiles walked with 4 quads hit; quad-z pipe 0 (\jSC_QZ0_QUAD_PER_TILE_H5: SC_QZ0_QUAD_PER_TILE_H5 tiles walked with 5 quads hit; quad-z pipe 0 p]jSC_QZ0_QUAD_PER_TILE_H6: SC_QZ0_QUAD_PER_TILE_H6 tiles walked with 6 quads hit; quad-z pipe 0 `^jSC_QZ0_QUAD_PER_TILE_H7: SC_QZ0_QUAD_PER_TILE_H7 tiles walked with 7 quads hit; quad-z pipe 0 P_jSC_QZ0_QUAD_PER_TILE_H8: SC_QZ0_QUAD_PER_TILE_H8 tiles walked with 8 quads hit; quad-z pipe 0 @`jSC_QZ0_QUAD_PER_TILE_H9: SC_QZ0_QUAD_PER_TILE_H9 tiles walked with 9 quads hit; quad-z pipe 0 0akSC_QZ0_QUAD_PER_TILE_H10: SC_QZ0_QUAD_PER_TILE_H10 tiles walked with 10 quads hit; quad-z pipe 0  bkSC_QZ0_QUAD_PER_TILE_H11: SC_QZ0_QUAD_PER_TILE_H11 tiles walked with 11 quads hit; quad-z pipe 0 ckSC_QZ0_QUAD_PER_TILE_H12: SC_QZ0_QUAD_PER_TILE_H12 tiles walked with 12 quads hit; quad-z pipe 0 dkSC_QZ0_QUAD_PER_TILE_H13: SC_QZ0_QUAD_PER_TILE_H13 tiles walked with 13 quads hit; quad-z pipe 0 ekSC_QZ0_QUAD_PER_TILE_H14: SC_QZ0_QUAD_PER_TILE_H14 tiles walked with 14 quads hit; quad-z pipe 0 fkSC_QZ0_QUAD_PER_TILE_H15: SC_QZ0_QUAD_PER_TILE_H15 tiles walked with 15 quads hit; quad-z pipe 0 x gkSC_QZ0_QUAD_PER_TILE_H16: SC_QZ0_QUAD_PER_TILE_H16 tiles walked with 16 quads hit; quad-z pipe 0 h hjSC_QZ1_QUAD_PER_TILE_H0: SC_QZ1_QUAD_PER_TILE_H0 tiles walked with 0 quads hit; quad-z pipe 1 X ijSC_QZ1_QUAD_PER_TILE_H1: SC_QZ1_QUAD_PER_TILE_H1 tiles walked with 1 quads hit; quad-z pipe 1 H jjSC_QZ1_QUAD_PER_TILE_H2: SC_QZ1_QUAD_PER_TILE_H2 tiles walked with 2 quads hit; quad-z pipe 1 8kjSC_QZ1_QUAD_PER_TILE_H3: SC_QZ1_QUAD_PER_TILE_H3 tiles walked with 3 quads hit; quad-z pipe 1 (ljSC_QZ1_QUAD_PER_TILE_H4: SC_QZ1_QUAD_PER_TILE_H4 tiles walked with 4 quads hit; quad-z pipe 1 pmjSC_QZ1_QUAD_PER_TILE_H5: SC_QZ1_QUAD_PER_TILE_H5 tiles walked with 5 quads hit; quad-z pipe 1 `njSC_QZ1_QUAD_PER_TILE_H6: SC_QZ1_QUAD_PER_TILE_H6 tiles walked with 6 quads hit; quad-z pipe 1 PojSC_QZ1_QUAD_PER_TILE_H7: SC_QZ1_QUAD_PER_TILE_H7 tiles walked with 7 quads hit; quad-z pipe 1 @pjSC_QZ1_QUAD_PER_TILE_H8: SC_QZ1_QUAD_PER_TILE_H8 tiles walked with 8 quads hit; quad-z pipe 1 0qjSC_QZ1_QUAD_PER_TILE_H9: SC_QZ1_QUAD_PER_TILE_H9 tiles walked with 9 quads hit; quad-z pipe 1  rkSC_QZ1_QUAD_PER_TILE_H10: SC_QZ1_QUAD_PER_TILE_H10 tiles walked with 10 quads hit; quad-z pipe 1 skSC_QZ1_QUAD_PER_TILE_H11: SC_QZ1_QUAD_PER_TILE_H11 tiles walked with 11 quads hit; quad-z pipe 1 tkSC_QZ1_QUAD_PER_TILE_H12: SC_QZ1_QUAD_PER_TILE_H12 tiles walked with 12 quads hit; quad-z pipe 1 ukSC_QZ1_QUAD_PER_TILE_H13: SC_QZ1_QUAD_PER_TILE_H13 tiles walked with 13 quads hit; quad-z pipe 1 vkSC_QZ1_QUAD_PER_TILE_H14: SC_QZ1_QUAD_PER_TILE_H14 tiles walked with 14 quads hit; quad-z pipe 1 xwkSC_QZ1_QUAD_PER_TILE_H15: SC_QZ1_QUAD_PER_TILE_H15 tiles walked with 15 quads hit; quad-z pipe 1 hxkSC_QZ1_QUAD_PER_TILE_H16: SC_QZ1_QUAD_PER_TILE_H16 tiles walked with 16 quads hit; quad-z pipe 1 @yPSC_QZ0_QUAD_COUNT: SC_QZ0_QUAD_COUNT quad count; quad-z pipe 0 zPSC_QZ1_QUAD_COUNT: SC_QZ1_QUAD_COUNT quad count; quad-z pipe 1 `{TSC_QUAD0_NOT_PICKED_TB_R6XX: SC_QUAD0_NOT_PICKED_TB_GPU6 deprecated for GPU7 8|TSC_QUAD1_NOT_PICKED_TB_R6XX: SC_QUAD1_NOT_PICKED_TB_GPU6 deprecated for GPU7 }TSC_QUAD2_NOT_PICKED_TB_R6XX: SC_QUAD2_NOT_PICKED_TB_GPU6 deprecated for GPU7 x ~TSC_QUAD3_NOT_PICKED_TB_R6XX: SC_QUAD3_NOT_PICKED_TB_GPU6 deprecated for GPU7 `! _SC_P0_HIZ_TILE_COUNT: SC_P0_HIZ_TILE_COUNT total tiles surviving hi-z; db pipe 0 H"!_SC_P1_HIZ_TILE_COUNT: SC_P1_HIZ_TILE_COUNT total tiles surviving hi-z; db pipe 1 0#"_SC_P2_HIZ_TILE_COUNT: SC_P2_HIZ_TILE_COUNT total tiles surviving hi-z; db pipe 2 $x#_SC_P3_HIZ_TILE_COUNT: SC_P3_HIZ_TILE_COUNT total tiles surviving hi-z; db pipe 3 %`$mSC_P0_HIZ_QUAD_PER_TILE_H0: SC_P0_HIZ_QUAD_PER_TILE_H0 tiles with 0 quads surviving hi-z; db pipe 0 &X%mSC_P0_HIZ_QUAD_PER_TILE_H1: SC_P0_HIZ_QUAD_PER_TILE_H1 tiles with 1 quads surviving hi-z; db pipe 0 'P&mSC_P0_HIZ_QUAD_PER_TILE_H2: SC_P0_HIZ_QUAD_PER_TILE_H2 tiles with 2 quads surviving hi-z; db pipe 0 'H'mSC_P0_HIZ_QUAD_PER_TILE_H3: SC_P0_HIZ_QUAD_PER_TILE_H3 tiles with 3 quads surviving hi-z; db pipe 0 (@(mSC_P0_HIZ_QUAD_PER_TILE_H4: SC_P0_HIZ_QUAD_PER_TILE_H4 tiles with 4 quads surviving hi-z; db pipe 0 )8)mSC_P0_HIZ_QUAD_PER_TILE_H5: SC_P0_HIZ_QUAD_PER_TILE_H5 tiles with 5 quads surviving hi-z; db pipe 0 *0*mSC_P0_HIZ_QUAD_PER_TILE_H6: SC_P0_HIZ_QUAD_PER_TILE_H6 tiles with 6 quads surviving hi-z; db pipe 0 +(+mSC_P0_HIZ_QUAD_PER_TILE_H7: SC_P0_HIZ_QUAD_PER_TILE_H7 tiles with 7 quads surviving hi-z; db pipe 0 , ,mSC_P0_HIZ_QUAD_PER_TILE_H8: SC_P0_HIZ_QUAD_PER_TILE_H8 tiles with 8 quads surviving hi-z; db pipe 0 --mSC_P0_HIZ_QUAD_PER_TILE_H9: SC_P0_HIZ_QUAD_PER_TILE_H9 tiles with 9 quads surviving hi-z; db pipe 0 ..nSC_P0_HIZ_QUAD_PER_TILE_H10: SC_P0_HIZ_QUAD_PER_TILE_H10 tiles with 10 quads surviving hi-z; db pipe 0 //nSC_P0_HIZ_QUAD_PER_TILE_H11: SC_P0_HIZ_QUAD_PER_TILE_H11 tiles with 11 quads surviving hi-z; db pipe 0 00nSC_P0_HIZ_QUAD_PER_TILE_H12: SC_P0_HIZ_QUAD_PER_TILE_H12 tiles with 12 quads surviving hi-z; db pipe 0 11nSC_P0_HIZ_QUAD_PER_TILE_H13: SC_P0_HIZ_QUAD_PER_TILE_H13 tiles with 13 quads surviving hi-z; db pipe 0 21nSC_P0_HIZ_QUAD_PER_TILE_H14: SC_P0_HIZ_QUAD_PER_TILE_H14 tiles with 14 quads surviving hi-z; db pipe 0 32nSC_P0_HIZ_QUAD_PER_TILE_H15: SC_P0_HIZ_QUAD_PER_TILE_H15 tiles with 15 quads surviving hi-z; db pipe 0 43nSC_P0_HIZ_QUAD_PER_TILE_H16: SC_P0_HIZ_QUAD_PER_TILE_H16 tiles with 16 quads surviving hi-z; db pipe 0 54mSC_P1_HIZ_QUAD_PER_TILE_H0: SC_P0_HIZ_QUAD_PER_TILE_H0 tiles with 0 quads surviving hi-z; db pipe 1 65mSC_P1_HIZ_QUAD_PER_TILE_H1: SC_P0_HIZ_QUAD_PER_TILE_H1 tiles with 1 quads surviving hi-z; db pipe 1 76mSC_P1_HIZ_QUAD_PER_TILE_H2: SC_P1_HIZ_QUAD_PER_TILE_H2 tiles with 2 quads surviving hi-z; db pipe 1 x87mSC_P1_HIZ_QUAD_PER_TILE_H3: SC_P1_HIZ_QUAD_PER_TILE_H3 tiles with 3 quads surviving hi-z; db pipe 1 p98mSC_P1_HIZ_QUAD_PER_TILE_H4: SC_P1_HIZ_QUAD_PER_TILE_H4 tiles with 4 quads surviving hi-z; db pipe 1 h:9mSC_P1_HIZ_QUAD_PER_TILE_H5: SC_P1_HIZ_QUAD_PER_TILE_H5 tiles with 5 quads surviving hi-z; db pipe 1 `;:mSC_P1_HIZ_QUAD_PER_TILE_H6: SC_P1_HIZ_QUAD_PER_TILE_H6 tiles with 6 quads surviving hi-z; db pipe 1 X<;mSC_P1_HIZ_QUAD_PER_TILE_H7: SC_P1_HIZ_QUAD_PER_TILE_H7 tiles with 7 quads surviving hi-z; db pipe 1 P=<mSC_P1_HIZ_QUAD_PER_TILE_H8: SC_P1_HIZ_QUAD_PER_TILE_H8 tiles with 8 quads surviving hi-z; db pipe 1 H>=mSC_P1_HIZ_QUAD_PER_TILE_H9: SC_P1_HIZ_QUAD_PER_TILE_H9 tiles with 9 quads surviving hi-z; db pipe 1 @?>nSC_P1_HIZ_QUAD_PER_TILE_H10: SC_P1_HIZ_QUAD_PER_TILE_H10 tiles with 10 quads surviving hi-z; db pipe 1 8@?nSC_P1_HIZ_QUAD_PER_TILE_H11: SC_P1_HIZ_QUAD_PER_TILE_H11 tiles with 11 quads surviving hi-z; db pipe 1 0A@nSC_P1_HIZ_QUAD_PER_TILE_H12: SC_P1_HIZ_QUAD_PER_TILE_H12 tiles with 12 quads surviving hi-z; db pipe 1 (BxAnSC_P1_HIZ_QUAD_PER_TILE_H13: SC_P1_HIZ_QUAD_PER_TILE_H13 tiles with 13 quads surviving hi-z; db pipe 1 CpBnSC_P1_HIZ_QUAD_PER_TILE_H14: SC_P1_HIZ_QUAD_PER_TILE_H14 tiles with 14 quads surviving hi-z; db pipe 1 DhCnSC_P1_HIZ_QUAD_PER_TILE_H15: SC_P1_HIZ_QUAD_PER_TILE_H15 tiles with 15 quads surviving hi-z; db pipe 1 E`DnSC_P1_HIZ_QUAD_PER_TILE_H16: SC_P1_HIZ_QUAD_PER_TILE_H16 tiles with 16 quads surviving hi-z; db pipe 1 FXEmSC_P2_HIZ_QUAD_PER_TILE_H0: SC_P2_HIZ_QUAD_PER_TILE_H0 tiles with 0 quads surviving hi-z; db pipe 2 GPFmSC_P2_HIZ_QUAD_PER_TILE_H1: SC_P2_HIZ_QUAD_PER_TILE_H1 tiles with 1 quads surviving hi-z; db pipe 2 GHGmSC_P2_HIZ_QUAD_PER_TILE_H2: SC_P2_HIZ_QUAD_PER_TILE_H2 tiles with 2 quads surviving hi-z; db pipe 2 H@HmSC_P2_HIZ_QUAD_PER_TILE_H3: SC_P2_HIZ_QUAD_PER_TILE_H3 tiles with 3 quads surviving hi-z; db pipe 2 I8ImSC_P2_HIZ_QUAD_PER_TILE_H4: SC_P2_HIZ_QUAD_PER_TILE_H4 tiles with 4 quads surviving hi-z; db pipe 2 J0JmSC_P2_HIZ_QUAD_PER_TILE_H5: SC_P2_HIZ_QUAD_PER_TILE_H5 tiles with 5 quads surviving hi-z; db pipe 2 K(KmSC_P2_HIZ_QUAD_PER_TILE_H6: SC_P2_HIZ_QUAD_PER_TILE_H6 tiles with 6 quads surviving hi-z; db pipe 2 L LmSC_P2_HIZ_QUAD_PER_TILE_H7: SC_P2_HIZ_QUAD_PER_TILE_H7 tiles with 7 quads surviving hi-z; db pipe 2 MMmSC_P2_HIZ_QUAD_PER_TILE_H8: SC_P2_HIZ_QUAD_PER_TILE_H8 tiles with 8 quads surviving hi-z; db pipe 2 NNmSC_P2_HIZ_QUAD_PER_TILE_H9: SC_P2_HIZ_QUAD_PER_TILE_H9 tiles with 9 quads surviving hi-z; db pipe 2 OOnSC_P2_HIZ_QUAD_PER_TILE_H10: SC_P2_HIZ_QUAD_PER_TILE_H10 tiles with 10 quads surviving hi-z; db pipe 2 PPnSC_P2_HIZ_QUAD_PER_TILE_H11: SC_P2_HIZ_QUAD_PER_TILE_H11 tiles with 11 quads surviving hi-z; db pipe 2 QQnSC_P2_HIZ_QUAD_PER_TILE_H12: SC_P2_HIZ_QUAD_PER_TILE_H12 tiles with 12 quads surviving hi-z; db pipe 2 RQnSC_P2_HIZ_QUAD_PER_TILE_H13: SC_P2_HIZ_QUAD_PER_TILE_H13 tiles with 13 quads surviving hi-z; db pipe 2 SRnSC_P2_HIZ_QUAD_PER_TILE_H14: SC_P2_HIZ_QUAD_PER_TILE_H14 tiles with 14 quads surviving hi-z; db pipe 2 TSnSC_P2_HIZ_QUAD_PER_TILE_H15: SC_P2_HIZ_QUAD_PER_TILE_H15 tiles with 15 quads surviving hi-z; db pipe 2 UTnSC_P2_HIZ_QUAD_PER_TILE_H16: SC_P2_HIZ_QUAD_PER_TILE_H16 tiles with 16 quads surviving hi-z; db pipe 2 VUmSC_P3_HIZ_QUAD_PER_TILE_H0: SC_P3_HIZ_QUAD_PER_TILE_H0 tiles with 0 quads surviving hi-z; db pipe 3 WVmSC_P3_HIZ_QUAD_PER_TILE_H1: SC_P3_HIZ_QUAD_PER_TILE_H1 tiles with 1 quads surviving hi-z; db pipe 3 xXWmSC_P3_HIZ_QUAD_PER_TILE_H2: SC_P3_HIZ_QUAD_PER_TILE_H2 tiles with 2 quads surviving hi-z; db pipe 3 pYXmSC_P3_HIZ_QUAD_PER_TILE_H3: SC_P3_HIZ_QUAD_PER_TILE_H3 tiles with 3 quads surviving hi-z; db pipe 3 hZYmSC_P3_HIZ_QUAD_PER_TILE_H4: SC_P3_HIZ_QUAD_PER_TILE_H4 tiles with 4 quads surviving hi-z; db pipe 3 `[ZmSC_P3_HIZ_QUAD_PER_TILE_H5: SC_P3_HIZ_QUAD_PER_TILE_H5 tiles with 5 quads surviving hi-z; db pipe 3 X\[mSC_P3_HIZ_QUAD_PER_TILE_H6: SC_P3_HIZ_QUAD_PER_TILE_H6 tiles with 6 quads surviving hi-z; db pipe 3 P]\mSC_P3_HIZ_QUAD_PER_TILE_H7: SC_P3_HIZ_QUAD_PER_TILE_H7 tiles with 7 quads surviving hi-z; db pipe 3 H^]mSC_P3_HIZ_QUAD_PER_TILE_H8: SC_P3_HIZ_QUAD_PER_TILE_H8 tiles with 8 quads surviving hi-z; db pipe 3 @_^mSC_P3_HIZ_QUAD_PER_TILE_H9: SC_P3_HIZ_QUAD_PER_TILE_H9 tiles with 9 quads surviving hi-z; db pipe 3 8`_nSC_P3_HIZ_QUAD_PER_TILE_H10: SC_P3_HIZ_QUAD_PER_TILE_H10 tiles with 10 quads surviving hi-z; db pipe 3 0a`nSC_P3_HIZ_QUAD_PER_TILE_H11: SC_P3_HIZ_QUAD_PER_TILE_H11 tiles with 11 quads surviving hi-z; db pipe 3 (bxanSC_P3_HIZ_QUAD_PER_TILE_H12: SC_P3_HIZ_QUAD_PER_TILE_H12 tiles with 12 quads surviving hi-z; db pipe 3 cpbnSC_P3_HIZ_QUAD_PER_TILE_H13: SC_P3_HIZ_QUAD_PER_TILE_H13 tiles with 13 quads surviving hi-z; db pipe 3 dhcnSC_P3_HIZ_QUAD_PER_TILE_H14: SC_P3_HIZ_QUAD_PER_TILE_H14 tiles with 14 quads surviving hi-z; db pipe 3 e`dnSC_P3_HIZ_QUAD_PER_TILE_H15: SC_P3_HIZ_QUAD_PER_TILE_H15 tiles with 15 quads surviving hi-z; db pipe 3 fXenSC_P3_HIZ_QUAD_PER_TILE_H16: SC_P3_HIZ_QUAD_PER_TILE_H16 tiles with 16 quads surviving hi-z; db pipe 3 fPf_SC_P0_HIZ_QUAD_COUNT: SC_P0_HIZ_QUAD_COUNT total quads surviving hi-z; db pipe 0 g8g_SC_P1_HIZ_QUAD_COUNT: SC_P1_HIZ_QUAD_COUNT total quads surviving hi-z; db pipe 1 h h_SC_P2_HIZ_QUAD_COUNT: SC_P2_HIZ_QUAD_COUNT total quads surviving hi-z; db pipe 2 ii_SC_P3_HIZ_QUAD_COUNT: SC_P3_HIZ_QUAD_COUNT total quads surviving hi-z; db pipe 3 jilSC_P0_DETAIL_QUAD_COUNT: SC_P0_DETAIL_QUAD_COUNT total quads surviving detail sampler; db pipe 0 kjlSC_P1_DETAIL_QUAD_COUNT: SC_P1_DETAIL_QUAD_COUNT total quads surviving detail sampler; db pipe 1 xlklSC_P2_DETAIL_QUAD_COUNT: SC_P2_DETAIL_QUAD_COUNT total quads surviving detail sampler; db pipe 2 hmllSC_P3_DETAIL_QUAD_COUNT: SC_P3_DETAIL_QUAD_COUNT total quads surviving detail sampler; db pipe 3 `nmpSC_P0_DETAIL_QUAD_WITH_1_PIX: SC_P0_DETAIL_QUAD_WITH_1_PIX quads with 1 pixel surviving detail; db pipe 0 XonqSC_P0_DETAIL_QUAD_WITH_2_PIX: SC_P0_DETAIL_QUAD_WITH_2_PIX quads with 2 pixels surviving detail; db pipe 0 PpoqSC_P0_DETAIL_QUAD_WITH_3_PIX: SC_P0_DETAIL_QUAD_WITH_3_PIX quads with 3 pixels surviving detail; db pipe 0 HqpqSC_P0_DETAIL_QUAD_WITH_4_PIX: SC_P0_DETAIL_QUAD_WITH_4_PIX quads with 4 pixels surviving detail; db pipe 0 @rqpSC_P1_DETAIL_QUAD_WITH_1_PIX: SC_P1_DETAIL_QUAD_WITH_1_PIX quads with 1 pixel surviving detail; db pipe 1 8srqSC_P1_DETAIL_QUAD_WITH_2_PIX: SC_P1_DETAIL_QUAD_WITH_2_PIX quads with 2 pixels surviving detail; db pipe 1 0tsqSC_P1_DETAIL_QUAD_WITH_3_PIX: SC_P1_DETAIL_QUAD_WITH_3_PIX quads with 3 pixels surviving detail; db pipe 1 (uxtqSC_P1_DETAIL_QUAD_WITH_4_PIX: SC_P1_DETAIL_QUAD_WITH_4_PIX quads with 4 pixels surviving detail; db pipe 1 vpupSC_P2_DETAIL_QUAD_WITH_1_PIX: SC_P2_DETAIL_QUAD_WITH_1_PIX quads with 1 pixel surviving detail; db pipe 2 whvqSC_P2_DETAIL_QUAD_WITH_2_PIX: SC_P2_DETAIL_QUAD_WITH_2_PIX quads with 2 pixels surviving detail; db pipe 2 x`wqSC_P2_DETAIL_QUAD_WITH_3_PIX: SC_P2_DETAIL_QUAD_WITH_3_PIX quads with 3 pixels surviving detail; db pipe 2 yXxqSC_P2_DETAIL_QUAD_WITH_4_PIX: SC_P2_DETAIL_QUAD_WITH_4_PIX quads with 4 pixels surviving detail; db pipe 2 zPypSC_P3_DETAIL_QUAD_WITH_1_PIX: SC_P3_DETAIL_QUAD_WITH_1_PIX quads with 1 pixel surviving detail; db pipe 3 zHzqSC_P3_DETAIL_QUAD_WITH_2_PIX: SC_P3_DETAIL_QUAD_WITH_2_PIX quads with 2 pixels surviving detail; db pipe 3 {@{qSC_P3_DETAIL_QUAD_WITH_3_PIX: SC_P3_DETAIL_QUAD_WITH_3_PIX quads with 3 pixels surviving detail; db pipe 3 |8|qSC_P3_DETAIL_QUAD_WITH_4_PIX: SC_P3_DETAIL_QUAD_WITH_4_PIX quads with 4 pixels surviving detail; db pipe 3 }0}WSC_EARLYZ_QUAD_COUNT: SC_EARLYZ_QUAD_COUNT total quads surviving early-z ~~cSC_EARLYZ_QUAD_WITH_1_PIX: SC_EARLYZ_QUAD_WITH_1_PIX quads with 1 pixel surviving early-z ~dSC_EARLYZ_QUAD_WITH_2_PIX: SC_EARLYZ_QUAD_WITH_2_PIX quads with 2 pixels surviving early-z dSC_EARLYZ_QUAD_WITH_3_PIX: SC_EARLYZ_QUAD_WITH_3_PIX quads with 3 pixels surviving early-z hȀdSC_EARLYZ_QUAD_WITH_4_PIX: SC_EARLYZ_QUAD_WITH_4_PIX quads with 4 pixels surviving early-z HYSC_TILE_REORDER_DB_CONFLICT_R6XX: SC_TILE_REORDER_DB_CONFLICT_GPU6 deprecated for GPU7 0`SC_PKR_QUAD_PER_ROW_H1: SC_PKR_QUAD_PER_ROW_H1 packer row outputs with 1 valid quad x`SC_PKR_QUAD_PER_ROW_H2: SC_PKR_QUAD_PER_ROW_H2 packer row outputs with 2 valid quad ``SC_PKR_QUAD_PER_ROW_H3: SC_PKR_QUAD_PER_ROW_H3 packer row outputs with 3 valid quad 腘H`SC_PKR_QUAD_PER_ROW_H4: SC_PKR_QUAD_PER_ROW_H4 packer row outputs with 4 valid quad 0QSC_PKR_END_OF_VECTOR: SC_PKR_END_OF_VECTOR number of pixel vectors TSC_PKR_CONTROL_XFER: SC_PKR_CONTROL_XFER number of control transfers |SC_PKR_DBHANG_FORCE_EOV: SC_PKR_DBHANG_FORCE_EOV number of times partial vector ejected b/c of DB hang condition ]SC_REG_SCLK_BUSY: SC_REG_SCLK_BUSY number of cycles register clock is busy pȉhSC_GRP0_DYN_SCLK_BUSY: SC_GRP0_DYN_SCLK_BUSY number of cycles group0 dynamic clock is busy `hSC_GRP1_DYN_SCLK_BUSY: SC_GRP1_DYN_SCLK_BUSY number of cycles group1 dynamic clock is busy PhSC_GRP2_DYN_SCLK_BUSY: SC_GRP2_DYN_SCLK_BUSY number of cycles group2 dynamic clock is busy @hSC_GRP3_DYN_SCLK_BUSY: SC_GRP3_DYN_SCLK_BUSY number of cycles group3 dynamic clock is busy hSC_GRP4_DYN_SCLK_BUSY: SC_GRP4_DYN_SCLK_BUSY number of cycles group4 dynamic clock is busy ǖʖ"" ʖPA_SC_PERFCOUNTER0_SELECT8˖˖ PERF_SEL̖˖SC_SRPS_WINDOW_VALID: SC_SRPS_WINDOW_VALID Number of clocks event-window is valid at stage register/primitive setup ͖̖SC_PSSW_WINDOW_VALID: SC_PSSW_WINDOW_VALID Number of clocks event-window is valid at primitive setup/supertile walker Ζ͖vSC_TPQZ_WINDOW_VALID: SC_TPQZ_WINDOW_VALID Number of clocks event-window is valid at tile picker/quad-z ϖΖySC_QZQP_WINDOW_VALID: SC_QZQP_WINDOW_VALID Number of clocks event-window is valid at quad-z/quad processor ЖϖwSC_TRPK_WINDOW_VALID: SC_TRPK_WINDOW_VALID Number of clocks event-window is valid at tile reorder/packer іЖSC_SRPS_WINDOW_VALID_BUSY: SC_SRPS_WINDOW_VALID_BUSY Number of clocks event-window is valid at stage register/primitive setup with SC busy ҖіSC_PSSW_WINDOW_VALID_BUSY: SC_PSSW_WINDOW_VALID_BUSY Number of clocks event-window is valid at primitive setup/supertile walker with SC busy ӖӖSC_TPQZ_WINDOW_VALID_BUSY: SC_TPQZ_WINDOW_VALID_BUSY Number of clocks event-window is valid at tile picker/quad-z with SC busy Ԗ ԖSC_QZQP_WINDOW_VALID_BUSY: SC_QZQP_WINDOW_VALID_BUSY Number of clocks event-window is valid at quad-z/quad processor with SC busy Ֆ0Ֆ SC_TRPK_WINDOW_VALID_BUSY: SC_TRPK_WINDOW_VALID_BUSY Number of clocks event-window is valid at tile reorder/packer with SC busy ֖@֖ FSC_STARVED_BY_PA: SC_STARVED_BY_PA sc starved by pa זז XSC_STALLED_BY_PRIMFIFO: SC_STALLED_BY_PRIMFIFO sc stalled by primitive fifo ؖז PSC_STARVED_BY_DB_TILE: SC_STARVED_BY_DB_TILE sc starved by db tile Xٖؖ PSC_STARVED_BY_DB_QUAD: SC_STARVED_BY_DB_QUAD sc starved by db quad @ږٖ^SC_STALLED_BY_TILEORDERFIFO: SC_STALLED_BY_TILEORDERFIFO sc stalled by tile order fifo ۖږSSC_STALLED_BY_TILEFIFO: SC_STALLED_BY_TILEFIFO sc stalled by tile fifo ۖ`ۖSSC_STALLED_BY_QUADFIFO: SC_STALLED_BY_QUADFIFO sc stalled by quad fifo ܖ8ܖPSC_STALLED_BY_DB_TILE: SC_STALLED_BY_DB_TILE sc stalled by db tile ݖݖPSC_STALLED_BY_DB_QUAD: SC_STALLED_BY_DB_QUAD sc stalled by db quad pޖݖFSC_STALLED_BY_SX: SC_STALLED_BY_SX sc stalled by sx @ߖޖHSC_STALLED_BY_SPI: SC_STALLED_BY_SPI sc stalled by spi (ߖaSC_SCISSOR_DISCARD: SC_SCISSOR_DISCARD primitive completely discarded by scissor pkSC_BB_DISCARD: SC_BB_DISCARD primitive discarded by bounding-box check, no pixels hit `mSC_MULTICHIP_PRIM_DISCARD: SC_MULTICHIP_PRIM_DISCARD primitive completely discarded by optimization XGSC_SUPERTILE_COUNT: SC_SUPERTILE_COUNT supertile count (YSC_SUPERTILE_PER_PRIM_H0: SC_SUPERTILE_PER_PRIM_H0 prims with < 2 supertiles YSC_SUPERTILE_PER_PRIM_H1: SC_SUPERTILE_PER_PRIM_H1 prims with < 4 supertiles YSC_SUPERTILE_PER_PRIM_H2: SC_SUPERTILE_PER_PRIM_H2 prims with < 8 supertiles `YSC_SUPERTILE_PER_PRIM_H3: SC_SUPERTILE_PER_PRIM_H3 prims with < 16 supertiles @YSC_SUPERTILE_PER_PRIM_H4: SC_SUPERTILE_PER_PRIM_H4 prims with < 32 supertiles YSC_SUPERTILE_PER_PRIM_H5: SC_SUPERTILE_PER_PRIM_H5 prims with < 64 supertiles hYSC_SUPERTILE_PER_PRIM_H6: SC_SUPERTILE_PER_PRIM_H6 prims with < 128 supertiles H YSC_SUPERTILE_PER_PRIM_H7: SC_SUPERTILE_PER_PRIM_H7 prims with < 256 supertiles (!YSC_SUPERTILE_PER_PRIM_H8: SC_SUPERTILE_PER_PRIM_H8 prims with < 512 supertiles "YSC_SUPERTILE_PER_PRIM_H9: SC_SUPERTILE_PER_PRIM_H9 prims with < 1K supertiles #ZSC_SUPERTILE_PER_PRIM_H10: SC_SUPERTILE_PER_PRIM_H10 prims with < 2K supertiles `$ZSC_SUPERTILE_PER_PRIM_H11: SC_SUPERTILE_PER_PRIM_H11 prims with < 4K supertiles @%ZSC_SUPERTILE_PER_PRIM_H12: SC_SUPERTILE_PER_PRIM_H12 prims with < 8K supertiles &ZSC_SUPERTILE_PER_PRIM_H13: SC_SUPERTILE_PER_PRIM_H13 prims with < 16K supertiles h'ZSC_SUPERTILE_PER_PRIM_H14: SC_SUPERTILE_PER_PRIM_H14 prims with < 32K supertiles P(ZSC_SUPERTILE_PER_PRIM_H15: SC_SUPERTILE_PER_PRIM_H15 prims with < 64K supertiles 0)ZSC_SUPERTILE_PER_PRIM_H16: SC_SUPERTILE_PER_PRIM_H16 prims with < 1M supertiles *OSC_TILE_PER_PRIM_H0: SC_TILE_PER_PRIM_H0 prims with < 2 tiles x+OSC_TILE_PER_PRIM_H1: SC_TILE_PER_PRIM_H1 prims with < 4 tiles P,OSC_TILE_PER_PRIM_H2: SC_TILE_PER_PRIM_H2 prims with < 8 tiles (-OSC_TILE_PER_PRIM_H3: SC_TILE_PER_PRIM_H3 prims with < 16 tiles p.OSC_TILE_PER_PRIM_H4: SC_TILE_PER_PRIM_H4 prims with < 32 tiles H/OSC_TILE_PER_PRIM_H5: SC_TILE_PER_PRIM_H5 prims with < 64 tiles 0OSC_TILE_PER_PRIM_H6: SC_TILE_PER_PRIM_H6 prims with < 128 tiles 1OSC_TILE_PER_PRIM_H7: SC_TILE_PER_PRIM_H7 prims with < 256 tiles `2OSC_TILE_PER_PRIM_H8: SC_TILE_PER_PRIM_H8 prims with < 512 tiles 83OSC_TILE_PER_PRIM_H9: SC_TILE_PER_PRIM_H9 prims with < 1K tiles 4PSC_TILE_PER_PRIM_H10: SC_TILE_PER_PRIM_H10 prims with < 2K tiles X5PSC_TILE_PER_PRIM_H11: SC_TILE_PER_PRIM_H11 prims with < 4K tiles 06PSC_TILE_PER_PRIM_H12: SC_TILE_PER_PRIM_H12 prims with < 8K tiles 7PSC_TILE_PER_PRIM_H13: SC_TILE_PER_PRIM_H13 prims with < 16K tiles p8PSC_TILE_PER_PRIM_H14: SC_TILE_PER_PRIM_H14 prims with < 32K tiles H9PSC_TILE_PER_PRIM_H15: SC_TILE_PER_PRIM_H15 prims with < 64K tiles :PSC_TILE_PER_PRIM_H16: SC_TILE_PER_PRIM_H16 prims with < 1M tiles h;aSC_TILE_PER_SUPERTILE_H0: SC_TILE_PER_SUPERTILE_H0 supertiles walked with 0 tiles hit P<aSC_TILE_PER_SUPERTILE_H1: SC_TILE_PER_SUPERTILE_H1 supertiles walked with 1 tiles hit 8=aSC_TILE_PER_SUPERTILE_H2: SC_TILE_PER_SUPERTILE_H2 supertiles walked with 2 tiles hit  >aSC_TILE_PER_SUPERTILE_H3: SC_TILE_PER_SUPERTILE_H3 supertiles walked with 3 tiles hit ?aSC_TILE_PER_SUPERTILE_H4: SC_TILE_PER_SUPERTILE_H4 supertiles walked with 4 tiles hit @aSC_TILE_PER_SUPERTILE_H5: SC_TILE_PER_SUPERTILE_H5 supertiles walked with 5 tiles hit xAaSC_TILE_PER_SUPERTILE_H6: SC_TILE_PER_SUPERTILE_H6 supertiles walked with 6 tiles hit `BaSC_TILE_PER_SUPERTILE_H7: SC_TILE_PER_SUPERTILE_H7 supertiles walked with 7 tiles hit HCaSC_TILE_PER_SUPERTILE_H8: SC_TILE_PER_SUPERTILE_H8 supertiles walked with 8 tiles hit 0 DaSC_TILE_PER_SUPERTILE_H9: SC_TILE_PER_SUPERTILE_H9 supertiles walked with 9 tiles hit  x EbSC_TILE_PER_SUPERTILE_H10: SC_TILE_PER_SUPERTILE_H10 supertiles walked with 10 tiles hit ` FbSC_TILE_PER_SUPERTILE_H11: SC_TILE_PER_SUPERTILE_H11 supertiles walked with 11 tiles hit H GbSC_TILE_PER_SUPERTILE_H12: SC_TILE_PER_SUPERTILE_H12 supertiles walked with 12 tiles hit 0 HbSC_TILE_PER_SUPERTILE_H13: SC_TILE_PER_SUPERTILE_H13 supertiles walked with 13 tiles hit  IbSC_TILE_PER_SUPERTILE_H14: SC_TILE_PER_SUPERTILE_H14 supertiles walked with 14 tiles hit JbSC_TILE_PER_SUPERTILE_H15: SC_TILE_PER_SUPERTILE_H15 supertiles walked with 15 tiles hit KbSC_TILE_PER_SUPERTILE_H16: SC_TILE_PER_SUPERTILE_H16 supertiles walked with 16 tiles hit `LTSC_TILE_PICKED_H1: SC_TILE_PICKED_H1 number of times 1 tile picked @MUSC_TILE_PICKED_H2: SC_TILE_PICKED_H2 number of times 2 tiles picked 0NjSC_TILE_PICKED_CONFLICT: SC_TILE_PICKED_CONFLICT number of times 1 tile picked b/c of conflict (xOqSC_QZ0_MULTICHIP_TILE_DISCARD: SC_QZ0_MULTICHIP_TILE_DISCARD tiles discarded by optimization; quad-z pipe 0 pPqSC_QZ1_MULTICHIP_TILE_DISCARD: SC_QZ1_MULTICHIP_TILE_DISCARD tiles discarded by optimization; quad-z pipe 1 hQPSC_QZ0_TILE_COUNT: SC_QZ0_TILE_COUNT tile count; quad-z pipe 0 @RPSC_QZ1_TILE_COUNT: SC_QZ1_TILE_COUNT tile count; quad-z pipe 1 S`SC_QZ0_TILE_COVERED_COUNT: SC_QZ0_TILE_COVERED_COUNT tile covered count; quad-z pipe 0 T`SC_QZ1_TILE_COVERED_COUNT: SC_QZ1_TILE_COVERED_COUNT tile covered count; quad-z pipe 1 UhSC_QZ0_TILE_NOT_COVERED_COUNT: SC_QZ0_TILE_NOT_COVERED_COUNT tile not covered count; quad-z pipe 0 VhSC_QZ1_TILE_NOT_COVERED_COUNT: SC_QZ1_TILE_NOT_COVERED_COUNT tile not covered count; quad-z pipe 1 pWjSC_QZ0_QUAD_PER_TILE_H0: SC_QZ0_QUAD_PER_TILE_H0 tiles walked with 0 quads hit; quad-z pipe 0 `XjSC_QZ0_QUAD_PER_TILE_H1: SC_QZ0_QUAD_PER_TILE_H1 tiles walked with 1 quads hit; quad-z pipe 0 PYjSC_QZ0_QUAD_PER_TILE_H2: SC_QZ0_QUAD_PER_TILE_H2 tiles walked with 2 quads hit; quad-z pipe 0 @ZjSC_QZ0_QUAD_PER_TILE_H3: SC_QZ0_QUAD_PER_TILE_H3 tiles walked with 3 quads hit; quad-z pipe 0 0[jSC_QZ0_QUAD_PER_TILE_H4: SC_QZ0_QUAD_PER_TILE_H4 tiles walked with 4 quads hit; quad-z pipe 0 x\jSC_QZ0_QUAD_PER_TILE_H5: SC_QZ0_QUAD_PER_TILE_H5 tiles walked with 5 quads hit; quad-z pipe 0  h]jSC_QZ0_QUAD_PER_TILE_H6: SC_QZ0_QUAD_PER_TILE_H6 tiles walked with 6 quads hit; quad-z pipe 0 !X ^jSC_QZ0_QUAD_PER_TILE_H7: SC_QZ0_QUAD_PER_TILE_H7 tiles walked with 7 quads hit; quad-z pipe 0 !H!_jSC_QZ0_QUAD_PER_TILE_H8: SC_QZ0_QUAD_PER_TILE_H8 tiles walked with 8 quads hit; quad-z pipe 0 "8"`jSC_QZ0_QUAD_PER_TILE_H9: SC_QZ0_QUAD_PER_TILE_H9 tiles walked with 9 quads hit; quad-z pipe 0 #(#akSC_QZ0_QUAD_PER_TILE_H10: SC_QZ0_QUAD_PER_TILE_H10 tiles walked with 10 quads hit; quad-z pipe 0 $$bkSC_QZ0_QUAD_PER_TILE_H11: SC_QZ0_QUAD_PER_TILE_H11 tiles walked with 11 quads hit; quad-z pipe 0 %%ckSC_QZ0_QUAD_PER_TILE_H12: SC_QZ0_QUAD_PER_TILE_H12 tiles walked with 12 quads hit; quad-z pipe 0 &%dkSC_QZ0_QUAD_PER_TILE_H13: SC_QZ0_QUAD_PER_TILE_H13 tiles walked with 13 quads hit; quad-z pipe 0 '&ekSC_QZ0_QUAD_PER_TILE_H14: SC_QZ0_QUAD_PER_TILE_H14 tiles walked with 14 quads hit; quad-z pipe 0 ('fkSC_QZ0_QUAD_PER_TILE_H15: SC_QZ0_QUAD_PER_TILE_H15 tiles walked with 15 quads hit; quad-z pipe 0 p)(gkSC_QZ0_QUAD_PER_TILE_H16: SC_QZ0_QUAD_PER_TILE_H16 tiles walked with 16 quads hit; quad-z pipe 0 `*)hjSC_QZ1_QUAD_PER_TILE_H0: SC_QZ1_QUAD_PER_TILE_H0 tiles walked with 0 quads hit; quad-z pipe 1 P+*ijSC_QZ1_QUAD_PER_TILE_H1: SC_QZ1_QUAD_PER_TILE_H1 tiles walked with 1 quads hit; quad-z pipe 1 @,+jjSC_QZ1_QUAD_PER_TILE_H2: SC_QZ1_QUAD_PER_TILE_H2 tiles walked with 2 quads hit; quad-z pipe 1 0-,kjSC_QZ1_QUAD_PER_TILE_H3: SC_QZ1_QUAD_PER_TILE_H3 tiles walked with 3 quads hit; quad-z pipe 1 .x-ljSC_QZ1_QUAD_PER_TILE_H4: SC_QZ1_QUAD_PER_TILE_H4 tiles walked with 4 quads hit; quad-z pipe 1 /h.mjSC_QZ1_QUAD_PER_TILE_H5: SC_QZ1_QUAD_PER_TILE_H5 tiles walked with 5 quads hit; quad-z pipe 1 0X/njSC_QZ1_QUAD_PER_TILE_H6: SC_QZ1_QUAD_PER_TILE_H6 tiles walked with 6 quads hit; quad-z pipe 1 0P0ojSC_QZ1_QUAD_PER_TILE_H7: SC_QZ1_QUAD_PER_TILE_H7 tiles walked with 7 quads hit; quad-z pipe 1 1@1pjSC_QZ1_QUAD_PER_TILE_H8: SC_QZ1_QUAD_PER_TILE_H8 tiles walked with 8 quads hit; quad-z pipe 1 202qjSC_QZ1_QUAD_PER_TILE_H9: SC_QZ1_QUAD_PER_TILE_H9 tiles walked with 9 quads hit; quad-z pipe 1 3 3rkSC_QZ1_QUAD_PER_TILE_H10: SC_QZ1_QUAD_PER_TILE_H10 tiles walked with 10 quads hit; quad-z pipe 1 44skSC_QZ1_QUAD_PER_TILE_H11: SC_QZ1_QUAD_PER_TILE_H11 tiles walked with 11 quads hit; quad-z pipe 1 55tkSC_QZ1_QUAD_PER_TILE_H12: SC_QZ1_QUAD_PER_TILE_H12 tiles walked with 12 quads hit; quad-z pipe 1 65ukSC_QZ1_QUAD_PER_TILE_H13: SC_QZ1_QUAD_PER_TILE_H13 tiles walked with 13 quads hit; quad-z pipe 1 76vkSC_QZ1_QUAD_PER_TILE_H14: SC_QZ1_QUAD_PER_TILE_H14 tiles walked with 14 quads hit; quad-z pipe 1 x87wkSC_QZ1_QUAD_PER_TILE_H15: SC_QZ1_QUAD_PER_TILE_H15 tiles walked with 15 quads hit; quad-z pipe 1 h98xkSC_QZ1_QUAD_PER_TILE_H16: SC_QZ1_QUAD_PER_TILE_H16 tiles walked with 16 quads hit; quad-z pipe 1 @:9yPSC_QZ0_QUAD_COUNT: SC_QZ0_QUAD_COUNT quad count; quad-z pipe 0 ;:zPSC_QZ1_QUAD_COUNT: SC_QZ1_QUAD_COUNT quad count; quad-z pipe 1 ;`;{TSC_QUAD0_NOT_PICKED_TB_R6XX: SC_QUAD0_NOT_PICKED_TB_GPU6 deprecated for GPU7 <8<|TSC_QUAD1_NOT_PICKED_TB_R6XX: SC_QUAD1_NOT_PICKED_TB_GPU6 deprecated for GPU7 ==}TSC_QUAD2_NOT_PICKED_TB_R6XX: SC_QUAD2_NOT_PICKED_TB_GPU6 deprecated for GPU7 x>=~TSC_QUAD3_NOT_PICKED_TB_R6XX: SC_QUAD3_NOT_PICKED_TB_GPU6 deprecated for GPU7 `?>_SC_P0_HIZ_TILE_COUNT: SC_P0_HIZ_TILE_COUNT total tiles surviving hi-z; db pipe 0 H@?_SC_P1_HIZ_TILE_COUNT: SC_P1_HIZ_TILE_COUNT total tiles surviving hi-z; db pipe 1 0A@_SC_P2_HIZ_TILE_COUNT: SC_P2_HIZ_TILE_COUNT total tiles surviving hi-z; db pipe 2 BxA_SC_P3_HIZ_TILE_COUNT: SC_P3_HIZ_TILE_COUNT total tiles surviving hi-z; db pipe 3 C`BmSC_P0_HIZ_QUAD_PER_TILE_H0: SC_P0_HIZ_QUAD_PER_TILE_H0 tiles with 0 quads surviving hi-z; db pipe 0 DXCmSC_P0_HIZ_QUAD_PER_TILE_H1: SC_P0_HIZ_QUAD_PER_TILE_H1 tiles with 1 quads surviving hi-z; db pipe 0 EPDmSC_P0_HIZ_QUAD_PER_TILE_H2: SC_P0_HIZ_QUAD_PER_TILE_H2 tiles with 2 quads surviving hi-z; db pipe 0 EHEmSC_P0_HIZ_QUAD_PER_TILE_H3: SC_P0_HIZ_QUAD_PER_TILE_H3 tiles with 3 quads surviving hi-z; db pipe 0 F@FmSC_P0_HIZ_QUAD_PER_TILE_H4: SC_P0_HIZ_QUAD_PER_TILE_H4 tiles with 4 quads surviving hi-z; db pipe 0 G8GmSC_P0_HIZ_QUAD_PER_TILE_H5: SC_P0_HIZ_QUAD_PER_TILE_H5 tiles with 5 quads surviving hi-z; db pipe 0 H0HmSC_P0_HIZ_QUAD_PER_TILE_H6: SC_P0_HIZ_QUAD_PER_TILE_H6 tiles with 6 quads surviving hi-z; db pipe 0 I(ImSC_P0_HIZ_QUAD_PER_TILE_H7: SC_P0_HIZ_QUAD_PER_TILE_H7 tiles with 7 quads surviving hi-z; db pipe 0 J JmSC_P0_HIZ_QUAD_PER_TILE_H8: SC_P0_HIZ_QUAD_PER_TILE_H8 tiles with 8 quads surviving hi-z; db pipe 0 KKmSC_P0_HIZ_QUAD_PER_TILE_H9: SC_P0_HIZ_QUAD_PER_TILE_H9 tiles with 9 quads surviving hi-z; db pipe 0 LLnSC_P0_HIZ_QUAD_PER_TILE_H10: SC_P0_HIZ_QUAD_PER_TILE_H10 tiles with 10 quads surviving hi-z; db pipe 0 MMnSC_P0_HIZ_QUAD_PER_TILE_H11: SC_P0_HIZ_QUAD_PER_TILE_H11 tiles with 11 quads surviving hi-z; db pipe 0 NNnSC_P0_HIZ_QUAD_PER_TILE_H12: SC_P0_HIZ_QUAD_PER_TILE_H12 tiles with 12 quads surviving hi-z; db pipe 0 ONnSC_P0_HIZ_QUAD_PER_TILE_H13: SC_P0_HIZ_QUAD_PER_TILE_H13 tiles with 13 quads surviving hi-z; db pipe 0 POnSC_P0_HIZ_QUAD_PER_TILE_H14: SC_P0_HIZ_QUAD_PER_TILE_H14 tiles with 14 quads surviving hi-z; db pipe 0 QPnSC_P0_HIZ_QUAD_PER_TILE_H15: SC_P0_HIZ_QUAD_PER_TILE_H15 tiles with 15 quads surviving hi-z; db pipe 0 RQnSC_P0_HIZ_QUAD_PER_TILE_H16: SC_P0_HIZ_QUAD_PER_TILE_H16 tiles with 16 quads surviving hi-z; db pipe 0 SRmSC_P1_HIZ_QUAD_PER_TILE_H0: SC_P0_HIZ_QUAD_PER_TILE_H0 tiles with 0 quads surviving hi-z; db pipe 1 TSmSC_P1_HIZ_QUAD_PER_TILE_H1: SC_P0_HIZ_QUAD_PER_TILE_H1 tiles with 1 quads surviving hi-z; db pipe 1 xUTmSC_P1_HIZ_QUAD_PER_TILE_H2: SC_P1_HIZ_QUAD_PER_TILE_H2 tiles with 2 quads surviving hi-z; db pipe 1 pVUmSC_P1_HIZ_QUAD_PER_TILE_H3: SC_P1_HIZ_QUAD_PER_TILE_H3 tiles with 3 quads surviving hi-z; db pipe 1 hWVmSC_P1_HIZ_QUAD_PER_TILE_H4: SC_P1_HIZ_QUAD_PER_TILE_H4 tiles with 4 quads surviving hi-z; db pipe 1 `XWmSC_P1_HIZ_QUAD_PER_TILE_H5: SC_P1_HIZ_QUAD_PER_TILE_H5 tiles with 5 quads surviving hi-z; db pipe 1 XYXmSC_P1_HIZ_QUAD_PER_TILE_H6: SC_P1_HIZ_QUAD_PER_TILE_H6 tiles with 6 quads surviving hi-z; db pipe 1 PZYmSC_P1_HIZ_QUAD_PER_TILE_H7: SC_P1_HIZ_QUAD_PER_TILE_H7 tiles with 7 quads surviving hi-z; db pipe 1 H[ZmSC_P1_HIZ_QUAD_PER_TILE_H8: SC_P1_HIZ_QUAD_PER_TILE_H8 tiles with 8 quads surviving hi-z; db pipe 1 @\[mSC_P1_HIZ_QUAD_PER_TILE_H9: SC_P1_HIZ_QUAD_PER_TILE_H9 tiles with 9 quads surviving hi-z; db pipe 1 8]\nSC_P1_HIZ_QUAD_PER_TILE_H10: SC_P1_HIZ_QUAD_PER_TILE_H10 tiles with 10 quads surviving hi-z; db pipe 1 0^]nSC_P1_HIZ_QUAD_PER_TILE_H11: SC_P1_HIZ_QUAD_PER_TILE_H11 tiles with 11 quads surviving hi-z; db pipe 1 (_x^nSC_P1_HIZ_QUAD_PER_TILE_H12: SC_P1_HIZ_QUAD_PER_TILE_H12 tiles with 12 quads surviving hi-z; db pipe 1 `p_nSC_P1_HIZ_QUAD_PER_TILE_H13: SC_P1_HIZ_QUAD_PER_TILE_H13 tiles with 13 quads surviving hi-z; db pipe 1 ah`nSC_P1_HIZ_QUAD_PER_TILE_H14: SC_P1_HIZ_QUAD_PER_TILE_H14 tiles with 14 quads surviving hi-z; db pipe 1 b`anSC_P1_HIZ_QUAD_PER_TILE_H15: SC_P1_HIZ_QUAD_PER_TILE_H15 tiles with 15 quads surviving hi-z; db pipe 1 cXbnSC_P1_HIZ_QUAD_PER_TILE_H16: SC_P1_HIZ_QUAD_PER_TILE_H16 tiles with 16 quads surviving hi-z; db pipe 1 dPcmSC_P2_HIZ_QUAD_PER_TILE_H0: SC_P2_HIZ_QUAD_PER_TILE_H0 tiles with 0 quads surviving hi-z; db pipe 2 dHdmSC_P2_HIZ_QUAD_PER_TILE_H1: SC_P2_HIZ_QUAD_PER_TILE_H1 tiles with 1 quads surviving hi-z; db pipe 2 e@emSC_P2_HIZ_QUAD_PER_TILE_H2: SC_P2_HIZ_QUAD_PER_TILE_H2 tiles with 2 quads surviving hi-z; db pipe 2 f8fmSC_P2_HIZ_QUAD_PER_TILE_H3: SC_P2_HIZ_QUAD_PER_TILE_H3 tiles with 3 quads surviving hi-z; db pipe 2 g0gmSC_P2_HIZ_QUAD_PER_TILE_H4: SC_P2_HIZ_QUAD_PER_TILE_H4 tiles with 4 quads surviving hi-z; db pipe 2 h(hmSC_P2_HIZ_QUAD_PER_TILE_H5: SC_P2_HIZ_QUAD_PER_TILE_H5 tiles with 5 quads surviving hi-z; db pipe 2 i imSC_P2_HIZ_QUAD_PER_TILE_H6: SC_P2_HIZ_QUAD_PER_TILE_H6 tiles with 6 quads surviving hi-z; db pipe 2 jjmSC_P2_HIZ_QUAD_PER_TILE_H7: SC_P2_HIZ_QUAD_PER_TILE_H7 tiles with 7 quads surviving hi-z; db pipe 2 kkmSC_P2_HIZ_QUAD_PER_TILE_H8: SC_P2_HIZ_QUAD_PER_TILE_H8 tiles with 8 quads surviving hi-z; db pipe 2 llmSC_P2_HIZ_QUAD_PER_TILE_H9: SC_P2_HIZ_QUAD_PER_TILE_H9 tiles with 9 quads surviving hi-z; db pipe 2 mmnSC_P2_HIZ_QUAD_PER_TILE_H10: SC_P2_HIZ_QUAD_PER_TILE_H10 tiles with 10 quads surviving hi-z; db pipe 2 nmnSC_P2_HIZ_QUAD_PER_TILE_H11: SC_P2_HIZ_QUAD_PER_TILE_H11 tiles with 11 quads surviving hi-z; db pipe 2 onnSC_P2_HIZ_QUAD_PER_TILE_H12: SC_P2_HIZ_QUAD_PER_TILE_H12 tiles with 12 quads surviving hi-z; db pipe 2 ponSC_P2_HIZ_QUAD_PER_TILE_H13: SC_P2_HIZ_QUAD_PER_TILE_H13 tiles with 13 quads surviving hi-z; db pipe 2 qpnSC_P2_HIZ_QUAD_PER_TILE_H14: SC_P2_HIZ_QUAD_PER_TILE_H14 tiles with 14 quads surviving hi-z; db pipe 2 rqnSC_P2_HIZ_QUAD_PER_TILE_H15: SC_P2_HIZ_QUAD_PER_TILE_H15 tiles with 15 quads surviving hi-z; db pipe 2 srnSC_P2_HIZ_QUAD_PER_TILE_H16: SC_P2_HIZ_QUAD_PER_TILE_H16 tiles with 16 quads surviving hi-z; db pipe 2 xtsmSC_P3_HIZ_QUAD_PER_TILE_H0: SC_P3_HIZ_QUAD_PER_TILE_H0 tiles with 0 quads surviving hi-z; db pipe 3 putmSC_P3_HIZ_QUAD_PER_TILE_H1: SC_P3_HIZ_QUAD_PER_TILE_H1 tiles with 1 quads surviving hi-z; db pipe 3 hvumSC_P3_HIZ_QUAD_PER_TILE_H2: SC_P3_HIZ_QUAD_PER_TILE_H2 tiles with 2 quads surviving hi-z; db pipe 3 `wvmSC_P3_HIZ_QUAD_PER_TILE_H3: SC_P3_HIZ_QUAD_PER_TILE_H3 tiles with 3 quads surviving hi-z; db pipe 3 XxwmSC_P3_HIZ_QUAD_PER_TILE_H4: SC_P3_HIZ_QUAD_PER_TILE_H4 tiles with 4 quads surviving hi-z; db pipe 3 PyxmSC_P3_HIZ_QUAD_PER_TILE_H5: SC_P3_HIZ_QUAD_PER_TILE_H5 tiles with 5 quads surviving hi-z; db pipe 3 HzymSC_P3_HIZ_QUAD_PER_TILE_H6: SC_P3_HIZ_QUAD_PER_TILE_H6 tiles with 6 quads surviving hi-z; db pipe 3 @{zmSC_P3_HIZ_QUAD_PER_TILE_H7: SC_P3_HIZ_QUAD_PER_TILE_H7 tiles with 7 quads surviving hi-z; db pipe 3 8|{mSC_P3_HIZ_QUAD_PER_TILE_H8: SC_P3_HIZ_QUAD_PER_TILE_H8 tiles with 8 quads surviving hi-z; db pipe 3 0}|mSC_P3_HIZ_QUAD_PER_TILE_H9: SC_P3_HIZ_QUAD_PER_TILE_H9 tiles with 9 quads surviving hi-z; db pipe 3 (~x}nSC_P3_HIZ_QUAD_PER_TILE_H10: SC_P3_HIZ_QUAD_PER_TILE_H10 tiles with 10 quads surviving hi-z; db pipe 3 p~nSC_P3_HIZ_QUAD_PER_TILE_H11: SC_P3_HIZ_QUAD_PER_TILE_H11 tiles with 11 quads surviving hi-z; db pipe 3 hnSC_P3_HIZ_QUAD_PER_TILE_H12: SC_P3_HIZ_QUAD_PER_TILE_H12 tiles with 12 quads surviving hi-z; db pipe 3 `nSC_P3_HIZ_QUAD_PER_TILE_H13: SC_P3_HIZ_QUAD_PER_TILE_H13 tiles with 13 quads surviving hi-z; db pipe 3 XnSC_P3_HIZ_QUAD_PER_TILE_H14: SC_P3_HIZ_QUAD_PER_TILE_H14 tiles with 14 quads surviving hi-z; db pipe 3 PnSC_P3_HIZ_QUAD_PER_TILE_H15: SC_P3_HIZ_QUAD_PER_TILE_H15 tiles with 15 quads surviving hi-z; db pipe 3 HnSC_P3_HIZ_QUAD_PER_TILE_H16: SC_P3_HIZ_QUAD_PER_TILE_H16 tiles with 16 quads surviving hi-z; db pipe 3 @_SC_P0_HIZ_QUAD_COUNT: SC_P0_HIZ_QUAD_COUNT total quads surviving hi-z; db pipe 0 ȅ(_SC_P1_HIZ_QUAD_COUNT: SC_P1_HIZ_QUAD_COUNT total quads surviving hi-z; db pipe 1 _SC_P2_HIZ_QUAD_COUNT: SC_P2_HIZ_QUAD_COUNT total quads surviving hi-z; db pipe 2 _SC_P3_HIZ_QUAD_COUNT: SC_P3_HIZ_QUAD_COUNT total quads surviving hi-z; db pipe 3 lSC_P0_DETAIL_QUAD_COUNT: SC_P0_DETAIL_QUAD_COUNT total quads surviving detail sampler; db pipe 0 xЈlSC_P1_DETAIL_QUAD_COUNT: SC_P1_DETAIL_QUAD_COUNT total quads surviving detail sampler; db pipe 1 hlSC_P2_DETAIL_QUAD_COUNT: SC_P2_DETAIL_QUAD_COUNT total quads surviving detail sampler; db pipe 2 XlSC_P3_DETAIL_QUAD_COUNT: SC_P3_DETAIL_QUAD_COUNT total quads surviving detail sampler; db pipe 3 PpSC_P0_DETAIL_QUAD_WITH_1_PIX: SC_P0_DETAIL_QUAD_WITH_1_PIX quads with 1 pixel surviving detail; db pipe 0 HqSC_P0_DETAIL_QUAD_WITH_2_PIX: SC_P0_DETAIL_QUAD_WITH_2_PIX quads with 2 pixels surviving detail; db pipe 0 @qSC_P0_DETAIL_QUAD_WITH_3_PIX: SC_P0_DETAIL_QUAD_WITH_3_PIX quads with 3 pixels surviving detail; db pipe 0 8qSC_P0_DETAIL_QUAD_WITH_4_PIX: SC_P0_DETAIL_QUAD_WITH_4_PIX quads with 4 pixels surviving detail; db pipe 0 0pSC_P1_DETAIL_QUAD_WITH_1_PIX: SC_P1_DETAIL_QUAD_WITH_1_PIX quads with 1 pixel surviving detail; db pipe 1 (xqSC_P1_DETAIL_QUAD_WITH_2_PIX: SC_P1_DETAIL_QUAD_WITH_2_PIX quads with 2 pixels surviving detail; db pipe 1 pqSC_P1_DETAIL_QUAD_WITH_3_PIX: SC_P1_DETAIL_QUAD_WITH_3_PIX quads with 3 pixels surviving detail; db pipe 1 hqSC_P1_DETAIL_QUAD_WITH_4_PIX: SC_P1_DETAIL_QUAD_WITH_4_PIX quads with 4 pixels surviving detail; db pipe 1 `pSC_P2_DETAIL_QUAD_WITH_1_PIX: SC_P2_DETAIL_QUAD_WITH_1_PIX quads with 1 pixel surviving detail; db pipe 2 XqSC_P2_DETAIL_QUAD_WITH_2_PIX: SC_P2_DETAIL_QUAD_WITH_2_PIX quads with 2 pixels surviving detail; db pipe 2 PqSC_P2_DETAIL_QUAD_WITH_3_PIX: SC_P2_DETAIL_QUAD_WITH_3_PIX quads with 3 pixels surviving detail; db pipe 2 HqSC_P2_DETAIL_QUAD_WITH_4_PIX: SC_P2_DETAIL_QUAD_WITH_4_PIX quads with 4 pixels surviving detail; db pipe 2 @pSC_P3_DETAIL_QUAD_WITH_1_PIX: SC_P3_DETAIL_QUAD_WITH_1_PIX quads with 1 pixel surviving detail; db pipe 3 蘗8qSC_P3_DETAIL_QUAD_WITH_2_PIX: SC_P3_DETAIL_QUAD_WITH_2_PIX quads with 2 pixels surviving detail; db pipe 3 0qSC_P3_DETAIL_QUAD_WITH_3_PIX: SC_P3_DETAIL_QUAD_WITH_3_PIX quads with 3 pixels surviving detail; db pipe 3 ؚ(qSC_P3_DETAIL_QUAD_WITH_4_PIX: SC_P3_DETAIL_QUAD_WITH_4_PIX quads with 4 pixels surviving detail; db pipe 3 WSC_EARLYZ_QUAD_COUNT: SC_EARLYZ_QUAD_COUNT total quads surviving early-z cSC_EARLYZ_QUAD_WITH_1_PIX: SC_EARLYZ_QUAD_WITH_1_PIX quads with 1 pixel surviving early-z 蜗dSC_EARLYZ_QUAD_WITH_2_PIX: SC_EARLYZ_QUAD_WITH_2_PIX quads with 2 pixels surviving early-z pНdSC_EARLYZ_QUAD_WITH_3_PIX: SC_EARLYZ_QUAD_WITH_3_PIX quads with 3 pixels surviving early-z XdSC_EARLYZ_QUAD_WITH_4_PIX: SC_EARLYZ_QUAD_WITH_4_PIX quads with 4 pixels surviving early-z 8YSC_TILE_REORDER_DB_CONFLICT_R6XX: SC_TILE_REORDER_DB_CONFLICT_GPU6 deprecated for GPU7 `SC_PKR_QUAD_PER_ROW_H1: SC_PKR_QUAD_PER_ROW_H1 packer row outputs with 1 valid quad h`SC_PKR_QUAD_PER_ROW_H2: SC_PKR_QUAD_PER_ROW_H2 packer row outputs with 2 valid quad P`SC_PKR_QUAD_PER_ROW_H3: SC_PKR_QUAD_PER_ROW_H3 packer row outputs with 3 valid quad أ8`SC_PKR_QUAD_PER_ROW_H4: SC_PKR_QUAD_PER_ROW_H4 packer row outputs with 4 valid quad QSC_PKR_END_OF_VECTOR: SC_PKR_END_OF_VECTOR number of pixel vectors TSC_PKR_CONTROL_XFER: SC_PKR_CONTROL_XFER number of control transfers Х|SC_PKR_DBHANG_FORCE_EOV: SC_PKR_DBHANG_FORCE_EOV number of times partial vector ejected b/c of DB hang condition pЦ]SC_REG_SCLK_BUSY: SC_REG_SCLK_BUSY number of cycles register clock is busy `hSC_GRP0_DYN_SCLK_BUSY: SC_GRP0_DYN_SCLK_BUSY number of cycles group0 dynamic clock is busy PhSC_GRP1_DYN_SCLK_BUSY: SC_GRP1_DYN_SCLK_BUSY number of cycles group1 dynamic clock is busy @hSC_GRP2_DYN_SCLK_BUSY: SC_GRP2_DYN_SCLK_BUSY number of cycles group2 dynamic clock is busy 0hSC_GRP3_DYN_SCLK_BUSY: SC_GRP3_DYN_SCLK_BUSY number of cycles group3 dynamic clock is busy xhSC_GRP4_DYN_SCLK_BUSY: SC_GRP4_DYN_SCLK_BUSY number of cycles group4 dynamic clock is busy ŖXȖԋԋ"" ȖPA_SC_IF_FIFO_SIZE`ɖɖ SC_DB_QUAD_IF_FIFO_SIZE_R6XX"ɖ SC_SX_CMD_IF_FIFO_SIZE"8–ŖЋЋ"" ŖPA_SC_FIFO_SIZEƖ0ƖSC_PRIM_FIFO_SIZE"0ǖƖSC_HIZ_TILE_FIFO_SIZE"ǖSC_EARLYZ_TILE_FIFO_SIZE"躖–̋̋"" ÖPA_SC_FIFO_SIZE_R7XXÖ`Ö SC_PRIM_FIFO_SIZE"`ĖĖ SC_HIZ_TILE_FIFO_SIZE"Ė SC_EARLYZ_TILE_FIFO_SIZE"`(("" CGTT_SC_CLK_CTRL P ON_DELAY"OFF_HYSTERESIS"PSOFT_OVERRIDE7"HSOFT_OVERRIDE6"SOFT_OVERRIDE5"HSOFT_OVERRIDE4"@SOFT_OVERRIDE3"SOFT_OVERRIDE2"@SOFT_OVERRIDE1"SOFT_OVERRIDE0"0$$"" PA_SC_FORCE_EOV_MAX_CNTS8๖FORCE_EOV_MAX_CLK_CNT"FORCE_EOV_MAX_REZ_CNT"دh "" PA_SC_MULTI_CHIP_CNTLhLOG2_NUM_CHIPS"MULTI_CHIP_TILE_SIZE`16 x 16 pixel tile per chip. h32 x 32 pixel tile per chip. 64 x 64 pixel tile per chip. X128x128 pixel tile per chip. `CHIP_TILE_X_LOC"CHIP_TILE_Y_LOC"` CHIP_SUPER_TILE_B_R6XX"P"" PA_SC_LINE_STIPPLE_STATEH CURRENT_PTR"CURRENT_COUNT"Ȝ0HH"" PA_SC_MPASS_PS_CNTL0خMPASS_PIX_VEC_PER_PASS" MPASS_PS_ENA"`@LL"" PA_SC_MODE_CNTL0蝖 MSAA_ENABLE"CLIPRECT_ENABLE_R6XX"8LINE_STIPPLE_ENABLE"@MULTI_CHIP_PRIM_DISCARD_ENABLE"TILE_WALK_ORDER_ENABLE"HHALVE_DETAIL_SAMPLE_PERF_R6XX"H WALK_SIZE"WALK_ALIGNMENT"HWALK_ALIGN8_PRIM_FITS_ST"P TILE_COVER_NO_SCISSOR" KILL_PIX_POST_HI_Z"P KILL_PIX_POST_DETAIL_MASK"X MULTI_CHIP_SUPERTILE_ENABLE" TILE_COVER_DISABLE"XFORCE_EOV_CNTDWN_ENABLE"`FORCE_EOV_TILE_ENABLE_R6XX"FORCE_EOV_REZ_ENABLE"hPS_ITER_SAMPLE"`CHIP_SUPER_TILE_B"ZMM_LINE_EXTENT"`ZMM_LINE_OFFSET"XZMM_RECT_EXTENT"VPORT_SCISSOR_ENABLE"`SUPERTILE_WALK_ORDER_ENABLE"؛LL"" (PA_SC_VPORT_ZMAX_15 VPORT_ZMAX"pDD"" PA_SC_VPORT_ZMAX_14 VPORT_ZMAX"(<<"" XPA_SC_VPORT_ZMAX_13 VPORT_ZMAX"44"" PA_SC_VPORT_ZMAX_12H VPORT_ZMAX"X8,,"" PA_SC_VPORT_ZMAX_11 VPORT_ZMAX"Д$$"" PA_SC_VPORT_ZMAX_10x VPORT_ZMAX"h"" PA_SC_VPORT_ZMAX_9 VPORT_ZMAX" "" PPA_SC_VPORT_ZMAX_8 VPORT_ZMAX"  "" 萖PA_SC_VPORT_ZMAX_7@ VPORT_ZMAX"P0"" PA_SC_VPORT_ZMAX_6؏ VPORT_ZMAX"苖ȍ"" PA_SC_VPORT_ZMAX_5p VPORT_ZMAX"`"" PA_SC_VPORT_ZMAX_4 VPORT_ZMAX""" HPA_SC_VPORT_ZMAX_3 VPORT_ZMAX""" PA_SC_VPORT_ZMAX_28 VPORT_ZMAX"H(܂܂"" xPA_SC_VPORT_ZMAX_1Ј VPORT_ZMAX"ԂԂ"" PA_SC_VPORT_ZMAX_0h VPORT_ZMAX"xXHH"" PA_SC_VPORT_ZMIN_15 VPORT_ZMIN"@@"" @PA_SC_VPORT_ZMIN_14 VPORT_ZMIN"88"" ؂PA_SC_VPORT_ZMIN_130 VPORT_ZMIN"@ 00"" pPA_SC_VPORT_ZMIN_12ȁ VPORT_ZMIN"}(("" PA_SC_VPORT_ZMIN_11` VPORT_ZMIN"p|P~  "" ~PA_SC_VPORT_ZMIN_10~ VPORT_ZMIN"{|"" 8}PA_SC_VPORT_ZMIN_9} VPORT_ZMIN"y{"" {PA_SC_VPORT_ZMIN_8(| VPORT_ZMIN"8xz"" hzPA_SC_VPORT_ZMIN_7z VPORT_ZMIN"vx"" yPA_SC_VPORT_ZMIN_6Xy VPORT_ZMIN"huHw"" wPA_SC_VPORT_ZMIN_5w VPORT_ZMIN"tu"" 0vPA_SC_VPORT_ZMIN_4v VPORT_ZMIN"rxt"" tPA_SC_VPORT_ZMIN_3 u VPORT_ZMIN"0qs"" `sPA_SC_VPORT_ZMIN_2s VPORT_ZMIN"oq؂؂"" qPA_SC_VPORT_ZMIN_1Pr VPORT_ZMIN"m@pЂЂ"" pPA_SC_VPORT_ZMIN_0p VPORT_ZMIN"k0n̂̂"" nPA_SC_VPORT_SCISSOR_15_BR(onBR_X"oBR_Y"i lĂĂ"" xlPA_SC_VPORT_SCISSOR_14_BRmlBR_X"pmBR_Y"gj"" hjPA_SC_VPORT_SCISSOR_13_BRkjBR_X"`kBR_Y"xeh"" XhPA_SC_VPORT_SCISSOR_12_BRhhBR_X"PiBR_Y"hce"" HfPA_SC_VPORT_SCISSOR_11_BRffBR_X"@gBR_Y"Xac"" 8dPA_SC_VPORT_SCISSOR_10_BRddBR_X"0eBR_Y"H_a"" (bPA_SC_VPORT_SCISSOR_9_BRbbBR_X" cBR_Y"8]_"" `PA_SC_VPORT_SCISSOR_8_BR`p`BR_X"aBR_Y"([]"" ^PA_SC_VPORT_SCISSOR_7_BR^`^BR_X"_BR_Y"Y["" [PA_SC_VPORT_SCISSOR_6_BR\P\BR_X"\BR_Y"WY||"" YPA_SC_VPORT_SCISSOR_5_BRZ@ZBR_X"ZBR_Y"TWtt"" WPA_SC_VPORT_SCISSOR_4_BRxX0XBR_X"XBR_Y"RpUll"" UPA_SC_VPORT_SCISSOR_3_BRhV VBR_X"VBR_Y"P`Sdd"" SPA_SC_VPORT_SCISSOR_2_BRXTTBR_X"TBR_Y"NPQ\\"" QPA_SC_VPORT_SCISSOR_1_BRHRRBR_X"RBR_Y"L@OTT"" OPA_SC_VPORT_SCISSOR_0_BR8POBR_X"PBR_Y"HILȂȂ"" LPA_SC_VPORT_SCISSOR_15_TLxM0MTL_X"NMTL_Y"pNWINDOW_OFFSET_DISABLE"FI"" JPA_SC_VPORT_SCISSOR_14_TLJpJTL_X"XKKTL_Y"KWINDOW_OFFSET_DISABLE"CG"" XGPA_SC_VPORT_SCISSOR_13_TLGGTL_X"HPHTL_Y"HWINDOW_OFFSET_DISABLE"A@D"" DPA_SC_VPORT_SCISSOR_12_TL8EDTL_X"EETL_Y"0FWINDOW_OFFSET_DISABLE"H>A"" APA_SC_VPORT_SCISSOR_11_TLxB0BTL_X"CBTL_Y"pCWINDOW_OFFSET_DISABLE";>"" ?PA_SC_VPORT_SCISSOR_10_TL?p?TL_X"X@@TL_Y"@WINDOW_OFFSET_DISABLE"8<"" X<PA_SC_VPORT_SCISSOR_9_TL<<TL_X"=P=TL_Y"=WINDOW_OFFSET_DISABLE"6@9"" 9PA_SC_VPORT_SCISSOR_8_TL8:9TL_X"::TL_Y"0;WINDOW_OFFSET_DISABLE"H36"" 6PA_SC_VPORT_SCISSOR_7_TLx707TL_X"87TL_Y"p8WINDOW_OFFSET_DISABLE"03"" 4PA_SC_VPORT_SCISSOR_6_TL4p4TL_X"X55TL_Y"5WINDOW_OFFSET_DISABLE"-1xx"" X1PA_SC_VPORT_SCISSOR_5_TL11TL_X"2P2TL_Y"2WINDOW_OFFSET_DISABLE"+@.pp"" .PA_SC_VPORT_SCISSOR_4_TL8/.TL_X"//TL_Y"00WINDOW_OFFSET_DISABLE"H(+hh"" +PA_SC_VPORT_SCISSOR_3_TLx,0,TL_X"-,TL_Y"p-WINDOW_OFFSET_DISABLE"%(``"" )PA_SC_VPORT_SCISSOR_2_TL)p)TL_X"X**TL_Y"*WINDOW_OFFSET_DISABLE""&XX"" X&PA_SC_VPORT_SCISSOR_1_TL&&TL_X"'P'TL_Y"'WINDOW_OFFSET_DISABLE" @#PP"" #PA_SC_VPORT_SCISSOR_0_TL8$#TL_X"$$TL_Y"0%WINDOW_OFFSET_DISABLE"0!DD"" !PA_SC_GENERIC_SCISSOR_BR("!BR_X""BR_Y"h@@"" PA_SC_GENERIC_SCISSOR_TL`TL_X" TL_Y"` WINDOW_OFFSET_DISABLE"@00"" PA_SC_EDGERULE0ER_TRI" ER_POINT"p(ER_RECT"  ER_LINE_LR"h ER_LINE_RL"P ER_LINE_TB" ER_LINE_BT"8,,"" PA_SC_CLIPRECT_3_BR(BR_X"BR_Y"0(("" PA_SC_CLIPRECT_3_TL TL_X"xTL_Y"($$"" xPA_SC_CLIPRECT_2_BRBR_X"pBR_Y"   "" pPA_SC_CLIPRECT_2_TLTL_X"hTL_Y" "" hPA_SC_CLIPRECT_1_BRBR_X"`BR_Y"  "" ` PA_SC_CLIPRECT_1_TL TL_X"XTL_Y" "" X PA_SC_CLIPRECT_0_BR BR_X"P BR_Y"  "" P PA_SC_CLIPRECT_0_TL TL_X"H TL_Y"  "" PA_SC_CLIPRECT_RULE@ CLIP_RULE"P"" PA_SC_WINDOW_SCISSOR_BR8BR_X"BR_Y"@"" PA_SC_WINDOW_SCISSOR_TLxTL_X"`TL_Y"WINDOW_OFFSET_DISABLE"044"" PA_SC_SCREEN_SCISSOR_BRhBR_X"BR_Y"p00"" PA_SC_SCREEN_SCISSOR_TLXTL_X"TL_Y""" 8PA_SC_LINE_CNTLBRES_CNTL_R6XX"8USE_BRES_CNTL_R6XX"0 EXPAND_LINE_WIDTH"  LAST_PIXEL"( PERPENDICULAR_ENDCAP_ENA" DX10_DIAMOND_TEST_ENA"0  "" PA_SC_LINE_STIPPLEx( LINE_PATTERN"  REPEAT_COUNT"xPATTERN_BIT_ORDER" AUTO_RESET_CNTL"`  "" !PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX`S4_X"HS4_Y"S5_X"@ S5_Y"(S6_X"S6_Y"h S7_X"S7_Y""" 0PA_SC_AA_SAMPLE_LOCS_MCTXS0_X"p(S0_Y"S1_X"h S1_Y"PS2_X"S2_Y"HS3_X"S3_Y"0pHH"" PA_SC_AA_MASK AA_MASK""" PA_SC_AA_CONFIGPMSAA_NUM_SAMPLES"PAA_MASK_CENTROID_DTMN" MAX_SAMPLE_DIST""" PA_SC_WINDOW_OFFSET8WINDOW_X_OFFSET"WINDOW_Y_OFFSET"8 LL"" xPA_SU_PERFCOUNTER3_HI PERF_COUNT"ߕHH"" PA_SU_PERFCOUNTER3_LOW` PERF_COUNT"Xޕ@DD"" PA_SU_PERFCOUNTER2_HI PERF_COUNT"ܕޕ@@"" (ߕPA_SU_PERFCOUNTER2_LOWߕ PERF_COUNT"xە`ݕ<<"" ݕPA_SU_PERFCOUNTER1_HIޕ PERF_COUNT"ڕە88"" HܕPA_SU_PERFCOUNTER1_LOWܕ PERF_COUNT"ؕڕ44"" ڕPA_SU_PERFCOUNTER0_HI0ە PERF_COUNT"dٕ00"" hٕPA_SU_PERFCOUNTER0_LOWٕ PERF_COUNT"`pe,,"" ePA_SU_PERFCOUNTER3_SELECT fhf PERF_SELpHgfVPERF_PAPC_PASX_REQ: PERF_PAPC_PASX_REQ Number of PA->SX requests @hgsPERF_PAPC_PASX_DISABLE_PIPE: PERF_PAPC_PASX_DISABLE_PIPE Number of transfers lost due to disabled pipe 0ihkPERF_PAPC_PASX_FIRST_VECTOR: PERF_PAPC_PASX_FIRST_VECTOR Number of First Vectors from SX to PA (jximPERF_PAPC_PASX_SECOND_VECTOR: PERF_PAPC_PASX_SECOND_VECTOR Number of Second Vectors from SX to PA (kpj|PERF_PAPC_PASX_FIRST_DEAD: PERF_PAPC_PASX_FIRST_DEAD Number of Unused First Vectors (due to granularity of 4) 0lpk~PERF_PAPC_PASX_SECOND_DEAD: PERF_PAPC_PASX_SECOND_DEAD Number of Unused Second Vectors (due to granularity of 4) 8mxlPERF_PAPC_PASX_VTX_KILL_DISCARD: PERF_PAPC_PASX_VTX_KILL_DISCARD Number of vertices which have VTX KILL Enabled and Set HnmPERF_PAPC_PASX_VTX_NAN_DISCARD: PERF_PAPC_PASX_VTX_NAN_DISCARD Number of vertices which have NaN and corresponding NaN discard 0onbPERF_PAPC_PA_INPUT_PRIM: PERF_PAPC_PA_INPUT_PRIM Number of Primitives input to PA pxo lPERF_PAPC_PA_INPUT_NULL_PRIM: PERF_PAPC_PA_INPUT_NULL_PRIM Number of Null Primitives input to PA qhp dPERF_PAPC_PA_INPUT_EVENT_FLAG: PERF_PAPC_PA_INPUT_EVENT_FLAG Number of Events input to PA rPq vPERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT: PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT Number of First-Prim-Of-Slots input to PA sPr oPERF_PAPC_PA_INPUT_END_OF_PACKET: PERF_PAPC_PA_INPUT_END_OF_PACKET Number of End-Of-Packets input to PA sHs qPERF_PAPC_PA_INPUT_EXTENDED_EVENT: PERF_PAPC_PA_INPUT_EXTENDED_EVENT Number of Extended Events input to PA u@tPERF_PAPC_CLPR_CULL_PRIM: PERF_PAPC_CLPR_CULL_PRIM Number of Prims Culled by Clipper for VV, UCP, VTX_KILL, VTX_NAN vHuyPERF_PAPC_CLPR_VVUCP_CULL_PRIM: PERF_PAPC_CLPR_VVUCP_CULL_PRIM Number of Prims Culled by Clipper for VV and UCP vHvnPERF_PAPC_CLPR_VV_CULL_PRIM: PERF_PAPC_CLPR_VV_CULL_PRIM Number of Prims Culled by Clipper for VV w@wpPERF_PAPC_CLPR_UCP_CULL_PRIM: PERF_PAPC_CLPR_UCP_CULL_PRIM Number of Prims Culled by Clipper for UCP x8xzPERF_PAPC_CLPR_VTX_KILL_CULL_PRIM: PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM Number of Prims Culled by Clipper for VTX_KILL y8yxPERF_PAPC_CLPR_VTX_NAN_CULL_PRIM: PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM Number of Prims Culled by Clipper for VTX_NAN z8zPERF_PAPC_CLPR_CULL_TO_NULL_PRIM: PERF_PAPC_CLPR_CULL_TO_NULL_PRIM Number of Clipper Culled Prims Retained for Pipe Info |@{}PERF_PAPC_CLPR_VVUCP_CLIP_PRIM: PERF_PAPC_CLPR_VVUCP_CLIP_PRIM Number of Prims Clipped by Clipper for VV and/or UCP |H|oPERF_PAPC_CLPR_VV_CLIP_PRIM: PERF_PAPC_CLPR_VV_CLIP_PRIM Number of Prims Clipped by Clipper for VV }@}qPERF_PAPC_CLPR_UCP_CLIP_PRIM: PERF_PAPC_CLPR_UCP_CLIP_PRIM Number of Prims Clipped by Clipper for UCP ~8~PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE: PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE Number of Points which require detailed clip checked @PERF_PAPC_CLPR_CLIP_PLANE_CNT_1: PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 Number of Prims with 1 Clip Plane Intersection (includes VV and UCP) (XPERF_PAPC_CLPR_CLIP_PLANE_CNT_2: PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 Number of Prims with 2 Clip Plane Intersections (includes VV and UCP) @pPERF_PAPC_CLPR_CLIP_PLANE_CNT_3: PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 Number of Prims with 3 Clip Plane Intersections (includes VV and UCP) XPERF_PAPC_CLPR_CLIP_PLANE_CNT_4: PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 Number of Prims with 4 Clip Plane Intersections (includes VV and UCP) pPERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8: PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 Number of Prims with 5-8 Clip Plane Intersections (includes VV and UCP) PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12: PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 Number of Prims with 9-12 Clip Plane Intersections (includes VV and UCP) ؅|PERF_PAPC_CLPR_CLIP_PLANE_NEAR: PERF_PAPC_CLPR_CLIP_PLANE_NEAR Number of Prims which intersect the NEAR VV Plane ؆ {PERF_PAPC_CLPR_CLIP_PLANE_FAR: PERF_PAPC_CLPR_CLIP_PLANE_FAR Number of Prims which intersect the FAR VV Plane ؇!|PERF_PAPC_CLPR_CLIP_PLANE_LEFT: PERF_PAPC_CLPR_CLIP_PLANE_LEFT Number of Prims which intersect the LEFT VV Plane ؈"}PERF_PAPC_CLPR_CLIP_PLANE_RIGHT: PERF_PAPC_CLPR_CLIP_PLANE_RIGHT Number of Prims which intersect the RIGHT VV Plane #{PERF_PAPC_CLPR_CLIP_PLANE_TOP: PERF_PAPC_CLPR_CLIP_PLANE_TOP Number of Prims which intersect the TOP VV Plane $~PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM: PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM Number of Prims which intersect the BOTTOM VV Plane 苕%PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM: PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM Number of Prims Culled by Clipper for Geometry Shader Scenario C Cuts ؍&PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM: PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM Number of Prims Culled by Clipper for DX10 Rasterization Kill (null PS) '}PERF_PAPC_CLSM_NULL_PRIM: PERF_PAPC_CLSM_NULL_PRIM Number of null primitives at Clip State Machine pipe stage (({PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM: PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM Number of totally visible (no-clipping) prims 萕()PERF_PAPC_CLSM_CULL_TO_NULL_PRIM: PERF_PAPC_CLSM_CULL_TO_NULL_PRIM Number of primitives which are culled during clip process 0*PERF_PAPC_CLSM_OUT_PRIM_CNT_1: PERF_PAPC_CLSM_OUT_PRIM_CNT_1 Number of primitives which were clipped and result in 1 primitive @+PERF_PAPC_CLSM_OUT_PRIM_CNT_2: PERF_PAPC_CLSM_OUT_PRIM_CNT_2 Number of primitives which were clipped and result in 2 primitives P,PERF_PAPC_CLSM_OUT_PRIM_CNT_3: PERF_PAPC_CLSM_OUT_PRIM_CNT_3 Number of primitives which were clipped and result in 3 primitives (`-PERF_PAPC_CLSM_OUT_PRIM_CNT_4: PERF_PAPC_CLSM_OUT_PRIM_CNT_4 Number of primitives which were clipped and result in 4 primitives @p.PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8: PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 Number of primitives which were clipped and result in 5-8 primitives X/PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13: PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 Number of primitives which were clipped and result in 9-13 primitives `0PERF_PAPC_CLIPGA_VTE_KILL_PRIM: PERF_PAPC_CLIPGA_VTE_KILL_PRIM Number of primitives which are culled by VTE nan/inf logic X1oPERF_PAPC_SU_INPUT_PRIM: PERF_PAPC_SU_INPUT_PRIM Number of primitives input to the Setup block X2|PERF_PAPC_SU_INPUT_CLIP_PRIM: PERF_PAPC_SU_INPUT_CLIP_PRIM Number of clipped primitives input to the Setup block X3yPERF_PAPC_SU_INPUT_NULL_PRIM: PERF_PAPC_SU_INPUT_NULL_PRIM Number of null primitives input to the Setup block `4PERF_PAPC_SU_INPUT_PRIM_DUAL: PERF_PAPC_SU_INPUT_PRIM_DUAL Number of dual gradient primitives input to the Setup block x5PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL: PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL Number of dual gradient clipped primitives input to the Setup block x6wPERF_PAPC_SU_ZERO_AREA_CULL_PRIM: PERF_PAPC_SU_ZERO_AREA_CULL_PRIM Number of primitives culled due to zero area 7PERF_PAPC_SU_BACK_FACE_CULL_PRIM: PERF_PAPC_SU_BACK_FACE_CULL_PRIM Number of back-face primitives culled due to facedness ȟ8PERF_PAPC_SU_FRONT_FACE_CULL_PRIM: PERF_PAPC_SU_FRONT_FACE_CULL_PRIM Number of front-face primitives culled due to facedness Р9PERF_PAPC_SU_POLYMODE_FACE_CULL: PERF_PAPC_SU_POLYMODE_FACE_CULL Number of polymode cull-determination primitives culled ء:PERF_PAPC_SU_POLYMODE_BACK_CULL: PERF_PAPC_SU_POLYMODE_BACK_CULL Number of polymode primitives discarded due to Back-Face Cull 袕;PERF_PAPC_SU_POLYMODE_FRONT_CULL: PERF_PAPC_SU_POLYMODE_FRONT_CULL Number of polymode primitives discarded due to Front-Face Cull 褕<PERF_PAPC_SU_POLYMODE_INVALID_FILL: PERF_PAPC_SU_POLYMODE_INVALID_FILL Number of polymode lines and/or points which are culled because they are an internal edge or point ॕ0=sPERF_PAPC_SU_OUTPUT_PRIM: PERF_PAPC_SU_OUTPUT_PRIM Number of primitives output from the Setup block 覕(>PERF_PAPC_SU_OUTPUT_CLIP_PRIM: PERF_PAPC_SU_OUTPUT_CLIP_PRIM Number of clipped primitives output from the Setup block 0?}PERF_PAPC_SU_OUTPUT_NULL_PRIM: PERF_PAPC_SU_OUTPUT_NULL_PRIM Number of null primitives output from the Setup block 8@uPERF_PAPC_SU_OUTPUT_EVENT_FLAG: PERF_PAPC_SU_OUTPUT_EVENT_FLAG Number of events output from the Setup block 8APERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT: PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT Number of First-Prim-Of-Slots output from the Setup block HBPERF_PAPC_SU_OUTPUT_END_OF_PACKET: PERF_PAPC_SU_OUTPUT_END_OF_PACKET Number of End-Of-Packets output from the Setup block PCPERF_PAPC_SU_OUTPUT_POLYMODE_FACE: PERF_PAPC_SU_OUTPUT_POLYMODE_FACE Number of polymode facing primitives output from the Setup block 0`DPERF_PAPC_SU_OUTPUT_POLYMODE_BACK: PERF_PAPC_SU_OUTPUT_POLYMODE_BACK Number of polymode back-face primitives output from the Setup block HxEPERF_PAPC_SU_OUTPUT_POLYMODE_FRONT: PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT Number of polymode front-face primitives output from the Setup block hFPERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE: PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE Number of clipped polymode facing primitives output from the Setup block GPERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK: PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK Number of clipped polymode back-face primitives output from the Setup block аHPERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT: PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT Number of clipped polymode front-face primitives output from the Setup block IPERF_PAPC_SU_OUTPUT_PRIM_DUAL: PERF_PAPC_SU_OUTPUT_PRIM_DUAL Number of dual gradient primitives output from the Setup block гJPERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL: PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL Number of dual gradient clipped primitives output from the Setup block 贕KPERF_PAPC_SU_OUTPUT_POLYMODE_DUAL: PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL Number of dual gradient polymode primitives output from the Setup block 0LPERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL: PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL Number of dual gradient clip polymode primitives output from the Setup block XMiPERF_PAPC_PASX_REQ_IDLE: PERF_PAPC_PASX_REQ_IDLE Number of clocks PASX Requestor is Idle HNiPERF_PAPC_PASX_REQ_BUSY: PERF_PAPC_PASX_REQ_BUSY Number of clocks PASX Requestor is Busy 踕8OoPERF_PAPC_PASX_REQ_STALLED: PERF_PAPC_PASX_REQ_STALLED Number of clocks PASX Requestor is Stalled ع0PhPERF_PAPC_PASX_REC_IDLE: PERF_PAPC_PASX_REC_IDLE Number of clocks PASX Receiver is Idle Ⱥ QhPERF_PAPC_PASX_REC_BUSY: PERF_PAPC_PASX_REC_BUSY Number of clocks PASX Receiver is Busy ȻRwPERF_PAPC_PASX_REC_STARVED_SX: PERF_PAPC_PASX_REC_STARVED_SX Number of clocks PASX Receiver is Stalled by SX 輕SPERF_PAPC_PASX_REC_STALLED: PERF_PAPC_PASX_REC_STALLED Number of clocks PASX Reciever is Stalled by Position Memory or Clip Code Generator 0TPERF_PAPC_PASX_REC_STALLED_POS_MEM: PERF_PAPC_PASX_REC_STALLED_POS_MEM Number of clocks PASX Reciever is Stalled by Position Memory @UPERF_PAPC_PASX_REC_STALLED_CCGSM_IN: PERF_PAPC_PASX_REC_STALLED_CCGSM_IN Number of clocks PASX Reciever is Stalled by Clip Code Generator XVePERF_PAPC_CCGSM_IDLE: PERF_PAPC_CCGSM_IDLE Number of clocks Clip Code Gen is Idle PWePERF_PAPC_CCGSM_BUSY: PERF_PAPC_CCGSM_BUSY Number of clocks Clip Code Gen is Busy @XkPERF_PAPC_CCGSM_STALLED: PERF_PAPC_CCGSM_STALLED Number of clocks Clip Code Gen is Stalled •0•YoPERF_PAPC_CLPRIM_IDLE: PERF_PAPC_CLPRIM_IDLE Number of clocks Clip Primitive Machine is Idle Õ(ÕZoPERF_PAPC_CLPRIM_BUSY: PERF_PAPC_CLPRIM_BUSY Number of clocks Clip Primitive Machine is Busy ĕ ĕ[PERF_PAPC_CLPRIM_STALLED: PERF_PAPC_CLPRIM_STALLED Number of clocks Clip Primitive Machine is stalled by Clip State Machines ƕ0ŕ\PERF_PAPC_CLPRIM_STARVED_CCGSM: PERF_PAPC_CLPRIM_STARVED_CCGSM Number of clocks Clip Primitive Machine is starved by Clip Code Generator ƕHƕ]mPERF_PAPC_CLIPSM_IDLE: PERF_PAPC_CLIPSM_IDLE Number of clocks Clip State Machines are Idle Ǖ@Ǖ^mPERF_PAPC_CLIPSM_BUSY: PERF_PAPC_CLIPSM_BUSY Number of clocks Clip State Machines are Busy ɕ8ȕ_PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH: PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH Number of clocks Clip State Mahcines are waiting for Clip Vert storage resources 8ʕ`ɕ`PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ: PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ Number of clocks Clip State Machines are waiting for High Priority Sequencer @˕ʕaPERF_PAPC_CLIPSM_WAIT_CLIPGA: PERF_PAPC_CLIPSM_WAIT_CLIPGA Number of clocks Clip State Machines are waiting for ClipGA X̕˕bPERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP: PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP Number of clocks Clip State Machines are waiting for VTE cycles x͕̕cPERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM: PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM Number of clocks Clip State Machines are waiting for Clip Output State Machine `Ε͕d`PERF_PAPC_CLIPGA_IDLE: PERF_PAPC_CLIPGA_IDLE Number of clocks Clip Ga is Idle HϕΕe`PERF_PAPC_CLIPGA_BUSY: PERF_PAPC_CLIPGA_BUSY Number of clocks Clip Ga is Busy PЕϕfPERF_PAPC_CLIPGA_STARVED_VTE_CLIP: PERF_PAPC_CLIPGA_STARVED_VTE_CLIP Number of clocks Clip Ga is Starved by VTE or Clipper @ѕЕgfPERF_PAPC_CLIPGA_STALLED: PERF_PAPC_CLIPGA_STALLED Number of clocks Clip Ga is stalled ҕѕh[PERF_PAPC_CLIP_IDLE: PERF_PAPC_CLIP_IDLE Number of clocks Clip is Idle ӕhҕi[PERF_PAPC_CLIP_BUSY: PERF_PAPC_CLIP_BUSY Number of clocks Clip is Busy ӕHӕjZPERF_PAPC_SU_IDLE: PERF_PAPC_SU_IDLE Number of clocks Setup is Idle ԕ(ԕkZPERF_PAPC_SU_BUSY: PERF_PAPC_SU_BUSY Number of clocks Setup is Busy ՕՕlpPERF_PAPC_SU_STARVED_CLIP: PERF_PAPC_SU_STARVED_CLIP Number of clocks Setup is starved by Clipper ֕֕miPERF_PAPC_SU_STALLED_SC: PERF_PAPC_SU_STALLED_SC Number of clocks Setup is stalled by SC ו֕nsPERF_PAPC_PA_DYN_SCLK_VLD: PERF_PAPC_PA_DYN_SCLK_VLD Number of clocks the PA dynamic clock is active וotPERF_PAPC_PA_REG_SCLK_VLD: PERF_PAPC_PA_REG_SCLK_VLD Number of clocks the PA register clock is active }(("" 0PA_SU_PERFCOUNTER2_SELECT PERF_SELpVPERF_PAPC_PASX_REQ: PERF_PAPC_PASX_REQ Number of PA->SX requests sPERF_PAPC_PASX_DISABLE_PIPE: PERF_PAPC_PASX_DISABLE_PIPE Number of transfers lost due to disabled pipe kPERF_PAPC_PASX_FIRST_VECTOR: PERF_PAPC_PASX_FIRST_VECTOR Number of First Vectors from SX to PA mPERF_PAPC_PASX_SECOND_VECTOR: PERF_PAPC_PASX_SECOND_VECTOR Number of Second Vectors from SX to PA |PERF_PAPC_PASX_FIRST_DEAD: PERF_PAPC_PASX_FIRST_DEAD Number of Unused First Vectors (due to granularity of 4) ~PERF_PAPC_PASX_SECOND_DEAD: PERF_PAPC_PASX_SECOND_DEAD Number of Unused Second Vectors (due to granularity of 4) PERF_PAPC_PASX_VTX_KILL_DISCARD: PERF_PAPC_PASX_VTX_KILL_DISCARD Number of vertices which have VTX KILL Enabled and Set PERF_PAPC_PASX_VTX_NAN_DISCARD: PERF_PAPC_PASX_VTX_NAN_DISCARD Number of vertices which have NaN and corresponding NaN discard bPERF_PAPC_PA_INPUT_PRIM: PERF_PAPC_PA_INPUT_PRIM Number of Primitives input to PA lPERF_PAPC_PA_INPUT_NULL_PRIM: PERF_PAPC_PA_INPUT_NULL_PRIM Number of Null Primitives input to PA p dPERF_PAPC_PA_INPUT_EVENT_FLAG: PERF_PAPC_PA_INPUT_EVENT_FLAG Number of Events input to PA p vPERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT: PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT Number of First-Prim-Of-Slots input to PA h oPERF_PAPC_PA_INPUT_END_OF_PACKET: PERF_PAPC_PA_INPUT_END_OF_PACKET Number of End-Of-Packets input to PA ` qPERF_PAPC_PA_INPUT_EXTENDED_EVENT: PERF_PAPC_PA_INPUT_EXTENDED_EVENT Number of Extended Events input to PA hPERF_PAPC_CLPR_CULL_PRIM: PERF_PAPC_CLPR_CULL_PRIM Number of Prims Culled by Clipper for VV, UCP, VTX_KILL, VTX_NAN hyPERF_PAPC_CLPR_VVUCP_CULL_PRIM: PERF_PAPC_CLPR_VVUCP_CULL_PRIM Number of Prims Culled by Clipper for VV and UCP `nPERF_PAPC_CLPR_VV_CULL_PRIM: PERF_PAPC_CLPR_VV_CULL_PRIM Number of Prims Culled by Clipper for VV XpPERF_PAPC_CLPR_UCP_CULL_PRIM: PERF_PAPC_CLPR_UCP_CULL_PRIM Number of Prims Culled by Clipper for UCP XzPERF_PAPC_CLPR_VTX_KILL_CULL_PRIM: PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM Number of Prims Culled by Clipper for VTX_KILL XxPERF_PAPC_CLPR_VTX_NAN_CULL_PRIM: PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM Number of Prims Culled by Clipper for VTX_NAN `PERF_PAPC_CLPR_CULL_TO_NULL_PRIM: PERF_PAPC_CLPR_CULL_TO_NULL_PRIM Number of Clipper Culled Prims Retained for Pipe Info h}PERF_PAPC_CLPR_VVUCP_CLIP_PRIM: PERF_PAPC_CLPR_VVUCP_CLIP_PRIM Number of Prims Clipped by Clipper for VV and/or UCP ` oPERF_PAPC_CLPR_VV_CLIP_PRIM: PERF_PAPC_CLPR_VV_CLIP_PRIM Number of Prims Clipped by Clipper for VV X qPERF_PAPC_CLPR_UCP_CLIP_PRIM: PERF_PAPC_CLPR_UCP_CLIP_PRIM Number of Prims Clipped by Clipper for UCP ` PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE: PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE Number of Points which require detailed clip checked x PERF_PAPC_CLPR_CLIP_PLANE_CNT_1: PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 Number of Prims with 1 Clip Plane Intersection (includes VV and UCP) PERF_PAPC_CLPR_CLIP_PLANE_CNT_2: PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 Number of Prims with 2 Clip Plane Intersections (includes VV and UCP)  PERF_PAPC_CLPR_CLIP_PLANE_CNT_3: PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 Number of Prims with 3 Clip Plane Intersections (includes VV and UCP) PERF_PAPC_CLPR_CLIP_PLANE_CNT_4: PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 Number of Prims with 4 Clip Plane Intersections (includes VV and UCP) PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8: PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 Number of Prims with 5-8 Clip Plane Intersections (includes VV and UCP)  PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12: PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 Number of Prims with 9-12 Clip Plane Intersections (includes VV and UCP) @|PERF_PAPC_CLPR_CLIP_PLANE_NEAR: PERF_PAPC_CLPR_CLIP_PLANE_NEAR Number of Prims which intersect the NEAR VV Plane @ {PERF_PAPC_CLPR_CLIP_PLANE_FAR: PERF_PAPC_CLPR_CLIP_PLANE_FAR Number of Prims which intersect the FAR VV Plane @!|PERF_PAPC_CLPR_CLIP_PLANE_LEFT: PERF_PAPC_CLPR_CLIP_PLANE_LEFT Number of Prims which intersect the LEFT VV Plane @"}PERF_PAPC_CLPR_CLIP_PLANE_RIGHT: PERF_PAPC_CLPR_CLIP_PLANE_RIGHT Number of Prims which intersect the RIGHT VV Plane H#{PERF_PAPC_CLPR_CLIP_PLANE_TOP: PERF_PAPC_CLPR_CLIP_PLANE_TOP Number of Prims which intersect the TOP VV Plane H$~PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM: PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM Number of Prims which intersect the BOTTOM VV Plane P%PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM: PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM Number of Prims Culled by Clipper for Geometry Shader Scenario C Cuts @h&PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM: PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM Number of Prims Culled by Clipper for DX10 Rasterization Kill (null PS) H'}PERF_PAPC_CLSM_NULL_PRIM: PERF_PAPC_CLSM_NULL_PRIM Number of null primitives at Clip State Machine pipe stage H({PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM: PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM Number of totally visible (no-clipping) prims P)PERF_PAPC_CLSM_CULL_TO_NULL_PRIM: PERF_PAPC_CLSM_CULL_TO_NULL_PRIM Number of primitives which are culled during clip process `*PERF_PAPC_CLSM_OUT_PRIM_CNT_1: PERF_PAPC_CLSM_OUT_PRIM_CNT_1 Number of primitives which were clipped and result in 1 primitive p+PERF_PAPC_CLSM_OUT_PRIM_CNT_2: PERF_PAPC_CLSM_OUT_PRIM_CNT_2 Number of primitives which were clipped and result in 2 primitives ,PERF_PAPC_CLSM_OUT_PRIM_CNT_3: PERF_PAPC_CLSM_OUT_PRIM_CNT_3 Number of primitives which were clipped and result in 3 primitives ! -PERF_PAPC_CLSM_OUT_PRIM_CNT_4: PERF_PAPC_CLSM_OUT_PRIM_CNT_4 Number of primitives which were clipped and result in 4 primitives "!.PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8: PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 Number of primitives which were clipped and result in 5-8 primitives #"/PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13: PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 Number of primitives which were clipped and result in 9-13 primitives $$0PERF_PAPC_CLIPGA_VTE_KILL_PRIM: PERF_PAPC_CLIPGA_VTE_KILL_PRIM Number of primitives which are culled by VTE nan/inf logic %%1oPERF_PAPC_SU_INPUT_PRIM: PERF_PAPC_SU_INPUT_PRIM Number of primitives input to the Setup block &&2|PERF_PAPC_SU_INPUT_CLIP_PRIM: PERF_PAPC_SU_INPUT_CLIP_PRIM Number of clipped primitives input to the Setup block ''3yPERF_PAPC_SU_INPUT_NULL_PRIM: PERF_PAPC_SU_INPUT_NULL_PRIM Number of null primitives input to the Setup block ((4PERF_PAPC_SU_INPUT_PRIM_DUAL: PERF_PAPC_SU_INPUT_PRIM_DUAL Number of dual gradient primitives input to the Setup block ))5PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL: PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL Number of dual gradient clipped primitives input to the Setup block *(*6wPERF_PAPC_SU_ZERO_AREA_CULL_PRIM: PERF_PAPC_SU_ZERO_AREA_CULL_PRIM Number of primitives culled due to zero area +(+7PERF_PAPC_SU_BACK_FACE_CULL_PRIM: PERF_PAPC_SU_BACK_FACE_CULL_PRIM Number of back-face primitives culled due to facedness ,0,8PERF_PAPC_SU_FRONT_FACE_CULL_PRIM: PERF_PAPC_SU_FRONT_FACE_CULL_PRIM Number of front-face primitives culled due to facedness -8-9PERF_PAPC_SU_POLYMODE_FACE_CULL: PERF_PAPC_SU_POLYMODE_FACE_CULL Number of polymode cull-determination primitives culled /@.:PERF_PAPC_SU_POLYMODE_BACK_CULL: PERF_PAPC_SU_POLYMODE_BACK_CULL Number of polymode primitives discarded due to Back-Face Cull 0P/;PERF_PAPC_SU_POLYMODE_FRONT_CULL: PERF_PAPC_SU_POLYMODE_FRONT_CULL Number of polymode primitives discarded due to Front-Face Cull P1`0<PERF_PAPC_SU_POLYMODE_INVALID_FILL: PERF_PAPC_SU_POLYMODE_INVALID_FILL Number of polymode lines and/or points which are culled because they are an internal edge or point H21=sPERF_PAPC_SU_OUTPUT_PRIM: PERF_PAPC_SU_OUTPUT_PRIM Number of primitives output from the Setup block P32>PERF_PAPC_SU_OUTPUT_CLIP_PRIM: PERF_PAPC_SU_OUTPUT_CLIP_PRIM Number of clipped primitives output from the Setup block X43?}PERF_PAPC_SU_OUTPUT_NULL_PRIM: PERF_PAPC_SU_OUTPUT_NULL_PRIM Number of null primitives output from the Setup block X54@uPERF_PAPC_SU_OUTPUT_EVENT_FLAG: PERF_PAPC_SU_OUTPUT_EVENT_FLAG Number of events output from the Setup block h65APERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT: PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT Number of First-Prim-Of-Slots output from the Setup block p76BPERF_PAPC_SU_OUTPUT_END_OF_PACKET: PERF_PAPC_SU_OUTPUT_END_OF_PACKET Number of End-Of-Packets output from the Setup block 87CPERF_PAPC_SU_OUTPUT_POLYMODE_FACE: PERF_PAPC_SU_OUTPUT_POLYMODE_FACE Number of polymode facing primitives output from the Setup block 98DPERF_PAPC_SU_OUTPUT_POLYMODE_BACK: PERF_PAPC_SU_OUTPUT_POLYMODE_BACK Number of polymode back-face primitives output from the Setup block :9EPERF_PAPC_SU_OUTPUT_POLYMODE_FRONT: PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT Number of polymode front-face primitives output from the Setup block ;:FPERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE: PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE Number of clipped polymode facing primitives output from the Setup block <<GPERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK: PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK Number of clipped polymode back-face primitives output from the Setup block >8=HPERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT: PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT Number of clipped polymode front-face primitives output from the Setup block ?X>IPERF_PAPC_SU_OUTPUT_PRIM_DUAL: PERF_PAPC_SU_OUTPUT_PRIM_DUAL Number of dual gradient primitives output from the Setup block 8@h?JPERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL: PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL Number of dual gradient clipped primitives output from the Setup block PA@KPERF_PAPC_SU_OUTPUT_POLYMODE_DUAL: PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL Number of dual gradient polymode primitives output from the Setup block xBALPERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL: PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL Number of dual gradient clip polymode primitives output from the Setup block hCBMiPERF_PAPC_PASX_REQ_IDLE: PERF_PAPC_PASX_REQ_IDLE Number of clocks PASX Requestor is Idle XDCNiPERF_PAPC_PASX_REQ_BUSY: PERF_PAPC_PASX_REQ_BUSY Number of clocks PASX Requestor is Busy PEDOoPERF_PAPC_PASX_REQ_STALLED: PERF_PAPC_PASX_REQ_STALLED Number of clocks PASX Requestor is Stalled @FEPhPERF_PAPC_PASX_REC_IDLE: PERF_PAPC_PASX_REC_IDLE Number of clocks PASX Receiver is Idle 0GFQhPERF_PAPC_PASX_REC_BUSY: PERF_PAPC_PASX_REC_BUSY Number of clocks PASX Receiver is Busy 0HxGRwPERF_PAPC_PASX_REC_STARVED_SX: PERF_PAPC_PASX_REC_STARVED_SX Number of clocks PASX Receiver is Stalled by SX PIxHSPERF_PAPC_PASX_REC_STALLED: PERF_PAPC_PASX_REC_STALLED Number of clocks PASX Reciever is Stalled by Position Memory or Clip Code Generator `JITPERF_PAPC_PASX_REC_STALLED_POS_MEM: PERF_PAPC_PASX_REC_STALLED_POS_MEM Number of clocks PASX Reciever is Stalled by Position Memory xKJUPERF_PAPC_PASX_REC_STALLED_CCGSM_IN: PERF_PAPC_PASX_REC_STALLED_CCGSM_IN Number of clocks PASX Reciever is Stalled by Clip Code Generator hLKVePERF_PAPC_CCGSM_IDLE: PERF_PAPC_CCGSM_IDLE Number of clocks Clip Code Gen is Idle XMLWePERF_PAPC_CCGSM_BUSY: PERF_PAPC_CCGSM_BUSY Number of clocks Clip Code Gen is Busy HNMXkPERF_PAPC_CCGSM_STALLED: PERF_PAPC_CCGSM_STALLED Number of clocks Clip Code Gen is Stalled @ONYoPERF_PAPC_CLPRIM_IDLE: PERF_PAPC_CLPRIM_IDLE Number of clocks Clip Primitive Machine is Idle 8POZoPERF_PAPC_CLPRIM_BUSY: PERF_PAPC_CLPRIM_BUSY Number of clocks Clip Primitive Machine is Busy HQP[PERF_PAPC_CLPRIM_STALLED: PERF_PAPC_CLPRIM_STALLED Number of clocks Clip Primitive Machine is stalled by Clip State Machines `RQ\PERF_PAPC_CLPRIM_STARVED_CCGSM: PERF_PAPC_CLPRIM_STARVED_CCGSM Number of clocks Clip Primitive Machine is starved by Clip Code Generator XSR]mPERF_PAPC_CLIPSM_IDLE: PERF_PAPC_CLIPSM_IDLE Number of clocks Clip State Machines are Idle PTS^mPERF_PAPC_CLIPSM_BUSY: PERF_PAPC_CLIPSM_BUSY Number of clocks Clip State Machines are Busy xUT_PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH: PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH Number of clocks Clip State Mahcines are waiting for Clip Vert storage resources VU`PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ: PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ Number of clocks Clip State Machines are waiting for High Priority Sequencer WVaPERF_PAPC_CLIPSM_WAIT_CLIPGA: PERF_PAPC_CLIPSM_WAIT_CLIPGA Number of clocks Clip State Machines are waiting for ClipGA XWbPERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP: PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP Number of clocks Clip State Machines are waiting for VTE cycles YYcPERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM: PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM Number of clocks Clip State Machines are waiting for Clip Output State Machine Z Zd`PERF_PAPC_CLIPGA_IDLE: PERF_PAPC_CLIPGA_IDLE Number of clocks Clip Ga is Idle [[e`PERF_PAPC_CLIPGA_BUSY: PERF_PAPC_CLIPGA_BUSY Number of clocks Clip Ga is Busy \[fPERF_PAPC_CLIPGA_STARVED_VTE_CLIP: PERF_PAPC_CLIPGA_STARVED_VTE_CLIP Number of clocks Clip Ga is Starved by VTE or Clipper ]\gfPERF_PAPC_CLIPGA_STALLED: PERF_PAPC_CLIPGA_STALLED Number of clocks Clip Ga is stalled ^]h[PERF_PAPC_CLIP_IDLE: PERF_PAPC_CLIP_IDLE Number of clocks Clip is Idle `_^i[PERF_PAPC_CLIP_BUSY: PERF_PAPC_CLIP_BUSY Number of clocks Clip is Busy @`_jZPERF_PAPC_SU_IDLE: PERF_PAPC_SU_IDLE Number of clocks Setup is Idle a`kZPERF_PAPC_SU_BUSY: PERF_PAPC_SU_BUSY Number of clocks Setup is Busy bhalpPERF_PAPC_SU_STARVED_CLIP: PERF_PAPC_SU_STARVED_CLIP Number of clocks Setup is starved by Clipper c`bmiPERF_PAPC_SU_STALLED_SC: PERF_PAPC_SU_STALLED_SC Number of clocks Setup is stalled by SC dPcnsPERF_PAPC_PA_DYN_SCLK_VLD: PERF_PAPC_PA_DYN_SCLK_VLD Number of clocks the PA dynamic clock is active HdotPERF_PAPC_PA_REG_SCLK_VLD: PERF_PAPC_PA_REG_SCLK_VLD Number of clocks the PA register clock is active ( 8~$$"" ~PA_SU_PERFCOUNTER1_SELECT~0 PERF_SELpxVPERF_PAPC_PASX_REQ: PERF_PAPC_PASX_REQ Number of PA->SX requests XsPERF_PAPC_PASX_DISABLE_PIPE: PERF_PAPC_PASX_DISABLE_PIPE Number of transfers lost due to disabled pipe PkPERF_PAPC_PASX_FIRST_VECTOR: PERF_PAPC_PASX_FIRST_VECTOR Number of First Vectors from SX to PA @mPERF_PAPC_PASX_SECOND_VECTOR: PERF_PAPC_PASX_SECOND_VECTOR Number of Second Vectors from SX to PA 8|PERF_PAPC_PASX_FIRST_DEAD: PERF_PAPC_PASX_FIRST_DEAD Number of Unused First Vectors (due to granularity of 4) 8~PERF_PAPC_PASX_SECOND_DEAD: PERF_PAPC_PASX_SECOND_DEAD Number of Unused Second Vectors (due to granularity of 4) @PERF_PAPC_PASX_VTX_KILL_DISCARD: PERF_PAPC_PASX_VTX_KILL_DISCARD Number of vertices which have VTX KILL Enabled and Set HPERF_PAPC_PASX_VTX_NAN_DISCARD: PERF_PAPC_PASX_VTX_NAN_DISCARD Number of vertices which have NaN and corresponding NaN discard XbPERF_PAPC_PA_INPUT_PRIM: PERF_PAPC_PA_INPUT_PRIM Number of Primitives input to PA 舔@ lPERF_PAPC_PA_INPUT_NULL_PRIM: PERF_PAPC_PA_INPUT_NULL_PRIM Number of Null Primitives input to PA Љ0 dPERF_PAPC_PA_INPUT_EVENT_FLAG: PERF_PAPC_PA_INPUT_EVENT_FLAG Number of Events input to PA Њ vPERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT: PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT Number of First-Prim-Of-Slots input to PA ȋ oPERF_PAPC_PA_INPUT_END_OF_PACKET: PERF_PAPC_PA_INPUT_END_OF_PACKET Number of End-Of-Packets input to PA  qPERF_PAPC_PA_INPUT_EXTENDED_EVENT: PERF_PAPC_PA_INPUT_EXTENDED_EVENT Number of Extended Events input to PA ȍPERF_PAPC_CLPR_CULL_PRIM: PERF_PAPC_CLPR_CULL_PRIM Number of Prims Culled by Clipper for VV, UCP, VTX_KILL, VTX_NAN ȎyPERF_PAPC_CLPR_VVUCP_CULL_PRIM: PERF_PAPC_CLPR_VVUCP_CULL_PRIM Number of Prims Culled by Clipper for VV and UCP nPERF_PAPC_CLPR_VV_CULL_PRIM: PERF_PAPC_CLPR_VV_CULL_PRIM Number of Prims Culled by Clipper for VV pPERF_PAPC_CLPR_UCP_CULL_PRIM: PERF_PAPC_CLPR_UCP_CULL_PRIM Number of Prims Culled by Clipper for UCP zPERF_PAPC_CLPR_VTX_KILL_CULL_PRIM: PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM Number of Prims Culled by Clipper for VTX_KILL xPERF_PAPC_CLPR_VTX_NAN_CULL_PRIM: PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM Number of Prims Culled by Clipper for VTX_NAN PERF_PAPC_CLPR_CULL_TO_NULL_PRIM: PERF_PAPC_CLPR_CULL_TO_NULL_PRIM Number of Clipper Culled Prims Retained for Pipe Info Ȕ}PERF_PAPC_CLPR_VVUCP_CLIP_PRIM: PERF_PAPC_CLPR_VVUCP_CLIP_PRIM Number of Prims Clipped by Clipper for VV and/or UCP oPERF_PAPC_CLPR_VV_CLIP_PRIM: PERF_PAPC_CLPR_VV_CLIP_PRIM Number of Prims Clipped by Clipper for VV qPERF_PAPC_CLPR_UCP_CLIP_PRIM: PERF_PAPC_CLPR_UCP_CLIP_PRIM Number of Prims Clipped by Clipper for UCP PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE: PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE Number of Points which require detailed clip checked ؘPERF_PAPC_CLPR_CLIP_PLANE_CNT_1: PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 Number of Prims with 1 Clip Plane Intersection (includes VV and UCP) PERF_PAPC_CLPR_CLIP_PLANE_CNT_2: PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 Number of Prims with 2 Clip Plane Intersections (includes VV and UCP) 8PERF_PAPC_CLPR_CLIP_PLANE_CNT_3: PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 Number of Prims with 3 Clip Plane Intersections (includes VV and UCP) PPERF_PAPC_CLPR_CLIP_PLANE_CNT_4: PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 Number of Prims with 4 Clip Plane Intersections (includes VV and UCP) 8hPERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8: PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 Number of Prims with 5-8 Clip Plane Intersections (includes VV and UCP) XPERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12: PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 Number of Prims with 9-12 Clip Plane Intersections (includes VV and UCP) X|PERF_PAPC_CLPR_CLIP_PLANE_NEAR: PERF_PAPC_CLPR_CLIP_PLANE_NEAR Number of Prims which intersect the NEAR VV Plane X {PERF_PAPC_CLPR_CLIP_PLANE_FAR: PERF_PAPC_CLPR_CLIP_PLANE_FAR Number of Prims which intersect the FAR VV Plane X!|PERF_PAPC_CLPR_CLIP_PLANE_LEFT: PERF_PAPC_CLPR_CLIP_PLANE_LEFT Number of Prims which intersect the LEFT VV Plane `"}PERF_PAPC_CLPR_CLIP_PLANE_RIGHT: PERF_PAPC_CLPR_CLIP_PLANE_RIGHT Number of Prims which intersect the RIGHT VV Plane `#{PERF_PAPC_CLPR_CLIP_PLANE_TOP: PERF_PAPC_CLPR_CLIP_PLANE_TOP Number of Prims which intersect the TOP VV Plane h$~PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM: PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM Number of Prims which intersect the BOTTOM VV Plane %PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM: PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM Number of Prims Culled by Clipper for Geometry Shader Scenario C Cuts ȥ&PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM: PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM Number of Prims Culled by Clipper for DX10 Rasterization Kill (null PS) 覔'}PERF_PAPC_CLSM_NULL_PRIM: PERF_PAPC_CLSM_NULL_PRIM Number of null primitives at Clip State Machine pipe stage ({PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM: PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM Number of totally visible (no-clipping) prims )PERF_PAPC_CLSM_CULL_TO_NULL_PRIM: PERF_PAPC_CLSM_CULL_TO_NULL_PRIM Number of primitives which are culled during clip process *PERF_PAPC_CLSM_OUT_PRIM_CNT_1: PERF_PAPC_CLSM_OUT_PRIM_CNT_1 Number of primitives which were clipped and result in 1 primitive Ы+PERF_PAPC_CLSM_OUT_PRIM_CNT_2: PERF_PAPC_CLSM_OUT_PRIM_CNT_2 Number of primitives which were clipped and result in 2 primitives ଔ,PERF_PAPC_CLSM_OUT_PRIM_CNT_3: PERF_PAPC_CLSM_OUT_PRIM_CNT_3 Number of primitives which were clipped and result in 3 primitives (-PERF_PAPC_CLSM_OUT_PRIM_CNT_4: PERF_PAPC_CLSM_OUT_PRIM_CNT_4 Number of primitives which were clipped and result in 4 primitives 8.PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8: PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 Number of primitives which were clipped and result in 5-8 primitives P/PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13: PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 Number of primitives which were clipped and result in 9-13 primitives (h0PERF_PAPC_CLIPGA_VTE_KILL_PRIM: PERF_PAPC_CLIPGA_VTE_KILL_PRIM Number of primitives which are culled by VTE nan/inf logic p1oPERF_PAPC_SU_INPUT_PRIM: PERF_PAPC_SU_INPUT_PRIM Number of primitives input to the Setup block h2|PERF_PAPC_SU_INPUT_CLIP_PRIM: PERF_PAPC_SU_INPUT_CLIP_PRIM Number of clipped primitives input to the Setup block h3yPERF_PAPC_SU_INPUT_NULL_PRIM: PERF_PAPC_SU_INPUT_NULL_PRIM Number of null primitives input to the Setup block (h4PERF_PAPC_SU_INPUT_PRIM_DUAL: PERF_PAPC_SU_INPUT_PRIM_DUAL Number of dual gradient primitives input to the Setup block @p5PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL: PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL Number of dual gradient clipped primitives input to the Setup block @6wPERF_PAPC_SU_ZERO_AREA_CULL_PRIM: PERF_PAPC_SU_ZERO_AREA_CULL_PRIM Number of primitives culled due to zero area H7PERF_PAPC_SU_BACK_FACE_CULL_PRIM: PERF_PAPC_SU_BACK_FACE_CULL_PRIM Number of back-face primitives culled due to facedness P8PERF_PAPC_SU_FRONT_FACE_CULL_PRIM: PERF_PAPC_SU_FRONT_FACE_CULL_PRIM Number of front-face primitives culled due to facedness X9PERF_PAPC_SU_POLYMODE_FACE_CULL: PERF_PAPC_SU_POLYMODE_FACE_CULL Number of polymode cull-determination primitives culled h:PERF_PAPC_SU_POLYMODE_BACK_CULL: PERF_PAPC_SU_POLYMODE_BACK_CULL Number of polymode primitives discarded due to Back-Face Cull x;PERF_PAPC_SU_POLYMODE_FRONT_CULL: PERF_PAPC_SU_POLYMODE_FRONT_CULL Number of polymode primitives discarded due to Front-Face Cull <PERF_PAPC_SU_POLYMODE_INVALID_FILL: PERF_PAPC_SU_POLYMODE_INVALID_FILL Number of polymode lines and/or points which are culled because they are an internal edge or point =sPERF_PAPC_SU_OUTPUT_PRIM: PERF_PAPC_SU_OUTPUT_PRIM Number of primitives output from the Setup block >PERF_PAPC_SU_OUTPUT_CLIP_PRIM: PERF_PAPC_SU_OUTPUT_CLIP_PRIM Number of clipped primitives output from the Setup block ?}PERF_PAPC_SU_OUTPUT_NULL_PRIM: PERF_PAPC_SU_OUTPUT_NULL_PRIM Number of null primitives output from the Setup block @uPERF_PAPC_SU_OUTPUT_EVENT_FLAG: PERF_PAPC_SU_OUTPUT_EVENT_FLAG Number of events output from the Setup block ””APERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT: PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT Number of First-Prim-Of-Slots output from the Setup block ÔÔBPERF_PAPC_SU_OUTPUT_END_OF_PACKET: PERF_PAPC_SU_OUTPUT_END_OF_PACKET Number of End-Of-Packets output from the Setup block ĔĔCPERF_PAPC_SU_OUTPUT_POLYMODE_FACE: PERF_PAPC_SU_OUTPUT_POLYMODE_FACE Number of polymode facing primitives output from the Setup block Ŕ(ŔDPERF_PAPC_SU_OUTPUT_POLYMODE_BACK: PERF_PAPC_SU_OUTPUT_POLYMODE_BACK Number of polymode back-face primitives output from the Setup block ǔ@ƔEPERF_PAPC_SU_OUTPUT_POLYMODE_FRONT: PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT Number of polymode front-face primitives output from the Setup block 0ȔXǔFPERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE: PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE Number of clipped polymode facing primitives output from the Setup block PɔxȔGPERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK: PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK Number of clipped polymode back-face primitives output from the Setup block pʔɔHPERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT: PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT Number of clipped polymode front-face primitives output from the Setup block ˔ʔIPERF_PAPC_SU_OUTPUT_PRIM_DUAL: PERF_PAPC_SU_OUTPUT_PRIM_DUAL Number of dual gradient primitives output from the Setup block ̔˔JPERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL: PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL Number of dual gradient clipped primitives output from the Setup block ͔̔KPERF_PAPC_SU_OUTPUT_POLYMODE_DUAL: PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL Number of dual gradient polymode primitives output from the Setup block Δ͔LPERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL: PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL Number of dual gradient clip polymode primitives output from the Setup block ϔ ϔMiPERF_PAPC_PASX_REQ_IDLE: PERF_PAPC_PASX_REQ_IDLE Number of clocks PASX Requestor is Idle ДДNiPERF_PAPC_PASX_REQ_BUSY: PERF_PAPC_PASX_REQ_BUSY Number of clocks PASX Requestor is Busy єєOoPERF_PAPC_PASX_REQ_STALLED: PERF_PAPC_PASX_REQ_STALLED Number of clocks PASX Requestor is Stalled ҔєPhPERF_PAPC_PASX_REC_IDLE: PERF_PAPC_PASX_REC_IDLE Number of clocks PASX Receiver is Idle ӔҔQhPERF_PAPC_PASX_REC_BUSY: PERF_PAPC_PASX_REC_BUSY Number of clocks PASX Receiver is Busy ԔӔRwPERF_PAPC_PASX_REC_STARVED_SX: PERF_PAPC_PASX_REC_STARVED_SX Number of clocks PASX Receiver is Stalled by SX ՔԔSPERF_PAPC_PASX_REC_STALLED: PERF_PAPC_PASX_REC_STALLED Number of clocks PASX Reciever is Stalled by Position Memory or Clip Code Generator ֔ՔTPERF_PAPC_PASX_REC_STALLED_POS_MEM: PERF_PAPC_PASX_REC_STALLED_POS_MEM Number of clocks PASX Reciever is Stalled by Position Memory ההUPERF_PAPC_PASX_REC_STALLED_CCGSM_IN: PERF_PAPC_PASX_REC_STALLED_CCGSM_IN Number of clocks PASX Reciever is Stalled by Clip Code Generator ؔ ؔVePERF_PAPC_CCGSM_IDLE: PERF_PAPC_CCGSM_IDLE Number of clocks Clip Code Gen is Idle ٔٔWePERF_PAPC_CCGSM_BUSY: PERF_PAPC_CCGSM_BUSY Number of clocks Clip Code Gen is Busy ڔڔXkPERF_PAPC_CCGSM_STALLED: PERF_PAPC_CCGSM_STALLED Number of clocks Clip Code Gen is Stalled ۔ڔYoPERF_PAPC_CLPRIM_IDLE: PERF_PAPC_CLPRIM_IDLE Number of clocks Clip Primitive Machine is Idle ܔ۔ZoPERF_PAPC_CLPRIM_BUSY: PERF_PAPC_CLPRIM_BUSY Number of clocks Clip Primitive Machine is Busy ݔܔ[PERF_PAPC_CLPRIM_STALLED: PERF_PAPC_CLPRIM_STALLED Number of clocks Clip Primitive Machine is stalled by Clip State Machines ޔݔ\PERF_PAPC_CLPRIM_STARVED_CCGSM: PERF_PAPC_CLPRIM_STARVED_CCGSM Number of clocks Clip Primitive Machine is starved by Clip Code Generator ߔߔ]mPERF_PAPC_CLIPSM_IDLE: PERF_PAPC_CLIPSM_IDLE Number of clocks Clip State Machines are Idle ^mPERF_PAPC_CLIPSM_BUSY: PERF_PAPC_CLIPSM_BUSY Number of clocks Clip State Machines are Busy _PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH: PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH Number of clocks Clip State Mahcines are waiting for Clip Vert storage resources (`PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ: PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ Number of clocks Clip State Machines are waiting for High Priority Sequencer HaPERF_PAPC_CLIPSM_WAIT_CLIPGA: PERF_PAPC_CLIPSM_WAIT_CLIPGA Number of clocks Clip State Machines are waiting for ClipGA PbPERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP: PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP Number of clocks Clip State Machines are waiting for VTE cycles @hcPERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM: PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM Number of clocks Clip State Machines are waiting for Clip Output State Machine (d`PERF_PAPC_CLIPGA_IDLE: PERF_PAPC_CLIPGA_IDLE Number of clocks Clip Ga is Idle pe`PERF_PAPC_CLIPGA_BUSY: PERF_PAPC_CLIPGA_BUSY Number of clocks Clip Ga is Busy XfPERF_PAPC_CLIPGA_STARVED_VTE_CLIP: PERF_PAPC_CLIPGA_STARVED_VTE_CLIP Number of clocks Clip Ga is Starved by VTE or Clipper `gfPERF_PAPC_CLIPGA_STALLED: PERF_PAPC_CLIPGA_STALLED Number of clocks Clip Ga is stalled Ph[PERF_PAPC_CLIP_IDLE: PERF_PAPC_CLIP_IDLE Number of clocks Clip is Idle 0i[PERF_PAPC_CLIP_BUSY: PERF_PAPC_CLIP_BUSY Number of clocks Clip is Busy jZPERF_PAPC_SU_IDLE: PERF_PAPC_SU_IDLE Number of clocks Setup is Idle kZPERF_PAPC_SU_BUSY: PERF_PAPC_SU_BUSY Number of clocks Setup is Busy lpPERF_PAPC_SU_STARVED_CLIP: PERF_PAPC_SU_STARVED_CLIP Number of clocks Setup is starved by Clipper pmiPERF_PAPC_SU_STALLED_SC: PERF_PAPC_SU_STALLED_SC Number of clocks Setup is stalled by SC hnsPERF_PAPC_PA_DYN_SCLK_VLD: PERF_PAPC_PA_DYN_SCLK_VLD Number of clocks the PA dynamic clock is active otPERF_PAPC_PA_REG_SCLK_VLD: PERF_PAPC_PA_REG_SCLK_VLD Number of clocks the PA register clock is active   "" PA_SU_PERFCOUNTER0_SELECTP  PERF_SELpx VPERF_PAPC_PASX_REQ: PERF_PAPC_PASX_REQ Number of PA->SX requests p sPERF_PAPC_PASX_DISABLE_PIPE: PERF_PAPC_PASX_DISABLE_PIPE Number of transfers lost due to disabled pipe ` kPERF_PAPC_PASX_FIRST_VECTOR: PERF_PAPC_PASX_FIRST_VECTOR Number of First Vectors from SX to PA XmPERF_PAPC_PASX_SECOND_VECTOR: PERF_PAPC_PASX_SECOND_VECTOR Number of Second Vectors from SX to PA X|PERF_PAPC_PASX_FIRST_DEAD: PERF_PAPC_PASX_FIRST_DEAD Number of Unused First Vectors (due to granularity of 4) `~PERF_PAPC_PASX_SECOND_DEAD: PERF_PAPC_PASX_SECOND_DEAD Number of Unused Second Vectors (due to granularity of 4) hPERF_PAPC_PASX_VTX_KILL_DISCARD: PERF_PAPC_PASX_VTX_KILL_DISCARD Number of vertices which have VTX KILL Enabled and Set xPERF_PAPC_PASX_VTX_NAN_DISCARD: PERF_PAPC_PASX_VTX_NAN_DISCARD Number of vertices which have NaN and corresponding NaN discard `bPERF_PAPC_PA_INPUT_PRIM: PERF_PAPC_PA_INPUT_PRIM Number of Primitives input to PA P lPERF_PAPC_PA_INPUT_NULL_PRIM: PERF_PAPC_PA_INPUT_NULL_PRIM Number of Null Primitives input to PA 8 dPERF_PAPC_PA_INPUT_EVENT_FLAG: PERF_PAPC_PA_INPUT_EVENT_FLAG Number of Events input to PA 8 vPERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT: PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT Number of First-Prim-Of-Slots input to PA 0 oPERF_PAPC_PA_INPUT_END_OF_PACKET: PERF_PAPC_PA_INPUT_END_OF_PACKET Number of End-Of-Packets input to PA (x qPERF_PAPC_PA_INPUT_EXTENDED_EVENT: PERF_PAPC_PA_INPUT_EXTENDED_EVENT Number of Extended Events input to PA 0pPERF_PAPC_CLPR_CULL_PRIM: PERF_PAPC_CLPR_CULL_PRIM Number of Prims Culled by Clipper for VV, UCP, VTX_KILL, VTX_NAN 0xyPERF_PAPC_CLPR_VVUCP_CULL_PRIM: PERF_PAPC_CLPR_VVUCP_CULL_PRIM Number of Prims Culled by Clipper for VV and UCP (xnPERF_PAPC_CLPR_VV_CULL_PRIM: PERF_PAPC_CLPR_VV_CULL_PRIM Number of Prims Culled by Clipper for VV ppPERF_PAPC_CLPR_UCP_CULL_PRIM: PERF_PAPC_CLPR_UCP_CULL_PRIM Number of Prims Culled by Clipper for UCP hzPERF_PAPC_CLPR_VTX_KILL_CULL_PRIM: PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM Number of Prims Culled by Clipper for VTX_KILL hxPERF_PAPC_CLPR_VTX_NAN_CULL_PRIM: PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM Number of Prims Culled by Clipper for VTX_NAN ( hPERF_PAPC_CLPR_CULL_TO_NULL_PRIM: PERF_PAPC_CLPR_CULL_TO_NULL_PRIM Number of Clipper Culled Prims Retained for Pipe Info 0!p }PERF_PAPC_CLPR_VVUCP_CLIP_PRIM: PERF_PAPC_CLPR_VVUCP_CLIP_PRIM Number of Prims Clipped by Clipper for VV and/or UCP ("x!oPERF_PAPC_CLPR_VV_CLIP_PRIM: PERF_PAPC_CLPR_VV_CLIP_PRIM Number of Prims Clipped by Clipper for VV #p"qPERF_PAPC_CLPR_UCP_CLIP_PRIM: PERF_PAPC_CLPR_UCP_CLIP_PRIM Number of Prims Clipped by Clipper for UCP ($h#PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE: PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE Number of Points which require detailed clip checked @%p$PERF_PAPC_CLPR_CLIP_PLANE_CNT_1: PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 Number of Prims with 1 Clip Plane Intersection (includes VV and UCP) X&%PERF_PAPC_CLPR_CLIP_PLANE_CNT_2: PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 Number of Prims with 2 Clip Plane Intersections (includes VV and UCP) p'&PERF_PAPC_CLPR_CLIP_PLANE_CNT_3: PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 Number of Prims with 3 Clip Plane Intersections (includes VV and UCP) ('PERF_PAPC_CLPR_CLIP_PLANE_CNT_4: PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 Number of Prims with 4 Clip Plane Intersections (includes VV and UCP) )(PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8: PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 Number of Prims with 5-8 Clip Plane Intersections (includes VV and UCP) *)PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12: PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 Number of Prims with 9-12 Clip Plane Intersections (includes VV and UCP) ++|PERF_PAPC_CLPR_CLIP_PLANE_NEAR: PERF_PAPC_CLPR_CLIP_PLANE_NEAR Number of Prims which intersect the NEAR VV Plane ,, {PERF_PAPC_CLPR_CLIP_PLANE_FAR: PERF_PAPC_CLPR_CLIP_PLANE_FAR Number of Prims which intersect the FAR VV Plane --!|PERF_PAPC_CLPR_CLIP_PLANE_LEFT: PERF_PAPC_CLPR_CLIP_PLANE_LEFT Number of Prims which intersect the LEFT VV Plane .."}PERF_PAPC_CLPR_CLIP_PLANE_RIGHT: PERF_PAPC_CLPR_CLIP_PLANE_RIGHT Number of Prims which intersect the RIGHT VV Plane //#{PERF_PAPC_CLPR_CLIP_PLANE_TOP: PERF_PAPC_CLPR_CLIP_PLANE_TOP Number of Prims which intersect the TOP VV Plane 00$~PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM: PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM Number of Prims which intersect the BOTTOM VV Plane 11%PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM: PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM Number of Prims Culled by Clipper for Geometry Shader Scenario C Cuts 302&PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM: PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM Number of Prims Culled by Clipper for DX10 Rasterization Kill (null PS) 4P3'}PERF_PAPC_CLSM_NULL_PRIM: PERF_PAPC_CLSM_NULL_PRIM Number of null primitives at Clip State Machine pipe stage 5X4({PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM: PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM Number of totally visible (no-clipping) prims 6X5)PERF_PAPC_CLSM_CULL_TO_NULL_PRIM: PERF_PAPC_CLSM_CULL_TO_NULL_PRIM Number of primitives which are culled during clip process (7`6*PERF_PAPC_CLSM_OUT_PRIM_CNT_1: PERF_PAPC_CLSM_OUT_PRIM_CNT_1 Number of primitives which were clipped and result in 1 primitive 88p7+PERF_PAPC_CLSM_OUT_PRIM_CNT_2: PERF_PAPC_CLSM_OUT_PRIM_CNT_2 Number of primitives which were clipped and result in 2 primitives H98,PERF_PAPC_CLSM_OUT_PRIM_CNT_3: PERF_PAPC_CLSM_OUT_PRIM_CNT_3 Number of primitives which were clipped and result in 3 primitives X:9-PERF_PAPC_CLSM_OUT_PRIM_CNT_4: PERF_PAPC_CLSM_OUT_PRIM_CNT_4 Number of primitives which were clipped and result in 4 primitives p;:.PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8: PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 Number of primitives which were clipped and result in 5-8 primitives <;/PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13: PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 Number of primitives which were clipped and result in 9-13 primitives =<0PERF_PAPC_CLIPGA_VTE_KILL_PRIM: PERF_PAPC_CLIPGA_VTE_KILL_PRIM Number of primitives which are culled by VTE nan/inf logic >=1oPERF_PAPC_SU_INPUT_PRIM: PERF_PAPC_SU_INPUT_PRIM Number of primitives input to the Setup block ?>2|PERF_PAPC_SU_INPUT_CLIP_PRIM: PERF_PAPC_SU_INPUT_CLIP_PRIM Number of clipped primitives input to the Setup block @?3yPERF_PAPC_SU_INPUT_NULL_PRIM: PERF_PAPC_SU_INPUT_NULL_PRIM Number of null primitives input to the Setup block A@4PERF_PAPC_SU_INPUT_PRIM_DUAL: PERF_PAPC_SU_INPUT_PRIM_DUAL Number of dual gradient primitives input to the Setup block BA5PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL: PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL Number of dual gradient clipped primitives input to the Setup block CB6wPERF_PAPC_SU_ZERO_AREA_CULL_PRIM: PERF_PAPC_SU_ZERO_AREA_CULL_PRIM Number of primitives culled due to zero area DC7PERF_PAPC_SU_BACK_FACE_CULL_PRIM: PERF_PAPC_SU_BACK_FACE_CULL_PRIM Number of back-face primitives culled due to facedness ED8PERF_PAPC_SU_FRONT_FACE_CULL_PRIM: PERF_PAPC_SU_FRONT_FACE_CULL_PRIM Number of front-face primitives culled due to facedness FF9PERF_PAPC_SU_POLYMODE_FACE_CULL: PERF_PAPC_SU_POLYMODE_FACE_CULL Number of polymode cull-determination primitives culled GG:PERF_PAPC_SU_POLYMODE_BACK_CULL: PERF_PAPC_SU_POLYMODE_BACK_CULL Number of polymode primitives discarded due to Back-Face Cull HH;PERF_PAPC_SU_POLYMODE_FRONT_CULL: PERF_PAPC_SU_POLYMODE_FRONT_CULL Number of polymode primitives discarded due to Front-Face Cull J(I<PERF_PAPC_SU_POLYMODE_INVALID_FILL: PERF_PAPC_SU_POLYMODE_INVALID_FILL Number of polymode lines and/or points which are culled because they are an internal edge or point K`J=sPERF_PAPC_SU_OUTPUT_PRIM: PERF_PAPC_SU_OUTPUT_PRIM Number of primitives output from the Setup block LXK>PERF_PAPC_SU_OUTPUT_CLIP_PRIM: PERF_PAPC_SU_OUTPUT_CLIP_PRIM Number of clipped primitives output from the Setup block M`L?}PERF_PAPC_SU_OUTPUT_NULL_PRIM: PERF_PAPC_SU_OUTPUT_NULL_PRIM Number of null primitives output from the Setup block NhM@uPERF_PAPC_SU_OUTPUT_EVENT_FLAG: PERF_PAPC_SU_OUTPUT_EVENT_FLAG Number of events output from the Setup block 0OhNAPERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT: PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT Number of First-Prim-Of-Slots output from the Setup block 8PxOBPERF_PAPC_SU_OUTPUT_END_OF_PACKET: PERF_PAPC_SU_OUTPUT_END_OF_PACKET Number of End-Of-Packets output from the Setup block HQPCPERF_PAPC_SU_OUTPUT_POLYMODE_FACE: PERF_PAPC_SU_OUTPUT_POLYMODE_FACE Number of polymode facing primitives output from the Setup block `RQDPERF_PAPC_SU_OUTPUT_POLYMODE_BACK: PERF_PAPC_SU_OUTPUT_POLYMODE_BACK Number of polymode back-face primitives output from the Setup block xSREPERF_PAPC_SU_OUTPUT_POLYMODE_FRONT: PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT Number of polymode front-face primitives output from the Setup block TSFPERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE: PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE Number of clipped polymode facing primitives output from the Setup block UTGPERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK: PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK Number of clipped polymode back-face primitives output from the Setup block VVHPERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT: PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT Number of clipped polymode front-face primitives output from the Setup block W WIPERF_PAPC_SU_OUTPUT_PRIM_DUAL: PERF_PAPC_SU_OUTPUT_PRIM_DUAL Number of dual gradient primitives output from the Setup block Y0XJPERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL: PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL Number of dual gradient clipped primitives output from the Setup block ZHYKPERF_PAPC_SU_OUTPUT_POLYMODE_DUAL: PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL Number of dual gradient polymode primitives output from the Setup block @[`ZLPERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL: PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL Number of dual gradient clip polymode primitives output from the Setup block 0\[MiPERF_PAPC_PASX_REQ_IDLE: PERF_PAPC_PASX_REQ_IDLE Number of clocks PASX Requestor is Idle ]x\NiPERF_PAPC_PASX_REQ_BUSY: PERF_PAPC_PASX_REQ_BUSY Number of clocks PASX Requestor is Busy ^h]OoPERF_PAPC_PASX_REQ_STALLED: PERF_PAPC_PASX_REQ_STALLED Number of clocks PASX Requestor is Stalled _`^PhPERF_PAPC_PASX_REC_IDLE: PERF_PAPC_PASX_REC_IDLE Number of clocks PASX Receiver is Idle _P_QhPERF_PAPC_PASX_REC_BUSY: PERF_PAPC_PASX_REC_BUSY Number of clocks PASX Receiver is Busy `@`RwPERF_PAPC_PASX_REC_STARVED_SX: PERF_PAPC_PASX_REC_STARVED_SX Number of clocks PASX Receiver is Stalled by SX b@aSPERF_PAPC_PASX_REC_STALLED: PERF_PAPC_PASX_REC_STALLED Number of clocks PASX Reciever is Stalled by Position Memory or Clip Code Generator (c`bTPERF_PAPC_PASX_REC_STALLED_POS_MEM: PERF_PAPC_PASX_REC_STALLED_POS_MEM Number of clocks PASX Reciever is Stalled by Position Memory @dpcUPERF_PAPC_PASX_REC_STALLED_CCGSM_IN: PERF_PAPC_PASX_REC_STALLED_CCGSM_IN Number of clocks PASX Reciever is Stalled by Clip Code Generator 0edVePERF_PAPC_CCGSM_IDLE: PERF_PAPC_CCGSM_IDLE Number of clocks Clip Code Gen is Idle fxeWePERF_PAPC_CCGSM_BUSY: PERF_PAPC_CCGSM_BUSY Number of clocks Clip Code Gen is Busy ghfXkPERF_PAPC_CCGSM_STALLED: PERF_PAPC_CCGSM_STALLED Number of clocks Clip Code Gen is Stalled hXgYoPERF_PAPC_CLPRIM_IDLE: PERF_PAPC_CLPRIM_IDLE Number of clocks Clip Primitive Machine is Idle iPhZoPERF_PAPC_CLPRIM_BUSY: PERF_PAPC_CLPRIM_BUSY Number of clocks Clip Primitive Machine is Busy jHi[PERF_PAPC_CLPRIM_STALLED: PERF_PAPC_CLPRIM_STALLED Number of clocks Clip Primitive Machine is stalled by Clip State Machines (kXj\PERF_PAPC_CLPRIM_STARVED_CCGSM: PERF_PAPC_CLPRIM_STARVED_CCGSM Number of clocks Clip Primitive Machine is starved by Clip Code Generator lpk]mPERF_PAPC_CLIPSM_IDLE: PERF_PAPC_CLIPSM_IDLE Number of clocks Clip State Machines are Idle mhl^mPERF_PAPC_CLIPSM_BUSY: PERF_PAPC_CLIPSM_BUSY Number of clocks Clip State Machines are Busy @n`m_PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH: PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH Number of clocks Clip State Mahcines are waiting for Clip Vert storage resources `on`PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ: PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ Number of clocks Clip State Machines are waiting for High Priority Sequencer hpoaPERF_PAPC_CLIPSM_WAIT_CLIPGA: PERF_PAPC_CLIPSM_WAIT_CLIPGA Number of clocks Clip State Machines are waiting for ClipGA qpbPERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP: PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP Number of clocks Clip State Machines are waiting for VTE cycles rqcPERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM: PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM Number of clocks Clip State Machines are waiting for Clip Output State Machine srd`PERF_PAPC_CLIPGA_IDLE: PERF_PAPC_CLIPGA_IDLE Number of clocks Clip Ga is Idle ptse`PERF_PAPC_CLIPGA_BUSY: PERF_PAPC_CLIPGA_BUSY Number of clocks Clip Ga is Busy xutfPERF_PAPC_CLIPGA_STARVED_VTE_CLIP: PERF_PAPC_CLIPGA_STARVED_VTE_CLIP Number of clocks Clip Ga is Starved by VTE or Clipper hvugfPERF_PAPC_CLIPGA_STALLED: PERF_PAPC_CLIPGA_STALLED Number of clocks Clip Ga is stalled Hwvh[PERF_PAPC_CLIP_IDLE: PERF_PAPC_CLIP_IDLE Number of clocks Clip is Idle (xwi[PERF_PAPC_CLIP_BUSY: PERF_PAPC_CLIP_BUSY Number of clocks Clip is Busy ypxjZPERF_PAPC_SU_IDLE: PERF_PAPC_SU_IDLE Number of clocks Setup is Idle yPykZPERF_PAPC_SU_BUSY: PERF_PAPC_SU_BUSY Number of clocks Setup is Busy z0zlpPERF_PAPC_SU_STARVED_CLIP: PERF_PAPC_SU_STARVED_CLIP Number of clocks Setup is starved by Clipper {({miPERF_PAPC_SU_STALLED_SC: PERF_PAPC_SU_STALLED_SC Number of clocks Setup is stalled by SC ||nsPERF_PAPC_PA_DYN_SCLK_VLD: PERF_PAPC_PA_DYN_SCLK_VLD Number of clocks the PA dynamic clock is active }otPERF_PAPC_PA_REG_SCLK_VLD: PERF_PAPC_PA_REG_SCLK_VLD Number of clocks the PA register clock is active 8(   "" PA_SU_POLY_OFFSET_BACK_OFFSET OFFSET""" PA_SU_POLY_OFFSET_BACK_SCALEh SCALE"H8"" PA_SU_POLY_OFFSET_FRONT_OFFSET OFFSET""" PA_SU_POLY_OFFSET_FRONT_SCALEx SCALE"P"" PA_SU_POLY_OFFSET_CLAMP CLAMP"`"" xPA_SU_POLY_OFFSET_DB_FMT_CNTL(POLY_OFFSET_NEG_NUM_DB_BITS"POLY_OFFSET_DB_IS_FLOAT_FMT""" (PA_SU_SC_MODE_CNTL  CULL_FRONTx%Do not cull front-facing triangles. Cull front-facing triangles. x CULL_BACKh$Do not cull back-facing triangles. Cull back-facing triangles. hFACE`(Positive cross product is front (CCW). 'Negative cross product is front (CW). h POLY_MODE`'Disable poly mode (render triangles). (>Dual mode (send 2 sets of 3 polys with specified poly type). p Reserved hPOLYMODE_FRONT_PTYPEDraw points. H Draw lines. 0Draw triangles. xReserved 3 - 7. pPOLYMODE_BACK_PTYPEDraw points. P Draw lines. 8Draw triangles. Reserved 3 - 7. ( POLY_OFFSET_FRONT_ENABLE Disable front offset. hEnable front offset.  pPOLY_OFFSET_BACK_ENABLEDisable back offset. XEnable back offset.  `POLY_OFFSET_PARA_ENABLE*Disable front offset for parallelograms. X)Enable front offset for parallelograms. pVTX_WINDOW_OFFSET_ENABLE"PPROVOKING_VTX_LAST`0 = First Vtx (D3D) 1 = Last Vtx (OGL) PERSP_CORR_DIS"PMULTI_PRIM_IB_ENA"p"" PA_SU_LINE_CNTLWIDTH"h"" PA_SU_POINT_MINMAXX MIN_SIZE" MAX_SIZE"(ؓ`"" PA_SU_POINT_SIZEPHEIGHT"WIDTH"ѓؓ"" ؓPA_SU_VTX_CNTLړHٓٓ PIX_CENTER8ړٓ0 = Pixel Center @ 0.0 (D3D) ړ1 = Pixel Center @ 0.5 (OGL) ݓ8ۓۓ ROUND_MODEܓۓ0 = Truncate (OGL) ܓ`ܓ 1 = Round Hݓܓ2 = Round to Even (D3D) ݓ3 = Round to Odd 8ޓޓ QUANT_MODEߓޓ 0 = 1/16th ߓXߓ 1 = 1/8th 0ߓ 2 = 1/4th x 3 = 1/2 P4 = 1  5 = 1/256th ˓xѓ"" ѓPA_SC_ENHANCE xғ ғ FORCE_EOV_MAX_CLK_CNT_R6XX"(ӓғ FORCE_EOV_MAX_TILE_CNT_R6XX"ӓӓ ECO_SPARE7"hԓ ԓ ECO_SPARE6"Փԓ ECO_SPARE5"Փ`Փ ECO_SPARE4"H֓֓ ECO_SPARE3"֓֓ ECO_SPARE2"ד@ד ECO_SPARE1"ד ECO_SPARE0"Ó˓"" ˓PA_CL_ENHANCE̓(̓CLIP_VTX_REORDER_ENA"(͓̓ NUM_CLIP_SEQ"͓͓CLIPPED_PRIM_SEQ_STALL"Γ0ΓVE_NAN_PROC_DISABLE" ϓΓ ECO_SPARE3"ϓxϓ ECO_SPARE2"`ГГ ECO_SPARE1"Г ECO_SPARE0"@“0ē"" ēCGTT_PA_CLK_CTRL œē ON_DELAY"œxœOFF_HYSTERESIS"pƓ ƓSOFT_OVERRIDE7"ǓƓSOFT_OVERRIDE6"ǓpǓSOFT_OVERRIDE5"hȓȓSOFT_OVERRIDE4"ɓȓSOFT_OVERRIDE3"ɓhɓSOFT_OVERRIDE2"`ʓʓSOFT_OVERRIDE1"ʓSOFT_OVERRIDE0"“"" ÓPA_CL_POINT_CULL_RADhÓ DATA_REGISTER"`H"" PA_CL_POINT_SIZE DATA_REGISTER"ؿ"" (PA_CL_POINT_Y_RAD DATA_REGISTER"h"" PA_CL_POINT_X_RAD DATA_REGISTER"||"" HPA_CL_UCP_5_W DATA_REGISTER"xx"" ػPA_CL_UCP_5_Z0 DATA_REGISTER"0tt"" hPA_CL_UCP_5_Y DATA_REGISTER"pp"" PA_CL_UCP_5_XP DATA_REGISTER"P8ll"" PA_CL_UCP_4_Wී DATA_REGISTER"೓ȵhh"" PA_CL_UCP_4_Zp DATA_REGISTER"pXdd"" PA_CL_UCP_4_Y DATA_REGISTER"貓``"" 8PA_CL_UCP_4_X DATA_REGISTER"x\\"" ȱPA_CL_UCP_3_W DATA_REGISTER"XX"" XPA_CL_UCP_3_Z DATA_REGISTER"TT"" ஓPA_CL_UCP_3_Y8 DATA_REGISTER"8 PP"" pPA_CL_UCP_3_Xȭ DATA_REGISTER"ȩLL"" PA_CL_UCP_2_WX DATA_REGISTER"X@HH"" PA_CL_UCP_2_Z誓 DATA_REGISTER"覓ШDD"" PA_CL_UCP_2_Yx DATA_REGISTER"x`@@"" PA_CL_UCP_2_X DATA_REGISTER"<<"" @PA_CL_UCP_1_W DATA_REGISTER"88"" ФPA_CL_UCP_1_Z( DATA_REGISTER"(44"" `PA_CL_UCP_1_Y DATA_REGISTER"00"" PA_CL_UCP_1_XH DATA_REGISTER"H0,,"" PA_CL_UCP_0_Wؠ DATA_REGISTER"؜(("" PA_CL_UCP_0_Zh DATA_REGISTER"hP$$"" PA_CL_UCP_0_Y DATA_REGISTER"  "" 0PA_CL_UCP_0_X DATA_REGISTER"xh"" PA_CL_GB_HORZ_DISC_ADJ DATA_REGISTER""" HPA_CL_GB_HORZ_CLIP_ADJ DATA_REGISTER"x"" ЗPA_CL_GB_VERT_DISC_ADJ( DATA_REGISTER"h  "" XPA_CL_GB_VERT_CLIP_ADJ DATA_REGISTER"}"" 0PA_CL_CLIP_CNTLЉ UCP_ENA_0"p( UCP_ENA_1"Ȋ UCP_ENA_2"h UCP_ENA_3"P UCP_ENA_4" UCP_ENA_5"H PS_UCP_Y_SCALE_NEG"8 PS_UCP_MODE" CLIP_DISABLE"8UCP_CULL_ONLY_ENA"8BOUNDARY_EDGE_FLAG_ENA"DX_CLIP_SPACE_DEF"8DIS_CLIP_ERR_DETECT"( VTX_KILL_OR"ؒDX_RASTERIZATION_KILL"0DX_LINEAR_ATTR_CLIP_ENA"8VTE_VPORT_PROVOKE_DISABLE"ZCLIP_NEAR_DISABLE"8ZCLIP_FAR_DISABLE"k}  "" }PA_CL_NANINF_CNTL~0~VTE_XY_INF_DISCARD"(~VTE_Z_INF_DISCARD"VTE_W_INF_DISCARD"x(VTE_0XNANINF_IS_0" ЀVTE_XY_NAN_RETAIN"ȁxVTE_Z_NAN_RETAIN"p VTE_W_NAN_RETAIN" ȂVTE_W_RECIP_NAN_IS_0"ȃxVS_XY_NAN_TO_INF"p VS_XY_INF_RETAIN"Ȅ VS_Z_NAN_TO_INF"p VS_Z_INF_RETAIN"h VS_W_NAN_TO_INF" VS_W_INF_RETAIN"hVS_CLIP_DIST_INF_DISCARD"VTE_NO_OUTPUT_NEG_0"ck"" kPA_CL_VS_OUT_CNTLl0lCLIP_DIST_ENA_0"(mlCLIP_DIST_ENA_1"mmCLIP_DIST_ENA_2"xn(nCLIP_DIST_ENA_3" onCLIP_DIST_ENA_4"oxoCLIP_DIST_ENA_5"pp pCLIP_DIST_ENA_6"qpCLIP_DIST_ENA_7"qpqCULL_DIST_ENA_0"hrr CULL_DIST_ENA_1"sr CULL_DIST_ENA_2"shs CULL_DIST_ENA_3"`tt CULL_DIST_ENA_4"ut CULL_DIST_ENA_5"u`uCULL_DIST_ENA_6"XvvCULL_DIST_ENA_7"wvUSE_VTX_POINT_SIZE"wXwUSE_VTX_EDGE_FLAG"XxxUSE_VTX_RENDER_TARGET_INDX"yxUSE_VTX_VIEWPORT_INDX"y`yUSE_VTX_KILL_FLAG"XzzVS_OUT_MISC_VEC_ENA"{zVS_OUT_CCDIST0_VEC_ENA"{`{VS_OUT_CCDIST1_VEC_ENA"h||VS_OUT_MISC_SIDE_BUS_ENA"|USE_VTX_GS_CUT_FLAG"XbHd"" dPA_CL_VTE_CNTL @edVPORT_X_SCALE_ENA"eeVPORT_X_OFFSET_ENA"f@fVPORT_Y_SCALE_ENA"8gfVPORT_Y_OFFSET_ENA"ggVPORT_Z_SCALE_ENA"h8hVPORT_Z_OFFSET_ENA"(ih VTX_XY_FMT"ii  VTX_Z_FMT"hj j  VTX_W0_FMT"j PERFCOUNTER_REF"`b"" (cPA_CL_VPORT_ZOFFSET_15c VPORT_ZOFFSET"h_Xa"" aPA_CL_VPORT_ZOFFSET_14b VPORT_ZOFFSET"]_"" 8`PA_CL_VPORT_ZOFFSET_13` VPORT_ZOFFSET"x\h^pp"" ^PA_CL_VPORT_ZOFFSET_12_ VPORT_ZOFFSET"[\XX"" H]PA_CL_VPORT_ZOFFSET_11] VPORT_ZOFFSET"Yx[@@"" [PA_CL_VPORT_ZOFFSET_10(\ VPORT_ZOFFSET"XZ(("" XZPA_CL_VPORT_ZOFFSET_9Z VPORT_ZOFFSET"VX"" XPA_CL_VPORT_ZOFFSET_88Y VPORT_ZOFFSET" UW"" hWPA_CL_VPORT_ZOFFSET_7W VPORT_ZOFFSET"SU"" UPA_CL_VPORT_ZOFFSET_6HV VPORT_ZOFFSET"0R TȄȄ"" xTPA_CL_VPORT_ZOFFSET_5T VPORT_ZOFFSET"PR"" SPA_CL_VPORT_ZOFFSET_4XS VPORT_ZOFFSET"@O0Q"" QPA_CL_VPORT_ZOFFSET_3Q VPORT_ZOFFSET"MO"" PPA_CL_VPORT_ZOFFSET_2hP VPORT_ZOFFSET"PL@Nhh"" NPA_CL_VPORT_ZOFFSET_1N VPORT_ZOFFSET"JL"" MPA_CL_VPORT_ZSCALE_15xM VPORT_ZSCALE"`IPK"" KPA_CL_VPORT_ZSCALE_14L VPORT_ZSCALE"GI"" 0JPA_CL_VPORT_ZSCALE_13J VPORT_ZSCALE"pF`Hll"" HPA_CL_VPORT_ZSCALE_12I VPORT_ZSCALE"DFTT"" @GPA_CL_VPORT_ZSCALE_11G VPORT_ZSCALE"CpE<<"" EPA_CL_VPORT_ZSCALE_10 F VPORT_ZSCALE"BC$$"" PDPA_CL_VPORT_ZSCALE_9D VPORT_ZSCALE"@B  "" BPA_CL_VPORT_ZSCALE_80C VPORT_ZSCALE"?A"" `APA_CL_VPORT_ZSCALE_7A VPORT_ZSCALE"=?܄܄"" ?PA_CL_VPORT_ZSCALE_6@@ VPORT_ZSCALE"(<>ĄĄ"" p>PA_CL_VPORT_ZSCALE_5> VPORT_ZSCALE":<"" <PA_CL_VPORT_ZSCALE_4P= VPORT_ZSCALE"89(;"" ;PA_CL_VPORT_ZSCALE_3; VPORT_ZSCALE"79||"" :PA_CL_VPORT_ZSCALE_2`: VPORT_ZSCALE"H688dd"" 8PA_CL_VPORT_ZSCALE_18 VPORT_ZSCALE"46"" 7PA_CL_VPORT_YOFFSET_15p7 VPORT_YOFFSET"X3H5"" 5PA_CL_VPORT_YOFFSET_145 VPORT_YOFFSET"13"" (4PA_CL_VPORT_YOFFSET_134 VPORT_YOFFSET"h0X2hh"" 2PA_CL_VPORT_YOFFSET_123 VPORT_YOFFSET".0PP"" 81PA_CL_VPORT_YOFFSET_111 VPORT_YOFFSET"x-h/88"" /PA_CL_VPORT_YOFFSET_100 VPORT_YOFFSET",-  "" H.PA_CL_VPORT_YOFFSET_9. VPORT_YOFFSET"*x,"" ,PA_CL_VPORT_YOFFSET_8(- VPORT_YOFFSET")+"" X+PA_CL_VPORT_YOFFSET_7+ VPORT_YOFFSET"')؄؄"" )PA_CL_VPORT_YOFFSET_68* VPORT_YOFFSET" &("" h(PA_CL_VPORT_YOFFSET_5( VPORT_YOFFSET"$&"" &PA_CL_VPORT_YOFFSET_4H' VPORT_YOFFSET"0# %"" x%PA_CL_VPORT_YOFFSET_3% VPORT_YOFFSET"!#xx"" $PA_CL_VPORT_YOFFSET_2X$ VPORT_YOFFSET"@ 0"``"" "PA_CL_VPORT_YOFFSET_1" VPORT_YOFFSET" "" !PA_CL_VPORT_YSCALE_15h! VPORT_YSCALE"P@"" PA_CL_VPORT_YSCALE_14 VPORT_YSCALE"||"" PA_CL_VPORT_YSCALE_13x VPORT_YSCALE"`Pdd"" PA_CL_VPORT_YSCALE_12 VPORT_YSCALE"LL"" 0PA_CL_VPORT_YSCALE_11 VPORT_YSCALE"p`44"" PA_CL_VPORT_YSCALE_10 VPORT_YSCALE""" @PA_CL_VPORT_YSCALE_9 VPORT_YSCALE"p"" PA_CL_VPORT_YSCALE_8  VPORT_YSCALE""" PPA_CL_VPORT_YSCALE_7 VPORT_YSCALE"ԄԄ"" PA_CL_VPORT_YSCALE_60 VPORT_YSCALE""" `PA_CL_VPORT_YSCALE_5 VPORT_YSCALE""" PA_CL_VPORT_YSCALE_4@ VPORT_YSCALE"( "" pPA_CL_VPORT_YSCALE_3 VPORT_YSCALE" tt"" PA_CL_VPORT_YSCALE_2P VPORT_YSCALE"8 ( \\"" PA_CL_VPORT_YSCALE_1 VPORT_YSCALE" ""  PA_CL_VPORT_XOFFSET_15` VPORT_XOFFSET"H8 "" PA_CL_VPORT_XOFFSET_14 VPORT_XOFFSET"xx"" PA_CL_VPORT_XOFFSET_13p VPORT_XOFFSET"XH``"" PA_CL_VPORT_XOFFSET_12 VPORT_XOFFSET"HH"" (PA_CL_VPORT_XOFFSET_11 VPORT_XOFFSET"hX00"" PA_CL_VPORT_XOFFSET_10 VPORT_XOFFSET"p"" 8PA_CL_VPORT_XOFFSET_9 VPORT_XOFFSET"h"" PA_CL_VPORT_XOFFSET_8 VPORT_XOFFSET"p"" PA_CL_VPORT_XOFFSET_7  VPORT_XOFFSET"ЄЄ"" PPA_CL_VPORT_XOFFSET_6 VPORT_XOFFSET""" PA_CL_VPORT_XOFFSET_50 VPORT_XOFFSET""" `PA_CL_VPORT_XOFFSET_4 VPORT_XOFFSET""" PA_CL_VPORT_XOFFSET_3@ VPORT_XOFFSET"(pp"" pPA_CL_VPORT_XOFFSET_2 VPORT_XOFFSET"XX"" PA_CL_VPORT_XOFFSET_1P VPORT_XOFFSET"8("" PA_CL_VPORT_XSCALE_15 VPORT_XSCALE""" PA_CL_VPORT_XSCALE_14` VPORT_XSCALE"H8tt"" PA_CL_VPORT_XSCALE_13 VPORT_XSCALE"\\"" PA_CL_VPORT_XSCALE_12p VPORT_XSCALE"XHDD"" PA_CL_VPORT_XSCALE_11 VPORT_XSCALE",,"" (PA_CL_VPORT_XSCALE_10 VPORT_XSCALE"hX"" PA_CL_VPORT_XSCALE_9 VPORT_XSCALE""" 8PA_CL_VPORT_XSCALE_8 VPORT_XSCALE"xh"" PA_CL_VPORT_XSCALE_7 VPORT_XSCALE"̄̄"" HPA_CL_VPORT_XSCALE_6 VPORT_XSCALE"x"" PA_CL_VPORT_XSCALE_5( VPORT_XSCALE""" XPA_CL_VPORT_XSCALE_4 VPORT_XSCALE""" PA_CL_VPORT_XSCALE_38 VPORT_XSCALE" ll"" hPA_CL_VPORT_XSCALE_2 VPORT_XSCALE"TT"" PA_CL_VPORT_XSCALE_1H VPORT_XSCALE"@(PP"" xPA_CL_VPORT_ZOFFSET VPORT_ZOFFSET"LL"" PA_CL_VPORT_ZSCALE` VPORT_ZSCALE"`HHH"" PA_CL_VPORT_YOFFSET VPORT_YOFFSET"DD"" (PA_CL_VPORT_YSCALE VPORT_YSCALE"h@@"" PA_CL_VPORT_XOFFSET VPORT_XOFFSET"<<"" HPA_CL_VPORT_XSCALE VPORT_XSCALE"h||"" PGC_USER_RB_BACKEND_DISABLEBACKEND_DISABLE""" 8CC_RB_BACKEND_DISABLE WRITE_DIS"0BACKEND_DISABLE""" HGB_TILING_CONFIG PIPE_TILING0)CONFIG_1_PIPE: 1 logical rendering pipe H*CONFIG_2_PIPE: 2 logical rendering pipes *CONFIG_4_PIPE: 4 logical rendering pipes @*CONFIG_8_PIPE: 8 logical rendering pipes P BANK_TILING%CONFIG_4_BANK: 4 logical DRAM banks H%CONFIG_8_BANK: 8 logical DRAM banks P GROUP_SIZE1CONFIG_256B_GROUP: 256B memory interleve groups P1CONFIG_512B_GROUP: 512B memory interleve groups ` ROW_TILING0CONFIG_1KB_ROW: Treat 1KB as DRAM row boundary `0CONFIG_2KB_ROW: Treat 2KB as DRAM row boundary 0CONFIG_4KB_ROW: Treat 4KB as DRAM row boundary @0CONFIG_8KB_ROW: Treat 8KB as DRAM row boundary OCONFIG_1KB_ROW_OPT: Treat 1KB as DRAM row boundary; Use optimized bank tiling `OCONFIG_2KB_ROW_OPT: Treat 2KB as DRAM row boundary; Use optimized bank tiling 8OCONFIG_4KB_ROW_OPT: Treat 4KB as DRAM row boundary; Use optimized bank tiling OCONFIG_8KB_ROW_OPT: Treat 8KB as DRAM row boundary; Use optimized bank tiling  @ BANK_SWAPS1CONFIG_128B_SWAPS: Perform bank swap after 128B @1CONFIG_256B_SWAPS: Perform bank swap after 256B h1CONFIG_512B_SWAPS: Perform bank swap after 512B /CONFIG_1KB_SWAPS: Perform bank swap after 1KB x SAMPLE_SPLIT5CONFIG_1KB_SPLIT: Split multi-sample tiles over 1KB H5CONFIG_2KB_SPLIT: Split multi-sample tiles over 2KB 5CONFIG_4KB_SPLIT: Split multi-sample tiles over 4KB P5CONFIG_8KB_SPLIT: Split multi-sample tiles over 8KB  BACKEND_MAP"DEINTDEBUGINDJ  DMCUDEBUGINDJp UVDCTXINDJظ DCDEBUGINDJP@ DRMDEBUGINDJ DCCGDEBUGINDJ IDCTDEBUGINDJx` DOUTDEBUGINDJȵ DCPDEBUGINDJH0 LBDEBUGINDJ SCLDEBUGINDJ CRTCDEBUGINDJx` SQADBGINDJȲ SQDBGINDJH0 TCADBGINDJ TCCDBGINDJ VCDEBUGINDJh VGTDEBUGINDJЯ SCDEBUGINDJP8 SUDEBUGINDJGpuVGAJ GpuROMJpGpuF0FBJج AudioRegJX@ GpuF1RegJY GpuF0Reg( GpuSparseIOJx GpuBlockIOJ TAudioPcieJ`H TGpuF1PcieJȧ TGpuF0PcieJ0 AudioPcieJ GpuF1PcieJ GpuF0PcieJ8`W)XCP`WGRBMPCBDBŲHSX)ŲSPIh*SQTCC TPehTA8fVGT@PA@GBGX2_TRUEGX2_FALSEGX2_FRONT_FACE_CCWGX2_FRONT_FACE_CW[UNKNOWN FRONT FACE MODE]GX2_POLYGON_MODE_POINTGX2_POLYGON_MODE_LINEGX2_POLYGON_MODE_TRIANGLE[UNKNOWN POLYGON MODE]GX2_COMPARE_NEVERGX2_COMPARE_LESSGX2_COMPARE_EQUALGX2_COMPARE_LEQUALGX2_COMPARE_GREATERGX2_COMPARE_NOTEQUALGX2_COMPARE_GEQUALGX2_COMPARE_ALWAYS[UNKNOWN COMPARE FUNCTION]GX2_STENCIL_KEEPGX2_STENCIL_ZEROGX2_STENCIL_REPLACEGX2_STENCIL_INCRGX2_STENCIL_DECRGX2_STENCIL_INVERTGX2_STENCIL_INCR_WRAPGX2_STENCIL_DECR_WRAP[UNKNOWN STENCIL FUNCTION]GX2_CHANNEL_MASK_NONEGX2_CHANNEL_MASK_RGX2_CHANNEL_MASK_GGX2_CHANNEL_MASK_RGGX2_CHANNEL_MASK_BGX2_CHANNEL_MASK_RBGX2_CHANNEL_MASK_GBGX2_CHANNEL_MASK_RGBGX2_CHANNEL_MASK_AGX2_CHANNEL_MASK_RAGX2_CHANNEL_MASK_GAGX2_CHANNEL_MASK_RGAGX2_CHANNEL_MASK_BAGX2_CHANNEL_MASK_RBAGX2_CHANNEL_MASK_GBAGX2_CHANNEL_MASK_RGBA[UNKNOWN CHANNEL MASK]GX2_LOGIC_OP_CLEARGX2_LOGIC_OP_SETGX2_LOGIC_OP_COPYGX2_LOGIC_OP_INVCOPYGX2_LOGIC_OP_NOOPGX2_LOGIC_OP_INVGX2_LOGIC_OP_ANDGX2_LOGIC_OP_NANDGX2_LOGIC_OP_ORGX2_LOGIC_OP_NORGX2_LOGIC_OP_XORGX2_LOGIC_OP_EQUIVGX2_LOGIC_OP_REVANDGX2_LOGIC_OP_INVANDGX2_LOGIC_OP_REVORGX2_LOGIC_OP_INVOR[UNKNOWN LOGIC OP]GX2_BLEND_ZEROGX2_BLEND_ONEGX2_BLEND_SRC_COLORGX2_BLEND_ONE_MINUS_SRC_COLORGX2_BLEND_SRC_ALPHAGX2_BLEND_ONE_MINUS_SRC_ALPHAGX2_BLEND_DST_ALPHAGX2_BLEND_ONE_MINUS_DST_ALPHAGX2_BLEND_DST_COLORGX2_BLEND_ONE_MINUS_DST_COLORGX2_BLEND_SRC_ALPHA_SATURATEGX2_BLEND_CONSTANT_COLORGX2_BLEND_ONE_MINUS_CONSTANT_COLORGX2_BLEND_SRC1_COLORGX2_BLEND_ONE_MINUS_SRC1_COLORGX2_BLEND_SRC1_ALPHAGX2_BLEND_ONE_MINUS_SRC1_ALPHAGX2_BLEND_CONSTANT_ALPHAGX2_BLEND_ONE_MINUS_CONSTANT_ALPHA[UNKNOWN BLEND FUNCTION]GX2_BLEND_COMBINE_ADDGX2_BLEND_COMBINE_SRC_MINUS_DSTGX2_BLEND_COMBINE_MINGX2_BLEND_COMBINE_MAXGX2_BLEND_COMBINE_DST_MINUS_SRC[UNKNOWN BLEND COMBINE]GX2_ALPHA_TO_MASK_0GX2_ALPHA_TO_MASK_1GX2_ALPHA_TO_MASK_2GX2_ALPHA_TO_MASK_3GX2_ALPHA_TO_MASK_4[UNKNOWN ALPHA TO MASK MODE][UNKNOWN TEX CLAMP]GX2_INDEX_FORMAT_U16_LEGX2_INDEX_FORMAT_U32_LEGX2_INDEX_FORMAT_U16GX2_INDEX_FORMAT_U32[UNKNOWN INDEX FORMAT]GX2_PRIMITIVE_POINTSGX2_PRIMITIVE_LINESGX2_PRIMITIVE_LINE_STRIPGX2_PRIMITIVE_TRIANGLESGX2_PRIMITIVE_TRIANGLE_FANGX2_PRIMITIVE_TRIANGLE_STRIPGX2_PRIMITIVE_LINES_ADJACENCYGX2_PRIMITIVE_LINE_STRIP_ADJACENCYGX2_PRIMITIVE_TRIANGLES_ADJACENCYGX2_PRIMITIVE_TRIANGLE_STRIP_ADJACENCYGX2_PRIMITIVE_RECTSGX2_PRIMITIVE_LINE_LOOPGX2_PRIMITIVE_QUADSGX2_PRIMITIVE_QUAD_STRIPGX2_PRIMITIVE_TESSELLATE_LINESGX2_PRIMITIVE_TESSELLATE_LINE_STRIPGX2_PRIMITIVE_TESSELLATE_TRIANGLESGX2_PRIMITIVE_TESSELLATE_TRIANGLE_STRIPGX2_PRIMITIVE_TESSELLATE_QUADSGX2_PRIMITIVE_TESSELLATE_QUAD_STRIP[UNKNOWN PRIMITIVE TYPE]GX2_SURFACE_FORMAT_TC_R8_UNORMGX2_SURFACE_FORMAT_TC_R8_UINTGX2_SURFACE_FORMAT_TC_R8_SNORMGX2_SURFACE_FORMAT_TC_R8_SINTGX2_SURFACE_FORMAT_T_R4_G4_UNORMGX2_SURFACE_FORMAT_TCD_R16_UNORMGX2_SURFACE_FORMAT_TC_R16_UINTGX2_SURFACE_FORMAT_TC_R16_SNORMGX2_SURFACE_FORMAT_TC_R16_SINTGX2_SURFACE_FORMAT_TC_R16_FLOATGX2_SURFACE_FORMAT_TC_R8_G8_UNORMGX2_SURFACE_FORMAT_TC_R8_G8_UINTGX2_SURFACE_FORMAT_TC_R8_G8_SNORMGX2_SURFACE_FORMAT_TC_R8_G8_SINTGX2_SURFACE_FORMAT_TCS_R5_G6_B5_UNORMGX2_SURFACE_FORMAT_TC_R5_G5_B5_A1_UNORMGX2_SURFACE_FORMAT_TC_R4_G4_B4_A4_UNORMGX2_SURFACE_FORMAT_TC_A1_B5_G5_R5_UNORMGX2_SURFACE_FORMAT_TC_R32_UINTGX2_SURFACE_FORMAT_TC_R32_SINTGX2_SURFACE_FORMAT_TCD_R32_FLOATGX2_SURFACE_FORMAT_TC_R16_G16_UNORMGX2_SURFACE_FORMAT_TC_R16_G16_UINTGX2_SURFACE_FORMAT_TC_R16_G16_SNORMGX2_SURFACE_FORMAT_TC_R16_G16_SINTGX2_SURFACE_FORMAT_TC_R16_G16_FLOATGX2_SURFACE_FORMAT_D_D24_S8_UNORMGX2_SURFACE_FORMAT_T_X24_G8_UINTGX2_SURFACE_FORMAT_TC_R11_G11_B10_FLOATGX2_SURFACE_FORMAT_TCS_R10_G10_B10_A2_UNORMGX2_SURFACE_FORMAT_TC_R10_G10_B10_A2_UINTGX2_SURFACE_FORMAT_TC_R10_G10_B10_A2_SNORMGX2_SURFACE_FORMAT_TC_R10_G10_B10_A2_SINTGX2_SURFACE_FORMAT_TCS_R8_G8_B8_A8_UNORMGX2_SURFACE_FORMAT_TC_R8_G8_B8_A8_UINTGX2_SURFACE_FORMAT_TC_R8_G8_B8_A8_SNORMGX2_SURFACE_FORMAT_TC_R8_G8_B8_A8_SINTGX2_SURFACE_FORMAT_TCS_R8_G8_B8_A8_SRGBGX2_SURFACE_FORMAT_TCS_A2_B10_G10_R10_UNORMGX2_SURFACE_FORMAT_TC_A2_B10_G10_R10_UINTGX2_SURFACE_FORMAT_D_D32_FLOAT_S8_UINT_X24GX2_SURFACE_FORMAT_T_X32_G8_UINT_X24GX2_SURFACE_FORMAT_TC_R32_G32_UINTGX2_SURFACE_FORMAT_TC_R32_G32_SINTGX2_SURFACE_FORMAT_TC_R32_G32_FLOATGX2_SURFACE_FORMAT_TC_R16_G16_B16_A16_UNORMGX2_SURFACE_FORMAT_TC_R16_G16_B16_A16_UINTGX2_SURFACE_FORMAT_TC_R16_G16_B16_A16_SNORMGX2_SURFACE_FORMAT_TC_R16_G16_B16_A16_SINTGX2_SURFACE_FORMAT_TC_R16_G16_B16_A16_FLOATGX2_SURFACE_FORMAT_TC_R32_G32_B32_A32_UINTGX2_SURFACE_FORMAT_TC_R32_G32_B32_A32_SINTGX2_SURFACE_FORMAT_TC_R32_G32_B32_A32_FLOATGX2_SURFACE_FORMAT_T_BC1_UNORMGX2_SURFACE_FORMAT_T_BC1_SRGBGX2_SURFACE_FORMAT_T_BC2_UNORMGX2_SURFACE_FORMAT_T_BC2_SRGBGX2_SURFACE_FORMAT_T_BC3_UNORMGX2_SURFACE_FORMAT_T_BC3_SRGBGX2_SURFACE_FORMAT_T_BC4_UNORMGX2_SURFACE_FORMAT_T_BC4_SNORMGX2_SURFACE_FORMAT_T_BC5_UNORMGX2_SURFACE_FORMAT_T_BC5_SNORMGX2_SURFACE_FORMAT_T_NV12_UNORM[UNSET][UNKNOWN SURFACE FORMAT]GX2_TILE_MODE_LINEAR_ALIGNEDGX2_TILE_MODE_1D_TILED_THIN1GX2_TILE_MODE_1D_TILED_THICKGX2_TILE_MODE_2D_TILED_THIN1GX2_TILE_MODE_2D_TILED_THIN2GX2_TILE_MODE_2D_TILED_THIN4GX2_TILE_MODE_2D_TILED_THICKGX2_TILE_MODE_2B_TILED_THIN1GX2_TILE_MODE_2B_TILED_THIN2GX2_TILE_MODE_2B_TILED_THIN4GX2_TILE_MODE_3D_TILED_THIN1GX2_TILE_MODE_3D_TILED_THICKGX2_TILE_MODE_3B_TILED_THIN1GX2_TILE_MODE_3B_TILED_THICK[UNKNOWN TILE MODE]GX2_SURFACE_USE_TEXTUREGX2_SURFACE_USE_COLOR_BUFFERGX2_SURFACE_USE_DEPTH_BUFFERGX2_SURFACE_USE_SCAN_BUFFERGX2_SURFACE_USE_COLOR_BUFFER_TEXTUREGX2_SURFACE_USE_DEPTH_BUFFER_TEXTURE[UNKNOWN SURFACE USE]GX2_SURFACE_DIM_1DGX2_SURFACE_DIM_2DGX2_SURFACE_DIM_3DGX2_SURFACE_DIM_CUBEGX2_SURFACE_DIM_1D_ARRAYGX2_SURFACE_DIM_2D_ARRAYGX2_SURFACE_DIM_2D_MSAAGX2_SURFACE_DIM_2D_MSAA_ARRAY[UNKNOWN SURFACE DIM]GX2_AA_MODE_1XGX2_AA_MODE_2XGX2_AA_MODE_4XGX2_AA_MODE_8X[UNKNOWN AA MODE]GX2_TEX_CLAMP_WRAPGX2_TEX_CLAMP_MIRRORGX2_TEX_CLAMP_CLAMPGX2_TEX_CLAMP_MIRROR_ONCEGX2_TEX_CLAMP_CLAMP_HALF_BORDERGX2_TEX_CLAMP_MIRROR_ONCE_HALF_BORDERGX2_TEX_CLAMP_CLAMP_BORDERGX2_TEX_CLAMP_MIRROR_ONCE_BORDERGX2_TEX_BORDER_CLEAR_BLACKGX2_TEX_BORDER_SOLID_BLACKGX2_TEX_BORDER_SOLID_WHITEGX2_TEX_BORDER_USE_REGISTER[UNKNOWN TEX BORDER TYPE]GX2_TEX_XY_FILTER_POINTGX2_TEX_XY_FILTER_BILINEAR[UNKNOWN TEX XY FILTER TYPE]GX2_TEX_Z_FILTER_USE_XYGX2_TEX_Z_FILTER_POINTGX2_TEX_Z_FILTER_LINEAR[UNKNOWN TEX Z FILTER TYPE]GX2_TEX_MIP_FILTER_NO_MIPGX2_TEX_MIP_FILTER_POINTGX2_TEX_MIP_FILTER_LINEAR[UNKNOWN TEX MIP FILTER TYPE]GX2_TEX_Z_PERF_0GX2_TEX_Z_PERF_1GX2_TEX_Z_PERF_2GX2_TEX_Z_PERF_3[UNKNOWN TEX Z PERF TYPE]GX2_TEX_MIP_PERF_0GX2_TEX_MIP_PERF_1GX2_TEX_MIP_PERF_2GX2_TEX_MIP_PERF_3GX2_TEX_MIP_PERF_4GX2_TEX_MIP_PERF_5GX2_TEX_MIP_PERF_6GX2_TEX_MIP_PERF_7[UNKNOWN TEX MIP PERF TYPE]GX2_TEX_ANISO_1_TO_1GX2_TEX_ANISO_2_TO_1GX2_TEX_ANISO_4_TO_1GX2_TEX_ANISO_8_TO_1GX2_TEX_ANISO_16_TO_1[UNKNOWN TEX ANISO RATIO] | GX2_INVALIDATE_ATTRIB_BUFFERGX2_INVALIDATE_TEXTUREGX2_INVALIDATE_UNIFORM_BLOCKGX2_INVALIDATE_SHADERGX2_INVALIDATE_COLOR_BUFFERGX2_INVALIDATE_DEPTH_BUFFERGX2_INVALIDATE_CPUGX2_INVALIDATE_STREAMOUT_BUFFERGX2_INVALIDATE_EXPORT_BUFFERGX2_RENDER_TARGET_0GX2_RENDER_TARGET_1GX2_RENDER_TARGET_2GX2_RENDER_TARGET_3GX2_RENDER_TARGET_4GX2_RENDER_TARGET_5GX2_RENDER_TARGET_6GX2_RENDER_TARGET_7[UNKNOWN RENDER TARGET]GX2_QUERY_TYPE_OCCLUSION_CPUGX2_QUERY_TYPE_STREAMOUT_STATS_CPUGX2_QUERY_TYPE_OCCLUSION_GPUGX2_QUERY_TYPE_STREAMOUT_STATS_GPU[UNKNOWN QUERY TYPE]VertexGeometryPixel[UNKNOWN SHADER TYPE]Reserved_0x00Reserved_0x01Reserved_0x02Reserved_0x03CACHE_FLUSH_TSCONTEXT_DONECACHE_FLUSHVIZQUERY_STARTVIZQUERY_ENDSC_WAIT_WCMPASS_PS_CP_REFETCHMPASS_PS_RST_STARTMPASS_PS_INCR_STARTRST_PIX_CNTRST_VTX_CNTVS_PARTIAL_FLUSHPS_PARTIAL_FLUSHReserved_0x11Reserved_0x12Reserved_0x13CACHE_FLUSH_AND_INV_TS_EVENTZPASS_DONECACHE_FLUSH_AND_INV_EVENTPERFCOUNTER_STARTPERFCOUNTER_STOPPIPELINESTAT_STARTPIPELINESTAT_STOPPERFCOUNTER_SAMPLEFLUSH_ES_OUTPUTFLUSH_GS_OUTPUTSAMPLE_PIPELINESTATSO_VGTSTREAMOUT_FLUSHSAMPLE_STREAMOUTSTATSRESET_VTX_CNTBLOCK_CONTEXT_DONEReserved_0x23VGT_FLUSHReserved_0x25SQ_NON_EVENTSC_SEND_DB_VPZBOTTOM_OF_PIPE_TSFLUSH_SX_TSDB_CACHE_FLUSH_AND_INVFLUSH_AND_INV_DB_DATA_TSFLUSH_AND_INV_DB_METAFLUSH_AND_INV_CB_DATA_TSFLUSH_AND_INV_CB_META[UNKNOWN VGT_EVENT_TYPE]map/set too longinvalid map/set iteratorprimaryRegisterApertureGpuF0Reg?O??B$B$Be+000~PAGAIsProcessorFeaturePresentKERNEL321#QNAN1#INF1#IND1#SNANHe\3\;RSDS(};FPxEc:\Users\matt\NTD\cafe\system\bin\win32\pm4parse.pdb`\(\(\(\x0\`\@(\܈\,\\4)\D)\P)\,\\@4)\`\)\)\)\`\@)\n\)\)\)\,\n\@)\0q\*\$*\0*\d+\0q\@*\q\`*\p*\|*\0+\q\@`*\q\*\*\*\*\q\@*\*\*\q\@*\(+\0+\ r\@+\\+\d+\8r\@L+\r\+\+\|,\+\+\,,\r\@+\+\+\+\,,\r\@,\ ,\+\,,\dr\@H,\X,\`,\dr\@H,\r\@+\\,\,\,\,\܈\@,\,\,\\@,\q\*\r\+\r\,\4\h-\x-\-\-\,\4\@h-\\-\-\-\,\\@-\T\.\.\<.\ .\8r\ML+\T\@.\t\l.\|.\.\00\x0\t\@l.\\.\.\.\ /\\@.\\/\/\ /\\@/\ċ\P/\`/\p/\0\,\ċ\@P/\ȉ\/\/\/\/\x0\ȉ\@/\/\/\x0\\@/\$0\00\x0\\@0\$\`0\p0\x0\$\@`0\\0\0\0\,\\@0\XD\0\1\1\2\1\1\1\D\@0\\L1\\1\h1\X2\\@L1\\1\1\2\1\1\1\l\@3\\@2\4\P2\\@1\\@2\P2\X2\\@@2\4\2\2\2\D3\2\4\@2\\2\2\D3\2\l\@3\ 3\(3\l\@3\\@2\\t3\3\3\-\,\\@t3\}Hk(Xd8h(XpHx8x'w(e5[@B"4\cB"4\B"5\BB"45\BB"h5\H[A\A]A^A(bA\=\=\@ >\\(@@ċ\(P@\>\@>\=\ @x>\\ =YA>\=\ZYA>\\(2A>\=\=\@>\ B" ?\PB"8?\B"d?\B"?\BBBB B"?\0B8BCBNBYB"@\B"T@\@:@@:@@\@\"@\@\B" A\B"8A\0B"dA\`B"A\BBB"A\B"A\ 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GetProcAddressExitProcessHeapAllocHeapReAllocZRaiseExceptionRtlUnwindMultiByteToWideCharLCMapStringAzWideCharToMultiByteLCMapStringW[GetCPInfoRGetACPGetOEMCPIsValidCodePage4TlsGetValue2TlsAlloc5TlsSetValue3TlsFreeSetLastErrorGetCurrentThreadIdSetHandleCount;GetStdHandleGetFileType9GetStartupInfoAWriteFileGetModuleFileNameAJFreeEnvironmentStringsAGetEnvironmentStringsKFreeEnvironmentStringsWGetEnvironmentStringsWHeapCreateWVirtualFreeTQueryPerformanceCounterfGetTickCountGetCurrentProcessIdOGetSystemTimeAsFileTimeCCloseHandleHeapSizeTVirtualAllochReadFileGetConsoleCPGetConsoleModeAFlushFileBuffersSetFilePointerLoadLibraryAInitializeCriticalSectionAndSpinCountmGetUserDefaultLCIDGetLocaleInfoAEnumSystemLocalesAIsValidLocale=GetStringTypeA@GetStringTypeWxCreateFileAGetLocaleInfoWSetStdHandleWriteConsoleAGetConsoleOutputCPWriteConsoleWCreateFileWSetEndOfFile#GetProcessHeapKERNEL32.dllGetModuleHandleA@C@C@CB.?AV_Locimp@locale@std@@@C B`B`BdBhBpBpBxBBBBBBB@C@C Copyright (c) 1992-2004 by P.J. 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