Hardware Specifications

Stage Structure Conceptual Diagram

	1	2	3	4	5	6	7	8	9
inst.1	p.fetch	fetch	decode	read	exec	post	write
inst.2		p.fetch	fetch	decode	read	exec	post	write
inst.3			p.fetch	fetch	decode	read	exec	post	write

Flow control (when the PC changes by +2)

	1	2	3	4	5	6	7	8	9	10
inst.1	p.fetch	fetch	decode	ifb	STALL
inst.2		p.fetch	fetch	drop
inst.3			p.fetch	fetch	decode	read	exec	post	write
inst.4				p.fetch	fetch	decode	read	exec	post	write

Flow control (when the PC changes by +3 or more)

	1	2	3	4	5	6	7	8	9	10	11
inst.1	p.fetch	fetch	decode	ifb	STALL
inst.2		p.fetch	decode	drop
inst.3			p.fetch	drop
inst.n				p.fetch	fetch	decode	read	exec	post	write
inst.n+1					p.fetch	fetch	decode	read	exec	post	write

Assuming a forced stall for 3 clock cycles when the mova instruction is executed

	1	2	3	4	5	6	7	8	9	10	11	12
mova	p.fetch	fetch	decode	read	mova	write
inst.2		p.fetch	fetch	decode	STALL			read	exec	post	write
inst.3			p.fetch	fetch	STALL			decode	read	exec	post	write

Assuming another fetch is performed when the mova instruction is executed

	1	2	3	4	5	6	7	8	9	10	11	12	13
mova	p.fetch	fetch	decode	read	mova	STALL
inst.2		p.fetch	fetch	decode	p.fetch	fetch	decode	read	exec	post	write
inst.3			p.fetch	fetch	drop	p.fetch	fetch	decode	read	exec	post	write
inst.4				p.fetch	drop		p.fetch	fetch	decode	read	exec	post	write

When two instructions can execute in parallel (when read can overlap write of the previous instruction)

	1	2	3	4	5	6	7	8	9	10	11
dp3	fetch	decode	read	MUL	ADD	ADD	write
mad	p.fetch	fetch	decode	read	MUL	STALL	ADD	write
add		p.fetch	fetch	decode	STALL		read	ADD	write
add			p.fetch	fetch	STALL		decode	read	ADD	write
add				p.fetch	STALL		fetch	decode	read	ADD	write

When dp3 and mad are called in succession repeatedly without any concern for the ability to run in parallel

	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20
dp3	fetch	decode	read	MUL	ADD	ADD	write
mad	p.fetch	fetch	decode	read	MUL	STALL	ADD	write
dp3		p.fetch	fetch	decode	read	MUL	STALL	ADD	ADD	write
mad			p.fetch	fetch	decode	read	MUL	STALL		ADD	write
dp3				p.fetch	fetch	decode	read	MUL	STALL		ADD	ADD	write
mad					p.fetch	fetch	decode	read	MUL	STALL			ADD	write
dp3						p.fetch	fetch	decode	read	MUL	STALL			ADD	ADD	write
mad							p.fetch	fetch	decode	read	MUL	STALL				ADD	write
dp3								p.fetch	fetch	decode	read	MUL	STALL				ADD	ADD	write
mad									p.fetch	fetch	decode	read	MUL	STALL					ADD	write

When two instructions are executed in parallel and the combination of dp3 and mad are called repeatedly

	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24
dp3	fetch	decode	read	MUL	ADD	ADD	write
mad	p.fetch	fetch	decode	read	MUL	STALL	ADD	write
dp3		p.fetch	fetch	decode	wait 1		read	MUL	ADD	ADD	write
mad			p.fetch	fetch	wait 1		decode	read	MUL	STALL	ADD	write
dp3				p.fetch	wait 1		fetch	decode	wait 1		read	MUL	ADD	ADD	write
mad							p.fetch	fetch	wait 1		decode	read	MUL	STALL	ADD	write
dp3								p.fetch	wait 1		fetch	decode	wait 1		read	MUL	ADD	ADD	write
mad											p.fetch	fetch	wait 1		decode	read	MUL	STALL	ADD	write
dp3												p.fetch	wait 1		fetch	decode	wait 1		read	MUL	ADD	ADD	write
mad															p.fetch	fetch	wait 1		decode	read	MUL	STALL	ADD	write

Details for when sincos has been called

	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29	30
mov	fetch	decode	read	write
mov	p.fetch	fetch	decode	read	write
mul		p.fetch	fetch	decode	read	MUL	write
mad			p.fetch	fetch	decode	STALL		read	MUL	ADD	write
mad				p.fetch	fetch	STALL		decode	STALL			read	MUL	ADD	write
mad					p.fetch	STALL		fetch	STALL			decode	STALL			read	MUL	ADD	write
mov								p.fetch	STALL			fetch	STALL			decode	read	write
mad												p.fetch	STALL			fetch	decode	STALL		read	MUL	ADD	write
mad																p.fetch	fetch	STALL		decode	STALL			read	MUL	ADD	write
mul																	p.fetch	STALL		fetch	STALL			decode	STALL			read	MUL	write

When two instructions are executed in parallel and dp4 is called repeatedly

	1	2	3	4	5	6	7	8	9	10	11	12
dp4	fetch	decode	read	MUL	ADD	ADD	write
dp4	p.fetch	fetch	decode	read	MUL	ADD	ADD	write
dp4		p.fetch	fetch	decode	wait 1		read	MUL	ADD	ADD	write
dp4			p.fetch	fetch	wait		decode	read	MUL	ADD	ADD	write

When the write of dp4 is cancelled by mov, and mul stalls due to dp4

	1	2	3	4	5	6	7	8	9	10	11	12	13
dp4	fetch	decode	read	MUL	ADD	ADD	cancel
mov	p.fetch	fetch	decode	read	write
mul		p.fetch	fetch	decode	STALL			read	MUL	write
dp4			p.fetch	fetch	STALL			decode	read	MUL	ADD	ADD	write

When the write of dp4 is cancelled by mov, but mul can execute even though the execution of dp4 is not complete

	1	2	3	4	5	6	7	8	9	10
dp4	fetch	decode	read	MUL	ADD	ADD	cancel
mov	p.fetch	fetch	decode	read	write
mul		p.fetch	fetch	decode	read	MUL	write
dp4			p.fetch	fetch	decode	read	MUL	ADD	ADD	write

When the write of dp4 is cancelled by mov, and mul cannot execute until the execution of dp4 has ended (only write is cancelled)

	1	2	3	4	5	6	7	8	9	10	11	12
dp4	fetch	decode	read	MUL	ADD	ADD	cancel
mov	p.fetch	fetch	decode	read	write
mul		p.fetch	fetch	decode	wait		read	MUL	write
dp4			p.fetch	fetch	wait		decode	read	MUL	ADD	ADD	write

	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20
test		p.fetch	fetch		exec	drop	STALL	read	wait	write	cancel	branch	if	call	ret	jump	loop	break
test	ADD	MUL	EXP		LOG		FLOOR	MAX	MIN	mova				RCP / RSQ		CMP		NOP	LITP
ifb	fetch		branch
...		fetch
...			fetch
...				fetch		exec
...					fetch		exec

FLOOR

EXP