Lines Matching refs:r0
41 and r0, r1, #HW_C1_DCACHE_ENABLE in DC_Enable()
42 mov r0, r0, LSR #HW_C1_DCACHE_ENABLE_SHIFT in DC_Enable()
60 and r0, r1, #HW_C1_DCACHE_ENABLE in DC_Disable()
61 mov r0, r0, LSR #HW_C1_DCACHE_ENABLE_SHIFT in DC_Disable()
79 cmp r0, #0 in DC_Restore()
84 and r0, r1, #HW_C1_DCACHE_ENABLE in DC_Restore()
85 mov r0, r0, LSR #HW_C1_DCACHE_ENABLE_SHIFT in DC_Restore()
106 mov r0, #0 in DC_InvalidateAll()
107 mcr p15, 0, r0, c7, c6, 0 in DC_InvalidateAll()
125 mov r0, #0 in DC_StoreAll()
127 orr r2, r1, r0 in DC_StoreAll()
129 add r0, r0, #HW_CACHE_LINE_SIZE in DC_StoreAll()
130 cmp r0, #HW_DCACHE_SIZE/4 in DC_StoreAll()
156 mov r0, #0 // r0: Line counter (0-DCACHE_SIZE/4) in DC_FlushAll()
159 orr r2, r1, r0 in DC_FlushAll()
162 add r0, r0, #HW_CACHE_LINE_SIZE in DC_FlushAll()
163 cmp r0, #HW_DCACHE_SIZE/4 in DC_FlushAll()
188 add r1, r1, r0 in DC_InvalidateRange()
189 bic r0, r0, #HW_CACHE_LINE_SIZE - 1 in DC_InvalidateRange()
192 mcr p15, 0, r0, c7, c6, 1 in DC_InvalidateRange()
193 add r0, r0, #HW_CACHE_LINE_SIZE in DC_InvalidateRange()
194 cmp r0, r1 in DC_InvalidateRange()
212 add r1, r1, r0 in DC_StoreRange()
213 bic r0, r0, #HW_CACHE_LINE_SIZE - 1 in DC_StoreRange()
216 mcr p15, 0, r0, c7, c10, 1 in DC_StoreRange()
217 add r0, r0, #HW_CACHE_LINE_SIZE in DC_StoreRange()
218 cmp r0, r1 in DC_StoreRange()
237 add r1, r1, r0 in DC_FlushRange()
238 bic r0, r0, #HW_CACHE_LINE_SIZE - 1 in DC_FlushRange()
241 mcr p15, 0, r0, c7, c14, 1 /* flush */ in DC_FlushRange()
242 add r0, r0, #HW_CACHE_LINE_SIZE in DC_FlushRange()
243 cmp r0, r1 in DC_FlushRange()
264 add r1, r1, r0 in DC_TouchRange()
265 bic r0, r0, #HW_CACHE_LINE_SIZE - 1 in DC_TouchRange()
268 pld [r0] in DC_TouchRange()
269 add r0, r0, #HW_CACHE_LINE_SIZE in DC_TouchRange()
270 cmp r0, r1 in DC_TouchRange()
287 add r1, r1, r0 // r1: End address in DC_LockdownRange()
288 bic r0, r0, #HW_CACHE_LINE_SIZE - 1 in DC_LockdownRange()
292 mvneq r0, #0 in DC_LockdownRange()
295 stmfd sp!, { lr, r0, r1 } in DC_LockdownRange()
296 ldr r0, =OS_DisableInterrupts in DC_LockdownRange()
297 blx r0 in DC_LockdownRange()
298 mov r2, r0 in DC_LockdownRange()
299 ldmfd sp!, { lr, r0, r1 } in DC_LockdownRange()
305 mcr p15, 0, r0, c7, c14, 1 // Clean/disable data in cache once in DC_LockdownRange()
306 ldr r12, [r0] // Read data and place in cache in DC_LockdownRange()
307 add r0, r0, #HW_CACHE_LINE_SIZE in DC_LockdownRange()
308 cmp r0, r1 in DC_LockdownRange()
311 bic r0, r3, #HW_C9_LOCKDOWN_LOAD_MODE in DC_LockdownRange()
315 mov r0, r2 in DC_LockdownRange()
353 subs r3, r3, r0 in DC_Unlockdown()
371 mov r0, #0 in DC_WaitWriteBufferEmpty()
372 mcr p15, 0, r0, c7, c10, 4 in DC_WaitWriteBufferEmpty()
392 and r0, r1, #HW_C1_ICACHE_ENABLE in IC_Enable()
393 mov r0, r0, LSR #HW_C1_ICACHE_ENABLE_SHIFT in IC_Enable()
411 and r0, r1, #HW_C1_ICACHE_ENABLE in IC_Disable()
412 mov r0, r0, LSR #HW_C1_ICACHE_ENABLE_SHIFT in IC_Disable()
430 cmp r0, #0 in IC_Restore()
435 and r0, r1, #HW_C1_ICACHE_ENABLE in IC_Restore()
436 mov r0, r0, LSR #HW_C1_ICACHE_ENABLE_SHIFT in IC_Restore()
457 mov r0, #0 in IC_InvalidateAll()
458 mcr p15, 0, r0, c7, c5, 0 in IC_InvalidateAll()
474 add r1, r1, r0 in IC_InvalidateRange()
475 bic r0, r0, #HW_CACHE_LINE_SIZE - 1 in IC_InvalidateRange()
478 mcr p15, 0, r0, c7, c5, 1 in IC_InvalidateRange()
479 add r0, r0, #HW_CACHE_LINE_SIZE in IC_InvalidateRange()
480 cmp r0, r1 in IC_InvalidateRange()
497 add r1, r1, r0 in IC_PrefetchRange()
498 bic r0, r0, #HW_CACHE_LINE_SIZE - 1 in IC_PrefetchRange()
501 mcr p15, 0, r0, c7, c13, 1 in IC_PrefetchRange()
502 add r0, r0, #HW_CACHE_LINE_SIZE in IC_PrefetchRange()
503 cmp r0, r1 in IC_PrefetchRange()
523 add r1, r1, r0 // r1: End address in IC_LockdownRange()
524 bic r0, r0, #HW_CACHE_LINE_SIZE - 1 in IC_LockdownRange()
528 mvneq r0, #0 in IC_LockdownRange()
531 stmfd sp!, { lr, r0, r1 } in IC_LockdownRange()
532 ldr r0, =OS_DisableInterrupts in IC_LockdownRange()
533 blx r0 in IC_LockdownRange()
534 mov r2, r0 in IC_LockdownRange()
535 ldmfd sp!, { lr, r0, r1 } in IC_LockdownRange()
541 mcr p15, 0, r0, c7, c5, 1 // Disable from cache once in IC_LockdownRange()
542 mcr p15, 0, r0, c7, c13, 1 // Prefetch in IC_LockdownRange()
543 add r0, r0, #HW_CACHE_LINE_SIZE in IC_LockdownRange()
544 cmp r0, r1 in IC_LockdownRange()
547 bic r0, r3, #HW_C9_LOCKDOWN_LOAD_MODE in IC_LockdownRange()
551 mov r0, r2 in IC_LockdownRange()
592 subs r3, r3, r0 in IC_Unlockdown()