Lines Matching refs:HW_MAIN_MEM
68 #define HW_TWL_CARD_ROM_HEADER_BUF (HW_MAIN_MEM + 0x00ffc000)
81 #define HW_SYSM_VER_INFO_CONTENT_ID (HW_MAIN_MEM + 0x00ffd7b0 ) // 8-byte, NULL-terminated cont…
82 #define HW_SYSM_VER_INFO_CONTENT_LAST_INITIAL_CODE (HW_MAIN_MEM + 0x00ffd7b9 )
87 #define HW_SYSM_DISABLE_SET_HOTBOOT (HW_MAIN_MEM + 0x00ffd7ba )
92 #define HW_SD_NAND_CONTEXT_BUF (HW_MAIN_MEM + 0x00ffd7bc ) // NAND context data for the SD driv…
93 #define HW_SD_NAND_CONTEXT_BUF_END (HW_MAIN_MEM + 0x00ffd800 )
98 #define HW_OS_TITLE_ID_LIST (HW_MAIN_MEM + 0x00ffd800 ) // User TitleID list
104 #define HW_TWL_FS_MOUNT_INFO_BUF (HW_MAIN_MEM + 0x00ffdc00 ) // Mount information (A…
105 #define HW_TWL_FS_BOOT_SRL_PATH_BUF (HW_MAIN_MEM + 0x00ffdfc0 ) // Path to the SRL file…
110 #define HW_TWL_ROM_HEADER_BUF (HW_MAIN_MEM + 0x00ffe000)
133 #define HW_RED_RESERVED (HW_MAIN_MEM + 0x00fff800)
141 #define HW_CARD_ROM_HEADER (HW_MAIN_MEM + 0x00fffa80)
145 #define HW_DOWNLOAD_PARAMETER (HW_MAIN_MEM + 0x00fffbe0)
149 #define HW_MAIN_MEM_SYSTEM (HW_MAIN_MEM + 0x00fffc00)
156 #define HW_WRAM_EX_LOCK_BUF (HW_MAIN_MEM + 0x00fff680) // WRAM lock buffer (END-0x…
157 #define HW_WRAM_EX_LOCK_BUF_END (HW_MAIN_MEM + 0x00fff684) // (END-0x…
158 #define HW_RESET_LOCK_FLAG_BUF (HW_MAIN_MEM + 0x00fff684) // (END-0x…
159 #define HW_RESET_LOCK_FLAG_BUF_END (HW_MAIN_MEM + 0x00fff688) // (END-0x…
164 #define HW_BOOT_CHECK_INFO_BUF (HW_MAIN_MEM + 0x00fffc00) // Boot check info (END-0x4…
165 #define HW_BOOT_CHECK_INFO_BUF_END (HW_MAIN_MEM + 0x00fffc20) // (END-0x3…
167 #define HW_RESET_PARAMETER_BUF (HW_MAIN_MEM + 0x00fffc20) // reset parameter (END-0x3…
169 #define HW_BOOT_SHAKEHAND_9 (HW_MAIN_MEM + 0x00fffc24) // to shake hand with ARM7 …
170 #define HW_BOOT_SHAKEHAND_7 (HW_MAIN_MEM + 0x00fffc26) // to shake hand with ARM9 …
171 #define HW_BOOT_SYNC_PHASE (HW_MAIN_MEM + 0x00fffc28) // to synchronize ARM7/ARM9…
174 #define HW_ROM_BASE_OFFSET_BUF (HW_MAIN_MEM + 0x00fffc2c) // ROM offset of own progra…
175 #define HW_ROM_BASE_OFFSET_BUF_END (HW_MAIN_MEM + 0x00fffc30) // …
177 #define HW_CTRDG_MODULE_INFO_BUF (HW_MAIN_MEM + 0x00fffc30) // Cartridge module info (E…
178 #define HW_CTRDG_MODULE_INFO_BUF_END (HW_MAIN_MEM + 0x00fffc3c) // (E…
180 #define HW_VBLANK_COUNT_BUF (HW_MAIN_MEM + 0x00fffc3c) // VBlank counter (END-0x3c…
182 #define HW_WM_BOOT_BUF (HW_MAIN_MEM + 0x00fffc40) // WM buffer for Multi-Boot…
183 #define HW_WM_BOOT_BUF_END (HW_MAIN_MEM + 0x00fffc80) // …
185 #define HW_NVRAM_USER_INFO (HW_MAIN_MEM + 0x00fffc80) // NVRAM user info (END-0x3…
186 #define HW_NVRAM_USER_INFO_END (HW_MAIN_MEM + 0x00fffd68) // …
187 #define HW_HW_SECURE_INFO (HW_MAIN_MEM + 0x00fffd68) // Secure system information (END-0x29…
188 #define HW_HW_SECURE_INFO_END (HW_MAIN_MEM + 0x00fffd80) // (END-0…
190 #define HW_BIOS_EXCP_STACK_MAIN (HW_MAIN_MEM + 0x00fffd80) // MAINP Debugger monitor e…
191 #define HW_BIOS_EXCP_STACK_MAIN_END (HW_MAIN_MEM + 0x00fffd9c) // …
192 #define HW_EXCP_VECTOR_MAIN (HW_MAIN_MEM + 0x00fffd9c) // HW_EXCP_VECTOR_BUF for M…
194 #define HW_ARENA_INFO_BUF (HW_MAIN_MEM + 0x00fffda0) // Arena data structure (27…
195 #define HW_REAL_TIME_CLOCK_BUF (HW_MAIN_MEM + 0x00fffde8) // RTC
197 #define HW_SYS_CONF_BUF (HW_MAIN_MEM + 0x00fffdf0) // System config data (END-…
198 #define HW_SYS_CONF_BUF_END (HW_MAIN_MEM + 0x00fffdf6) // (END-…
200 #define HW_PRINT_OUTPUT_ARM9 (HW_MAIN_MEM + 0x00fffdf6) // debug print window for A…
201 #define HW_PRINT_OUTPUT_ARM7 (HW_MAIN_MEM + 0x00fffdf7) // debug print window for A…
202 #define HW_PRINT_OUTPUT_ARM9ERR (HW_MAIN_MEM + 0x00fffdf8) // debug print window for A…
203 #define HW_PRINT_OUTPUT_ARM7ERR (HW_MAIN_MEM + 0x00fffdf9) // debug print window for A…
205 #define HW_NAND_FIRM_HOTSTART_FLAG (HW_MAIN_MEM + 0x00fffdfa) // debug print window for A…
206 #define HW_TWL_RED_LAUNCHER_VER (HW_MAIN_MEM + 0x00fffdfb) // RED launcher version
207 #define HW_PRELOAD_PARAMETER_ADDR (HW_MAIN_MEM + 0x00fffdfc) // preload parameter address
209 #define HW_ROM_HEADER_BUF (HW_MAIN_MEM + 0x00fffe00) // ROM-internal registratio…
210 #define HW_ROM_HEADER_BUF_END (HW_MAIN_MEM + 0x00ffff60) // …
211 #define HW_ISD_RESERVED (HW_MAIN_MEM + 0x00ffff60) // IS DEBUGGER Reserved (EN…
212 #define HW_ISD_RESERVED_END (HW_MAIN_MEM + 0x00ffff80) // (EN…
214 #define HW_PXI_SIGNAL_PARAM_ARM9 (HW_MAIN_MEM + 0x00ffff80) // PXI Signal Param for ARM9
215 #define HW_PXI_SIGNAL_PARAM_ARM7 (HW_MAIN_MEM + 0x00ffff84) // PXI Signal Param for ARM7
216 #define HW_PXI_HANDLE_CHECKER_ARM9 (HW_MAIN_MEM + 0x00ffff88) // PXI Handle Checker for A…
217 #define HW_PXI_HANDLE_CHECKER_ARM7 (HW_MAIN_MEM + 0x00ffff8c) // PXI Handle Checker for A…
219 #define HW_MIC_LAST_ADDRESS (HW_MAIN_MEM + 0x00ffff90) // MIC new sampling data st…
220 #define HW_MIC_SAMPLING_DATA (HW_MAIN_MEM + 0x00ffff94) // MIC individual sampling …
222 #define HW_WM_CALLBACK_CONTROL (HW_MAIN_MEM + 0x00ffff96) // Parameter to synchronize…
223 #define HW_WM_RSSI_POOL (HW_MAIN_MEM + 0x00ffff98) // Random number source dep…
225 #define HW_SET_CTRDG_MODULE_INFO_ONCE (HW_MAIN_MEM + 0x00ffff9a) // set ctrdg module info fl…
226 #define HW_IS_CTRDG_EXIST (HW_MAIN_MEM + 0x00ffff9b) // ctrdg exist flag
228 #define HW_COMPONENT_PARAM (HW_MAIN_MEM + 0x00ffff9c) // Parameter for component …
230 #define HW_THREADINFO_MAIN (HW_MAIN_MEM + 0x00ffffa0) // ThreadInfo for Main proc…
231 #define HW_THREADINFO_SUB (HW_MAIN_MEM + 0x00ffffa4) // ThreadInfo for subproces…
232 #define HW_BUTTON_XY_BUF (HW_MAIN_MEM + 0x00ffffa8) // buffer for X and Y button
233 #define HW_TOUCHPANEL_BUF (HW_MAIN_MEM + 0x00ffffaa) // buffer for touch panel
234 #define HW_AUTOLOAD_SYNC_BUF (HW_MAIN_MEM + 0x00ffffae) // buffer for autoload sync
236 #define HW_LOCK_ID_FLAG_MAIN (HW_MAIN_MEM + 0x00ffffb0) // lockID flag for Main pro…
237 #define HW_LOCK_ID_FLAG_SUB (HW_MAIN_MEM + 0x00ffffb8) // lockID flag for subproce…
240 #define HW_VRAM_C_LOCK_BUF (HW_MAIN_MEM + 0x00ffffc0) // VRAM-C lock buffer (END-…
241 #define HW_VRAM_D_LOCK_BUF (HW_MAIN_MEM + 0x00ffffc8) // VRAM-D lock buffer (END-…
242 #define HW_WRAM_BLOCK0_LOCK_BUF (HW_MAIN_MEM + 0x00ffffd0) // CPU internal work RAM - …
243 #define HW_WRAM_BLOCK1_LOCK_BUF (HW_MAIN_MEM + 0x00ffffd8) // CPU internal work RAM - …
244 #define HW_CARD_LOCK_BUF (HW_MAIN_MEM + 0x00ffffe0) // Game Card - lock buffer …
245 #define HW_CTRDG_LOCK_BUF (HW_MAIN_MEM + 0x00ffffe8) // DS Pak - lock buffer (EN…
246 #define HW_INIT_LOCK_BUF (HW_MAIN_MEM + 0x00fffff0) // Initialization lock buff…
248 #define HW_MMEMCHECKER_MAIN (HW_MAIN_MEM + 0x00fffff8) // MainMemory Size Checker …
249 #define HW_MMEMCHECKER_SUB (HW_MAIN_MEM + 0x00fffffa) // MainMemory Size Checker …
251 #define HW_CHIPTYPE_FLAG (HW_MAIN_MEM + 0x00fffffc) // chiptype flag (END-4)
253 #define HW_CMD_AREA (HW_MAIN_MEM + 0x00fffffe) // Main memory command issu…