Lines Matching refs:wordcnt
719 #define REG_MI_DMA0CNT_FIELD( e, i, mode, sb, cm, sar, dar, wordcnt ) \ argument
728 ((u32)(wordcnt) << REG_MI_DMA0CNT_WORDCNT_SHIFT))
793 #define REG_MI_DMA1CNT_FIELD( e, i, mode, sb, cm, sar, dar, wordcnt ) \ argument
802 ((u32)(wordcnt) << REG_MI_DMA1CNT_WORDCNT_SHIFT))
867 #define REG_MI_DMA2CNT_FIELD( e, i, mode, sb, cm, sar, dar, wordcnt ) \ argument
876 ((u32)(wordcnt) << REG_MI_DMA2CNT_WORDCNT_SHIFT))
941 #define REG_MI_DMA3CNT_FIELD( e, i, mode, sb, cm, sar, dar, wordcnt ) \ argument
950 ((u32)(wordcnt) << REG_MI_DMA3CNT_WORDCNT_SHIFT))
1026 #define REG_MI_NDMA0WCNT_FIELD( wordcnt ) \ argument
1028 ((u32)(wordcnt) << REG_MI_NDMA0WCNT_WORDCNT_SHIFT))
1106 #define REG_MI_NDMA0CNT_FIELD( e, i, cm, im, mode, wordcnt, srl, sar, drl, dar ) \ argument
1113 ((u32)(wordcnt) << REG_MI_NDMA0CNT_WORDCNT_SHIFT) | \
1167 #define REG_MI_NDMA1WCNT_FIELD( wordcnt ) \ argument
1169 ((u32)(wordcnt) << REG_MI_NDMA1WCNT_WORDCNT_SHIFT))
1247 #define REG_MI_NDMA1CNT_FIELD( e, i, cm, im, mode, wordcnt, srl, sar, drl, dar ) \ argument
1254 ((u32)(wordcnt) << REG_MI_NDMA1CNT_WORDCNT_SHIFT) | \
1308 #define REG_MI_NDMA2WCNT_FIELD( wordcnt ) \ argument
1310 ((u32)(wordcnt) << REG_MI_NDMA2WCNT_WORDCNT_SHIFT))
1388 #define REG_MI_NDMA2CNT_FIELD( e, i, cm, im, mode, wordcnt, srl, sar, drl, dar ) \ argument
1395 ((u32)(wordcnt) << REG_MI_NDMA2CNT_WORDCNT_SHIFT) | \
1449 #define REG_MI_NDMA3WCNT_FIELD( wordcnt ) \ argument
1451 ((u32)(wordcnt) << REG_MI_NDMA3WCNT_WORDCNT_SHIFT))
1529 #define REG_MI_NDMA3CNT_FIELD( e, i, cm, im, mode, wordcnt, srl, sar, drl, dar ) \ argument
1536 ((u32)(wordcnt) << REG_MI_NDMA3CNT_WORDCNT_SHIFT) | \