Lines Matching refs:add
129 add r0, r0, #HW_CACHE_LINE_SIZE in DC_StoreAll()
133 add r1, r1, #1<<HW_C7_CACHE_SET_NO_SHIFT in DC_StoreAll()
162 add r0, r0, #HW_CACHE_LINE_SIZE in DC_FlushAll()
166 add r1, r1, #1<<HW_C7_CACHE_SET_NO_SHIFT in DC_FlushAll()
188 add r1, r1, r0 in DC_InvalidateRange()
193 add r0, r0, #HW_CACHE_LINE_SIZE in DC_InvalidateRange()
212 add r1, r1, r0 in DC_StoreRange()
217 add r0, r0, #HW_CACHE_LINE_SIZE in DC_StoreRange()
237 add r1, r1, r0 in DC_FlushRange()
242 add r0, r0, #HW_CACHE_LINE_SIZE in DC_FlushRange()
264 add r1, r1, r0 in DC_TouchRange()
269 add r0, r0, #HW_CACHE_LINE_SIZE in DC_TouchRange()
287 add r1, r1, r0 // r1: End address in DC_LockdownRange()
307 add r0, r0, #HW_CACHE_LINE_SIZE in DC_LockdownRange()
310 add r3, r3, #1 // Cache normal mode & set number increment in DC_LockdownRange()
474 add r1, r1, r0 in IC_InvalidateRange()
479 add r0, r0, #HW_CACHE_LINE_SIZE in IC_InvalidateRange()
497 add r1, r1, r0 in IC_PrefetchRange()
502 add r0, r0, #HW_CACHE_LINE_SIZE in IC_PrefetchRange()
523 add r1, r1, r0 // r1: End address in IC_LockdownRange()
543 add r0, r0, #HW_CACHE_LINE_SIZE in IC_LockdownRange()
546 add r3, r3, #1 // Cache normal mode & set number increment in IC_LockdownRange()