Lines Matching refs:num
79 void MIi_SetWramBank_A( int num, MIWramProc proc, MIWramOffset offset, MIWramEnable enable ) in MIi_SetWramBank_A() argument
81 SDK_ASSERT( 0<=num && num<MI_WRAM_A_MAX_NUM ); in MIi_SetWramBank_A()
85 *(vu8*)(REG_MBK_A0_ADDR + num) in MIi_SetWramBank_A()
90 void MIi_SetWramBank_B( int num, MIWramProc proc, MIWramOffset offset, MIWramEnable enable ) in MIi_SetWramBank_B() argument
92 SDK_ASSERT( 0<=num && num<MI_WRAM_B_MAX_NUM ); in MIi_SetWramBank_B()
94 *(vu8*)(REG_MBK_B0_ADDR + num) in MIi_SetWramBank_B()
99 void MIi_SetWramBank_C( int num, MIWramProc proc, MIWramOffset offset, MIWramEnable enable ) in MIi_SetWramBank_C() argument
101 SDK_ASSERT( 0<=num && num<MI_WRAM_C_MAX_NUM ); in MIi_SetWramBank_C()
103 *(vu8*)(REG_MBK_C0_ADDR + num) in MIi_SetWramBank_C()
108 void MIi_SetWramBank( MIWramPos wram, int num, MIWramProc proc, MIWramOffset offset, MIWramEnable e… in MIi_SetWramBank() argument
116 (f[wram])( num, proc, offset, enable ); in MIi_SetWramBank()
128 vu8 MIi_GetWramBank_A( int num ) in MIi_GetWramBank_A() argument
130 SDK_ASSERT( 0<=num && num<MI_WRAM_A_MAX_NUM ); in MIi_GetWramBank_A()
131 return *(vu8*)(REG_MBK_A0_ADDR + num); in MIi_GetWramBank_A()
134 vu8 MIi_GetWramBank_B( int num ) in MIi_GetWramBank_B() argument
136 SDK_ASSERT( 0<=num && num<MI_WRAM_B_MAX_NUM ); in MIi_GetWramBank_B()
137 return *(vu8*)(REG_MBK_B0_ADDR + num); in MIi_GetWramBank_B()
140 vu8 MIi_GetWramBank_C( int num ) in MIi_GetWramBank_C() argument
142 SDK_ASSERT( 0<=num && num<MI_WRAM_C_MAX_NUM ); in MIi_GetWramBank_C()
143 return *(vu8*)(REG_MBK_C0_ADDR + num); in MIi_GetWramBank_C()
146 static vu8 MIi_GetWramBank( MIWramPos wram, int num ) in MIi_GetWramBank() argument
154 return (f[wram])( num ); in MIi_GetWramBank()
172 void MIi_SetWramBankMaster_A( int num, MIWramProc proc ) in MIi_SetWramBankMaster_A() argument
174 vu8* p = (vu8*)(REG_MBK_A0_ADDR + num); in MIi_SetWramBankMaster_A()
176 SDK_ASSERT( 0<=num && num<MI_WRAM_A_MAX_NUM ); in MIi_SetWramBankMaster_A()
180 void MIi_SetWramBankMaster_B( int num, MIWramProc proc ) in MIi_SetWramBankMaster_B() argument
182 vu8* p = (vu8*)(REG_MBK_B0_ADDR + num); in MIi_SetWramBankMaster_B()
184 SDK_ASSERT( 0<=num && num<MI_WRAM_B_MAX_NUM ); in MIi_SetWramBankMaster_B()
188 void MIi_SetWramBankMaster_C( int num, MIWramProc proc ) in MIi_SetWramBankMaster_C() argument
190 vu8* p = (vu8*)(REG_MBK_C0_ADDR + num); in MIi_SetWramBankMaster_C()
192 SDK_ASSERT( 0<=num && num<MI_WRAM_C_MAX_NUM ); in MIi_SetWramBankMaster_C()
196 void MIi_SetWramBankMaster( MIWramPos wram, int num, MIWramProc proc ) in MIi_SetWramBankMaster() argument
203 (f[wram])( num, proc ); in MIi_SetWramBankMaster()
220 void MIi_SetWramBankEnable_A( int num, MIWramEnable enable ) in MIi_SetWramBankEnable_A() argument
222 vu8* p = (vu8*)(REG_MBK_A0_ADDR + num); in MIi_SetWramBankEnable_A()
224 SDK_ASSERT( 0<=num && num<MI_WRAM_A_MAX_NUM ); in MIi_SetWramBankEnable_A()
228 void MIi_SetWramBankEnable_B( int num, MIWramEnable enable ) in MIi_SetWramBankEnable_B() argument
230 vu8* p = (vu8*)(REG_MBK_B0_ADDR + num); in MIi_SetWramBankEnable_B()
232 SDK_ASSERT( 0<=num && num<MI_WRAM_B_MAX_NUM ); in MIi_SetWramBankEnable_B()
236 void MIi_SetWramBankEnable_C( int num, MIWramEnable enable ) in MIi_SetWramBankEnable_C() argument
238 vu8* p = (vu8*)(REG_MBK_C0_ADDR + num); in MIi_SetWramBankEnable_C()
240 SDK_ASSERT( 0<=num && num<MI_WRAM_C_MAX_NUM ); in MIi_SetWramBankEnable_C()
244 void MIi_SetWramBankEnable( MIWramPos wram, int num, MIWramEnable enable ) in MIi_SetWramBankEnable() argument
252 (f[wram])( num, enable ); in MIi_SetWramBankEnable()
269 MIWramProc MI_GetWramBankMaster_A( int num ) in MI_GetWramBankMaster_A() argument
271 SDK_ASSERT( 0<=num && num<MI_WRAM_A_MAX_NUM ); in MI_GetWramBankMaster_A()
272 return (MIWramProc)( *(REGType8v*)(REG_MBK_A0_ADDR + num) & MI_WRAM_MASTER_MASK_A ); in MI_GetWramBankMaster_A()
274 MIWramProc MI_GetWramBankMaster_B( int num ) in MI_GetWramBankMaster_B() argument
276 SDK_ASSERT( 0<=num && num<MI_WRAM_B_MAX_NUM ); in MI_GetWramBankMaster_B()
277 return (MIWramProc)( *(REGType8v*)(REG_MBK_B0_ADDR + num) & MI_WRAM_MASTER_MASK_B ); in MI_GetWramBankMaster_B()
279 MIWramProc MI_GetWramBankMaster_C( int num ) in MI_GetWramBankMaster_C() argument
281 SDK_ASSERT( 0<=num && num<MI_WRAM_C_MAX_NUM ); in MI_GetWramBankMaster_C()
282 return (MIWramProc)( *(REGType8v*)(REG_MBK_C0_ADDR + num) & MI_WRAM_MASTER_MASK_C ); in MI_GetWramBankMaster_C()
284 MIWramProc MI_GetWramBankMaster( MIWramPos wram, int num ) in MI_GetWramBankMaster() argument
292 return (f[wram])( num ); in MI_GetWramBankMaster()
321 MIWramOffset MI_GetWramBankOffset_A( int num ) in MI_GetWramBankOffset_A() argument
323 SDK_ASSERT( 0<=num && num<MI_WRAM_A_MAX_NUM ); in MI_GetWramBankOffset_A()
324 …return (MIWramOffset)( (*(REGType8v*)(REG_MBK_A0_ADDR + num) & MI_WRAM_OFFSET_MASK_A) >> MI_WRAM_O… in MI_GetWramBankOffset_A()
326 MIWramOffset MI_GetWramBankOffset_B( int num ) in MI_GetWramBankOffset_B() argument
328 SDK_ASSERT( 0<=num && num<MI_WRAM_B_MAX_NUM ); in MI_GetWramBankOffset_B()
329 …return (MIWramOffset)( (*(REGType8v*)(REG_MBK_B0_ADDR + num) & MI_WRAM_OFFSET_MASK_B) >> MI_WRAM_O… in MI_GetWramBankOffset_B()
331 MIWramOffset MI_GetWramBankOffset_C( int num ) in MI_GetWramBankOffset_C() argument
333 SDK_ASSERT( 0<=num && num<MI_WRAM_C_MAX_NUM ); in MI_GetWramBankOffset_C()
334 …return (MIWramOffset)( (*(REGType8v*)(REG_MBK_C0_ADDR + num) & MI_WRAM_OFFSET_MASK_C) >> MI_WRAM_O… in MI_GetWramBankOffset_C()
336 MIWramOffset MI_GetWramBankOffset( MIWramPos wram, int num ) in MI_GetWramBankOffset() argument
344 return (f[wram])( num ); in MI_GetWramBankOffset()
360 MIWramEnable MI_GetWramBankEnable_A( int num ) in MI_GetWramBankEnable_A() argument
362 SDK_ASSERT( 0<=num && num<MI_WRAM_A_MAX_NUM ); in MI_GetWramBankEnable_A()
363 …return (*(REGType8v*)(REG_MBK_A0_ADDR + num) & MI_WRAM_ENABLE_MASK_A)? MI_WRAM_ENABLE: MI_WRAM_DIS… in MI_GetWramBankEnable_A()
365 MIWramEnable MI_GetWramBankEnable_B( int num ) in MI_GetWramBankEnable_B() argument
367 SDK_ASSERT( 0<=num && num<MI_WRAM_B_MAX_NUM ); in MI_GetWramBankEnable_B()
368 …return (*(REGType8v*)(REG_MBK_B0_ADDR + num) & MI_WRAM_ENABLE_MASK_B)? MI_WRAM_ENABLE: MI_WRAM_DIS… in MI_GetWramBankEnable_B()
370 MIWramEnable MI_GetWramBankEnable_C( int num ) in MI_GetWramBankEnable_C() argument
372 SDK_ASSERT( 0<=num && num<MI_WRAM_C_MAX_NUM ); in MI_GetWramBankEnable_C()
373 …return (*(REGType8v*)(REG_MBK_C0_ADDR + num) & MI_WRAM_ENABLE_MASK_C)? MI_WRAM_ENABLE: MI_WRAM_DIS… in MI_GetWramBankEnable_C()
375 MIWramEnable MI_GetWramBankEnable( MIWramPos wram, int num ) in MI_GetWramBankEnable() argument
383 return (f[wram])( num ); in MI_GetWramBankEnable()
640 BOOL MI_IsWramSlotLocked_A( int num ) in MI_IsWramSlotLocked_A() argument
642 SDK_ASSERT( 0<=num && num<MI_WRAM_A_MAX_NUM ); in MI_IsWramSlotLocked_A()
644 return ( reg_MI_MBK_A_LOCK & (1 << (num+REG_MI_MBK_A_LOCK_A0_SHIFT)) )? TRUE: FALSE; in MI_IsWramSlotLocked_A()
646 BOOL MI_IsWramSlotLocked_B( int num ) in MI_IsWramSlotLocked_B() argument
648 SDK_ASSERT( 0<=num && num<MI_WRAM_B_MAX_NUM ); in MI_IsWramSlotLocked_B()
650 return ( reg_MI_MBK_B_LOCK & (1 << (num+REG_MI_MBK_B_LOCK_B0_SHIFT)) )? TRUE: FALSE; in MI_IsWramSlotLocked_B()
652 BOOL MI_IsWramSlotLocked_C( int num ) in MI_IsWramSlotLocked_C() argument
654 SDK_ASSERT( 0<=num && num<MI_WRAM_C_MAX_NUM ); in MI_IsWramSlotLocked_C()
656 return ( reg_MI_MBK_C_LOCK & (1 << (num+REG_MI_MBK_C_LOCK_C0_SHIFT)) )? TRUE: FALSE; in MI_IsWramSlotLocked_C()
658 BOOL MI_IsWramSlotLocked( MIWramPos wram, int num ) in MI_IsWramSlotLocked() argument
665 return (f[wram])( num ); in MI_IsWramSlotLocked()
744 static inline int MIi_GetReservation( MIWramPos wram, int num ) in MIi_GetReservation() argument
746 return (MIi_Info.wram[wram][num] & MI_MAN_WRAM_RESERVE_MASK)>>MI_MAN_WRAM_RESERVE_SHIFT; in MIi_GetReservation()
748 #define MIi_GetReservation_A(num) (MIi_GetReservation( MI_WRAM_A, (num) )) argument
749 #define MIi_GetReservation_B(num) (MIi_GetReservation( MI_WRAM_B, (num) )) argument
750 #define MIi_GetReservation_C(num) (MIi_GetReservation( MI_WRAM_C, (num) )) argument
752 static inline void MIi_SetReservation( MIWramPos wram, int num, int val) in MIi_SetReservation() argument
754 MIi_Info.wram[wram][num] = (u16)(MIi_Info.wram[wram][num] in MIi_SetReservation()
758 #define MIi_SetReservation_A(num,val) do{ MIi_SetReservation( MI_WRAM_A, (num), (val) ); } while(0) argument
759 #define MIi_SetReservation_B(num,val) do{ MIi_SetReservation( MI_WRAM_B, (num), (val) ); } while(0) argument
760 #define MIi_SetReservation_C(num,val) do{ MIi_SetReservation( MI_WRAM_C, (num), (val) ); } while(0) argument
762 static inline int MIi_GetMaster( MIWramPos wram, int num ) in MIi_GetMaster() argument
764 return (MIi_Info.wram[wram][num] & MI_MAN_WRAM_MASTER_MASK)>>MI_MAN_WRAM_MASTER_SHIFT; in MIi_GetMaster()
766 #define MIi_GetMaster_A(num) (MIi_GetMaster( MI_WRAM_A, (num) )) argument
767 #define MIi_GetMaster_B(num) (MIi_GetMaster( MI_WRAM_B, (num) )) argument
768 #define MIi_GetMaster_C(num) (MIi_GetMaster( MI_WRAM_C, (num) )) argument
770 static inline void MIi_SetMaster( MIWramPos wram, int num, int val) in MIi_SetMaster() argument
772 MIi_Info.wram[wram][num] = (u16)(MIi_Info.wram[wram][num] in MIi_SetMaster()
776 #define MIi_SetMaster_A(num,val) do{ MIi_SetMaster( MI_WRAM_A, (num), (val) ); } while(0) argument
777 #define MIi_SetMaster_B(num,val) do{ MIi_SetMaster( MI_WRAM_B, (num), (val) ); } while(0) argument
778 #define MIi_SetMaster_C(num,val) do{ MIi_SetMaster( MI_WRAM_C, (num), (val) ); } while(0) argument
782 static u32 MIi_GetAddress_A( int num ) in MIi_GetAddress_A() argument
784 return (u32)(MI_GetWramMapStart_A() + MI_WRAM_A_SLOT_SIZE * num ); in MIi_GetAddress_A()
786 static u32 MIi_GetAddress_B( int num ) in MIi_GetAddress_B() argument
788 return (u32)(MI_GetWramMapStart_B() + MI_WRAM_B_SLOT_SIZE * num ); in MIi_GetAddress_B()
790 static u32 MIi_GetAddress_C( int num ) in MIi_GetAddress_C() argument
792 return (u32)(MI_GetWramMapStart_C() + MI_WRAM_C_SLOT_SIZE * num ); in MIi_GetAddress_C()
794 static inline u32 MIi_GetAddress( MIWramPos wram, int num ) in MIi_GetAddress() argument
798 return MIi_GetAddress_A( num ); in MIi_GetAddress()
802 return MIi_GetAddress_B( num ); in MIi_GetAddress()
806 return MIi_GetAddress_C( num ); in MIi_GetAddress()