Lines Matching refs:r1
35 ADD r1,r1,r3
40 VLDMIA r1,{s0-s2} // First line of matrix p1 to registers [S0-S2]
41 ADD r1,r1,r3
44 VLDMIA r1,{s3-s5} // Second line of matrix p1 to registers [S3-S5]
45 ADD r1,r1,r3
48 VLDMIA r1,{s6-s8} // Third line of matrix p1 to registers [S6-S8]
88 ADD r1,r0,r3
89 VSTMIA r1,{s21-s23} // Store result
91 ADD r1,r1,r3
92 VSTMIA r1,{s24-s26} // Store result
105 ADD r1,r1,r3
115 VLDR.F32 s16,[r1,#3*4*0+4*0] // Matrix p1[0][0]
116 VLDR.F32 s17,[r1,#3*4*1+4*0] // Matrix p1[1][0]
121 VLDR.F32 s16,[r1,#3*4*2+4*0] // Matrix p1[2][0]
126 VLDR.F32 s17,[r1,#3*4*0+4*1] // Matrix p1[0][1]
131 VLDR.F32 s16,[r1,#3*4*1+4*1] // Matrix p1[1][1]
137 VLDR.F32 s17,[r1,#3*4*2+4*1] // Matrix p1[2][1]
142 VLDR.F32 s16,[r1,#3*4*0+4*2] // Matrix p1[0][2]
147 VLDR.F32 s17,[r1,#3*4*1+4*2] // Matrix p1[1][2]
152 VLDR.F32 s16,[r1,#3*4*2+4*2] // Matrix p1[2][2]
170 VLDMIA r1,{s18-s20} // First line of matrix p1 to registers [S18-S20]
171 ADD r1,r1,r3
174 VLDMIA r1,{s21-s23} // Second line of matrix p1 to registers [S21-S23]
175 ADD r1,r1,r3
178 VLDMIA r1,{s24-s26} // Third line of matrix p1 to registers [S24-S26]
218 ADD r1,r0,r3
219 ADD r2,r1,r3
221 VSTMIA r1,{s3-s5} // Store result