Lines Matching refs:c5
68 #define HW_GET_CP15_C5(o,v) HW_INST_MRC(p15,0,c5,c0,o,v) // Opcode_1 and CRm are fixed
101 #define HW_SET_CP15_C5(o,v) HW_INST_MCR(p15,0,c5,c0,o,v) // Opcode_1 and CRm are fixed
143 #define HW_GET_CP15_DATA_FAULT_STATUS(v) HW_INST_MRC(p15,0,c5,c0,0,v)
144 #define HW_GET_CP15_INSTRUCTION_FAULT_STATUS(v) HW_INST_MRC(p15,0,c5,c0,1,v)
152 #define HW_GET_CP15_ACCESS_PERMISSION(v) HW_INST_MRC(p15,0,c5,c0,0,v)
154 #define HW_GET_CP15_INSTRUCTION_ACCESS_PERMISSION(v) HW_INST_MRC(p15,0,c5,c0,1,v)
155 #define HW_GET_CP15_DATA_ACCESS_PERMISSION_EX(v) HW_INST_MRC(p15,0,c5,c0,2,v)
156 #define HW_GET_CP15_INSTRUCTION_ACCESS_PERMISSION_EX(v) HW_INST_MRC(p15,0,c5,c0,3,v)
162 #define HW_GET_CP15_PROTECTION_REGION_5(v) HW_INST_MRC(p15,0,c6,c5,0,v)
215 #define HW_GET_CP15_MAIN_TLB_LOCKDOWN_VA(v) HW_INST_MRC(p15,5,c15,c5,2,v)
229 #define HW_SET_CP15_DATA_FAULT_STATUS(v) HW_INST_MCR(p15,0,c5,c0,0,v)
230 #define HW_SET_CP15_INSTRUCTION_FAULT_STATUS(v) HW_INST_MCR(p15,0,c5,c0,1,v)
238 #define HW_SET_CP15_ACCESS_PERMISSION(v) HW_INST_MCR(p15,0,c5,c0,0,v)
240 #define HW_SET_CP15_INSTRUCTION_ACCESS_PERMISSION(v) HW_INST_MCR(p15,0,c5,c0,1,v)
241 #define HW_SET_CP15_DATA_ACCESS_PERMISSION_EX(v) HW_INST_MCR(p15,0,c5,c0,2,v)
242 #define HW_SET_CP15_INSTRUCTION_ACCESS_PERMISSION_EX(v) HW_INST_MCR(p15,0,c5,c0,3,v)
248 #define HW_SET_CP15_PROTECTION_REGION_5(v) HW_INST_MCR(p15,0,c6,c5,0,v)
254 #define HW_SET_CP15_INVALIDATE_ENTIRE_INSTRUCTION_CACHE(v) HW_INST_MCR(p15,0,c7,c5,0,v)
255 #define HW_SET_CP15_INVALIDATE_INSTRUCTION_CACHE_MVA(v) HW_INST_MCR(p15,0,c7,c5,1,v)
256 #define HW_SET_CP15_INVALIDATE_INSTRUCTION_CACHE_INDEX(v) HW_INST_MCR(p15,0,c7,c5,2,v)
257 #define HW_SET_CP15_FLUSH_PREFETCH_BUFFER(v) HW_INST_MCR(p15,0,c7,c5,4,v)
258 #define HW_SET_CP15_FLUSH_ENTIRE_BRANCH_TARGET_CACHE(v) HW_INST_MCR(p15,0,c7,c5,6,v)
259 #define HW_SET_CP15_FLUSH_BRANCH_TARGET_CACHE_ENTRY(v) HW_INST_MCR(p15,0,c7,c5,7,v)
276 #define HW_SET_CP15_INVALIDATE_INSTRUCTION_TLB(v) HW_INST_MCR(p15,0,c8,c5,0,v)
277 #define HW_SET_CP15_INVALIDATE_INSTRUCTION_TLB_SINGLE(v) HW_INST_MCR(p15,0,c8,c5,1,v)
278 #define HW_SET_CP15_INVALIDATE_INSTRUCTION_TLB_ASID(v) HW_INST_MCR(p15,0,c8,c5,2,v)
279 #define HW_SET_CP15_INVALIDATE_INSTRUCTION_TLB_MVA(v) HW_INST_MCR(p15,0,c8,c5,3,v)
337 #define HW_SET_CP15_MAIN_TLB_LOCKDOWN_VA(v) HW_INST_MCR(p15,5,c15,c5,2,v)
346 #define HW_CP15_INVALIDATE_ENTIRE_INSTRUCTION_CACHE() HW_INST_MCR(p15,0,c7,c5,0,0)
347 #define HW_CP15_FLUSH_PREFETCH_BUFFER() HW_INST_MCR(p15,0,c7,c5,4,0)
348 #define HW_CP15_FLUSH_ENTIRE_BRANCH_TARGET_CACHE() HW_INST_MCR(p15,0,c7,c5,6,0)
355 #define HW_CP15_INVALIDATE_INSTRUCTION_TLB() HW_INST_MCR(p15,0,c8,c5,0,0)