Lines Matching refs:c5

68 #define HW_GET_CP15_C5(o,v)         HW_INST_MRC(p15,0,c5,c0,o,v)    // Opcode_1 and CRm are fixed
97 #define HW_SET_CP15_C5(o,v)         HW_INST_MCR(p15,0,c5,c0,o,v)    // Opcode_1 and CRm are fixed
138 #define HW_GET_CP15_DATA_FAULT_STATUS(v)                HW_INST_MRC(p15,0,c5,c0,0,v)
139 #define HW_GET_CP15_INSTRUCTION_FAULT_STATUS(v)         HW_INST_MRC(p15,0,c5,c0,1,v)
147 #define HW_GET_CP15_ACCESS_PERMISSION(v)                HW_INST_MRC(p15,0,c5,c0,0,v)
149 #define HW_GET_CP15_INSTRUCTION_ACCESS_PERMISSION(v)    HW_INST_MRC(p15,0,c5,c0,1,v)
150 #define HW_GET_CP15_DATA_ACCESS_PERMISSION_EX(v)        HW_INST_MRC(p15,0,c5,c0,2,v)
151 #define HW_GET_CP15_INSTRUCTION_ACCESS_PERMISSION_EX(v) HW_INST_MRC(p15,0,c5,c0,3,v)
157 #define HW_GET_CP15_PROTECTION_REGION_5(v)              HW_INST_MRC(p15,0,c6,c5,0,v)
203 #define HW_GET_CP15_MAIN_TLB_LOCKDOWN_VA(v)             HW_INST_MRC(p15,5,c15,c5,2,v)
216 #define HW_SET_CP15_DATA_FAULT_STATUS(v)                HW_INST_MCR(p15,0,c5,c0,0,v)
217 #define HW_SET_CP15_INSTRUCTION_FAULT_STATUS(v)         HW_INST_MCR(p15,0,c5,c0,1,v)
225 #define HW_SET_CP15_ACCESS_PERMISSION(v)                HW_INST_MCR(p15,0,c5,c0,0,v)
227 #define HW_SET_CP15_INSTRUCTION_ACCESS_PERMISSION(v)    HW_INST_MCR(p15,0,c5,c0,1,v)
228 #define HW_SET_CP15_DATA_ACCESS_PERMISSION_EX(v)        HW_INST_MCR(p15,0,c5,c0,2,v)
229 #define HW_SET_CP15_INSTRUCTION_ACCESS_PERMISSION_EX(v) HW_INST_MCR(p15,0,c5,c0,3,v)
235 #define HW_SET_CP15_PROTECTION_REGION_5(v)              HW_INST_MCR(p15,0,c6,c5,0,v)
240 #define HW_SET_CP15_INVALIDATE_ENTIRE_INSTRUCTION_CACHE(v)      HW_INST_MCR(p15,0,c7,c5,0,v)
241 #define HW_SET_CP15_INVALIDATE_INSTRUCTION_CACHE_MVA(v)         HW_INST_MCR(p15,0,c7,c5,1,v)
242 #define HW_SET_CP15_INVALIDATE_INSTRUCTION_CACHE_INDEX(v)       HW_INST_MCR(p15,0,c7,c5,2,v)
243 #define HW_SET_CP15_FLUSH_PREFETCH_BUFFER(v)            HW_INST_MCR(p15,0,c7,c5,4,v)
244 #define HW_SET_CP15_FLUSH_ENTIRE_BRANCH_TARGET_CACHE(v) HW_INST_MCR(p15,0,c7,c5,6,v)
245 #define HW_SET_CP15_FLUSH_BRANCH_TARGET_CACHE_ENTRY(v)  HW_INST_MCR(p15,0,c7,c5,7,v)
262 #define HW_SET_CP15_INVALIDATE_INSTRUCTION_TLB(v)               HW_INST_MCR(p15,0,c8,c5,0,v)
263 #define HW_SET_CP15_INVALIDATE_INSTRUCTION_TLB_SINGLE(v)        HW_INST_MCR(p15,0,c8,c5,1,v)
264 #define HW_SET_CP15_INVALIDATE_INSTRUCTION_TLB_ASID(v)          HW_INST_MCR(p15,0,c8,c5,2,v)
265 #define HW_SET_CP15_INVALIDATE_INSTRUCTION_TLB_MVA(v)           HW_INST_MCR(p15,0,c8,c5,3,v)
316 #define HW_SET_CP15_MAIN_TLB_LOCKDOWN_VA(v)             HW_INST_MCR(p15,5,c15,c5,2,v)
325 #define HW_CP15_INVALIDATE_ENTIRE_INSTRUCTION_CACHE()   HW_INST_MCR(p15,0,c7,c5,0,0)
326 #define HW_CP15_FLUSH_PREFETCH_BUFFER()                 HW_INST_MCR(p15,0,c7,c5,4,0)
327 #define HW_CP15_FLUSH_ENTIRE_BRANCH_TARGET_CACHE()      HW_INST_MCR(p15,0,c7,c5,6,0)
334 #define HW_CP15_INVALIDATE_INSTRUCTION_TLB()            HW_INST_MCR(p15,0,c8,c5,0,0)