Lines Matching refs:HW_INST_MCR
41 #define HW_INST_MCR(a,b,c,d,e,v) __asm { mcr a,b,v,c,d,e } macro
93 #define HW_SET_CP15_C0(c,o,v) HW_INST_MCR(p15,0,c0,c,o,v) // Opcode_1 is fixed
94 #define HW_SET_CP15_C1(o,v) HW_INST_MCR(p15,0,c1,c0,o,v) // Opcode_1 and CRm are fixed
95 #define HW_SET_CP15_C2(o,v) HW_INST_MCR(p15,0,c2,c0,o,v) // Opcode_1 and CRm are fixed
96 #define HW_SET_CP15_C3(v) HW_INST_MCR(p15,0,c3,c0,0,v) // fixed all
97 #define HW_SET_CP15_C5(o,v) HW_INST_MCR(p15,0,c5,c0,o,v) // Opcode_1 and CRm are fixed
98 #define HW_SET_CP15_C6(o,v) HW_INST_MCR(p15,0,c6,c0,o,v) // Opcode_1 and CRm are fixed
99 #define HW_SET_CP15_C7(c,o,v) HW_INST_MCR(p15,0,c7,c,o,v) // Opcode_1 is fixed
100 #define HW_SET_CP15_C8(c,o,v) HW_INST_MCR(p15,0,c8,c,o,v) // Opcode_1 is fixed
101 #define HW_SET_CP15_C9(v) HW_INST_MCR(p15,0,c9,c0,0,v) // fixed all
102 #define HW_SET_CP15_C10(c,o,v) HW_INST_MCR(p15,0,c10,c,o,v) // Opcode_1 is fixed
103 #define HW_SET_CP15_C13(o,v) HW_INST_MCR(p15,0,c13,c0,o,v) // Opcode_1 and CRm are fixed
104 #define HW_SET_CP15_C15(o1,c,o2,v) HW_INST_MCR(p15,o1,c15,c,o2,v) // not fixed all
106 #define HW_SET_CP15_C15_0(c,o,v) HW_INST_MCR(p15,0,c15,c,o,v)
107 #define HW_SET_CP15_C15_5(c,o,v) HW_INST_MCR(p15,5,c15,c,o,v)
108 #define HW_SET_CP15_C15_7(v) HW_INST_MCR(p15,7,c15,c1,0,v)
208 #define HW_SET_CP15_CONTROL(v) HW_INST_MCR(p15,0,c1,c0,0,v)
209 #define HW_SET_CP15_AUX_CONTROL(v) HW_INST_MCR(p15,0,c1,c0,1,v)
210 #define HW_SET_CP15_COPROCESSOR_ACCESS_CONTROL(v) HW_INST_MCR(p15,0,c1,c0,2,v)
212 #define HW_SET_CP15_TTB0(v) HW_INST_MCR(p15,0,c2,c0,0,v)
213 #define HW_SET_CP15_TTB1(v) HW_INST_MCR(p15,0,c2,c0,1,v)
214 #define HW_SET_CP15_TTB_CONTROL(v) HW_INST_MCR(p15,0,c2,c0,2,v)
215 #define HW_SET_CP15_DOMAIN_ACCESS_CONTROL(v) HW_INST_MCR(p15,0,c3,c0,0,v)
216 #define HW_SET_CP15_DATA_FAULT_STATUS(v) HW_INST_MCR(p15,0,c5,c0,0,v)
217 #define HW_SET_CP15_INSTRUCTION_FAULT_STATUS(v) HW_INST_MCR(p15,0,c5,c0,1,v)
218 #define HW_SET_CP15_DATA_FAULT_ADDRESS(v) HW_INST_MCR(p15,0,c6,c0,0,v)
219 #define HW_SET_CP15_WATCHPOINT_FAULT_ADDRESS(v) HW_INST_MCR(p15,0,c6,c0,1,v)
221 #define HW_SET_CP15_CACHE_ENABLE(v) HW_INST_MCR(p15,0,c2,c0,0,v)
223 #define HW_SET_CP15_INSTRUCTION_CACHE_ENABLE(v) HW_INST_MCR(p15,0,c2,c0,1,v)
224 #define HW_SET_CP15_WRITE_BUFFER_ENABLE(v) HW_INST_MCR(p15,0,c3,c0,0,v)
225 #define HW_SET_CP15_ACCESS_PERMISSION(v) HW_INST_MCR(p15,0,c5,c0,0,v)
227 #define HW_SET_CP15_INSTRUCTION_ACCESS_PERMISSION(v) HW_INST_MCR(p15,0,c5,c0,1,v)
228 #define HW_SET_CP15_DATA_ACCESS_PERMISSION_EX(v) HW_INST_MCR(p15,0,c5,c0,2,v)
229 #define HW_SET_CP15_INSTRUCTION_ACCESS_PERMISSION_EX(v) HW_INST_MCR(p15,0,c5,c0,3,v)
230 #define HW_SET_CP15_PROTECTION_REGION_0(v) HW_INST_MCR(p15,0,c6,c0,0,v)
231 #define HW_SET_CP15_PROTECTION_REGION_1(v) HW_INST_MCR(p15,0,c6,c1,0,v)
232 #define HW_SET_CP15_PROTECTION_REGION_2(v) HW_INST_MCR(p15,0,c6,c2,0,v)
233 #define HW_SET_CP15_PROTECTION_REGION_3(v) HW_INST_MCR(p15,0,c6,c3,0,v)
234 #define HW_SET_CP15_PROTECTION_REGION_4(v) HW_INST_MCR(p15,0,c6,c4,0,v)
235 #define HW_SET_CP15_PROTECTION_REGION_5(v) HW_INST_MCR(p15,0,c6,c5,0,v)
236 #define HW_SET_CP15_PROTECTION_REGION_6(v) HW_INST_MCR(p15,0,c6,c6,0,v)
237 #define HW_SET_CP15_PROTECTION_REGION_7(v) HW_INST_MCR(p15,0,c6,c7,0,v)
239 #define HW_SET_CP15_WFI(v) HW_INST_MCR(p15,0,c7,c0,4,v)
240 #define HW_SET_CP15_INVALIDATE_ENTIRE_INSTRUCTION_CACHE(v) HW_INST_MCR(p15,0,c7,c5,0,v)
241 #define HW_SET_CP15_INVALIDATE_INSTRUCTION_CACHE_MVA(v) HW_INST_MCR(p15,0,c7,c5,1,v)
242 #define HW_SET_CP15_INVALIDATE_INSTRUCTION_CACHE_INDEX(v) HW_INST_MCR(p15,0,c7,c5,2,v)
243 #define HW_SET_CP15_FLUSH_PREFETCH_BUFFER(v) HW_INST_MCR(p15,0,c7,c5,4,v)
244 #define HW_SET_CP15_FLUSH_ENTIRE_BRANCH_TARGET_CACHE(v) HW_INST_MCR(p15,0,c7,c5,6,v)
245 #define HW_SET_CP15_FLUSH_BRANCH_TARGET_CACHE_ENTRY(v) HW_INST_MCR(p15,0,c7,c5,7,v)
246 #define HW_SET_CP15_INVALIDATE_ENTIRE_DATA_CACHE(v) HW_INST_MCR(p15,0,c7,c6,0,v)
247 #define HW_SET_CP15_INVALIDATE_DATA_CACHE_MVA(v) HW_INST_MCR(p15,0,c7,c6,1,v)
248 #define HW_SET_CP15_INVALIDATE_DATA_CACHE_INDEX(v) HW_INST_MCR(p15,0,c7,c6,2,v)
249 #define HW_SET_CP15_INVALIDATE_BOTH_CACHE(v) HW_INST_MCR(p15,0,c7,c7,0,v)
250 #define HW_SET_CP15_VA_TO_PA_PRIVILEGED_READ(v) HW_INST_MCR(p15,0,c7,c8,0,v)
251 #define HW_SET_CP15_VA_TO_PA_PRIVILEGED_WRITE(v) HW_INST_MCR(p15,0,c7,c8,1,v)
252 #define HW_SET_CP15_VA_TO_PA_USER_READ(v) HW_INST_MCR(p15,0,c7,c8,2,v)
253 #define HW_SET_CP15_VA_TO_PA_USER_WRITE(v) HW_INST_MCR(p15,0,c7,c8,3,v)
254 #define HW_SET_CP15_CLEAN_ENTIRE_DATA_CACHE(v) HW_INST_MCR(p15,0,c7,c10,0,v)
255 #define HW_SET_CP15_CLEAN_DATA_CACHE_MVA(v) HW_INST_MCR(p15,0,c7,c10,1,v)
256 #define HW_SET_CP15_CLEAN_DATA_CACHE_INDEX(v) HW_INST_MCR(p15,0,c7,c10,2,v)
257 #define HW_SET_CP15_DATA_SYNC_BARRIER(v) HW_INST_MCR(p15,0,c7,c10,4,v)
258 #define HW_SET_CP15_DATA_MEMORY_BARRIER(v) HW_INST_MCR(p15,0,c7,c10,5,v)
259 #define HW_SET_CP15_CLEAN_INVALIDATE_ENTIRE_DATA_CACHE(v) HW_INST_MCR(p15,0,c7,c14,0,v)
260 #define HW_SET_CP15_CLEAN_INVALIDATE_DATA_CACHE_MVA(v) HW_INST_MCR(p15,0,c7,c14,1,v)
261 #define HW_SET_CP15_CLEAN_INVALIDATE_DATA_CACHE_INDEX(v) HW_INST_MCR(p15,0,c7,c14,2,v)
262 #define HW_SET_CP15_INVALIDATE_INSTRUCTION_TLB(v) HW_INST_MCR(p15,0,c8,c5,0,v)
263 #define HW_SET_CP15_INVALIDATE_INSTRUCTION_TLB_SINGLE(v) HW_INST_MCR(p15,0,c8,c5,1,v)
264 #define HW_SET_CP15_INVALIDATE_INSTRUCTION_TLB_ASID(v) HW_INST_MCR(p15,0,c8,c5,2,v)
265 #define HW_SET_CP15_INVALIDATE_INSTRUCTION_TLB_MVA(v) HW_INST_MCR(p15,0,c8,c5,3,v)
266 #define HW_SET_CP15_INVALIDATE_DATA_TLB(v) HW_INST_MCR(p15,0,c8,c6,0,v)
267 #define HW_SET_CP15_INVALIDATE_DATA_TLB_SINGLE(v) HW_INST_MCR(p15,0,c8,c6,1,v)
268 #define HW_SET_CP15_INVALIDATE_DATA_TLB_ASID(v) HW_INST_MCR(p15,0,c8,c6,2,v)
269 #define HW_SET_CP15_INVALIDATE_DATA_TLB_MVA(v) HW_INST_MCR(p15,0,c8,c6,3,v)
270 #define HW_SET_CP15_INVALIDATE_UNIFIED_TLB(v) HW_INST_MCR(p15,0,c8,c7,0,v)
271 #define HW_SET_CP15_INVALIDATE_UNIFIED_TLB_SINGLE(v) HW_INST_MCR(p15,0,c8,c7,1,v)
272 #define HW_SET_CP15_INVALIDATE_UNIFIED_TLB_ASID(v) HW_INST_MCR(p15,0,c8,c7,2,v)
273 #define HW_SET_CP15_INVALIDATE_UNIFIED_TLB_MVA(v) HW_INST_MCR(p15,0,c8,c7,3,v)
274 #define HW_SET_CP15_DATA_CACHE_LOCKDOWN(v) HW_INST_MCR(p15,0,c9,c0,0,v)
276 #define HW_SET_CP15_INSTRUCTION_CACHE_LOCKDOWN(v) HW_INST_MCR(p15,0,c9,c0,1,v)
277 #define HW_SET_CP15_DTCM(v) HW_INST_MCR(p15,0,c9,c1,0,v)
278 #define HW_SET_CP15_ITCM(v) HW_INST_MCR(p15,0,c9,c1,1,v)
280 #define HW_SET_CP15_PRIMARY_REGION_REMAP(v) HW_INST_MCR(p15,0,c10,c2,0,v)
281 #define HW_SET_CP15_NORMAL_REGION_REMAP(v) HW_INST_MCR(p15,0,c10,c2,1,v)
282 #define HW_SET_CP15_FSCSE_PID(v) HW_INST_MCR(p15,0,c13,c0,0,v)
283 #define HW_SET_CP15_CONTEXT_ID(v) HW_INST_MCR(p15,0,c13,c0,1,v)
284 #define HW_SET_CP15_THREAD_ID(v) HW_INST_MCR(p15,0,c13,c0,2,v)
285 #define HW_SET_CP15_THREAD_ID_USER_READ_ONLY(v) HW_INST_MCR(p15,0,c13,c0,3,v)
286 #define HW_SET_CP15_THREAD_ID_PRIVILEGED_ONLY(v) HW_INST_MCR(p15,0,c13,c0,4,v)
288 #define HW_SET_CP15_TEST_STATE(v) HW_INST_MCR(p15,0,c15,c0,0,v)
289 #define HW_SET_CP15_INSTRUCTIN_TAG_BIST_ADDRESS(v) HW_INST_MCR(p15,0,c15,c0,2,v)
290 #define HW_SET_CP15_INSTRUCTIN_TAG_BIST_GENERAL(v) HW_INST_MCR(p15,0,c15,c0,3,v)
291 #define HW_SET_CP15_DATA_TAG_BIST_ADDRESS(v) HW_INST_MCR(p15,0,c15,c0,6,v)
292 #define HW_SET_CP15_DATA_TAG_BIST_GENERAL(v) HW_INST_MCR(p15,0,c15,c0,7,v)
293 #define HW_SET_CP15_ITCM_BIST_ADDRESS(v) HW_INST_MCR(p15,1,c15,c0,2,v)
294 #define HW_SET_CP15_ITCM_BIST_GENERAL(v) HW_INST_MCR(p15,1,c15,c0,3,v)
295 #define HW_SET_CP15_DTCM_BIST_ADDRESS(v) HW_INST_MCR(p15,1,c15,c0,6,v)
296 #define HW_SET_CP15_DTCM_BIST_GENERAL(v) HW_INST_MCR(p15,1,c15,c0,7,v)
297 #define HW_SET_CP15_TRACE_STATE_CONTROL(v) HW_INST_MCR(p15,1,c15,c1,0,v)
298 #define HW_SET_CP15_INSTRUCTIN_CACHE_RAM_BIST_ADDRESS(v) HW_INST_MCR(p15,2,c15,c0,2,v)
299 #define HW_SET_CP15_INSTRUCTIN_CACHE_RAM_BIST_GENERAL(v) HW_INST_MCR(p15,2,c15,c0,3,v)
300 #define HW_SET_CP15_DATA_CACHE_RAM_BIST_ADDRESS(v) HW_INST_MCR(p15,2,c15,c0,6,v)
301 #define HW_SET_CP15_DATA_CACHE_RAM_BIST_GENERAL(v) HW_INST_MCR(p15,2,c15,c0,7,v)
303 #define HW_SET_CP15_PERFORMANCE_MONITOR_CONTROL(v) HW_INST_MCR(p15,0,c15,c12,0,v)
304 #define HW_SET_CP15_CCNT(v) HW_INST_MCR(p15,0,c15,c12,1,v)
305 #define HW_SET_CP15_PMN0(v) HW_INST_MCR(p15,0,c15,c12,2,v)
306 #define HW_SET_CP15_PMN1(v) HW_INST_MCR(p15,0,c15,c12,3,v)
307 #define HW_SET_CP15_READ_MAIN_TLB_LOCKDOWN_ENTRY(v) HW_INST_MCR(p15,0,c15,c4,2,v)
308 #define HW_SET_CP15_WRITE_MAIN_TLB_LOCKDOWN_ENTRY(v) HW_INST_MCR(p15,0,c15,c4,4,v)
310 #define HW_SET_CP15_CACHE_DEBUG_INDEX(v) HW_INST_MCR(p15,3,c15,c0,0,v)
311 #define HW_SET_CP15_INSTRUCTION_TAG(v) HW_INST_MCR(p15,3,c15,c1,0,v)
312 #define HW_SET_CP15_DATA_TAG(v) HW_INST_MCR(p15,3,c15,c2,0,v)
313 #define HW_SET_CP15_INSTRUCTION_CACHE(v) HW_INST_MCR(p15,3,c15,c3,0,v)
314 #define HW_SET_CP15_DATA_CACHE(v) HW_INST_MCR(p15,3,c15,c4,0,v)
316 #define HW_SET_CP15_MAIN_TLB_LOCKDOWN_VA(v) HW_INST_MCR(p15,5,c15,c5,2,v)
317 #define HW_SET_CP15_MAIN_TLB_LOCKDOWN_PA(v) HW_INST_MCR(p15,5,c15,c6,2,v)
318 #define HW_SET_CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE(v) HW_INST_MCR(p15,5,c15,c7,2,v)
319 #define HW_SET_CP15_TLB_DEBUG_CONTROL(v) HW_INST_MCR(p15,7,c15,c1,0,v)
324 #define HW_CP15_WFI() HW_INST_MCR(p15,0,c7,c0,4,0)
325 #define HW_CP15_INVALIDATE_ENTIRE_INSTRUCTION_CACHE() HW_INST_MCR(p15,0,c7,c5,0,0)
326 #define HW_CP15_FLUSH_PREFETCH_BUFFER() HW_INST_MCR(p15,0,c7,c5,4,0)
327 #define HW_CP15_FLUSH_ENTIRE_BRANCH_TARGET_CACHE() HW_INST_MCR(p15,0,c7,c5,6,0)
328 #define HW_CP15_INVALIDATE_ENTIRE_DATA_CACHE() HW_INST_MCR(p15,0,c7,c6,0,0)
329 #define HW_CP15_INVALIDATE_BOTH_CACHE() HW_INST_MCR(p15,0,c7,c7,0,0)
330 #define HW_CP15_CLEAN_ENTIRE_DATA_CACHE() HW_INST_MCR(p15,0,c7,c10,0,0)
331 #define HW_CP15_DATA_SYNC_BARRIER() HW_INST_MCR(p15,0,c7,c10,4,0)
332 #define HW_CP15_DATA_MEMORY_BARRIER() HW_INST_MCR(p15,0,c7,c10,5,0)
333 #define HW_CP15_CLEAN_INVALIDATE_ENTIRE_DATA_CACHE() HW_INST_MCR(p15,0,c7,c14,0,0)
334 #define HW_CP15_INVALIDATE_INSTRUCTION_TLB() HW_INST_MCR(p15,0,c8,c5,0,0)
335 #define HW_CP15_INVALIDATE_DATA_TLB() HW_INST_MCR(p15,0,c8,c6,0,0)
336 #define HW_CP15_INVALIDATE_UNIFIED_TLB() HW_INST_MCR(p15,0,c8,c7,0,0)